SIMTight files for Vivado

[Tevofrost]

Hi, Please I am new to hardware and vivado and I don't know how to find the files which are required for creating a Vivado project for the SIMTight project. Please what do i need to create the Vivado project. Thank you.

[mn416]

Hi @Tevofrost,

SIMTight is not yet supported on Vivado (Xilinx), only Quartus (Intel).

[Tevofrost]

I am currently working on a project for SIMTight to work on a lower end board and I am aware that there is no support but I want to create a project for a Xilinx board (PYNQ Z2 board) but for that I'll need the src code or verilog files or the RTL codes. I aim having issues with the installation of Quartus because I don't have the license for the pro version and the lite version 22.1 and 20.1 has an issue with the quartus_ipgenerate. I get an error that the command is not found and when I check the Quartus bin folder, the quartus_ip generate is not found, this is probably because it is a lite version. Would it be possible to provide the src code or verilog files or the RTL codes so that I can build the project from scratch in Vivado?

[mn416]

The Verlog RTL can be generated by typing make in the src/ directory.

Please see issue #16 for a similar question asked before.

[Tevofrost]

Hi, I ran the command (./cheribuild.py run-riscv64-purecap -d) because I was trying to build the cheri dependencies but I am stuck at a place where I am being asked for a login and password but that was not indicated in the Cheribuild Readme.md.

[mn416]

Hi @Tevofrost, I've not seen that problem before. I recommend looking at the add-cheri-tools branch of SIMTight (soon to be merged into master and documented). There, you can type make build-cheri-tools to build CHERI-LLVM and source cheri-tools/add-cheri-tools-to-path.sh to setup your PATH. Maybe this will solve your problem? In any case, SIMTight needs a specific version of CHERI LLVM, and make build-cheri-tools will take care of this. Hope this helps...

[Tevofrost]

"The DRAM bandwidth on the PYNQ is lower, so one would probably halve the DRAM bus width and the number of vector lanes in Config.h." This statement is in an open issue, I checked the config.h file but I don't see a Dram bus width, please what is the Dram bus width in the config.h file or is the Dram bus width an equivalent of the DRAMBURSTWIDTH in the config.h file?

[mn416]

These lines control the DRAM bus width:

https://github.com/CTSRD-CHERI/SIMTight/blob/master/inc/Config.h#L8-L13

There are restrictions (not well documented) on what values can be set here. So a better approach may be to narrow the bus width outside of SIMTight. For example, on Intel FPGAs, QSys should take care of width adaption automatically.

[Tevofrost]

Hi, Please I'm currently working on the constraint files and I have found the .qsf and .sdc files but I don't really understand how to find the signals and their corresponding pins in the .qsf files so that I can convert it to .xdc for xilinx and the information on intel site isn't very helpful. I would also like to confirm if simtight.v is the top module. Thank you.

[Tevofrost]

I've found the top module. Thanks

[Tevofrost]

I have a couple of issues that i am facing:
1)The DE10-pro board/Simtight uses 6 clocks but i have just 1 clock on my PYNQ Z2 board.
2) There are 50 flash interfaces but i have a 16mb quad SPI flash and i don't know if that is sufficient, your board has ddr4 which utilized 134 pins but mine has ddr3.
3) What is EXP_EN in the .qsf file and the top module used for?
4) I am aware that the 2 UFL connectors are used for connecting external clock inputs but what purpose do they serve in Simtight and are they a crucial element of the project because the PYNQ z2 doesn't have a UFL connector.

The above issues are what i am currently facing, please can you suggest how i can go about solving them.