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RVM.core_desc
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RVM.core_desc
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import "RISCVBase.core_desc"
InstructionSet RVM extends RISCVBase {
architectural_state {
unsigned<34> MUL_LEN = 2 * XLEN;
}
instructions {
MUL {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0110011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
signed<MUL_LEN> res = (signed)X[rs1] * (signed)X[rs2];
if(rd!=0) X[rd] = (unsigned<XLEN>)res;
}
}
MULH {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0110011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
signed<MUL_LEN> res = (signed)X[rs1] * (signed)X[rs2];
if(rd!=0) X[rd] = (unsigned<XLEN>)(res >> XLEN);
}
}
MULHSU {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0110011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
signed<MUL_LEN> res = (signed)X[rs1] * X[rs2];
if(rd!=0) X[rd] = (unsigned<XLEN>)(res >> XLEN);
}
}
MULHU {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0110011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
unsigned<MUL_LEN> res = X[rs1] * X[rs2];
if(rd!=0) X[rd] = (unsigned<XLEN>)(res >> XLEN);
}
}
DIV {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b0110011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
signed<XLEN> dividend = (signed)X[rs1];
signed<XLEN> divisor = (signed)X[rs2];
if(rd != 0) {
if (divisor != 0) {
unsigned<XLEN> MMIN = ((unsigned<XLEN>)1)<<(XLEN-1);
if (X[rs1] == MMIN && divisor == -1) {
X[rd] = MMIN;
} else
X[rd] = (unsigned<XLEN>)(dividend / divisor);
} else
X[rd] = (unsigned<XLEN>)-1;
}
}
}
DIVU {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0110011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
if (X[rs2] != 0) {
if(rd!=0) X[rd] = X[rs1] / X[rs2];
} else
if(rd!=0) X[rd] = (unsigned<XLEN>)-1;
}
}
REM {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b0110011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
if (X[rs2] != 0) {
unsigned<XLEN> MMIN = (unsigned<XLEN>)1<<(XLEN-1);
if (X[rs1] == MMIN && (signed<XLEN>)X[rs2] == -1) {
if(rd!=0) X[rd] = 0;
} else {
if(rd!=0) X[rd] = (unsigned)((signed)X[rs1] % (signed)X[rs2]);
}
} else
if(rd!=0) X[rd] = X[rs1];
}
}
REMU {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b0110011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
if (X[rs2] != 0) {
if(rd!=0) X[rd] = X[rs1] % X[rs2];
} else {
if(rd!=0) X[rd] = X[rs1];
}
}
}
MULW [[enable=XLEN==64]] {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0111011;
assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
if(rd!=0) {
signed<32> resw = (signed<32>)((signed<32>)X[rs1] * (signed<32>)X[rs2]);
X[rd] = (unsigned)(signed<XLEN>)resw;
}
}
}
DIVW [[enable=XLEN==64]] {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b0111011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
signed<32> dividend = (signed<32>)X[rs1];
signed<32> divisor = (signed<32>)X[rs2];
if (divisor != 0) {
signed<32> MMIN = (signed<32>)1<<31;
if (dividend == MMIN && divisor == -1) {
if(rd!=0) X[rd] = (unsigned<XLEN>)-1<<31;
} else {
if(rd!=0) X[rd] = (unsigned<XLEN>)(dividend / divisor);
}
} else
if(rd!=0) X[rd] = (unsigned<XLEN>)-1;
}
}
DIVUW [[enable=XLEN==64]] {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0111011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
unsigned<32> divisor = (unsigned<32>)X[rs2];
if (divisor != 0) {
signed<32> res = (signed<32>)((unsigned<32>)X[rs1] / divisor);
if(rd!=0) X[rd] = (unsigned)(signed<XLEN>)res;
} else
if(rd!=0) X[rd] = (unsigned<XLEN>)-1;
}
}
REMW [[enable=XLEN==64]] {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b0111011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
if (((signed<32>)X[rs2]) != 0) {
signed<32> SMIN = (signed<32>)1<<31;
if ((signed<32>)X[rs1] == SMIN && (signed<32>)X[rs2] == -1) {
if(rd!=0) X[rd] = 0;
} else {
if(rd!=0) X[rd] = (unsigned<XLEN>)((signed<32>)X[rs1] % (signed<32>)X[rs2]);
}
} else
if(rd!=0) X[rd] = (unsigned<XLEN>)((signed<32>)X[rs1]);
}
}
REMUW [[enable=XLEN==64]] {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b0111011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
unsigned<32> divisor = (unsigned<32>)X[rs2];
if (divisor != 0) {
signed<32> res = (signed<32>)((unsigned<32>)X[rs1] % divisor);
if(rd!=0) X[rd] = (unsigned)(signed<XLEN>)res;
} else {
signed<32> res = (signed<32>)X[rs1];
if(rd!=0) X[rd] = (unsigned)(signed<XLEN>)res;
}
}
}
}
}