design.txt

ARCHITECTURE:

Word size = 32 bit

REGISTERS: 16 word sized REGISTERs, 12 General Use, Flags, Program Counter, Base Pointer and STACK Pointer

GENERAL USE:
R0 - Accumulator, by standard stores return values.
R1 - Accumulator.

FLAGS:

the FLAGS are set after a ADD, SUB, AND, OR, XOR and CMP INSTRUCTION.

ZF - indicates wether the latest calculation resulted in 0.
NF - indicates wether the most signifact bit was set in the last calculation.
CF - indicates wether the last calculation has a carry.
OF - indicates wether the latest calculation overflowed.


MEMORY: 2^16 addresses, all word sized. 
STACK:        0x0000 - 0x1fff
Heap:         0x2000 - 0x5fff
Data Segment: 0x6000 - 0x7fff   
Code Segment: 0x8000 - 0xffff
INSTRUCTIONS:

The INSTRUCTIONS are the representations of OPCODES in an assembly file (.ec file).
an INSTRUCTION may correspond directly to an OPCODE or may be translated to a variety of OPCODES
depending on arguements provided.
The corresponding OPCODE for an INSTRUCTION will start with the INSTRUCTION mnemonic.

END => END
NOP => NOP
PUSH => PUSHI, PUSHL, PUSHR
POP => POP
LDR => LDR
STR => STR
MOV => MOVRI, MOVRL, MOVRR
(The same translations apply to ADD, SUB, MUL, IMUL, DIV, IDIV, AND, OR, XOR)
JMP => JMP
JNZ => JNZ
JZ  => JZ   
JG  => JG   
JGE => JGE   
JL  => JL   
JLE => JLE   
JA  => JA   
JAE => JAE  
JB  => JB   
JBE => JBE 


OPERATIONS:

The OPERATIONS are the machine specification for the assembly lagnuage INSTRUCTIONS, 
for exmaple MOVRI is the specific OPERATION for a MOV INSTRUCTION with a REGISTER as destination and an IMMEDIATE VALUE as source.
The INSTRUCTION SET is a RISC ISA, meaning there is no interaction with memory besides loading from it and jumping to it.

Word sized, design:
                            32 bits
|----------------------------------------------------------------|
|          |  1st operard |             immediate                |         
|  opcode  |   REGISTER   |            20 bit value              |
|          |              |                                      |
|----------------------------------------------------------------|
    8 bits    4 bits               20 bits

Note that some INSTRUCTIONS may have an OPCODE for larger than 20bit values that will include a jump to the next ADDRESS stored in the CODE SEGMENT.

OPCODES:

END:   Labels end of code
NOP:   Move to next instruction

PUSH:
PUSHI: Pushes immediate value to STACK
PUSHL: Pushes 32bit value to STACK
PUSHR: Pushes value from REGISTER

POP:   Pops value from STACK to REGISTER

LDR:   Moves value from MEMORY ADDRESS pointed to by the 2nd operand REGISTER 
       to REGISTER in first operand.

STR:   Stores into MEMORY ADDRESS pointed by the 1st operand REGISTER 
       the value stored in the 2nd REGISTER in first operand.

MOV:
MOVRI: Moves immediate value to REGISTER
MOVRL: Moves 32bit value to REGISTER
MOVRR: Moves from REGISTER to REGISTER

ADD:
ADDRI: Adds immediate value to REGISTER
ADDRL: Adds 32bit value to REGISTER
ADDRR: Adds from REGISTER to REGISTER

(Same opcodes specification for SUB, MUL and DIV instructions)
(MUL and DIV have corresponding IMUL and IDIV INSTRUCTIONS for signed calculations)

CMP: 
CMPRI: Compares immediate value to REGISTER
CMPRL: Compares 32bit value to REGISTER
CMPRR: Compares from REGISTER to REGISTER

JMP:   Jumps to memory address
JNZ:   Jumps to memory address if ZF = 0
JZ:    Jumps to memory address if ZF = 1
JG:    Signed > check, works if ZF = 0 and NF = OF
JGE:   Signed >= check, works if NF = OF
JL:    Signed < check, works if NF != OF
JLE:   Signed <= check, works if ZF = 0 or NF != OF
JA:    Unsigned > check, works if CF = 0
JAE:   Unsigned >= check, works if CF = 0 or ZF = 1
JB:    Unsigned < check, works if CF = 1
JBE:   Unsigned >= check, works if CF = 1 or ZF = 1

NOT:   Logical NOT on value in REGISTER

AND:
ANDRI: Logical end between immediate value to REGISTER
ANDRL: Logical end between 32bit value to REGISTER
ANDRR: Logical end between REGISTER to REGISTER

(Same opcode specification OR and XOR instruction)