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'\' must not be interpreted as an escape character inside a string in VHDL.
E.g. when defining:
variable s : string := "test\";
The second " is not recognized as an end-of-string character, braking all syntax highlighting following this line.
The text was updated successfully, but these errors were encountered:
'\' must not be interpreted as an escape character inside a string in VHDL.
E.g. when defining:
variable s : string := "test\";
The second " is not recognized as an end-of-string character, braking all syntax highlighting following this line.
The text was updated successfully, but these errors were encountered: