Can we vary AxiRam response delays ?

[0BAB1]

I am verifying some cache module and I would like to verify its behavior when axi_bvalid (write response valid) takes time to arrive. It would be cool if we can randomize this too.

Maybe it's already an existing feature. Is it ?

Right now the bvalid always takes 1 cycle to arrive, here is an example :

assert dut.cache_system.next_state.value == WAITING_WRITE_RES

await RisingEdge(dut.clk) # STATE SWITCH !
await Timer(1, units="ps")

assert dut.cache_system.state.value == WAITING_WRITE_RES
assert dut.axi_wvalid.value == 0b0
assert dut.axi_bready.value == 0b1

while not dut.axi_bvalid.value == 0b1:
    # if we have no response from memory, then we wait
    await RisingEdge(dut.clk)
    await Timer(1, units="ps")
    print("wait")

The code above will print "wait" once everytime.

Here is how I use the AxiRam if that's relevant :

axi_ram_slave = AxiRam(AxiBus.from_prefix(dut, "axi"), dut.clk, dut.rst_n, size=SIZE, reset_active_level=False)