Error with negative indices in unpacked array

[StefanoBettelli]

The following module can be processed by Surelog v1.47,

module shifter
  #(parameter SBITS = 5,
    parameter NBITS = 32)
   (input  logic [NBITS-1:0] A,  // bit sequence to be shifted
    input  logic [SBITS-1:0] S,  // amount of shift
    output logic [NBITS-1:0] R); // shifted sequence
   localparam F = 0; // index offset
   wire    logic [NBITS-1:0] Output   [-1+F:SBITS-1+F];
   wire    logic [NBITS-1:0] LShifted [0:SBITS-1];
   assign Output[-1+F] = A;
   for (genvar i=0; i<SBITS; i=i+1) begin
      assign LShifted[i] = { Output[i-1+F][NBITS-1-2**i:0], {(2**i){1'b0}} };
      assign Output[i+F] = S[i] ? Output[i-1+F] : LShifted[i];
   end
   assign R = Output[SBITS-1+F];
endmodule

but cannot be read by the UHDM import plugin (commit d843c71) when F = 0

(i.e., when the Output array starts from -1 rather than 0.

Yosys 0.25+83 (git sha1 755b753e1, gcc 12.2.0-3ubuntu1 -fPIC -Os)
yosys> plugin -i systemverilog; read_uhdm slpp_all/surelog.uhdm
1. Executing UHDM frontend.
Generating RTLIL representation for module `\shifter'.
Warning: Replacing memory \LShifted with list of registers.
Warning: Replacing memory \Output with list of registers.
[...]shifter.sv:16: ERROR: Failed to resolve identifier \Output[-1] for width detection!

As long as I know this code is legal, and it compiles and executes correctly with verilator.

Being able to use negative indices in unpacked arrays makes the code a lot more expressive in some cases ...

[alaindargelas]

UHDM creates a valid model.
Both Yosys default parser and read_systemverilog using UHDM end-up with the same error.

[wsipak]

Currently the plugin does not handle negative indexes, and this won't be an easy fix since the plugin has to translate the indexes to positive zero-based range for Yosys and the other way round.

Let's keep this issue open to track the progress.