From f1816b68c8e9972e37191b0f469315ee05c9a85a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 5 Dec 2023 12:20:42 -0800 Subject: [PATCH] OUTBUF -> OBUFT Signed-off-by: Eddie Hung --- docs/score.md | 2 +- wirelength_analyzer/xcvup_device_data.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/score.md b/docs/score.md index 390d63f..9902c5c 100644 --- a/docs/score.md +++ b/docs/score.md @@ -119,7 +119,7 @@ BEL input and output pins for each type of PhysCell. |`LUT1`, `LUT2`, `LUT3`, `LUT4`, `LUT5`, `LUT6` | (all) <- (all) | Look Up Table | |`CARRY8` | [see table CARRY8](#carry8-connectivity) | Fast Carry Logic | |`MUXF7`, `MUXF8`, `MUXF9` | (all) <- (all) | Intrasite Mux | -|`IBUFCTRL`, `INBUF`, `OUTBUF` | (all) <- (all) | I/O Buffer | +|`IBUFCTRL`, `INBUF`, `OBUFT` | (all) <- (all) | I/O Buffer | |`DSP_A_B_DATA`, `DSP_C_DATA`, `DSP_M_DATA`,
`DSP_PREADD_DATA`, `DSP_OUTPUT`, `DSP_ALU` | (none) <- (none) [see note](#dsp-cell-connectivity) | DSP Logic | |`DSP_MULTIPLIER`, `DSP_PREADD` | (all) <- (all) [see note](#dsp-cell-connectivity) | DSP Logic | |`PCIE40E4` | (none) <- (none) | PCIe Hard Macro | diff --git a/wirelength_analyzer/xcvup_device_data.py b/wirelength_analyzer/xcvup_device_data.py index d484442..259056b 100644 --- a/wirelength_analyzer/xcvup_device_data.py +++ b/wirelength_analyzer/xcvup_device_data.py @@ -80,7 +80,7 @@ def __contains__(self, item): 'IBUFCTRL': self.all_to_all, 'INBUF': self.all_to_all, - 'OUTBUF': self.all_to_all, + 'OBUFT': self.all_to_all, # The following cell types are BELs that make up a DSP macro. # Such DSPs contains a number of optional pipelining registers,