From abe33067e6a67e2334e0329d994ccd1faf386717 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kevin=20L=C3=A4ufer?= Date: Mon, 8 Jan 2024 15:20:19 -0800 Subject: [PATCH] repair: wip add guard template --- rtlrepair/templates/add_guard.py | 33 ++++++++++++++++++++ rtlrepair/templates/conditional_overwrite.py | 2 +- 2 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 rtlrepair/templates/add_guard.py diff --git a/rtlrepair/templates/add_guard.py b/rtlrepair/templates/add_guard.py new file mode 100644 index 0000000..a775916 --- /dev/null +++ b/rtlrepair/templates/add_guard.py @@ -0,0 +1,33 @@ +# Copyright 2023-2024 The Regents of the University of California +# released under BSD 3-Clause License +# author: Kevin Laeufer + + +from rtlrepair.repair import RepairTemplate +from rtlrepair.types import InferWidths +from rtlrepair.utils import Namespace, ensure_block +import pyverilog.vparser.ast as vast + + +def add_guard(ast: vast.Source): + """ Adds a condition to a boolean expression. """ + namespace = Namespace(ast) + infer = InferWidths() + infer.run(ast) + repl = AddGuard(infer.widths) + repl.apply(namespace, ast) + return repl.blockified + + +class AddGuard(RepairTemplate): + def __init__(self, widths): + super().__init__(name="add_guard") + self.widths = widths + self.use_blocking = False + self.assigned_vars = [] + # we use this list to track which new blocks we introduced in order to minimize the diff between + # buggy and repaired version + self.blockified = [] + # remember all 1-bit registers + self.bool_registers = set() + diff --git a/rtlrepair/templates/conditional_overwrite.py b/rtlrepair/templates/conditional_overwrite.py index d24f95e..1f820ab 100644 --- a/rtlrepair/templates/conditional_overwrite.py +++ b/rtlrepair/templates/conditional_overwrite.py @@ -1,4 +1,4 @@ -# Copyright 2023 The Regents of the University of California +# Copyright 2023-2024 The Regents of the University of California # released under BSD 3-Clause License # author: Kevin Laeufer