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segbits_bram.origin_info.db
270 lines (270 loc) · 14.4 KB
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segbits_bram.origin_info.db
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BRAM.RAMB18E2_L.CLKARDCLKINV.V0 origin:020-bram !05_91
BRAM.RAMB18E2_L.CLKARDCLKINV.V1 origin:020-bram 05_91
BRAM.RAMB18E2_L.CLKBWRCLKINV.V0 origin:020-bram !05_94
BRAM.RAMB18E2_L.CLKBWRCLKINV.V1 origin:020-bram 05_94
BRAM.RAMB18E2_L.CLOCK_DOMAINS.COMMON origin:020-bram 04_98
BRAM.RAMB18E2_L.CLOCK_DOMAINS.INDEPENDENT origin:020-bram !04_98
BRAM.RAMB18E2_L.DOA_REG.V0 origin:020-bram !04_58
BRAM.RAMB18E2_L.DOA_REG.V1 origin:020-bram 04_58
BRAM.RAMB18E2_L.DOB_REG.V0 origin:020-bram !04_61
BRAM.RAMB18E2_L.DOB_REG.V1 origin:020-bram 04_61
BRAM.RAMB18E2_L.ENADDRENA.FALSE origin:020-bram !04_101
BRAM.RAMB18E2_L.ENADDRENA.TRUE origin:020-bram 04_101
BRAM.RAMB18E2_L.ENADDRENB.FALSE origin:020-bram !04_100
BRAM.RAMB18E2_L.ENADDRENB.TRUE origin:020-bram 04_100
BRAM.RAMB18E2_L.ENARDENINV.V0 origin:020-bram !04_93
BRAM.RAMB18E2_L.ENARDENINV.V1 origin:020-bram 04_93
BRAM.RAMB18E2_L.ENBWRENINV.V0 origin:020-bram !04_92
BRAM.RAMB18E2_L.ENBWRENINV.V1 origin:020-bram 04_92
BRAM.RAMB18E2_L.INIT_A[0] origin:020-bram 05_02
BRAM.RAMB18E2_L.INIT_A[1] origin:020-bram 05_14
BRAM.RAMB18E2_L.INIT_A[2] origin:020-bram 05_26
BRAM.RAMB18E2_L.INIT_A[3] origin:020-bram 05_38
BRAM.RAMB18E2_L.INIT_A[4] origin:020-bram 05_62
BRAM.RAMB18E2_L.INIT_A[5] origin:020-bram 05_74
BRAM.RAMB18E2_L.INIT_A[6] origin:020-bram 05_86
BRAM.RAMB18E2_L.INIT_A[7] origin:020-bram 05_98
BRAM.RAMB18E2_L.INIT_A[8] origin:020-bram 05_08
BRAM.RAMB18E2_L.INIT_A[9] origin:020-bram 05_20
BRAM.RAMB18E2_L.INIT_A[10] origin:020-bram 05_32
BRAM.RAMB18E2_L.INIT_A[11] origin:020-bram 05_44
BRAM.RAMB18E2_L.INIT_A[12] origin:020-bram 05_68
BRAM.RAMB18E2_L.INIT_A[13] origin:020-bram 05_80
BRAM.RAMB18E2_L.INIT_A[14] origin:020-bram 05_92
BRAM.RAMB18E2_L.INIT_A[15] origin:020-bram 05_104
BRAM.RAMB18E2_L.INIT_A[16] origin:020-bram 05_50
BRAM.RAMB18E2_L.INIT_A[17] origin:020-bram 05_56
BRAM.RAMB18E2_L.INIT_B[0] origin:020-bram 05_05
BRAM.RAMB18E2_L.INIT_B[1] origin:020-bram 05_17
BRAM.RAMB18E2_L.INIT_B[2] origin:020-bram 05_29
BRAM.RAMB18E2_L.INIT_B[3] origin:020-bram 05_41
BRAM.RAMB18E2_L.INIT_B[4] origin:020-bram 05_65
BRAM.RAMB18E2_L.INIT_B[5] origin:020-bram 05_77
BRAM.RAMB18E2_L.INIT_B[6] origin:020-bram 05_89
BRAM.RAMB18E2_L.INIT_B[7] origin:020-bram 05_101
BRAM.RAMB18E2_L.INIT_B[8] origin:020-bram 05_11
BRAM.RAMB18E2_L.INIT_B[9] origin:020-bram 05_23
BRAM.RAMB18E2_L.INIT_B[10] origin:020-bram 05_35
BRAM.RAMB18E2_L.INIT_B[11] origin:020-bram 05_47
BRAM.RAMB18E2_L.INIT_B[12] origin:020-bram 05_71
BRAM.RAMB18E2_L.INIT_B[13] origin:020-bram 05_83
BRAM.RAMB18E2_L.INIT_B[14] origin:020-bram 05_95
BRAM.RAMB18E2_L.INIT_B[15] origin:020-bram 05_107
BRAM.RAMB18E2_L.INIT_B[16] origin:020-bram 05_53
BRAM.RAMB18E2_L.INIT_B[17] origin:020-bram 05_59
BRAM.RAMB18E2_L.RDADDRCHANGEA.FALSE origin:020-bram !04_97
BRAM.RAMB18E2_L.RDADDRCHANGEA.TRUE origin:020-bram 04_97
BRAM.RAMB18E2_L.RDADDRCHANGEB.FALSE origin:020-bram !04_96
BRAM.RAMB18E2_L.RDADDRCHANGEB.TRUE origin:020-bram 04_96
BRAM.RAMB18E2_L.READ_WIDTH_A.36 origin:020-bram 05_49
BRAM.RAMB18E2_L.RSTRAMARSTRAMINV.V0 origin:020-bram !04_91
BRAM.RAMB18E2_L.RSTRAMARSTRAMINV.V1 origin:020-bram 04_91
BRAM.RAMB18E2_L.RSTRAMBINV.V0 origin:020-bram !04_90
BRAM.RAMB18E2_L.RSTRAMBINV.V1 origin:020-bram 04_90
BRAM.RAMB18E2_L.RSTREG_PRIORITY_A.REGCE origin:020-bram 04_83
BRAM.RAMB18E2_L.RSTREG_PRIORITY_A.RSTREG origin:020-bram !04_83
BRAM.RAMB18E2_L.RSTREG_PRIORITY_B.REGCE origin:020-bram 04_82
BRAM.RAMB18E2_L.RSTREG_PRIORITY_B.RSTREG origin:020-bram !04_82
BRAM.RAMB18E2_L.RSTREGARSTREGINV.V0 origin:020-bram !04_85
BRAM.RAMB18E2_L.RSTREGARSTREGINV.V1 origin:020-bram 04_85
BRAM.RAMB18E2_L.SLEEP_ASYNC.FALSE origin:020-bram !05_88
BRAM.RAMB18E2_L.SLEEP_ASYNC.TRUE origin:020-bram 05_88
BRAM.RAMB18E2_L.SRVAL_A[0] origin:020-bram 05_00
BRAM.RAMB18E2_L.SRVAL_A[1] origin:020-bram 05_12
BRAM.RAMB18E2_L.SRVAL_A[2] origin:020-bram 05_24
BRAM.RAMB18E2_L.SRVAL_A[3] origin:020-bram 05_36
BRAM.RAMB18E2_L.SRVAL_A[4] origin:020-bram 05_60
BRAM.RAMB18E2_L.SRVAL_A[5] origin:020-bram 05_72
BRAM.RAMB18E2_L.SRVAL_A[6] origin:020-bram 05_84
BRAM.RAMB18E2_L.SRVAL_A[7] origin:020-bram 05_96
BRAM.RAMB18E2_L.SRVAL_A[8] origin:020-bram 05_06
BRAM.RAMB18E2_L.SRVAL_A[9] origin:020-bram 05_18
BRAM.RAMB18E2_L.SRVAL_A[10] origin:020-bram 05_30
BRAM.RAMB18E2_L.SRVAL_A[11] origin:020-bram 05_42
BRAM.RAMB18E2_L.SRVAL_A[12] origin:020-bram 05_66
BRAM.RAMB18E2_L.SRVAL_A[13] origin:020-bram 05_78
BRAM.RAMB18E2_L.SRVAL_A[14] origin:020-bram 05_90
BRAM.RAMB18E2_L.SRVAL_A[15] origin:020-bram 05_102
BRAM.RAMB18E2_L.SRVAL_A[16] origin:020-bram 05_48
BRAM.RAMB18E2_L.SRVAL_A[17] origin:020-bram 05_54
BRAM.RAMB18E2_L.SRVAL_B[0] origin:020-bram 05_03
BRAM.RAMB18E2_L.SRVAL_B[1] origin:020-bram 05_15
BRAM.RAMB18E2_L.SRVAL_B[2] origin:020-bram 05_27
BRAM.RAMB18E2_L.SRVAL_B[3] origin:020-bram 05_39
BRAM.RAMB18E2_L.SRVAL_B[4] origin:020-bram 05_63
BRAM.RAMB18E2_L.SRVAL_B[5] origin:020-bram 05_75
BRAM.RAMB18E2_L.SRVAL_B[6] origin:020-bram 05_87
BRAM.RAMB18E2_L.SRVAL_B[7] origin:020-bram 05_99
BRAM.RAMB18E2_L.SRVAL_B[8] origin:020-bram 05_09
BRAM.RAMB18E2_L.SRVAL_B[9] origin:020-bram 05_21
BRAM.RAMB18E2_L.SRVAL_B[10] origin:020-bram 05_33
BRAM.RAMB18E2_L.SRVAL_B[11] origin:020-bram 05_45
BRAM.RAMB18E2_L.SRVAL_B[12] origin:020-bram 05_69
BRAM.RAMB18E2_L.SRVAL_B[13] origin:020-bram 05_81
BRAM.RAMB18E2_L.SRVAL_B[14] origin:020-bram 05_93
BRAM.RAMB18E2_L.SRVAL_B[15] origin:020-bram 05_105
BRAM.RAMB18E2_L.SRVAL_B[16] origin:020-bram 05_51
BRAM.RAMB18E2_L.SRVAL_B[17] origin:020-bram 05_57
BRAM.RAMB18E2_L.WRITE_MODE_A.NO_CHANGE origin:020-bram !05_46 05_43
BRAM.RAMB18E2_L.WRITE_MODE_A.READ_FIRST origin:020-bram !05_43 05_46
BRAM.RAMB18E2_L.WRITE_MODE_A.WRITE_FIRST origin:020-bram !05_43 !05_46
BRAM.RAMB18E2_L.WRITE_MODE_B.NO_CHANGE origin:020-bram !05_52 05_55
BRAM.RAMB18E2_L.WRITE_MODE_B.READ_FIRST origin:020-bram !05_55 05_52
BRAM.RAMB18E2_L.WRITE_MODE_B.WRITE_FIRST origin:020-bram !05_52 !05_55
BRAM.RAMB18E2_L.WRITE_WIDTH_B.36 origin:020-bram 05_64
BRAM.RAMB18E2_U.CLKARDCLKINV.V0 origin:020-bram !04_165
BRAM.RAMB18E2_U.CLKARDCLKINV.V1 origin:020-bram 04_165
BRAM.RAMB18E2_U.CLKBWRCLKINV.V0 origin:020-bram !05_163
BRAM.RAMB18E2_U.CLKBWRCLKINV.V1 origin:020-bram 05_163
BRAM.RAMB18E2_U.CLOCK_DOMAINS.COMMON origin:020-bram 04_206
BRAM.RAMB18E2_U.CLOCK_DOMAINS.INDEPENDENT origin:020-bram !04_206
BRAM.RAMB18E2_U.DOA_REG.V0 origin:020-bram !05_184
BRAM.RAMB18E2_U.DOA_REG.V1 origin:020-bram 05_184
BRAM.RAMB18E2_U.DOB_REG.V0 origin:020-bram !05_181
BRAM.RAMB18E2_U.DOB_REG.V1 origin:020-bram 05_181
BRAM.RAMB18E2_U.ENADDRENA.FALSE origin:020-bram !04_195
BRAM.RAMB18E2_U.ENADDRENA.TRUE origin:020-bram 04_195
BRAM.RAMB18E2_U.ENADDRENB.FALSE origin:020-bram !04_193
BRAM.RAMB18E2_U.ENADDRENB.TRUE origin:020-bram 04_193
BRAM.RAMB18E2_U.ENARDENINV.V0 origin:020-bram !05_160
BRAM.RAMB18E2_U.ENARDENINV.V1 origin:020-bram 05_160
BRAM.RAMB18E2_U.ENBWRENINV.V0 origin:020-bram !05_157
BRAM.RAMB18E2_U.ENBWRENINV.V1 origin:020-bram 05_157
BRAM.RAMB18E2_U.INIT_A[0] origin:020-bram 05_134
BRAM.RAMB18E2_U.INIT_A[1] origin:020-bram 05_146
BRAM.RAMB18E2_U.INIT_A[2] origin:020-bram 05_158
BRAM.RAMB18E2_U.INIT_A[3] origin:020-bram 05_170
BRAM.RAMB18E2_U.INIT_A[4] origin:020-bram 05_194
BRAM.RAMB18E2_U.INIT_A[5] origin:020-bram 05_206
BRAM.RAMB18E2_U.INIT_A[6] origin:020-bram 05_218
BRAM.RAMB18E2_U.INIT_A[7] origin:020-bram 05_230
BRAM.RAMB18E2_U.INIT_A[8] origin:020-bram 05_140
BRAM.RAMB18E2_U.INIT_A[9] origin:020-bram 05_152
BRAM.RAMB18E2_U.INIT_A[10] origin:020-bram 05_164
BRAM.RAMB18E2_U.INIT_A[11] origin:020-bram 05_176
BRAM.RAMB18E2_U.INIT_A[12] origin:020-bram 05_200
BRAM.RAMB18E2_U.INIT_A[13] origin:020-bram 05_212
BRAM.RAMB18E2_U.INIT_A[14] origin:020-bram 05_224
BRAM.RAMB18E2_U.INIT_A[15] origin:020-bram 05_236
BRAM.RAMB18E2_U.INIT_A[16] origin:020-bram 05_182
BRAM.RAMB18E2_U.INIT_A[17] origin:020-bram 05_188
BRAM.RAMB18E2_U.INIT_B[0] origin:020-bram 05_137
BRAM.RAMB18E2_U.INIT_B[1] origin:020-bram 05_149
BRAM.RAMB18E2_U.INIT_B[2] origin:020-bram 05_161
BRAM.RAMB18E2_U.INIT_B[3] origin:020-bram 05_173
BRAM.RAMB18E2_U.INIT_B[4] origin:020-bram 05_197
BRAM.RAMB18E2_U.INIT_B[5] origin:020-bram 05_209
BRAM.RAMB18E2_U.INIT_B[6] origin:020-bram 05_221
BRAM.RAMB18E2_U.INIT_B[7] origin:020-bram 05_233
BRAM.RAMB18E2_U.INIT_B[8] origin:020-bram 05_143
BRAM.RAMB18E2_U.INIT_B[9] origin:020-bram 05_155
BRAM.RAMB18E2_U.INIT_B[10] origin:020-bram 05_167
BRAM.RAMB18E2_U.INIT_B[11] origin:020-bram 05_179
BRAM.RAMB18E2_U.INIT_B[12] origin:020-bram 05_203
BRAM.RAMB18E2_U.INIT_B[13] origin:020-bram 05_215
BRAM.RAMB18E2_U.INIT_B[14] origin:020-bram 05_227
BRAM.RAMB18E2_U.INIT_B[15] origin:020-bram 05_239
BRAM.RAMB18E2_U.INIT_B[16] origin:020-bram 05_185
BRAM.RAMB18E2_U.INIT_B[17] origin:020-bram 05_191
BRAM.RAMB18E2_U.RDADDRCHANGEA.FALSE origin:020-bram !04_191
BRAM.RAMB18E2_U.RDADDRCHANGEA.TRUE origin:020-bram 04_191
BRAM.RAMB18E2_U.RDADDRCHANGEB.FALSE origin:020-bram !04_192
BRAM.RAMB18E2_U.RDADDRCHANGEB.TRUE origin:020-bram 04_192
BRAM.RAMB18E2_U.READ_WIDTH_A.36 origin:020-bram 05_208
BRAM.RAMB18E2_U.RSTRAMARSTRAMINV.V0 origin:020-bram !05_154
BRAM.RAMB18E2_U.RSTRAMARSTRAMINV.V1 origin:020-bram 05_154
BRAM.RAMB18E2_U.RSTRAMBINV.V0 origin:020-bram !04_157
BRAM.RAMB18E2_U.RSTRAMBINV.V1 origin:020-bram 04_157
BRAM.RAMB18E2_U.RSTREG_PRIORITY_A.REGCE origin:020-bram 04_148
BRAM.RAMB18E2_U.RSTREG_PRIORITY_A.RSTREG origin:020-bram !04_148
BRAM.RAMB18E2_U.RSTREG_PRIORITY_B.REGCE origin:020-bram 04_145
BRAM.RAMB18E2_U.RSTREG_PRIORITY_B.RSTREG origin:020-bram !04_145
BRAM.RAMB18E2_U.RSTREGARSTREGINV.V0 origin:020-bram !05_151
BRAM.RAMB18E2_U.RSTREGARSTREGINV.V1 origin:020-bram 05_151
BRAM.RAMB18E2_U.SLEEP_ASYNC.FALSE origin:020-bram !05_166
BRAM.RAMB18E2_U.SLEEP_ASYNC.TRUE origin:020-bram 05_166
BRAM.RAMB18E2_U.SRVAL_A[0] origin:020-bram 05_132
BRAM.RAMB18E2_U.SRVAL_A[1] origin:020-bram 05_145
BRAM.RAMB18E2_U.SRVAL_A[2] origin:020-bram 05_156
BRAM.RAMB18E2_U.SRVAL_A[3] origin:020-bram 05_168
BRAM.RAMB18E2_U.SRVAL_A[4] origin:020-bram 05_192
BRAM.RAMB18E2_U.SRVAL_A[5] origin:020-bram 05_204
BRAM.RAMB18E2_U.SRVAL_A[6] origin:020-bram 05_216
BRAM.RAMB18E2_U.SRVAL_A[7] origin:020-bram 05_228
BRAM.RAMB18E2_U.SRVAL_A[8] origin:020-bram 05_138
BRAM.RAMB18E2_U.SRVAL_A[9] origin:020-bram 05_150
BRAM.RAMB18E2_U.SRVAL_A[10] origin:020-bram 05_162
BRAM.RAMB18E2_U.SRVAL_A[11] origin:020-bram 05_174
BRAM.RAMB18E2_U.SRVAL_A[12] origin:020-bram 05_198
BRAM.RAMB18E2_U.SRVAL_A[13] origin:020-bram 05_210
BRAM.RAMB18E2_U.SRVAL_A[14] origin:020-bram 05_222
BRAM.RAMB18E2_U.SRVAL_A[15] origin:020-bram 05_234
BRAM.RAMB18E2_U.SRVAL_A[16] origin:020-bram 05_180
BRAM.RAMB18E2_U.SRVAL_A[17] origin:020-bram 05_186
BRAM.RAMB18E2_U.SRVAL_B[0] origin:020-bram 05_135
BRAM.RAMB18E2_U.SRVAL_B[1] origin:020-bram 05_147
BRAM.RAMB18E2_U.SRVAL_B[2] origin:020-bram 05_159
BRAM.RAMB18E2_U.SRVAL_B[3] origin:020-bram 05_171
BRAM.RAMB18E2_U.SRVAL_B[4] origin:020-bram 05_195
BRAM.RAMB18E2_U.SRVAL_B[5] origin:020-bram 05_207
BRAM.RAMB18E2_U.SRVAL_B[6] origin:020-bram 05_219
BRAM.RAMB18E2_U.SRVAL_B[7] origin:020-bram 05_231
BRAM.RAMB18E2_U.SRVAL_B[8] origin:020-bram 05_141
BRAM.RAMB18E2_U.SRVAL_B[9] origin:020-bram 05_153
BRAM.RAMB18E2_U.SRVAL_B[10] origin:020-bram 05_165
BRAM.RAMB18E2_U.SRVAL_B[11] origin:020-bram 05_177
BRAM.RAMB18E2_U.SRVAL_B[12] origin:020-bram 05_201
BRAM.RAMB18E2_U.SRVAL_B[13] origin:020-bram 05_213
BRAM.RAMB18E2_U.SRVAL_B[14] origin:020-bram 05_225
BRAM.RAMB18E2_U.SRVAL_B[15] origin:020-bram 05_237
BRAM.RAMB18E2_U.SRVAL_B[16] origin:020-bram 05_183
BRAM.RAMB18E2_U.SRVAL_B[17] origin:020-bram 05_189
BRAM.RAMB18E2_U.WRITE_MODE_A.NO_CHANGE origin:020-bram !05_193 05_199
BRAM.RAMB18E2_U.WRITE_MODE_A.READ_FIRST origin:020-bram !05_199 05_193
BRAM.RAMB18E2_U.WRITE_MODE_A.WRITE_FIRST origin:020-bram !05_193 !05_199
BRAM.RAMB18E2_U.WRITE_MODE_B.NO_CHANGE origin:020-bram !05_187 05_190
BRAM.RAMB18E2_U.WRITE_MODE_B.READ_FIRST origin:020-bram !05_190 05_187
BRAM.RAMB18E2_U.WRITE_MODE_B.WRITE_FIRST origin:020-bram !05_187 !05_190
BRAM.RAMB18E2_U.WRITE_WIDTH_B.36 origin:020-bram 05_214
BRAM.RAMB36E2.CLKARDCLKINV.V0 origin:020-bram !04_165 !05_91
BRAM.RAMB36E2.CLKARDCLKINV.V1 origin:020-bram 04_165 05_91
BRAM.RAMB36E2.CLKBWRCLKINV.V0 origin:020-bram !05_163 !05_94
BRAM.RAMB36E2.CLKBWRCLKINV.V1 origin:020-bram 05_163 05_94
BRAM.RAMB36E2.CLOCK_DOMAINS.COMMON origin:020-bram 04_206 04_98
BRAM.RAMB36E2.CLOCK_DOMAINS.INDEPENDENT origin:020-bram !04_206 !04_98
BRAM.RAMB36E2.DOA_REG.V0 origin:020-bram !04_58 !05_184
BRAM.RAMB36E2.DOA_REG.V1 origin:020-bram 04_58 05_184
BRAM.RAMB36E2.EN_ECC_WRITE.FALSE origin:020-bram !05_130
BRAM.RAMB36E2.EN_ECC_WRITE.TRUE origin:020-bram 05_130
BRAM.RAMB36E2.ENADDRENA.FALSE origin:020-bram !04_101 !04_195
BRAM.RAMB36E2.ENADDRENA.TRUE origin:020-bram 04_101 04_195
BRAM.RAMB36E2.ENADDRENB.FALSE origin:020-bram !04_100 !04_193
BRAM.RAMB36E2.ENADDRENB.TRUE origin:020-bram 04_100 04_193
BRAM.RAMB36E2.ENARDENINV.V0 origin:020-bram !04_93 !05_160
BRAM.RAMB36E2.ENARDENINV.V1 origin:020-bram 04_93 05_160
BRAM.RAMB36E2.ENBWRENINV.V0 origin:020-bram !04_92 !05_157
BRAM.RAMB36E2.ENBWRENINV.V1 origin:020-bram 04_92 05_157
BRAM.RAMB36E2.RDADDRCHANGEA.FALSE origin:020-bram !04_191 !04_97
BRAM.RAMB36E2.RDADDRCHANGEA.TRUE origin:020-bram 04_191 04_97
BRAM.RAMB36E2.RDADDRCHANGEB.FALSE origin:020-bram !04_192 !04_96
BRAM.RAMB36E2.RDADDRCHANGEB.TRUE origin:020-bram 04_192 04_96
BRAM.RAMB36E2.READ_WIDTH_A.72 origin:020-bram 05_208 05_49
BRAM.RAMB36E2.RSTRAMARSTRAMINV.V0 origin:020-bram !04_91 !05_154
BRAM.RAMB36E2.RSTRAMARSTRAMINV.V1 origin:020-bram 04_91 05_154
BRAM.RAMB36E2.RSTRAMBINV.V0 origin:020-bram !04_157 !04_90
BRAM.RAMB36E2.RSTRAMBINV.V1 origin:020-bram 04_157 04_90
BRAM.RAMB36E2.RSTREG_PRIORITY_A.REGCE origin:020-bram 04_148 04_83
BRAM.RAMB36E2.RSTREG_PRIORITY_A.RSTREG origin:020-bram !04_148 !04_83
BRAM.RAMB36E2.RSTREG_PRIORITY_B.REGCE origin:020-bram 04_145 04_82
BRAM.RAMB36E2.RSTREG_PRIORITY_B.RSTREG origin:020-bram !04_145 !04_82
BRAM.RAMB36E2.RSTREGARSTREGINV.V0 origin:020-bram !04_85 !05_151
BRAM.RAMB36E2.RSTREGARSTREGINV.V1 origin:020-bram 04_85 05_151
BRAM.RAMB36E2.SLEEP_ASYNC.FALSE origin:020-bram !05_166 !05_88
BRAM.RAMB36E2.SLEEP_ASYNC.TRUE origin:020-bram 05_166 05_88
BRAM.RAMB36E2.WRITE_MODE_A.NO_CHANGE origin:020-bram !05_193 !05_46 05_199 05_43
BRAM.RAMB36E2.WRITE_MODE_A.READ_FIRST origin:020-bram !05_199 !05_43 05_193 05_46
BRAM.RAMB36E2.WRITE_MODE_A.WRITE_FIRST origin:020-bram !05_193 !05_199 !05_43 !05_46
BRAM.RAMB36E2.WRITE_MODE_B.NO_CHANGE origin:020-bram !05_187 !05_52 05_190 05_55
BRAM.RAMB36E2.WRITE_MODE_B.READ_FIRST origin:020-bram !05_190 !05_55 05_187 05_52
BRAM.RAMB36E2.WRITE_MODE_B.WRITE_FIRST origin:020-bram !05_187 !05_190 !05_52 !05_55
BRAM.RAMB36E2.WRITE_WIDTH_B.72 origin:020-bram 05_214 05_64