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segbits_rclk_bram_intf_td_r.origin_info.db
160 lines (160 loc) · 15.5 KB
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segbits_rclk_bram_intf_td_r.origin_info.db
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RCLK_BRAM_INTF_TD_R.PIP.CLK_BUFCE_ROW_FSR_0_CLK_IN.CLK_CMT_DRVR_TRI_ESD_0_CLK_OUT_SCHMITT_B origin:060-rclk-seed !00_34 00_41
RCLK_BRAM_INTF_TD_R.PIP.CLK_BUFCE_ROW_FSR_0_CLK_IN.CLK_CMT_DRVR_TRI_ESD_1_CLK_OUT_SCHMITT_B origin:060-rclk-seed 00_34 00_41
RCLK_BRAM_INTF_TD_R.PIP.CLK_BUFCE_ROW_FSR_2_CLK_IN.CLK_CMT_DRVR_TRI_ESD_4_CLK_OUT_SCHMITT_B origin:060-rclk-seed !01_34 01_41
RCLK_BRAM_INTF_TD_R.PIP.CLK_BUFCE_ROW_FSR_2_CLK_IN.CLK_CMT_DRVR_TRI_ESD_5_CLK_OUT_SCHMITT_B origin:060-rclk-seed 01_34 01_41
RCLK_BRAM_INTF_TD_R.PIP.CLK_BUFCE_ROW_FSR_4_CLK_IN.CLK_CMT_DRVR_TRI_ESD_8_CLK_OUT_SCHMITT_B origin:060-rclk-seed !02_34 02_41
RCLK_BRAM_INTF_TD_R.PIP.CLK_BUFCE_ROW_FSR_4_CLK_IN.CLK_CMT_DRVR_TRI_ESD_9_CLK_OUT_SCHMITT_B origin:060-rclk-seed 02_34 02_41
RCLK_BRAM_INTF_TD_R.PIP.CLK_BUFCE_ROW_FSR_6_CLK_IN.CLK_CMT_DRVR_TRI_ESD_12_CLK_OUT_SCHMITT_B origin:060-rclk-seed !03_34 03_41
RCLK_BRAM_INTF_TD_R.PIP.CLK_BUFCE_ROW_FSR_6_CLK_IN.CLK_CMT_DRVR_TRI_ESD_13_CLK_OUT_SCHMITT_B origin:060-rclk-seed 03_34 03_41
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_2TO1_1_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_2_CLK_OUT_SCHMITT_B origin:060-rclk-seed !00_33 00_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_2TO1_1_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_3_CLK_OUT_SCHMITT_B origin:060-rclk-seed 00_33 00_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_2TO1_3_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_6_CLK_OUT_SCHMITT_B origin:060-rclk-seed !01_33 01_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_2TO1_3_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_7_CLK_OUT_SCHMITT_B origin:060-rclk-seed 01_33 01_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_2TO1_5_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_10_CLK_OUT_SCHMITT_B origin:060-rclk-seed !02_33 02_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_2TO1_5_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_11_CLK_OUT_SCHMITT_B origin:060-rclk-seed 02_33 02_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_2TO1_7_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_14_CLK_OUT_SCHMITT_B origin:060-rclk-seed !03_33 03_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_2TO1_7_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_15_CLK_OUT_SCHMITT_B origin:060-rclk-seed 03_33 03_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_0_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_1_CLK_OUT_SCHMITT_B origin:060-rclk-seed !00_31 !00_32 00_24
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_0_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_3_CLK_OUT_SCHMITT_B origin:060-rclk-seed !00_31 00_24 00_32
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_0_CLK_OUT.CLK_HROUTE_CORE_OPT0 origin:060-rclk-seed !00_32 00_24 00_31
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_1_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_0_CLK_OUT_SCHMITT_B origin:060-rclk-seed !00_29 !00_30 00_23
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_1_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_2_CLK_OUT_SCHMITT_B origin:060-rclk-seed !00_29 00_23 00_30
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_1_CLK_OUT.CLK_HROUTE_CORE_OPT0 origin:060-rclk-seed !00_30 00_23 00_29
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_2_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_3_CLK_OUT_SCHMITT_B origin:060-rclk-seed !00_27 00_22
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_2_CLK_OUT.CLK_HROUTE_CORE_OPT0 origin:060-rclk-seed 00_22 00_27
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_2_CLK_OUT.CLK_TEST_BUF_SITE_1_CLK_OUT origin:060-rclk-seed !00_22 !00_27
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_3_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_2_CLK_OUT_SCHMITT_B origin:060-rclk-seed !00_25 00_21
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_3_CLK_OUT.CLK_HROUTE_CORE_OPT0 origin:060-rclk-seed 00_21 00_25
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_3_CLK_OUT.CLK_TEST_BUF_SITE_1_CLK_OUT origin:060-rclk-seed !00_21 !00_25
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_4_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_5_CLK_OUT_SCHMITT_B origin:060-rclk-seed !01_31 !01_32 01_24
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_4_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_7_CLK_OUT_SCHMITT_B origin:060-rclk-seed !01_31 01_24 01_32
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_4_CLK_OUT.CLK_HROUTE_CORE_OPT1 origin:060-rclk-seed !01_32 01_24 01_31
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_5_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_4_CLK_OUT_SCHMITT_B origin:060-rclk-seed !01_29 !01_30 01_23
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_5_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_6_CLK_OUT_SCHMITT_B origin:060-rclk-seed !01_29 01_23 01_30
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_5_CLK_OUT.CLK_HROUTE_CORE_OPT1 origin:060-rclk-seed !01_30 01_23 01_29
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_6_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_7_CLK_OUT_SCHMITT_B origin:060-rclk-seed !01_27 01_22
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_6_CLK_OUT.CLK_HROUTE_CORE_OPT1 origin:060-rclk-seed 01_22 01_27
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_6_CLK_OUT.CLK_TEST_BUF_SITE_3_CLK_OUT origin:060-rclk-seed !01_22 !01_27
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_7_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_6_CLK_OUT_SCHMITT_B origin:060-rclk-seed !01_25 01_21
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_7_CLK_OUT.CLK_HROUTE_CORE_OPT1 origin:060-rclk-seed 01_21 01_25
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_7_CLK_OUT.CLK_TEST_BUF_SITE_3_CLK_OUT origin:060-rclk-seed !01_21 !01_25
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_8_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_9_CLK_OUT_SCHMITT_B origin:060-rclk-seed !02_31 !02_32 02_24
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_8_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_11_CLK_OUT_SCHMITT_B origin:060-rclk-seed !02_31 02_24 02_32
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_8_CLK_OUT.CLK_HROUTE_CORE_OPT2 origin:060-rclk-seed !02_32 02_24 02_31
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_9_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_8_CLK_OUT_SCHMITT_B origin:060-rclk-seed !02_29 !02_30 02_23
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_9_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_10_CLK_OUT_SCHMITT_B origin:060-rclk-seed !02_29 02_23 02_30
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_9_CLK_OUT.CLK_HROUTE_CORE_OPT2 origin:060-rclk-seed !02_30 02_23 02_29
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_10_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_11_CLK_OUT_SCHMITT_B origin:060-rclk-seed !02_27 02_22
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_10_CLK_OUT.CLK_HROUTE_CORE_OPT2 origin:060-rclk-seed 02_22 02_27
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_10_CLK_OUT.CLK_TEST_BUF_SITE_5_CLK_OUT origin:060-rclk-seed !02_22 !02_27
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_11_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_10_CLK_OUT_SCHMITT_B origin:060-rclk-seed !02_25 02_21
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_11_CLK_OUT.CLK_HROUTE_CORE_OPT2 origin:060-rclk-seed 02_21 02_25
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_11_CLK_OUT.CLK_TEST_BUF_SITE_5_CLK_OUT origin:060-rclk-seed !02_21 !02_25
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_12_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_13_CLK_OUT_SCHMITT_B origin:060-rclk-seed !03_31 !03_32 03_24
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_12_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_15_CLK_OUT_SCHMITT_B origin:060-rclk-seed !03_31 03_24 03_32
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_12_CLK_OUT.CLK_HROUTE_CORE_OPT3 origin:060-rclk-seed !03_32 03_24 03_31
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_13_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_12_CLK_OUT_SCHMITT_B origin:060-rclk-seed !03_29 !03_30 03_23
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_13_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_14_CLK_OUT_SCHMITT_B origin:060-rclk-seed !03_29 03_23 03_30
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_13_CLK_OUT.CLK_HROUTE_CORE_OPT3 origin:060-rclk-seed !03_30 03_23 03_29
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_14_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_15_CLK_OUT_SCHMITT_B origin:060-rclk-seed !03_27 03_22
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_14_CLK_OUT.CLK_HROUTE_CORE_OPT3 origin:060-rclk-seed 03_22 03_27
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_14_CLK_OUT.CLK_TEST_BUF_SITE_7_CLK_OUT origin:060-rclk-seed !03_22 !03_27
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_15_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_14_CLK_OUT_SCHMITT_B origin:060-rclk-seed !03_25 03_21
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_15_CLK_OUT.CLK_HROUTE_CORE_OPT3 origin:060-rclk-seed 03_21 03_25
RCLK_BRAM_INTF_TD_R.PIP.CLK_CMT_MUX_3TO1_15_CLK_OUT.CLK_TEST_BUF_SITE_7_CLK_OUT origin:060-rclk-seed !03_21 !03_25
RCLK_BRAM_INTF_TD_R.PIP.CLK_HROUTE_CORE_OPT0.CLK_CMT_MUX_2TO1_1_CLK_OUT origin:060-rclk-seed 00_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_HROUTE_CORE_OPT0.VCC_WIRE origin:060-rclk-seed !00_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_HROUTE_CORE_OPT1.CLK_CMT_MUX_2TO1_3_CLK_OUT origin:060-rclk-seed 01_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_HROUTE_CORE_OPT1.VCC_WIRE origin:060-rclk-seed !01_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_HROUTE_CORE_OPT2.CLK_CMT_MUX_2TO1_5_CLK_OUT origin:060-rclk-seed 02_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_HROUTE_CORE_OPT2.VCC_WIRE origin:060-rclk-seed !02_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_HROUTE_CORE_OPT3.CLK_CMT_MUX_2TO1_7_CLK_OUT origin:060-rclk-seed 03_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_HROUTE_CORE_OPT3.VCC_WIRE origin:060-rclk-seed !03_46
RCLK_BRAM_INTF_TD_R.PIP.CLK_TEST_BUF_SITE_1_CLK_IN.CLK_BUFCE_ROW_FSR_0_CLK_OUT origin:060-rclk-seed 00_47
RCLK_BRAM_INTF_TD_R.PIP.CLK_TEST_BUF_SITE_1_CLK_IN.VCC_WIRE origin:060-rclk-seed !00_47
RCLK_BRAM_INTF_TD_R.PIP.CLK_TEST_BUF_SITE_3_CLK_IN.CLK_BUFCE_ROW_FSR_2_CLK_OUT origin:060-rclk-seed 01_47
RCLK_BRAM_INTF_TD_R.PIP.CLK_TEST_BUF_SITE_3_CLK_IN.VCC_WIRE origin:060-rclk-seed !01_47
RCLK_BRAM_INTF_TD_R.PIP.CLK_TEST_BUF_SITE_5_CLK_IN.CLK_BUFCE_ROW_FSR_4_CLK_OUT origin:060-rclk-seed 02_47
RCLK_BRAM_INTF_TD_R.PIP.CLK_TEST_BUF_SITE_5_CLK_IN.VCC_WIRE origin:060-rclk-seed !02_47
RCLK_BRAM_INTF_TD_R.PIP.CLK_TEST_BUF_SITE_7_CLK_IN.CLK_BUFCE_ROW_FSR_6_CLK_OUT origin:060-rclk-seed 03_47
RCLK_BRAM_INTF_TD_R.PIP.CLK_TEST_BUF_SITE_7_CLK_IN.VCC_WIRE origin:060-rclk-seed !03_47
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_BOT0.CLK_CMT_MUX_3TO1_0_CLK_OUT origin:060-rclk-seed 00_24
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_BOT0.VCC_WIRE origin:060-rclk-seed !00_24
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_BOT1.CLK_CMT_MUX_3TO1_4_CLK_OUT origin:060-rclk-seed 01_24
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_BOT1.VCC_WIRE origin:060-rclk-seed !01_24
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_BOT2.CLK_CMT_MUX_3TO1_8_CLK_OUT origin:060-rclk-seed 02_24
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_BOT2.VCC_WIRE origin:060-rclk-seed !02_24
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_BOT3.CLK_CMT_MUX_3TO1_12_CLK_OUT origin:060-rclk-seed 03_24
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_BOT3.VCC_WIRE origin:060-rclk-seed !03_24
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_TOP0.CLK_CMT_MUX_3TO1_1_CLK_OUT origin:060-rclk-seed 00_23
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_TOP0.VCC_WIRE origin:060-rclk-seed !00_23
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_TOP1.CLK_CMT_MUX_3TO1_5_CLK_OUT origin:060-rclk-seed 01_23
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_TOP1.VCC_WIRE origin:060-rclk-seed !01_23
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_TOP2.CLK_CMT_MUX_3TO1_9_CLK_OUT origin:060-rclk-seed 02_23
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_TOP2.VCC_WIRE origin:060-rclk-seed !02_23
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_TOP3.CLK_CMT_MUX_3TO1_13_CLK_OUT origin:060-rclk-seed 03_23
RCLK_BRAM_INTF_TD_R.PIP.CLK_VDISTR_TOP3.VCC_WIRE origin:060-rclk-seed !03_23
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_BOT0.CLK_CMT_MUX_3TO1_2_CLK_OUT origin:060-rclk-seed 00_22
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_BOT0.VCC_WIRE origin:060-rclk-seed !00_22
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_BOT1.CLK_CMT_MUX_3TO1_6_CLK_OUT origin:060-rclk-seed 01_22
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_BOT1.VCC_WIRE origin:060-rclk-seed !01_22
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_BOT2.CLK_CMT_MUX_3TO1_10_CLK_OUT origin:060-rclk-seed 02_22
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_BOT2.VCC_WIRE origin:060-rclk-seed !02_22
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_BOT3.CLK_CMT_MUX_3TO1_14_CLK_OUT origin:060-rclk-seed 03_22
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_BOT3.VCC_WIRE origin:060-rclk-seed !03_22
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_TOP0.CLK_CMT_MUX_3TO1_3_CLK_OUT origin:060-rclk-seed 00_21
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_TOP0.VCC_WIRE origin:060-rclk-seed !00_21
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_TOP1.CLK_CMT_MUX_3TO1_7_CLK_OUT origin:060-rclk-seed 01_21
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_TOP1.VCC_WIRE origin:060-rclk-seed !01_21
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_TOP2.CLK_CMT_MUX_3TO1_11_CLK_OUT origin:060-rclk-seed 02_21
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_TOP2.VCC_WIRE origin:060-rclk-seed !02_21
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_TOP3.CLK_CMT_MUX_3TO1_15_CLK_OUT origin:060-rclk-seed 03_21
RCLK_BRAM_INTF_TD_R.PIP.CLK_VROUTE_TOP3.VCC_WIRE origin:060-rclk-seed !03_21
RCLK_BRAM_INTF_TD_R.WIRE.CLK_HROUTE_CORE_OPT0.USED.V0 origin:060-rclk-seed !00_44
RCLK_BRAM_INTF_TD_R.WIRE.CLK_HROUTE_CORE_OPT0.USED.V1 origin:060-rclk-seed 00_44
RCLK_BRAM_INTF_TD_R.WIRE.CLK_HROUTE_CORE_OPT1.USED.V0 origin:060-rclk-seed !01_44
RCLK_BRAM_INTF_TD_R.WIRE.CLK_HROUTE_CORE_OPT1.USED.V1 origin:060-rclk-seed 01_44
RCLK_BRAM_INTF_TD_R.WIRE.CLK_HROUTE_CORE_OPT2.USED.V0 origin:060-rclk-seed !02_44
RCLK_BRAM_INTF_TD_R.WIRE.CLK_HROUTE_CORE_OPT2.USED.V1 origin:060-rclk-seed 02_44
RCLK_BRAM_INTF_TD_R.WIRE.CLK_HROUTE_CORE_OPT3.USED.V0 origin:060-rclk-seed !03_44
RCLK_BRAM_INTF_TD_R.WIRE.CLK_HROUTE_CORE_OPT3.USED.V1 origin:060-rclk-seed 03_44
RCLK_BRAM_INTF_TD_R.WIRE.CLK_TEST_BUF_SITE_1_CLK_IN.USED.V0 origin:060-rclk-seed !00_45
RCLK_BRAM_INTF_TD_R.WIRE.CLK_TEST_BUF_SITE_1_CLK_IN.USED.V1 origin:060-rclk-seed 00_45
RCLK_BRAM_INTF_TD_R.WIRE.CLK_TEST_BUF_SITE_3_CLK_IN.USED.V0 origin:060-rclk-seed !01_45
RCLK_BRAM_INTF_TD_R.WIRE.CLK_TEST_BUF_SITE_3_CLK_IN.USED.V1 origin:060-rclk-seed 01_45
RCLK_BRAM_INTF_TD_R.WIRE.CLK_TEST_BUF_SITE_5_CLK_IN.USED.V0 origin:060-rclk-seed !02_45
RCLK_BRAM_INTF_TD_R.WIRE.CLK_TEST_BUF_SITE_5_CLK_IN.USED.V1 origin:060-rclk-seed 02_45
RCLK_BRAM_INTF_TD_R.WIRE.CLK_TEST_BUF_SITE_7_CLK_IN.USED.V0 origin:060-rclk-seed !03_45
RCLK_BRAM_INTF_TD_R.WIRE.CLK_TEST_BUF_SITE_7_CLK_IN.USED.V1 origin:060-rclk-seed 03_45
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_BOT0.USED.V0 origin:060-rclk-seed !00_20
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_BOT0.USED.V1 origin:060-rclk-seed 00_20
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_BOT1.USED.V0 origin:060-rclk-seed !01_20
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_BOT1.USED.V1 origin:060-rclk-seed 01_20
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_BOT2.USED.V0 origin:060-rclk-seed !02_20
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_BOT2.USED.V1 origin:060-rclk-seed 02_20
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_BOT3.USED.V0 origin:060-rclk-seed !03_20
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_BOT3.USED.V1 origin:060-rclk-seed 03_20
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_TOP0.USED.V0 origin:060-rclk-seed !00_19
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_TOP0.USED.V1 origin:060-rclk-seed 00_19
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_TOP1.USED.V0 origin:060-rclk-seed !01_19
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_TOP1.USED.V1 origin:060-rclk-seed 01_19
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_TOP2.USED.V0 origin:060-rclk-seed !02_19
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_TOP2.USED.V1 origin:060-rclk-seed 02_19
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_TOP3.USED.V0 origin:060-rclk-seed !03_19
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VDISTR_TOP3.USED.V1 origin:060-rclk-seed 03_19
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_BOT0.USED.V0 origin:060-rclk-seed !00_18
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_BOT0.USED.V1 origin:060-rclk-seed 00_18
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_BOT1.USED.V0 origin:060-rclk-seed !01_18
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_BOT1.USED.V1 origin:060-rclk-seed 01_18
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_BOT2.USED.V0 origin:060-rclk-seed !02_18
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_BOT2.USED.V1 origin:060-rclk-seed 02_18
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_BOT3.USED.V0 origin:060-rclk-seed !03_18
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_BOT3.USED.V1 origin:060-rclk-seed 03_18
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_TOP0.USED.V0 origin:060-rclk-seed !00_17
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_TOP0.USED.V1 origin:060-rclk-seed 00_17
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_TOP1.USED.V0 origin:060-rclk-seed !01_17
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_TOP1.USED.V1 origin:060-rclk-seed 01_17
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_TOP2.USED.V0 origin:060-rclk-seed !02_17
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_TOP2.USED.V1 origin:060-rclk-seed 02_17
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_TOP3.USED.V0 origin:060-rclk-seed !03_17
RCLK_BRAM_INTF_TD_R.WIRE.CLK_VROUTE_TOP3.USED.V1 origin:060-rclk-seed 03_17