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segbits_rclk_dsp_intf_l.origin_info.db
80 lines (80 loc) · 7.41 KB
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segbits_rclk_dsp_intf_l.origin_info.db
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RCLK_DSP_INTF_L.PIP.CLK_BUFCE_ROW_FSR_0_CLK_IN.CLK_CMT_DRVR_TRI_ESD_0_CLK_OUT_SCHMITT_B origin:060-rclk-seed !04_34 04_41
RCLK_DSP_INTF_L.PIP.CLK_BUFCE_ROW_FSR_0_CLK_IN.CLK_CMT_DRVR_TRI_ESD_1_CLK_OUT_SCHMITT_B origin:060-rclk-seed 04_34 04_41
RCLK_DSP_INTF_L.PIP.CLK_BUFCE_ROW_FSR_2_CLK_IN.CLK_CMT_DRVR_TRI_ESD_4_CLK_OUT_SCHMITT_B origin:060-rclk-seed !05_34 05_41
RCLK_DSP_INTF_L.PIP.CLK_BUFCE_ROW_FSR_2_CLK_IN.CLK_CMT_DRVR_TRI_ESD_5_CLK_OUT_SCHMITT_B origin:060-rclk-seed 05_34 05_41
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_2TO1_1_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_2_CLK_OUT_SCHMITT_B origin:060-rclk-seed !04_33 04_46
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_2TO1_1_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_3_CLK_OUT_SCHMITT_B origin:060-rclk-seed 04_33 04_46
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_2TO1_3_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_6_CLK_OUT_SCHMITT_B origin:060-rclk-seed !05_33 05_46
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_2TO1_3_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_7_CLK_OUT_SCHMITT_B origin:060-rclk-seed 05_33 05_46
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_0_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_1_CLK_OUT_SCHMITT_B origin:060-rclk-seed !04_31 !04_32 04_24
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_0_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_3_CLK_OUT_SCHMITT_B origin:060-rclk-seed !04_31 04_24 04_32
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_0_CLK_OUT.CLK_HROUTE_CORE_OPT0 origin:060-rclk-seed !04_32 04_24 04_31
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_1_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_0_CLK_OUT_SCHMITT_B origin:060-rclk-seed !04_29 !04_30 04_23
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_1_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_2_CLK_OUT_SCHMITT_B origin:060-rclk-seed !04_29 04_23 04_30
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_1_CLK_OUT.CLK_HROUTE_CORE_OPT0 origin:060-rclk-seed !04_30 04_23 04_29
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_2_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_3_CLK_OUT_SCHMITT_B origin:060-rclk-seed !04_27 04_22
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_2_CLK_OUT.CLK_HROUTE_CORE_OPT0 origin:060-rclk-seed 04_22 04_27
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_2_CLK_OUT.CLK_TEST_BUF_SITE_1_CLK_OUT origin:060-rclk-seed !04_22 !04_27
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_3_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_2_CLK_OUT_SCHMITT_B origin:060-rclk-seed !04_25 04_21
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_3_CLK_OUT.CLK_HROUTE_CORE_OPT0 origin:060-rclk-seed 04_21 04_25
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_3_CLK_OUT.CLK_TEST_BUF_SITE_1_CLK_OUT origin:060-rclk-seed !04_21 !04_25
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_4_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_5_CLK_OUT_SCHMITT_B origin:060-rclk-seed !05_31 !05_32 05_24
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_4_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_7_CLK_OUT_SCHMITT_B origin:060-rclk-seed !05_31 05_24 05_32
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_4_CLK_OUT.CLK_HROUTE_CORE_OPT1 origin:060-rclk-seed !05_32 05_24 05_31
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_5_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_4_CLK_OUT_SCHMITT_B origin:060-rclk-seed !05_29 !05_30 05_23
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_5_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_6_CLK_OUT_SCHMITT_B origin:060-rclk-seed !05_29 05_23 05_30
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_5_CLK_OUT.CLK_HROUTE_CORE_OPT1 origin:060-rclk-seed !05_30 05_23 05_29
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_6_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_7_CLK_OUT_SCHMITT_B origin:060-rclk-seed !05_27 05_22
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_6_CLK_OUT.CLK_HROUTE_CORE_OPT1 origin:060-rclk-seed 05_22 05_27
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_6_CLK_OUT.CLK_TEST_BUF_SITE_3_CLK_OUT origin:060-rclk-seed !05_22 !05_27
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_7_CLK_OUT.CLK_CMT_DRVR_TRI_ESD_6_CLK_OUT_SCHMITT_B origin:060-rclk-seed !05_25 05_21
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_7_CLK_OUT.CLK_HROUTE_CORE_OPT1 origin:060-rclk-seed 05_21 05_25
RCLK_DSP_INTF_L.PIP.CLK_CMT_MUX_3TO1_7_CLK_OUT.CLK_TEST_BUF_SITE_3_CLK_OUT origin:060-rclk-seed !05_21 !05_25
RCLK_DSP_INTF_L.PIP.CLK_HROUTE_CORE_OPT0.CLK_CMT_MUX_2TO1_1_CLK_OUT origin:060-rclk-seed 04_46
RCLK_DSP_INTF_L.PIP.CLK_HROUTE_CORE_OPT0.VCC_WIRE origin:060-rclk-seed !04_46
RCLK_DSP_INTF_L.PIP.CLK_HROUTE_CORE_OPT1.CLK_CMT_MUX_2TO1_3_CLK_OUT origin:060-rclk-seed 05_46
RCLK_DSP_INTF_L.PIP.CLK_HROUTE_CORE_OPT1.VCC_WIRE origin:060-rclk-seed !05_46
RCLK_DSP_INTF_L.PIP.CLK_TEST_BUF_SITE_1_CLK_IN.CLK_BUFCE_ROW_FSR_0_CLK_OUT origin:060-rclk-seed 04_47
RCLK_DSP_INTF_L.PIP.CLK_TEST_BUF_SITE_1_CLK_IN.VCC_WIRE origin:060-rclk-seed !04_47
RCLK_DSP_INTF_L.PIP.CLK_TEST_BUF_SITE_3_CLK_IN.CLK_BUFCE_ROW_FSR_2_CLK_OUT origin:060-rclk-seed 05_47
RCLK_DSP_INTF_L.PIP.CLK_TEST_BUF_SITE_3_CLK_IN.VCC_WIRE origin:060-rclk-seed !05_47
RCLK_DSP_INTF_L.PIP.CLK_VDISTR_BOT0.CLK_CMT_MUX_3TO1_0_CLK_OUT origin:060-rclk-seed 04_24
RCLK_DSP_INTF_L.PIP.CLK_VDISTR_BOT0.VCC_WIRE origin:060-rclk-seed !04_24
RCLK_DSP_INTF_L.PIP.CLK_VDISTR_BOT1.CLK_CMT_MUX_3TO1_4_CLK_OUT origin:060-rclk-seed 05_24
RCLK_DSP_INTF_L.PIP.CLK_VDISTR_BOT1.VCC_WIRE origin:060-rclk-seed !05_24
RCLK_DSP_INTF_L.PIP.CLK_VDISTR_TOP0.CLK_CMT_MUX_3TO1_1_CLK_OUT origin:060-rclk-seed 04_23
RCLK_DSP_INTF_L.PIP.CLK_VDISTR_TOP0.VCC_WIRE origin:060-rclk-seed !04_23
RCLK_DSP_INTF_L.PIP.CLK_VDISTR_TOP1.CLK_CMT_MUX_3TO1_5_CLK_OUT origin:060-rclk-seed 05_23
RCLK_DSP_INTF_L.PIP.CLK_VDISTR_TOP1.VCC_WIRE origin:060-rclk-seed !05_23
RCLK_DSP_INTF_L.PIP.CLK_VROUTE_BOT0.CLK_CMT_MUX_3TO1_2_CLK_OUT origin:060-rclk-seed 04_22
RCLK_DSP_INTF_L.PIP.CLK_VROUTE_BOT0.VCC_WIRE origin:060-rclk-seed !04_22
RCLK_DSP_INTF_L.PIP.CLK_VROUTE_BOT1.CLK_CMT_MUX_3TO1_6_CLK_OUT origin:060-rclk-seed 05_22
RCLK_DSP_INTF_L.PIP.CLK_VROUTE_BOT1.VCC_WIRE origin:060-rclk-seed !05_22
RCLK_DSP_INTF_L.PIP.CLK_VROUTE_TOP0.CLK_CMT_MUX_3TO1_3_CLK_OUT origin:060-rclk-seed 04_21
RCLK_DSP_INTF_L.PIP.CLK_VROUTE_TOP0.VCC_WIRE origin:060-rclk-seed !04_21
RCLK_DSP_INTF_L.PIP.CLK_VROUTE_TOP1.CLK_CMT_MUX_3TO1_7_CLK_OUT origin:060-rclk-seed 05_21
RCLK_DSP_INTF_L.PIP.CLK_VROUTE_TOP1.VCC_WIRE origin:060-rclk-seed !05_21
RCLK_DSP_INTF_L.WIRE.CLK_HROUTE_CORE_OPT0.USED.V0 origin:060-rclk-seed !04_44
RCLK_DSP_INTF_L.WIRE.CLK_HROUTE_CORE_OPT0.USED.V1 origin:060-rclk-seed 04_44
RCLK_DSP_INTF_L.WIRE.CLK_HROUTE_CORE_OPT1.USED.V0 origin:060-rclk-seed !05_44
RCLK_DSP_INTF_L.WIRE.CLK_HROUTE_CORE_OPT1.USED.V1 origin:060-rclk-seed 05_44
RCLK_DSP_INTF_L.WIRE.CLK_TEST_BUF_SITE_1_CLK_IN.USED.V0 origin:060-rclk-seed !04_45
RCLK_DSP_INTF_L.WIRE.CLK_TEST_BUF_SITE_1_CLK_IN.USED.V1 origin:060-rclk-seed 04_45
RCLK_DSP_INTF_L.WIRE.CLK_TEST_BUF_SITE_3_CLK_IN.USED.V0 origin:060-rclk-seed !05_45
RCLK_DSP_INTF_L.WIRE.CLK_TEST_BUF_SITE_3_CLK_IN.USED.V1 origin:060-rclk-seed 05_45
RCLK_DSP_INTF_L.WIRE.CLK_VDISTR_BOT0.USED.V0 origin:060-rclk-seed !04_20
RCLK_DSP_INTF_L.WIRE.CLK_VDISTR_BOT0.USED.V1 origin:060-rclk-seed 04_20
RCLK_DSP_INTF_L.WIRE.CLK_VDISTR_BOT1.USED.V0 origin:060-rclk-seed !05_20
RCLK_DSP_INTF_L.WIRE.CLK_VDISTR_BOT1.USED.V1 origin:060-rclk-seed 05_20
RCLK_DSP_INTF_L.WIRE.CLK_VDISTR_TOP0.USED.V0 origin:060-rclk-seed !04_19
RCLK_DSP_INTF_L.WIRE.CLK_VDISTR_TOP0.USED.V1 origin:060-rclk-seed 04_19
RCLK_DSP_INTF_L.WIRE.CLK_VDISTR_TOP1.USED.V0 origin:060-rclk-seed !05_19
RCLK_DSP_INTF_L.WIRE.CLK_VDISTR_TOP1.USED.V1 origin:060-rclk-seed 05_19
RCLK_DSP_INTF_L.WIRE.CLK_VROUTE_BOT0.USED.V0 origin:060-rclk-seed !04_18
RCLK_DSP_INTF_L.WIRE.CLK_VROUTE_BOT0.USED.V1 origin:060-rclk-seed 04_18
RCLK_DSP_INTF_L.WIRE.CLK_VROUTE_BOT1.USED.V0 origin:060-rclk-seed !05_18
RCLK_DSP_INTF_L.WIRE.CLK_VROUTE_BOT1.USED.V1 origin:060-rclk-seed 05_18
RCLK_DSP_INTF_L.WIRE.CLK_VROUTE_TOP0.USED.V0 origin:060-rclk-seed !04_17
RCLK_DSP_INTF_L.WIRE.CLK_VROUTE_TOP0.USED.V1 origin:060-rclk-seed 04_17
RCLK_DSP_INTF_L.WIRE.CLK_VROUTE_TOP1.USED.V0 origin:060-rclk-seed !05_17
RCLK_DSP_INTF_L.WIRE.CLK_VROUTE_TOP1.USED.V1 origin:060-rclk-seed 05_17