diff --git a/docs/architecture/index.rst b/docs/architecture/index.rst
deleted file mode 100644
index 9701bdf09..000000000
--- a/docs/architecture/index.rst
+++ /dev/null
@@ -1,16 +0,0 @@
-============================
-Xilinx 7-series Architecture
-============================
-
-.. toctree::
-   :maxdepth: 1
-
-   overview
-   configuration
-   bitstream_format
-   interconnect
-   dram_configuration
-   glossary
-   reference
-   code_of_conduct
-   updating_the_docs
diff --git a/docs/db_dev_process/index.rst b/docs/db_dev_process/index.rst
deleted file mode 100644
index 7b78fa073..000000000
--- a/docs/db_dev_process/index.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-============================
-Database Development Process
-============================
-
-.. toctree::
-   :maxdepth: 1
-
-   readme
-   contributing
-   new_fuzzer
-   fuzzers/index
-   minitests/index
-   parts
-   newpart
-
diff --git a/docs/index.rst b/docs/index.rst
index 192e93bb8..9efb7baaf 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -25,13 +25,27 @@ to develop a free and open Verilog to bitstream toolchain for these devices.
    :maxdepth: 2
    :caption: Xilinx 7-Series Architecture
 
-   architecture/index
+   architecture/overview
+   architecture/configuration
+   architecture/bitstream_format
+   architecture/interconnect
+   architecture/dram_configuration
+   architecture/glossary
+   architecture/reference
+   architecture/code_of_conduct
+   architecture/updating_the_docs
 
 .. toctree::
    :maxdepth: 2
    :caption: Database Development Process
 
-   db_dev_process/index
+   db_dev_process/readme
+   db_dev_process/contributing
+   db_dev_process/new_fuzzer
+   db_dev_process/fuzzers/index
+   db_dev_process/minitests/index
+   db_dev_process/parts
+   db_dev_process/newpart
 
 .. toctree::
    :maxdepth: 2