kiwi.config

// Copyright (c) 2014-2024 John Seamons, ZL4VO/KF6VO

				// configuration
	
        #if USE_OTHER
                DEFc    RX_CFG          0
        #else
                // value set here used when building using Vivado UI
                DEFc    RX_CFG          4
                //DEFc    RX_CFG          1
                //DEFc    RX_CFG          8
                //DEFc    RX_CFG          3
                //DEFc    RX_CFG          14

                DEFp	NUM_CMDS_OTHER  0
        #endif

            #if RX_CFG
				DEFh	USE_SDR	        1
				DEFh    USE_24K_WIDE    0
				DEFh	USE_GPS	        1
			#else
				DEFh	USE_SDR	        0
				DEFh	USE_GPS	        0
			#endif


; ============================================================================

				// options

				DEFh    ARTIX_7A35      1
				DEFh    ZYNQ_7007       0
				
				DEFp	FPGA_VER		4'd1
				DEFp	FW_ID			0x5000

				DEFp	ADC_BITS		14
				DEFp	DEFAULT_NSYNC	2       // bits in synchronizers

            #if RX_CFG == 1
                DEFh    USE_WB          1
                DEFh    USE_RX_CICF     0
			#else
                DEFh    USE_WB          0
                DEFh    USE_RX_CICF     1
			#endif
			
            #if RX_CFG == 14
                DEFh    USE_OPTIONAL    1
			#else
                DEFh    USE_OPTIONAL    1
			#endif
			
			#if USE_OPTIONAL
                DEFh	USE_LOGGER		1
				DEFh	USE_CPU_CTR		1
				DEFh	USE_GEN			1       // needed by KiwiSDR 2+ self test
			#endif

				DEFh	USE_DEBUG		1
                DEFh	USE_RX_SEQ		0		// due to out-of-brams w/ rx4 config
				
				DEFh	USE_VIVADO		1
				DEFh	SERIES_7        1
				DEFh	SPI_PUMP_CHECK	0
				DEFh	STACK_CHECK		0
				DEFh	SND_SEQ_CHECK	0
				DEFh    SND_TIMING_CK   0
				
				DEFp    FPGA_ID_RX4_WF4     4'd0
				DEFp    FPGA_ID_RX8_WF2     4'd1
				DEFp    FPGA_ID_RX3_WF3     4'd2
				DEFp    FPGA_ID_RX14_WF0    4'd3
				DEFp    FPGA_ID_WB          4'd4
				DEFp    FPGA_ID_OTHER       4'd8

				DEFp    NUM_CMDS_BASE   13

			#if USE_SDR
				DEFp    NUM_CMDS_SDR    14
			#else
				DEFp    NUM_CMDS_SDR    0
			#endif

			#if USE_GPS
				DEFp	NUM_CMDS_GPS    17
			#else
				DEFp	NUM_CMDS_GPS    0
			#endif

                DEFp	NUM_CMDS		NUM_CMDS_BASE + NUM_CMDS_SDR + NUM_CMDS_GPS + NUM_CMDS_OTHER


; ============================================================================

				// SPI
				DEFh	SPI_32			1
				DEFp    SPIBUF_W        2048        // limited by use of single 2K x 16 (36 kb) BRAM in host.v
				DEFp    SPIBUF_B        SPIBUF_W * 2
				DEFp    SPIBUF_BMAX     SPIBUF_W - 1 * 2    // can't use last word for some reason


; ============================================================================

				// rx
            DEFp        SND_RATE_WB     12000

				// 12k/20.25k sample rates chosen to be integer multiples of WSPR 375 Hz sample rate
			#if USE_RX_CICF
				DEFp	RX1_WB_DECIM    926
				DEFp	RX2_WB_DECIM    3			// 926*3 = 2778, 66.6666M/2778 = 23998.056 Hz (-1.944) /2 = 11999.028 (-0.972)
				
				DEFp	RX1_WIDE_DECIM  823
				DEFp	RX2_WIDE_DECIM  2			// 823*2 = 1646, 66.6666M/1646 = 40502.187 Hz (+2.187) /2 = 20251.094 (+1.094)

				DEFp	RX1_STD_DECIM   926
				DEFp	RX2_STD_DECIM   3			// 926*3 = 2778, 66.6666M/2778 = 23998.056 Hz (-1.944) /2 = 11999.028 (-0.972)
				
				DEFh    CICF_DECIM_BY_2 2
			#else
			
			 #if USE_WB

			  #if 1
				DEFp	RX1_WB_DECIM    926         // 926*6 = 5556
				DEFp	RX2_WB_DECIM    6
				DEFp    V_WB_BUF_CHANS  0 + 6
				DEFp    WB_RATE         SND_RATE_WB * 6     // 72 kHz
			  #endif

			  #if 0
				DEFp	RX1_WB_DECIM    617         // 617*9 = 5553
				DEFp	RX2_WB_DECIM    9
				DEFp    V_WB_BUF_CHANS  0 + 9
				DEFp    WB_RATE         SND_RATE_WB * 9     // 108 kHz
			  #endif

			  #if 0
				DEFp	RX1_WB_DECIM    463         // 463*12 = 5556
				DEFp	RX2_WB_DECIM    12
				DEFp    V_WB_BUF_CHANS  0 + 12
				DEFp    WB_RATE         SND_RATE_WB * 12    // 144 kHz
			  #endif

			  #if 0
				DEFp	RX1_WB_DECIM    347         // 347*16 = 5552, +7.673 Hz, 639 ppm
				DEFp	RX2_WB_DECIM    16
                DEFp    V_WB_BUF_CHANS  0 + 16
                DEFp    WB_RATE         SND_RATE_WB * 16    // 192 kHz
			  #endif

			  #if 0
				DEFp	RX1_WB_DECIM    327         // 327*17 = 5559, -7.447 Hz, 621 ppm
				DEFp	RX2_WB_DECIM    17
                DEFp    V_WB_BUF_CHANS  0 + 17
                DEFp    WB_RATE         SND_RATE_WB * 17    // 204 kHz
			  #endif

			  #if 0
				DEFp	RX1_WB_DECIM    278         // 278*20 = 5560
				DEFp	RX2_WB_DECIM    20
                DEFp    V_WB_BUF_CHANS  0 + 20
                DEFp    WB_RATE         SND_RATE_WB * 20    // 240 kHz
			  #endif

			  #if 0
				DEFp	RX1_WB_DECIM    222         // 222*25 = 5550, 12.000 Hz, 999 ppm
				DEFp	RX2_WB_DECIM    25
                DEFp    V_WB_BUF_CHANS  0 + 25
                DEFp    WB_RATE         SND_RATE_WB * 25    // 300 kHz
			  #endif

			 #endif  // USE_WB
				
			 #if USE_24K_WIDE
				DEFp	RX1_WIDE_DECIM  463
				DEFp	RX2_WIDE_DECIM  6			// 463*6 = 2778, 66.6666M/2778 = 23998.056 Hz (-1.944)
			 #else
				DEFp	RX1_WIDE_DECIM  823
				DEFp	RX2_WIDE_DECIM  4			// 823*4 = 3292, 66.6666M/3292 = 20251.094 Hz (+1.094)
			 #endif
				
				// half as much error as below, but don't want to change status quo
			 #if USE_WB
				DEFp	RX1_STD_DECIM   RX1_WB_DECIM
				DEFp	RX2_STD_DECIM   RX2_WB_DECIM
			 #else
                //DEFp	RX1_STD_DECIM   926
                //DEFp	RX2_STD_DECIM   6			// 926*6 = 5556, 66.6666M/5556 = 11999.028 Hz (-0.972)
				DEFp	RX1_STD_DECIM   505
				DEFp	RX2_STD_DECIM   11			// 505*11 = 5555, 66.6666M/5555 = 12001.188 Hz (+1.188)
             #endif

				DEFh    CICF_DECIM_BY_2 1

            #endif  // !USE_RX_CICF
            
			 #if USE_24K_WIDE
                DEFp    MAX_SND_RATE    24000
                DEFp    SND_RATE_3CH    24000
			 #else
                DEFp    MAX_SND_RATE    20250
                DEFp    SND_RATE_3CH    20250
             #endif
                DEFp    MIN_SND_RATE    12000

                DEFp    SND_RATE_4CH    12000
                DEFp    SND_RATE_8CH    12000
                DEFp    SND_RATE_14CH   12000

                DEFp    RX_DECIM_3CH    RX1_WIDE_DECIM * RX2_WIDE_DECIM * CICF_DECIM_BY_2
                DEFp    RX_DECIM_4CH    RX1_STD_DECIM  * RX2_STD_DECIM  * CICF_DECIM_BY_2
                DEFp    RX_DECIM_8CH    RX1_STD_DECIM  * RX2_STD_DECIM  * CICF_DECIM_BY_2
                DEFp    RX_DECIM_14CH   RX1_STD_DECIM  * RX2_STD_DECIM  * CICF_DECIM_BY_2
                DEFp    RX_DECIM_WB     RX1_WB_DECIM   * RX2_WB_DECIM   * CICF_DECIM_BY_2

                DEFp    RXBUF_SIZE_4CH   8192       // given  8k x 16b audio buffer in receiver.v
                DEFp    RXBUF_SIZE_3CH  16384       // given 16k x 16b audio buffer in receiver.v
                DEFp    RXBUF_SIZE_8CH  16384       // given 16k x 16b audio buffer in receiver.v
                DEFp    RXBUF_SIZE_14CH 32768       // given 32k x 16b audio buffer in receiver.v
                DEFp    RXBUF_SIZE_WB   32768       // given 32k x 16b audio buffer in receiver.v

                DEFp    RXBUF_LARGE_4CH     0
                DEFp    RXBUF_LARGE_3CH     1
                DEFp    RXBUF_LARGE_8CH     1
                DEFp    RXBUF_LARGE_14CH    2
                DEFp    RXBUF_LARGE_WB      2

                // for SPIBUF_W = 2048, RX_CHANS = 3, => nrx_samps = 226
			    // 1/(24000/nrx_samps) = interrupt every 9.4 ms / 118 Hz
                // for RXBUF_SIZE_3CH = 16384 => nrx_bufs = 8

                // for SPIBUF_W = 2048, RX_CHANS = 3, => nrx_samps = 226
			    // 1/(20250/nrx_samps) = interrupt every 11.2 ms / 106 Hz
                // for RXBUF_SIZE_3CH = 16384 => nrx_bufs = 8

                // for SPIBUF_W = 2048, RX_CHANS = 4, => nrx_samps = 170
			    // 1/(12000/nrx_samps) = interrupt every 14 ms / 71 Hz
                // for RXBUF_SIZE_4CH = 8192 => nrx_bufs = 4

                // for SPIBUF_W = 2048, RX_CHANS = 8, => nrx_samps = 85
			    // 1/(12000/nrx_samps) = interrupt every 7 ms / 141 Hz
                // for RXBUF_SIZE_8CH = 16384 => nrx_bufs = 8

                // for SPIBUF_W = 2048, RX_CHANS = 14, => nrx_samps = 48
			    // 1/(12000/nrx_samps) = interrupt every 4 ms / 250 Hz
                // for RXBUF_SIZE_14CH = 32768 => nrx_bufs = 16

                DEFp    NRX_IQW         3               // 1.5 words (24-bits) per I,Q
                DEFp    NRX_SPI         SPIBUF_W - 1    // can't use last word for some reason
                
                DEFp    NRX_OVHD        3 + 1 + 1   // ticks 3w, count 1w, round up 1w
				DEFp	NRX_SAMPS_RPT	8

				DEFh	USE_RX_CIC24	0

			#if USE_RX_CIC24
				DEFp	RX1_BITS		24
				DEFp	RX2_BITS		23
			#else
				DEFp	RX1_BITS		22
				DEFp	RX2_BITS		18
			#endif
				DEFp	RXO_BITS		24

				DEFp	RX1_STAGES		3
				DEFp	RX2_STAGES		5


; ============================================================================

				// waterfall
				DEFp	MAX_ZOOM		14

				DEFp    NWF_FFT         8192
                DEFp    NWF_IQW         2           // 1 word (16-bits) per I,Q
				DEFp    NWF_NXFER       NWF_FFT * NWF_IQW / SPIBUF_W + 1
				DEFp	NWF_SAMPS		NWF_FFT / NWF_NXFER + 1

				DEFp	NWF_SAMPS_RPT	50
				DEFp	NWF_SAMPS_LOOP	NWF_SAMPS / NWF_SAMPS_RPT
				DEFp	NWF_SAMPS_LOOP2	NWF_SAMPS_LOOP * NWF_SAMPS_RPT
				DEFp	NWF_SAMPS_REM	NWF_SAMPS - NWF_SAMPS_LOOP2
				
				DEFh	USE_WF_1CIC		1
				DEFh	USE_WF_CIC24	1
				DEFh	USE_WF_MEM24	0
				DEFh	USE_WF_NEW		0

				DEFp	WF1_STAGES		5
				DEFp	WF2_STAGES		5
				
			#if USE_WF_CIC24
				DEFp	WF1_BITS		24
				DEFp	WF2_BITS		24
			#else
				DEFp	WF1_BITS		16
				DEFp	WF2_BITS		16
			#endif
			
			#if USE_WF_MEM24
				DEFp	WFO_BITS		24
			#else
				DEFp	WFO_BITS		16
			#endif
			
			#if USE_WF_1CIC
				DEFp	WF_1CIC_MAXD	8192
				DEFp	WF_2CIC_MAXD	0			// to keep Vivado happy
			#else
				DEFp	WF_2CIC_MAXD	128			// 8192 = 128 * 64
				DEFp	WF_2CIC_POW2	7
				DEFp	WF_1CIC_MAXD	0			// to keep Vivado happy
			#endif


; ============================================================================

				// gps
				DEFp    GPS_MAX_CHANS   12          // limited by ipcore_bram_gps_4k_12b
                DEFp	GPS_RX14_CHANS  10          // rx14: need more logic cells for USE_RX_CICF

				//DEFp    GPS_INTEG_BITS  16          // width of EPL I/Q integrators
				//DEFp    GPS_INTEG_BITS  18          // width of EPL I/Q integrators
				DEFp    GPS_INTEG_BITS  20          // width of EPL I/Q integrators
				
				DEFp    GPS_REPL_BITS   18          // width of clock replicas
				DEFp	MAX_NAV_BITS	128

			#if STACK_CHECK
			    DEFp    GPS_RPT         8
			#else
			    DEFp    GPS_RPT         32
			#endif
			
				DEFp	GPS_SAMPS		256
				DEFp	GPS_SAMPS_RPT	GPS_RPT
				DEFp	GPS_SAMPS_LOOP	GPS_SAMPS / GPS_SAMPS_RPT

				DEFp	GPS_IQ_SAMPS    255         // not 256 due to SPI buffer edge bug
				DEFp	GPS_IQ_SAMPS_W  GPS_IQ_SAMPS * 4    // *2 = IQ, *2 = 2 words each

				DEFp	L1_CODEBITS     10
				DEFp	L1_CODELEN      1023

				DEFp    E1B_MODE        0x800
				DEFp	E1B_CODEBITS    12
				DEFp	E1B_CODELEN     4092
				DEFp	E1B_CODE_XFERS  1 << E1B_CODEBITS / SPIBUF_W
				DEFp	E1B_CODE_LOOP   E1B_CODELEN / E1B_CODE_XFERS

				DEFp	E1B_CODE_RPT	GPS_RPT
				DEFp	E1B_CODE_LOOP2	E1B_CODE_LOOP / E1B_CODE_RPT
				DEFp	E1B_CODE_LOOP3	E1B_CODE_LOOP2 * E1B_CODE_RPT
				DEFp	E1B_CODE_REM	E1B_CODE_LOOP - E1B_CODE_LOOP3


; ============================================================================

                // e_cpu I/O
                // NB: [10:0] (0x400 max) because [11] is used for further decoding

				// read reg (rdReg & op[10:0], one hot)
				// always pushes {16'b0, par}
				// these 3 must be in these bit positions: see gps.v
				DEFb	GET_CHAN_IQ		0x001
				DEFb	GET_SRQ			0x002
				DEFb	GET_SNAPSHOT	0x004
				
				DEFb	HOST_RX			0x008
				DEFb	GET_RX_SRQ		0x010
				DEFb	GET_CPU_CTR0	0x020
				DEFb	GET_CPU_CTR1	0x040
				DEFb	GET_CPU_CTR2	0x080
				DEFb	GET_CPU_CTR3	0x100
				DEFb	GET_STATUS		0x200
				DEFb	RDREG_400		0x400
	
				// read reg (rdReg2 & op[10:0], one hot)
				// always pushes {16'b0, par}
			#if USE_SDR
				DEFb	GET_ADC_CTR0    0x001
				DEFb	GET_ADC_CTR1    0x002
			#endif
				DEFb	RDREG2_004		0x004
				DEFb	RDREG2_008		0x008
				DEFb	RDREG2_010		0x010
				DEFb	RDREG2_020		0x020
				DEFb	RDREG2_040		0x040
				DEFb	RDREG2_080		0x080
				DEFb	RDREG2_100		0x100
				DEFb	RDREG2_200		0x200
				DEFb	RDREG2_400		0x400

				// write reg (wrReg & op[10:0], one hot)
				// always pops stack
				DEFb	HOST_TX			0x001
				DEFb	SET_GPS_MASK    0x002
			#if USE_GPS
				DEFb	SET_GPS_CHAN    0x004
				DEFb	SET_CG_NCO		0x008
				DEFb	SET_LO_NCO		0x010
				DEFb	SET_SAT			0x020
				DEFb	SET_E1B_CODE    0x040
				DEFb	SET_PAUSE		0x080
			#endif
			#if USE_SDR
				DEFb	SET_ADC_LVL     0x100
				DEFb	SET_CNT_MASK    0x200
			#endif
				DEFb	SET_CTRL		0x400
				
				// write reg (wrReg2 & op[10:0], one hot)
				// always pops stack
			#if USE_SDR
				DEFb	SET_RX_CHAN		0x001
				DEFb	SET_RX_FREQ		0x002
				DEFb	FREQ_L          0x004
				DEFb	SET_RX_NSAMPS	0x008
				DEFb	SET_GEN_FREQ    0x010
				DEFb	SET_GEN_ATTN	0x020
				DEFb	SET_WF_CHAN		0x040
				DEFb	SET_WF_FREQ		0x080
				DEFb	SET_WF_DECIM	0x100
				DEFb	WF_SAMPLER_RST	0x200
				DEFb	WRREG2_400  	0x400
			#endif
	
				// events (wrEvt & op[10:0], one hot)
				// no stack change
				DEFb	HOST_RST		0x001
				DEFb	HOST_RDY		0x002
				DEFb	GET_MEMORY		0x004   // causes ecpu data memory (with TOS pointer++) to SPI BRAM transfer
			#if USE_GPS
				DEFb	GPS_SAMPLER_RST	0x008
				DEFb	GET_GPS_SAMPLES	0x010	// data transfer goes directly to SPI BRAM
				DEFb	GET_LOG			0x020	// data transfer goes directly to SPI BRAM
				DEFb	PUT_LOG			0x040
				DEFb	LOG_RST			0x080
			#endif
				DEFb	WREVT_100       0x100
				DEFb	WREVT_200       0x200
				DEFb	WREVT_400       0x400

				// events (wrEvt2 & op[10:0], one hot)
				// no stack change
			#if USE_SDR
				DEFb	GET_RX_SAMP		0x001	// data transfer goes directly to SPI BRAM
				DEFb	RX_BUFFER_RST	0x002
				DEFb	RX_GET_BUF_CTR	0x004	// data transfer goes directly to SPI BRAM
				DEFb	WREVT_008	    0x008
				DEFb	GET_WF_SAMP_I	0x010	// data transfer goes directly to SPI BRAM
				DEFb	GET_WF_SAMP_Q	0x020	// "
				DEFb	CLR_RX_OVFL		0x040
			#endif
				DEFb	FREEZE_TOS		0x080
				DEFb	CPU_CTR_CLR		0x100
				DEFb	CPU_CTR_ENA		0x200
				DEFb	CPU_CTR_DIS		0x400


				// WF_SAMPLER_RST
				DEFb	WF_SAMP_RD_RST	0x1
				DEFb	WF_SAMP_WR_RST	0x2
				DEFb	WF_SAMP_CONTIN	0x4
				DEFb	WF_SAMP_SYNC	0x8

				// GET_STATUS
				DEFp	STAT_FPGA_ID	0x000f
				DEFp	STAT_USER       0x00f0
				DEFb	STAT_DNA_DATA	0x0010
				DEFp	STAT_FPGA_VER	0x0f00
				DEFp	STAT_FW_ID		0x7000
				DEFb	STAT_OVFL		0x8000

				// SET_CTRL
				DEFp	CTRL_SER_NONE   0x0000
				DEFp	CTRL_SER_DNA    0x0001
				DEFp	CTRL_SER_ATTN   0x0002
				DEFp	CTRL_SER_GPS    0x0003
				DEFp	CTRL_SER_MASK   0x0003
				DEFb	CTRL_SER_LE_CSN	0x0004
				DEFb	CTRL_SER_CLK	0x0008
				DEFb	CTRL_SER_DATA	0x0010

				DEFb	CTRL_STEN		0x0020
				
				DEFb	CTRL_DEBUG1		0x0040
				DEFb	CTRL_DEBUG2		0x0080

				DEFb	CTRL_OSC_DIS    0x0100
				DEFb	CTRL_EEPROM_WP  0x0200
				DEFb	CTRL_USE_GEN	0x0400
				DEFb	CTRL_CMD_READY	0x0800
				DEFb	CTRL_SND_INTR	0x1000
				DEFb	CTRL_GPS_CLK_EN 0x2000
				DEFb	CTRL_4000		0x4000
				DEFb	CTRL_8000		0x8000

				DEFb	CTRL_UNUSED_OUT CTRL_EEPROM_WP