From 35ffd3503960a9a76183969cebb87d51799432b9 Mon Sep 17 00:00:00 2001
From: Hideto Ueno <uenoku.tokotoko@gmail.com>
Date: Tue, 3 Oct 2023 21:01:52 +0900
Subject: [PATCH] [Firtool] Rerun IMCP after register optimizations (#6179)

This PR adds extra IMCP just after register optimization pass.
We separated register optimization from IMCP to avoid changing
observable behaivor of hardward in IMCP but the separation started
to craete phase-ordering problem regarding IMCP and reg optimization pass.
This commit for now adds one more IMCP after register optimization
to fix one particular regression reported internally
---
 lib/Firtool/Firtool.cpp                |  3 +++
 test/firtool/register-optimization.fir | 35 ++++++++++++++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 test/firtool/register-optimization.fir

diff --git a/lib/Firtool/Firtool.cpp b/lib/Firtool/Firtool.cpp
index 48f28a764b41..b1410d58ad81 100644
--- a/lib/Firtool/Firtool.cpp
+++ b/lib/Firtool/Firtool.cpp
@@ -191,6 +191,9 @@ LogicalResult firtool::populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm,
         createSimpleCanonicalizerPass());
     pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
         circt::firrtl::createRegisterOptimizerPass());
+    // Re-run IMConstProp to propagate constants produced by register
+    // optimizations.
+    pm.nest<firrtl::CircuitOp>().addPass(firrtl::createIMConstPropPass());
     pm.addPass(firrtl::createIMDeadCodeElimPass());
   }
 
diff --git a/test/firtool/register-optimization.fir b/test/firtool/register-optimization.fir
new file mode 100644
index 000000000000..92de46e9743a
--- /dev/null
+++ b/test/firtool/register-optimization.fir
@@ -0,0 +1,35 @@
+; RUN: firtool %s | FileCheck %s
+; Check that `r` is optimized and the constant is propagated to the top-level port. 
+; CHECK-NOT:   Passthrough
+; CHECK-NOT:   Child
+; CHECK-LABEL: module Example
+; CHECK:       assign out = 1'h0;
+
+circuit Example :
+  module Passthrough:
+    input en: UInt<1>
+    output out: UInt<1>
+    out <= en
+
+  module Child:
+    input clock: Clock
+    input zero: UInt<1>
+    input unknown: UInt<1>
+    output out: UInt<1>
+    
+    reg r : UInt<1>, clock
+    r <= zero
+    node b = and(r, unknown)
+    inst p of Passthrough
+    p.en <= b
+    out <= p.out
+
+  module Example:
+    input clock: Clock
+    input unknown: UInt<1>
+    output out: UInt<1>
+    inst c of Child
+    c.clock <= clock
+    c.zero <= UInt<1>(0)
+    c.unknown <= unknown
+    out <= c.out