From 3e67926aa3983f29edc776f28dc689761de60eb0 Mon Sep 17 00:00:00 2001
From: Hideto Ueno <uenoku.tokotoko@gmail.com>
Date: Mon, 17 Jun 2024 19:44:20 +0900
Subject: [PATCH] [SimToSV] Fix DPICall lowering to use `replaceOp` (#7192)

Previously DPICallLowering called `rewriter.replaceAllUsesWith` for individual
results but it seems that is not equivalent to `replaceOp`.

This also adds missing dialect dependency to seq

Close #7191
---
 include/circt/Conversion/Passes.td |  1 +
 lib/Conversion/SimToSV/SimToSV.cpp |  8 ++++----
 test/Conversion/SimToSV/dpi.mlir   | 13 +++++++++++++
 3 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/include/circt/Conversion/Passes.td b/include/circt/Conversion/Passes.td
index aef3eeb6617c..9cb4aa8420f4 100644
--- a/include/circt/Conversion/Passes.td
+++ b/include/circt/Conversion/Passes.td
@@ -808,6 +808,7 @@ def LowerSimToSV: Pass<"lower-sim-to-sv",  "mlir::ModuleOp"> {
   let dependentDialects = [
     "circt::comb::CombDialect",
     "circt::emit::EmitDialect",
+    "circt::seq::SeqDialect",
     "circt::sv::SVDialect",
     "circt::hw::HWDialect"
   ];
diff --git a/lib/Conversion/SimToSV/SimToSV.cpp b/lib/Conversion/SimToSV/SimToSV.cpp
index aa606b1d4dcb..a1d0af51ab42 100644
--- a/lib/Conversion/SimToSV/SimToSV.cpp
+++ b/lib/Conversion/SimToSV/SimToSV.cpp
@@ -180,12 +180,12 @@ class DPICallLowering : public SimConversionPattern<DPICallOp> {
     bool hasEnable = !!op.getEnable();
 
     SmallVector<sv::RegOp> temporaries;
+    SmallVector<Value> reads;
     for (auto [type, result] :
          llvm::zip(op.getResultTypes(), op.getResults())) {
       temporaries.push_back(rewriter.create<sv::RegOp>(op.getLoc(), type));
-      auto read =
-          rewriter.create<sv::ReadInOutOp>(op.getLoc(), temporaries.back());
-      rewriter.replaceAllUsesWith(result, read);
+      reads.push_back(
+          rewriter.create<sv::ReadInOutOp>(op.getLoc(), temporaries.back()));
     }
 
     auto emitCall = [&]() {
@@ -229,7 +229,7 @@ class DPICallLowering : public SimConversionPattern<DPICallOp> {
       });
     }
 
-    rewriter.eraseOp(op);
+    rewriter.replaceOp(op, reads);
     return success();
   }
 };
diff --git a/test/Conversion/SimToSV/dpi.mlir b/test/Conversion/SimToSV/dpi.mlir
index 91a8ba9cbd6e..90659b286f63 100644
--- a/test/Conversion/SimToSV/dpi.mlir
+++ b/test/Conversion/SimToSV/dpi.mlir
@@ -92,3 +92,16 @@ hw.module @dpi_call(in %clock : !seq.clock, in %enable : i1, in %in: i1,
   // VERILOG-NEXT: assign o8 = [[RESULT_7]]; 
   hw.output %0, %1, %2, %3, %4, %5, %6, %7: i1, i1, i1, i1, i1, i1, i1, i1
 }
+
+sim.func.dpi private @increment_counter(in %in_0 : i64, out out_0 : i32)
+sim.func.dpi private @create_counter(out out_0 : i64)
+// CHECK-LABEL: hw.module @Issue7191
+// Check lowering successes.
+hw.module @Issue7191(out result : i32) {
+  // CHECK: call.procedural @create_counter
+  // CHECK: call.procedural @increment_counter
+
+  %0 = sim.func.dpi.call @create_counter() : () -> i64
+  %1 = sim.func.dpi.call @increment_counter(%0) : (i64) -> i32
+  hw.output %1 : i32
+}