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[FIRRTL] better wire canonicalization #7990

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youngar opened this issue Dec 13, 2024 · 0 comments
Open

[FIRRTL] better wire canonicalization #7990

youngar opened this issue Dec 13, 2024 · 0 comments
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FIRRTL Involving the `firrtl` dialect

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@youngar
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youngar commented Dec 13, 2024

FIRRTL version 4.1.0
circuit Foo:
  public module Foo:
    input clock : Clock
    input in : UInt<1>
    output out : UInt<1>

    wire w : Probe<UInt<1>>
    define w = probe(in)
    connect out, read(w)

gives

// Generated by CIRCT firtool-1.88.0-382-g0276e17b2
module Foo(
  input  clock,
         in,
  output out
);

  wire in_probe = in;
  assign out = Foo.in_probe;
endmodule

I would have expected the probe to have been removed entirely.

Removing the intermediate wire gives the expected result:

FIRRTL version 4.1.0
circuit Foo:
  public module Foo:
    input clock : Clock
    input in : UInt<1>
    output out : UInt<1>

    connect out, read(probe(in))
// Generated by CIRCT firtool-1.88.0-382-g0276e17b2
module Foo(
  input  clock,
         in,
  output out
);

  assign out = in;
endmodule
@youngar youngar added the FIRRTL Involving the `firrtl` dialect label Dec 13, 2024
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Labels
FIRRTL Involving the `firrtl` dialect
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