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FIRRTL version 4.1.0 circuit Foo: public module Foo: input clock : Clock input in : UInt<1> output out : UInt<1> wire w : Probe<UInt<1>> define w = probe(in) connect out, read(w)
gives
// Generated by CIRCT firtool-1.88.0-382-g0276e17b2 module Foo( input clock, in, output out ); wire in_probe = in; assign out = Foo.in_probe; endmodule
I would have expected the probe to have been removed entirely.
Removing the intermediate wire gives the expected result:
FIRRTL version 4.1.0 circuit Foo: public module Foo: input clock : Clock input in : UInt<1> output out : UInt<1> connect out, read(probe(in))
// Generated by CIRCT firtool-1.88.0-382-g0276e17b2 module Foo( input clock, in, output out ); assign out = in; endmodule
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gives
I would have expected the probe to have been removed entirely.
Removing the intermediate wire gives the expected result:
The text was updated successfully, but these errors were encountered: