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Makefile.common
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Makefile.common
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###########################################
# Environment
###########################################
ifeq ($(DEV_ROOT), )
$(error DEV_ROOT not define)
endif
CONNECTALDIR?=$(DEV_ROOT)/connectal
P4FPGADIR?=$(DEV_ROOT)/p4fpga
###########################################
# Connectal Support
###########################################
ifeq ($(S2H_INTERFACES), )
S2H_INTERFACES=MainRequest:Main.request
endif
ifeq ($(H2S_INTERFACES), )
H2S_INTERFACES=Main:MainIndication,MemServerIndication:host
endif
ifeq ($(BSVFILES), )
BSVFILES=$(P4FPGADIR)/src/bsv/infra/Main.bsv $(P4FPGADIR)/src/bsv/infra/MainAPI.bsv
endif
ifeq ($(CPPFILES), )
CPPFILES = $(P4FPGADIR)/cpp/main.cpp $(P4FPGADIR)/cpp/lpcap.c
endif
CONNECTALFLAGS += -I $(P4FPGADIR)/cpp/
CONNECTALFLAGS += -lpcap -lpthread
CONNECTALFLAGS += --bsvpath=$(P4FPGADIR)/src/bsv/datapath
CONNECTALFLAGS += --bsvpath=$(P4FPGADIR)/src/bsv/infra
CONNECTALFLAGS += --bsvpath=$(P4FPGADIR)/src/bsv/generated
CONNECTALFLAGS += --bsvpath=$(P4FPGADIR)/src/bsv/library
CONNECTALFLAGS += --bsvpath=$(P4FPGADIR)/src/bsv/library/AsymmetricBRAM
CONNECTALFLAGS += --bsvpath=$(P4FPGADIR)/src/bsv/library/Bcam
CONNECTALFLAGS += --bsvpath=$(P4FPGADIR)/src/bsv/library/DMHC
CONNECTALFLAGS += -D NicVersion=$(shell printf "%d" 0x`git rev-parse --short=8 HEAD`)
CONNECTALFLAGS += -D DataBusWidth=128
CONNECTALFLAGS += -D IMPORT_HOSTIF
CONNECTALFLAGS += -D BYTE_ENABLES
CONNECTALFLAGS += --bscflags="-show-range-conflict +RTS -K596777766 -RTS -demote-errors G0066:G0045 -suppress-warnings G0046:G0020:G0023:S0015:S0080:S0039 -steps-max-intervals 20"
CONNECTALFLAGS += -m $(P4FPGADIR)/src/bsv/library/AsymmetricBRAM/mem_model.c
CONNECTALFLAGS += --bsvpath=$(P4FPGADIR)/src/bsv/
CONNECTALFLAGS += --nocache
CONNECTALFLAGS += --cxxflags=-std=c++11
CONNECTALFLAGS += --bscflags="-no-warn-action-shadowing"
CONNECTALFLAGS += --verilog=$(P4FPGADIR)/src/bsv/verilog/
CONNECTALFLAGS += -D ClockDefaultParam
#CONNECTALFLAGS += -m matchtable_model.cpp
# add path to questasim LIBRARY_PATH to link xsimtop.so with libstdc++ provided by questasim
CONNECTALFLAGS += --cxxflags="-L\"/home/hwang/questasim/questa_sim/gcc-4.3.3-linux_x86_64/lib64\""
BURST_LEN_SIZE=12
PROJ_DIR:=$(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
########################################################
# NFSUME SUPPORT
########################################################
ifeq ($(BOARD), nfsume)
ifeq ($(AUTOTOP), )
AUTOTOP = --interface pins:Main.pins
endif
CONNECTALFLAGS += --verilog=$(P4FPGADIR)/src/bsv/AsymmetricBRAM
PIN_TYPE = NfsumePins
PIN_TYPE_INCLUDE = NfsumePins
PIN_BINDINGS ?= LED:LED SFP:SFP SFPA:SFPA SFPB:SFPB SFPC:SFPC SFPD:SFPD
PINOUT_FILE = $(P4FPGADIR)/boards/nfsume.json
CONNECTALFLAGS += -D XILINX_SYS_CLK
CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/ten_gig_eth_mac_0/ten_gig_eth_mac_0.xci
CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/ten_gig_eth_pcs_pma_shared/ten_gig_eth_pcs_pma_shared.xci
CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/ten_gig_eth_pcs_pma_non_shared/ten_gig_eth_pcs_pma_non_shared.xci
CONNECTALFLAGS += --constraint=timing_constraints.xdc --implconstraint=timing_constraints.xdc
prebuild::
(cd $(BOARD); BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) vivado -notrace -mode batch -source $(P4FPGADIR)/src/bsv/scripts/generate-mac.tcl)
(cd $(BOARD); BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) vivado -notrace -mode batch -source $(P4FPGADIR)/src/bsv/scripts/connectal-synth-phy.tcl)
endif
run:
(cd bluesim; ./bin/ubuntu.exe -p ../${T})
bitgen: codegen
make build.nfsume
clean:
rm -rf generatedbsv
rm -rf generatedcpp
rm -f matchtable_model.cpp
rm -f *_Evaluator.p4
###########################################
# Default Rules
###########################################
include $(CONNECTALDIR)/Makefile.connectal