Do externally-requested interrupts invalidate a cached I_STAT
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#37
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Hi! It's me again. :) Here it is written:
I think that IRQs caused by DMA transfers must invalidate the corresponding cache entry, and that this also must apply more generally to all IRQs issued outside the CPU (e.g., V-blank, timers, GPU). My reasoning stems from the following snippet of code found in the PSX BIOS (10j): In |
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The cache is only for code, not data. You can never hit the cache when loading or writing data, only when executing code. |
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The cache is only for code, not data. You can never hit the cache when loading or writing data, only when executing code.