diff --git a/Cargo.toml b/Cargo.toml
index c8ccb1f..c58b09b 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -4,7 +4,7 @@ version = "0.1.0"
 edition = "2021"
 
 [dependencies]
-stm32g0 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies", rev = "057da0d23" }
+stm32g0 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies", rev = "f9d02d3" }
 
 cortex-m = "0.7"
 embedded-hal = "1"
diff --git a/src/exti.rs b/src/exti.rs
index a12bcf5..218c08e 100644
--- a/src/exti.rs
+++ b/src/exti.rs
@@ -69,7 +69,7 @@ impl ExtiExt for EXTI {
                     .imr2()
                     .modify(|r, w| w.bits(r.bits() | (1 << (line - 32)))),
                 _ => unreachable!(),
-            }
+            };
         }
     }
 
@@ -84,7 +84,7 @@ impl ExtiExt for EXTI {
                     .imr2()
                     .modify(|r, w| w.bits(r.bits() & !(1 << (line - 32)))),
                 _ => unreachable!(),
-            }
+            };
         }
     }
 
diff --git a/src/gpio.rs b/src/gpio.rs
index 7bdbed3..e030f66 100644
--- a/src/gpio.rs
+++ b/src/gpio.rs
@@ -219,14 +219,16 @@ macro_rules! gpio_common {
                 fn set_high(&mut self) -> Result<(), Self::Error> {
                     unsafe {
                         let rb =  &(*$GPIO::ptr());
-                        Ok(rb.bsrr().write(|w| w.[<bs $i>]().set_bit()))
+                        rb.bsrr().write(|w| w.[<bs $i>]().set_bit());
+                        Ok(())
                     }
                 }
 
                 fn set_low(&mut self) -> Result<(), Self::Error> {
                     unsafe {
                         let rb =  &(*$GPIO::ptr());
-                        Ok(rb.bsrr().write(|w| w.[<br $i>]().set_bit()))
+                        rb.bsrr().write(|w| w.[<br $i>]().set_bit());
+                        Ok(())
                     }
                 }
             }
@@ -271,8 +273,12 @@ macro_rules! gpio {
                     #[cfg(feature = "stm32g071")]
                     pub fn trigger_on_edge(&mut self, edge: SignalEdge, exti: &mut EXTI) {
                         match edge {
-                            SignalEdge::Rising => exti.rtsr1().modify(|_, w| w.[<tr $i>]().enabled()),
-                            SignalEdge::Falling => exti.ftsr1().modify(|_, w| w.[<tr $i>]().enabled()),
+                            SignalEdge::Rising => {
+                                exti.rtsr1().modify(|_, w| w.[<tr $i>]().enabled());
+                            },
+                            SignalEdge::Falling => {
+                                exti.ftsr1().modify(|_, w| w.[<tr $i>]().enabled());
+                            },
                             SignalEdge::Both => {
                                 exti.rtsr1().modify(|_, w| w.[<tr $i>]().enabled());
                                 exti.ftsr1().modify(|_, w| w.[<tr $i>]().enabled());
@@ -283,8 +289,12 @@ macro_rules! gpio {
                     #[cfg(feature = "stm32g0b1")]
                     pub fn trigger_on_edge(&mut self, edge: SignalEdge, exti: &mut EXTI) {
                         match edge {
-                            SignalEdge::Rising => exti.rtsr1().modify(|_, w| w.[<rt $i>]().enabled()),
-                            SignalEdge::Falling => exti.ftsr1().modify(|_, w| w.[<ft $i>]().enabled()),
+                            SignalEdge::Rising => {
+                                exti.rtsr1().modify(|_, w| w.[<rt $i>]().enabled());
+                            },
+                            SignalEdge::Falling => {
+                                exti.ftsr1().modify(|_, w| w.[<ft $i>]().enabled());
+                            },
                             SignalEdge::Both => {
                                 exti.rtsr1().modify(|_, w| w.[<rt $i>]().enabled());
                                 exti.ftsr1().modify(|_, w| w.[<ft $i>]().enabled());
diff --git a/src/rcc.rs b/src/rcc.rs
index c04e31a..d2a4768 100644
--- a/src/rcc.rs
+++ b/src/rcc.rs
@@ -26,8 +26,7 @@ impl RccExt for RCC {
         let sysclk = match config.hsisys_prescaler {
             config::Prescaler::Div1 => HSI_FREQ,
             config::Prescaler::Div2 => HSI_FREQ / 2,
-            // TODO: fix when Div3 renamed to Div4
-            config::Prescaler::Div3 => HSI_FREQ / 4,
+            config::Prescaler::Div4 => HSI_FREQ / 4,
             config::Prescaler::Div8 => HSI_FREQ / 8,
             config::Prescaler::Div16 => HSI_FREQ / 16,
             config::Prescaler::Div32 => HSI_FREQ / 32,
diff --git a/src/timer/lptim.rs b/src/timer/lptim.rs
index abb4130..29a32ce 100644
--- a/src/timer/lptim.rs
+++ b/src/timer/lptim.rs
@@ -160,7 +160,7 @@ macro_rules! low_power_timer {
                     LptimEvent::ExtTrig => w.exttrigcf().set_bit(),
                     LptimEvent::ArrMatch => w.arrmcf().set_bit(),
                     LptimEvent::CmpMatch => w.cmpmcf().set_bit(),
-                })
+                });
             }
         }
 
@@ -189,7 +189,7 @@ macro_rules! low_power_timer {
                     LptimEvent::ExtTrig => w.exttrigie().set_bit(),
                     LptimEvent::ArrMatch => w.arrmie().set_bit(),
                     LptimEvent::CmpMatch => w.cmpmie().set_bit(),
-                })
+                });
             }
 
             pub fn unlisten(&self, event: LptimEvent) {
@@ -201,7 +201,7 @@ macro_rules! low_power_timer {
                     LptimEvent::ExtTrig => w.exttrigie().clear_bit(),
                     LptimEvent::ArrMatch => w.arrmie().clear_bit(),
                     LptimEvent::CmpMatch => w.cmpmie().clear_bit(),
-                })
+                });
             }
         }
     };