double-trace2.txt

33: hybrid_memory.access(0x128202b0, 3264, 64, read, instr, 0, L2)
33: hybrid_memory.access(0x12820630, 7168, 64, read, instr, 0, L2)
149: hybrid_memory.accessCompleted(0x128202b0, 3264, 64, read, dram)
185: hybrid_memory.access(0x1281bd50, 8704, 64, read, data, 0, L2)
315: hybrid_memory.accessCompleted(0x12820630, 7168, 64, read, dram)
349: hybrid_memory.access(0x12821430, 7232, 64, read, instr, 0, L2)
353: hybrid_memory.access(0x1282fa90, 8640, 64, read, data, 0, L2)
481: hybrid_memory.accessCompleted(0x1281bd50, 8704, 64, read, dram)
497: hybrid_memory.accessCompleted(0x1282fa90, 8640, 64, read, dram)
663: hybrid_memory.accessCompleted(0x12821430, 7232, 64, read, dram)
698: hybrid_memory.access(0x12822bb0, 7296, 64, read, instr, 0, L2)
701: hybrid_memory.access(0x1282e390, 15936, 64, read, data, 0, L2)
701: hybrid_memory.access(0x1282f830, 16384, 64, read, data, 0, L2)
701: hybrid_memory.access(0x1281bd50, 15488, 64, read, data, 0, L2)
702: hybrid_memory.access(0x1282f930, 18880, 64, read, data, 0, L2)
764: hybrid_memory.accessCompleted(0x12822bb0, 7296, 64, read, dram)
799: hybrid_memory.access(0x12823d30, 7360, 64, read, instr, 0, L2)
930: hybrid_memory.accessCompleted(0x1282e390, 15936, 64, read, dram)
946: hybrid_memory.accessCompleted(0x1281bd50, 15488, 64, read, dram)
1112: hybrid_memory.accessCompleted(0x1282f830, 16384, 64, read, dram)
1128: hybrid_memory.accessCompleted(0x1282f930, 18880, 64, read, dram)
1294: hybrid_memory.accessCompleted(0x12823d30, 7360, 64, read, dram)
1331: hybrid_memory.access(0x1282e390, 19072, 64, read, data, 0, L2)
1332: hybrid_memory.access(0x12826670, 7872, 64, read, instr, 0, L2)
1332: hybrid_memory.access(0x1281bd50, 16000, 64, read, data, 0, L2)
1333: hybrid_memory.access(0x1282f830, 18944, 64, read, data, 0, L2)
1497: hybrid_memory.accessCompleted(0x1282e390, 19072, 64, read, dram)
1513: hybrid_memory.accessCompleted(0x1282f830, 18944, 64, read, dram)
1679: hybrid_memory.accessCompleted(0x12826670, 7872, 64, read, dram)
1712: hybrid_memory.access(0x12826d70, 7936, 64, read, instr, 0, L2)
1845: hybrid_memory.accessCompleted(0x1281bd50, 16000, 64, read, dram)
2011: hybrid_memory.accessCompleted(0x12826d70, 7936, 64, read, dram)
2044: hybrid_memory.access(0x12827470, 20544, 64, read, instr, 0, L2)
2210: hybrid_memory.accessCompleted(0x12827470, 20544, 64, read, dram)
2247: hybrid_memory.access(0x1282e390, 19520, 64, read, data, 0, L2)
2249: hybrid_memory.access(0x1281bd50, 19008, 64, read, data, 0, L2)
2252: hybrid_memory.access(0x1282fec0, 16064, 64, read, data, 0, L2)
2260: hybrid_memory.access(0x2608790, 16128, 64, read, data, 0, L2)
2263: hybrid_memory.access(0x12831880, 19136, 64, read, data, 0, L2)
2268: hybrid_memory.access(0x12831d30, 16192, 64, read, data, 0, L2)
2269: hybrid_memory.access(0x12825070, 7424, 64, read, instr, 0, L2)
2413: hybrid_memory.accessCompleted(0x1282e390, 19520, 64, read, dram)
2429: hybrid_memory.accessCompleted(0x1281bd50, 19008, 64, read, dram)
2445: hybrid_memory.accessCompleted(0x12831880, 19136, 64, read, dram)
2611: hybrid_memory.accessCompleted(0x1282fec0, 16064, 64, read, dram)
2627: hybrid_memory.accessCompleted(0x2608790, 16128, 64, read, dram)
2643: hybrid_memory.accessCompleted(0x12831d30, 16192, 64, read, dram)
2809: hybrid_memory.accessCompleted(0x12825070, 7424, 64, read, dram)
2845: hybrid_memory.access(0x12832230, 19264, 64, read, data, 0, L2)
2848: hybrid_memory.access(0x1282e390, 19200, 64, read, data, 0, L2)
2852: hybrid_memory.access(0x128320e0, 19328, 64, read, data, 0, L2)
2852: hybrid_memory.access(0x1282f830, 16256, 64, read, data, 0, L2)
2855: hybrid_memory.access(0x1282b5f0, 7488, 64, read, instr, 0, L2)
3011: hybrid_memory.accessCompleted(0x12832230, 19264, 64, read, dram)
3027: hybrid_memory.accessCompleted(0x1282e390, 19200, 64, read, dram)
3043: hybrid_memory.accessCompleted(0x128320e0, 19328, 64, read, dram)
3209: hybrid_memory.accessCompleted(0x1282f830, 16256, 64, read, dram)
3375: hybrid_memory.accessCompleted(0x1282b5f0, 7488, 64, read, dram)
3411: hybrid_memory.access(0x1282d1f0, 7552, 64, read, instr, 0, L2)
3477: hybrid_memory.accessCompleted(0x1282d1f0, 7552, 64, read, dram)
3513: hybrid_memory.access(0x12820df0, 7616, 64, read, instr, 0, L2)
3579: hybrid_memory.accessCompleted(0x12820df0, 7616, 64, read, dram)
3613: hybrid_memory.access(0x12821cf0, 7680, 64, read, instr, 0, L2)
3679: hybrid_memory.accessCompleted(0x12821cf0, 7680, 64, read, dram)
3714: hybrid_memory.access(0x12822d70, 8000, 64, read, instr, 0, L2)
3780: hybrid_memory.accessCompleted(0x12822d70, 8000, 64, read, dram)
3815: hybrid_memory.access(0x128245f0, 8064, 64, read, instr, 0, L2)
3881: hybrid_memory.accessCompleted(0x128245f0, 8064, 64, read, dram)
3918: hybrid_memory.access(0x128264b0, 8128, 64, read, instr, 0, L2)
3921: hybrid_memory.access(0x1282e390, 2176, 64, read, data, 0, L2)
3984: hybrid_memory.accessCompleted(0x128264b0, 8128, 64, read, dram)
4021: hybrid_memory.access(0x12832230, 15744, 64, read, data, 0, L2)
4021: hybrid_memory.access(0x12832330, 2240, 64, read, data, 0, L2)
4027: hybrid_memory.access(0x12830d90, 2304, 64, read, data, 0, L2)
4034: hybrid_memory.access(0x12832bb0, 2368, 64, read, data, 0, L2)
4038: hybrid_memory.access(0x128333b0, 15808, 64, read, data, 0, L2)
4150: hybrid_memory.accessCompleted(0x1282e390, 2176, 64, read, dram)
4166: hybrid_memory.accessCompleted(0x12832330, 2240, 64, read, dram)
4182: hybrid_memory.accessCompleted(0x12830d90, 2304, 64, read, dram)
4198: hybrid_memory.accessCompleted(0x12832bb0, 2368, 64, read, dram)
4202: hybrid_memory.access(0x12831b00, 2432, 64, read, data, 0, L2)
4203: hybrid_memory.access(0x12823b70, 20480, 64, read, instr, 0, L2)
4364: hybrid_memory.accessCompleted(0x12832230, 15744, 64, read, dram)
4380: hybrid_memory.accessCompleted(0x128333b0, 15808, 64, read, dram)
4546: hybrid_memory.accessCompleted(0x12831b00, 2432, 64, read, dram)
4712: hybrid_memory.accessCompleted(0x12823b70, 20480, 64, read, dram)
4749: hybrid_memory.access(0x12826130, 20608, 64, read, instr, 0, L2)
4750: hybrid_memory.access(0x2608910, 1088, 64, read, data, 0, L2)
4752: hybrid_memory.access(0x12832f20, 26112, 64, read, data, 0, L2)
4815: hybrid_memory.accessCompleted(0x12826130, 20608, 64, read, dram)
4851: hybrid_memory.access(0x12833140, 16320, 64, read, data, 0, L2)
4855: hybrid_memory.access(0x1282f930, 1024, 64, read, data, 0, L2)
4858: hybrid_memory.access(0x12832330, 2496, 64, read, data, 0, L2)
4863: hybrid_memory.access(0x12831e30, 1152, 64, read, data, 0, L2)
4870: hybrid_memory.access(0x2608780, 1472, 64, read, data, 0, L2)
4870: hybrid_memory.access(0x12830d90, 1408, 64, read, data, 0, L2)
4874: hybrid_memory.access(0x12833900, 2560, 64, read, data, 0, L2)
4877: hybrid_memory.access(0x12833010, 1216, 64, read, data, 0, L2)
4981: hybrid_memory.accessCompleted(0x2608910, 1088, 64, read, dram)
4997: hybrid_memory.accessCompleted(0x1282f930, 1024, 64, read, dram)
5013: hybrid_memory.accessCompleted(0x12832330, 2496, 64, read, dram)
5029: hybrid_memory.accessCompleted(0x12831e30, 1152, 64, read, dram)
5045: hybrid_memory.accessCompleted(0x2608780, 1472, 64, read, dram)
5061: hybrid_memory.accessCompleted(0x12830d90, 1408, 64, read, dram)
5077: hybrid_memory.accessCompleted(0x12833900, 2560, 64, read, dram)
5093: hybrid_memory.accessCompleted(0x12833010, 1216, 64, read, dram)
5259: hybrid_memory.accessCompleted(0x12832f20, 26112, 64, read, dram)
5307: hybrid_memory.access(0x1282beb0, 7744, 64, read, instr, 0, L2)
5307: hybrid_memory.access(0x1282c170, 31872, 64, read, instr, 0, L2)
5425: hybrid_memory.accessCompleted(0x12833140, 16320, 64, read, dram)
5591: hybrid_memory.accessCompleted(0x1282beb0, 7744, 64, read, dram)
5627: hybrid_memory.access(0x12833010, 19648, 64, read, data, 0, L2)
5627: hybrid_memory.access(0x12832f20, 8576, 64, read, data, 0, L2)
5757: hybrid_memory.accessCompleted(0x1282c170, 31872, 64, read, dram)
5793: hybrid_memory.access(0x1282dff0, 31936, 64, read, instr, 0, L2)
5794: hybrid_memory.access(0x12832cd0, 640, 64, read, data, 0, L2)
5923: hybrid_memory.accessCompleted(0x12833010, 19648, 64, read, dram)
6089: hybrid_memory.accessCompleted(0x12832f20, 8576, 64, read, dram)
6255: hybrid_memory.accessCompleted(0x1282dff0, 31936, 64, read, dram)
6291: hybrid_memory.access(0x128216b0, 7808, 64, read, instr, 0, L2)
6294: hybrid_memory.access(0x2608910, 19712, 64, read, data, 0, L2)
6421: hybrid_memory.accessCompleted(0x12832cd0, 640, 64, read, dram)
6587: hybrid_memory.accessCompleted(0x128216b0, 7808, 64, read, dram)
6621: hybrid_memory.access(0x12822770, 4195264, 64, read, instr, 0, L2)
6625: hybrid_memory.access(0x1282fe70, 18816, 64, read, data, 0, L2)
6753: hybrid_memory.accessCompleted(0x2608910, 19712, 64, read, dram)
6769: hybrid_memory.accessCompleted(0x1282fe70, 18816, 64, read, dram)
6931: hybrid_memory.accessCompleted(0x12822770, 4195264, 64, read, pcm)
6966: hybrid_memory.access(0x128239b0, 4195328, 64, read, instr, 0, L2)
7276: hybrid_memory.accessCompleted(0x128239b0, 4195328, 64, read, pcm)
7312: hybrid_memory.access(0x128312e0, 8512, 64, read, data, 0, L2)
7312: hybrid_memory.access(0x12832e20, 15872, 64, read, data, 0, L2)
7313: hybrid_memory.access(0x128320e0, 4198656, 64, read, data, 0, L2)
7313: hybrid_memory.access(0x128319d0, 8768, 64, read, data, 0, L2)
7319: hybrid_memory.access(0x1282f930, 8832, 64, read, data, 0, L2)
7325: hybrid_memory.access(0x12832cd0, 8896, 64, read, data, 0, L2)
7331: hybrid_memory.access(0x12834970, 8960, 64, read, data, 0, L2)
7478: hybrid_memory.accessCompleted(0x128312e0, 8512, 64, read, dram)
7494: hybrid_memory.accessCompleted(0x128319d0, 8768, 64, read, dram)
7510: hybrid_memory.accessCompleted(0x1282f930, 8832, 64, read, dram)
7526: hybrid_memory.accessCompleted(0x12832cd0, 8896, 64, read, dram)
7531: hybrid_memory.access(0x12834770, 9024, 64, read, data, 0, L2)
7542: hybrid_memory.accessCompleted(0x12834970, 8960, 64, read, dram)
7548: hybrid_memory.access(0x1282f930, 9088, 64, read, data, 0, L2)
7564: hybrid_memory.access(0x12832cd0, 9152, 64, read, data, 0, L2)
7580: hybrid_memory.access(0x128337d0, 9216, 64, read, data, 0, L2)
7597: hybrid_memory.accessCompleted(0x12834770, 9024, 64, read, dram)
7614: hybrid_memory.accessCompleted(0x1282f930, 9088, 64, read, dram)
7623: hybrid_memory.accessCompleted(0x128320e0, 4198656, 64, read, pcm)
7630: hybrid_memory.accessCompleted(0x12832cd0, 9152, 64, read, dram)
7635: hybrid_memory.access(0x128319d0, 9280, 64, read, data, 0, L2)
7646: hybrid_memory.accessCompleted(0x128337d0, 9216, 64, read, dram)
7647: hybrid_memory.access(0x1282d570, 4195392, 64, read, instr, 0, L2)
7701: hybrid_memory.accessCompleted(0x128319d0, 9280, 64, read, dram)
7867: hybrid_memory.accessCompleted(0x12832e20, 15872, 64, read, dram)
7957: hybrid_memory.accessCompleted(0x1282d570, 4195392, 64, read, pcm)
7992: hybrid_memory.access(0x128208b0, 4195456, 64, read, instr, 0, L2)
7993: hybrid_memory.access(0x12834720, 15552, 64, read, data, 0, L2)
7994: hybrid_memory.access(0x12832f20, 15616, 64, read, data, 0, L2)
8059: hybrid_memory.accessCompleted(0x12834720, 15552, 64, read, dram)
8075: hybrid_memory.accessCompleted(0x12832f20, 15616, 64, read, dram)
8302: hybrid_memory.accessCompleted(0x128208b0, 4195456, 64, read, pcm)
8336: hybrid_memory.access(0x12821b30, 4195520, 64, read, instr, 0, L2)
8339: hybrid_memory.access(0x12832cd0, 15680, 64, read, data, 0, L2)
8405: hybrid_memory.accessCompleted(0x12832cd0, 15680, 64, read, dram)
8646: hybrid_memory.accessCompleted(0x12821b30, 4195520, 64, read, pcm)
8683: hybrid_memory.access(0x128312e0, 28416, 64, read, data, 0, L2)
8683: hybrid_memory.access(0x12823ab0, 4195840, 64, read, instr, 0, L2)
8684: hybrid_memory.access(0x128319d0, 9344, 64, read, data, 0, L2)
8686: hybrid_memory.access(0x2608220, 28352, 64, read, data, 0, L2)
8849: hybrid_memory.accessCompleted(0x128312e0, 28416, 64, read, dram)
8865: hybrid_memory.accessCompleted(0x2608220, 28352, 64, read, dram)
8993: hybrid_memory.accessCompleted(0x12823ab0, 4195840, 64, read, pcm)
9031: hybrid_memory.accessCompleted(0x128319d0, 9344, 64, read, dram)
9031: hybrid_memory.access(0x128264b0, 4195776, 64, read, instr, 0, L2)
9341: hybrid_memory.accessCompleted(0x128264b0, 4195776, 64, read, pcm)
9376: hybrid_memory.access(0x128279b0, 4195904, 64, read, instr, 0, L2)
9686: hybrid_memory.accessCompleted(0x128279b0, 4195904, 64, read, pcm)
9722: hybrid_memory.access(0x12831f20, 9408, 64, read, data, 0, L2)
9788: hybrid_memory.accessCompleted(0x12831f20, 9408, 64, read, dram)
10035: hybrid_memory.access(0x128344b0, 28672, 64, write, data, 0, HybridMemoryManager)
10035: hybrid_memory.access(0x128345c0, 28864, 64, write, data, 0, HybridMemoryManager)
10035: hybrid_memory.access(0x12834060, 28928, 64, write, data, 0, HybridMemoryManager)
10035: hybrid_memory.access(0x128341b0, 29120, 64, write, data, 0, HybridMemoryManager)
10035: hybrid_memory.access(0x128301c0, 29056, 64, write, data, 0, HybridMemoryManager)
10035: hybrid_memory.access(0x12830310, 28736, 64, write, data, 0, HybridMemoryManager)
10035: hybrid_memory.access(0x12830460, 28800, 64, write, data, 0, HybridMemoryManager)
10035: hybrid_memory.access(0x1282e7c0, 28992, 64, write, data, 0, HybridMemoryManager)
10070: hybrid_memory.access(0x12834690, 29184, 64, write, data, 0, HybridMemoryManager)
10070: hybrid_memory.access(0x128347a0, 29376, 64, write, data, 0, HybridMemoryManager)
10070: hybrid_memory.access(0x1282f200, 29440, 64, write, data, 0, HybridMemoryManager)
10070: hybrid_memory.access(0x1282f350, 29632, 64, write, data, 0, HybridMemoryManager)
10070: hybrid_memory.access(0x1282f4a0, 29568, 64, write, data, 0, HybridMemoryManager)
10070: hybrid_memory.access(0x1282ed10, 29248, 64, write, data, 0, HybridMemoryManager)
10070: hybrid_memory.access(0x1282ee60, 29312, 64, write, data, 0, HybridMemoryManager)
10070: hybrid_memory.access(0x1282efb0, 29504, 64, write, data, 0, HybridMemoryManager)
10105: hybrid_memory.access(0x12830a10, 29824, 64, write, data, 0, HybridMemoryManager)
10105: hybrid_memory.access(0x12834280, 29888, 64, write, data, 0, HybridMemoryManager)
10105: hybrid_memory.access(0x128343d0, 30144, 64, write, data, 0, HybridMemoryManager)
10105: hybrid_memory.access(0x12830ec0, 30080, 64, write, data, 0, HybridMemoryManager)
10105: hybrid_memory.access(0x12830fd0, 30016, 64, write, data, 0, HybridMemoryManager)
10105: hybrid_memory.access(0x12831120, 29696, 64, write, data, 0, HybridMemoryManager)
10105: hybrid_memory.access(0x12831270, 29760, 64, write, data, 0, HybridMemoryManager)
10105: hybrid_memory.access(0x12831470, 29952, 64, write, data, 0, HybridMemoryManager)
10140: hybrid_memory.access(0x12831600, 30336, 64, write, data, 0, HybridMemoryManager)
10140: hybrid_memory.access(0x12831750, 30400, 64, write, data, 0, HybridMemoryManager)
10140: hybrid_memory.access(0x128318a0, 30656, 64, write, data, 0, HybridMemoryManager)
10140: hybrid_memory.access(0x12832480, 30592, 64, write, data, 0, HybridMemoryManager)
10140: hybrid_memory.access(0x128325d0, 30528, 64, write, data, 0, HybridMemoryManager)
10140: hybrid_memory.access(0x12832720, 30208, 64, write, data, 0, HybridMemoryManager)
10140: hybrid_memory.access(0x12832870, 30272, 64, write, data, 0, HybridMemoryManager)
10140: hybrid_memory.access(0x128329c0, 30464, 64, write, data, 0, HybridMemoryManager)
10175: hybrid_memory.access(0x12832b50, 30912, 64, write, data, 0, HybridMemoryManager)
10175: hybrid_memory.access(0x1282e910, 30848, 64, write, data, 0, HybridMemoryManager)
10175: hybrid_memory.access(0x12833780, 30720, 64, write, data, 0, HybridMemoryManager)
10175: hybrid_memory.access(0x128338d0, 30784, 64, write, data, 0, HybridMemoryManager)
10175: hybrid_memory.access(0x12833a20, 31168, 64, write, data, 0, HybridMemoryManager)
10175: hybrid_memory.access(0x12833b70, 31104, 64, write, data, 0, HybridMemoryManager)
10175: hybrid_memory.access(0x12834d80, 30976, 64, write, data, 0, HybridMemoryManager)
10175: hybrid_memory.access(0x12834ed0, 31040, 64, write, data, 0, HybridMemoryManager)
10210: hybrid_memory.access(0x128344b0, 31232, 64, write, data, 0, HybridMemoryManager)
10210: hybrid_memory.access(0x1282fff0, 31680, 64, write, data, 0, HybridMemoryManager)
10210: hybrid_memory.access(0x12835370, 31616, 64, write, data, 0, HybridMemoryManager)
10210: hybrid_memory.access(0x2608470, 31552, 64, write, data, 0, HybridMemoryManager)
10210: hybrid_memory.access(0x128374a0, 31296, 64, write, data, 0, HybridMemoryManager)
10210: hybrid_memory.access(0x12837570, 31424, 64, write, data, 0, HybridMemoryManager)
10210: hybrid_memory.access(0x12837640, 31488, 64, write, data, 0, HybridMemoryManager)
10210: hybrid_memory.access(0x12837710, 31360, 64, write, data, 0, HybridMemoryManager)
10245: hybrid_memory.access(0x128345c0, 32064, 64, write, data, 0, HybridMemoryManager)
10245: hybrid_memory.access(0x12834060, 32128, 64, write, data, 0, HybridMemoryManager)
10245: hybrid_memory.access(0x12830610, 31936, 64, write, data, 0, HybridMemoryManager)
10245: hybrid_memory.access(0x12830760, 32000, 64, write, data, 0, HybridMemoryManager)
10245: hybrid_memory.access(0x128308b0, 31808, 64, write, data, 0, HybridMemoryManager)
10245: hybrid_memory.access(0x12837be0, 31872, 64, write, data, 0, HybridMemoryManager)
10245: hybrid_memory.access(0x12837cb0, 31744, 64, write, data, 0, HybridMemoryManager)
10245: hybrid_memory.access(0x12837d80, 32192, 64, write, data, 0, HybridMemoryManager)
10280: hybrid_memory.access(0x128341b0, 32512, 64, write, data, 0, HybridMemoryManager)
10280: hybrid_memory.access(0x128301c0, 32576, 64, write, data, 0, HybridMemoryManager)
10280: hybrid_memory.access(0x12837a20, 32384, 64, write, data, 0, HybridMemoryManager)
10280: hybrid_memory.access(0x12838310, 32448, 64, write, data, 0, HybridMemoryManager)
10280: hybrid_memory.access(0x12838420, 32256, 64, write, data, 0, HybridMemoryManager)
10280: hybrid_memory.access(0x12833580, 32320, 64, write, data, 0, HybridMemoryManager)
10280: hybrid_memory.access(0x12838570, 32640, 64, write, data, 0, HybridMemoryManager)
10280: hybrid_memory.access(0x12838640, 32704, 64, write, data, 0, HybridMemoryManager)
10280: hybrid_memory.copyPage(7, 1026)
10280: hybrid_memory.copyPage: dram(28672) to pcm(4202496)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1282f630
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x1282f630, 28672, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1282f930
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x1282f930, 28736, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12831ad0
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x12831ad0, 28800, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x2608a10
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x2608a10, 28864, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12833f30
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x12833f30, 28928, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x2608710
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x2608710, 28992, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1282e390
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x1282e390, 29056, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1282e540
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x1282e540, 29120, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x2608220
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x2608220, 29184, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x128333b0
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x128333b0, 29248, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12832140
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x12832140, 29312, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12832290
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x12832290, 29376, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12832f20
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x12832f20, 29440, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12833070
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x12833070, 29504, 64, read, data, 1)
10280: hybrid_memory.accessCompleted(0x12833070, 29504, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 64
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x128393a0
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: dram.access(0x128393a0, 29568, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 13
10280: hybrid_memory.process: blocksLeftToWrite: 64
10280: hybrid_memory.process: pcm.access(0x12833070, 4203328, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 63
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 63
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12838110
10280: hybrid_memory.process: blocksLeftToWrite: 63
10280: hybrid_memory.process: dram.access(0x12838110, 29632, 64, read, data, 1)
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12839470
10280: hybrid_memory.process: blocksLeftToWrite: 63
10280: hybrid_memory.process: dram.access(0x12839470, 29696, 64, read, data, 1)
10280: hybrid_memory.accessCompleted(0x12839470, 29696, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 63
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12839540
10280: hybrid_memory.process: blocksLeftToWrite: 63
10280: hybrid_memory.process: dram.access(0x12839540, 29760, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 16
10280: hybrid_memory.process: blocksLeftToWrite: 63
10280: hybrid_memory.process: pcm.access(0x12839470, 4203520, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 62
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 62
10280: hybrid_memory.accessCompleted(0x12839540, 29760, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 62
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12839610
10280: hybrid_memory.process: blocksLeftToWrite: 62
10280: hybrid_memory.process: dram.access(0x12839610, 29824, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 17
10280: hybrid_memory.process: blocksLeftToWrite: 62
10280: hybrid_memory.process: pcm.access(0x12839540, 4203584, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 61
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 61
10280: hybrid_memory.accessCompleted(0x12839610, 29824, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 61
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x128396e0
10280: hybrid_memory.process: blocksLeftToWrite: 61
10280: hybrid_memory.process: dram.access(0x128396e0, 29888, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 18
10280: hybrid_memory.process: blocksLeftToWrite: 61
10280: hybrid_memory.process: pcm.access(0x12839610, 4203648, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 60
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 60
10280: hybrid_memory.accessCompleted(0x128396e0, 29888, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 60
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x128397b0
10280: hybrid_memory.process: blocksLeftToWrite: 60
10280: hybrid_memory.process: dram.access(0x128397b0, 29952, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 19
10280: hybrid_memory.process: blocksLeftToWrite: 60
10280: hybrid_memory.process: pcm.access(0x128396e0, 4203712, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 59
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 59
10280: hybrid_memory.accessCompleted(0x128397b0, 29952, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 59
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12839a80
10280: hybrid_memory.process: blocksLeftToWrite: 59
10280: hybrid_memory.process: dram.access(0x12839a80, 30016, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 20
10280: hybrid_memory.process: blocksLeftToWrite: 59
10280: hybrid_memory.process: pcm.access(0x128397b0, 4203776, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 58
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 58
10280: hybrid_memory.accessCompleted(0x12839a80, 30016, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 58
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x128391a0
10280: hybrid_memory.process: blocksLeftToWrite: 58
10280: hybrid_memory.process: dram.access(0x128391a0, 30080, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 21
10280: hybrid_memory.process: blocksLeftToWrite: 58
10280: hybrid_memory.process: pcm.access(0x12839a80, 4203840, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 57
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 57
10280: hybrid_memory.accessCompleted(0x128391a0, 30080, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 57
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12839b50
10280: hybrid_memory.process: blocksLeftToWrite: 57
10280: hybrid_memory.process: dram.access(0x12839b50, 30144, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 22
10280: hybrid_memory.process: blocksLeftToWrite: 57
10280: hybrid_memory.process: pcm.access(0x128391a0, 4203904, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 56
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 56
10280: hybrid_memory.accessCompleted(0x12839b50, 30144, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 56
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12839c20
10280: hybrid_memory.process: blocksLeftToWrite: 56
10280: hybrid_memory.process: dram.access(0x12839c20, 30208, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 23
10280: hybrid_memory.process: blocksLeftToWrite: 56
10280: hybrid_memory.process: pcm.access(0x12839b50, 4203968, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 55
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 55
10280: hybrid_memory.accessCompleted(0x12839c20, 30208, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 55
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12839cf0
10280: hybrid_memory.process: blocksLeftToWrite: 55
10280: hybrid_memory.process: dram.access(0x12839cf0, 30272, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 24
10280: hybrid_memory.process: blocksLeftToWrite: 55
10280: hybrid_memory.process: pcm.access(0x12839c20, 4204032, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 54
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 54
10280: hybrid_memory.accessCompleted(0x12839cf0, 30272, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 54
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12839fc0
10280: hybrid_memory.process: blocksLeftToWrite: 54
10280: hybrid_memory.process: dram.access(0x12839fc0, 30336, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 25
10280: hybrid_memory.process: blocksLeftToWrite: 54
10280: hybrid_memory.process: pcm.access(0x12839cf0, 4204096, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 53
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 53
10280: hybrid_memory.accessCompleted(0x12839fc0, 30336, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 53
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12839880
10280: hybrid_memory.process: blocksLeftToWrite: 53
10280: hybrid_memory.process: dram.access(0x12839880, 30400, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 26
10280: hybrid_memory.process: blocksLeftToWrite: 53
10280: hybrid_memory.process: pcm.access(0x12839fc0, 4204160, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 52
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 52
10280: hybrid_memory.accessCompleted(0x12839880, 30400, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 52
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283a090
10280: hybrid_memory.process: blocksLeftToWrite: 52
10280: hybrid_memory.process: dram.access(0x1283a090, 30464, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 27
10280: hybrid_memory.process: blocksLeftToWrite: 52
10280: hybrid_memory.process: pcm.access(0x12839880, 4204224, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 51
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 51
10280: hybrid_memory.accessCompleted(0x1283a090, 30464, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 51
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283a160
10280: hybrid_memory.process: blocksLeftToWrite: 51
10280: hybrid_memory.process: dram.access(0x1283a160, 30528, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 28
10280: hybrid_memory.process: blocksLeftToWrite: 51
10280: hybrid_memory.process: pcm.access(0x1283a090, 4204288, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 50
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 50
10280: hybrid_memory.accessCompleted(0x1283a160, 30528, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 50
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283a230
10280: hybrid_memory.process: blocksLeftToWrite: 50
10280: hybrid_memory.process: dram.access(0x1283a230, 30592, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 29
10280: hybrid_memory.process: blocksLeftToWrite: 50
10280: hybrid_memory.process: pcm.access(0x1283a160, 4204352, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 49
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 49
10280: hybrid_memory.accessCompleted(0x1283a230, 30592, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 49
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283a300
10280: hybrid_memory.process: blocksLeftToWrite: 49
10280: hybrid_memory.process: dram.access(0x1283a300, 30656, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 30
10280: hybrid_memory.process: blocksLeftToWrite: 49
10280: hybrid_memory.process: pcm.access(0x1283a230, 4204416, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 48
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 48
10280: hybrid_memory.accessCompleted(0x1283a300, 30656, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 48
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12839dc0
10280: hybrid_memory.process: blocksLeftToWrite: 48
10280: hybrid_memory.process: dram.access(0x12839dc0, 30720, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 31
10280: hybrid_memory.process: blocksLeftToWrite: 48
10280: hybrid_memory.process: pcm.access(0x1283a300, 4204480, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 47
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 47
10280: hybrid_memory.accessCompleted(0x12839dc0, 30720, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 47
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12839ed0
10280: hybrid_memory.process: blocksLeftToWrite: 47
10280: hybrid_memory.process: dram.access(0x12839ed0, 30784, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 32
10280: hybrid_memory.process: blocksLeftToWrite: 47
10280: hybrid_memory.process: pcm.access(0x12839dc0, 4204544, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 46
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 46
10280: hybrid_memory.accessCompleted(0x12839ed0, 30784, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 46
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283a5d0
10280: hybrid_memory.process: blocksLeftToWrite: 46
10280: hybrid_memory.process: dram.access(0x1283a5d0, 30848, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 33
10280: hybrid_memory.process: blocksLeftToWrite: 46
10280: hybrid_memory.process: pcm.access(0x12839ed0, 4204608, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 45
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 45
10280: hybrid_memory.accessCompleted(0x1283a5d0, 30848, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 45
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283a6a0
10280: hybrid_memory.process: blocksLeftToWrite: 45
10280: hybrid_memory.process: dram.access(0x1283a6a0, 30912, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 34
10280: hybrid_memory.process: blocksLeftToWrite: 45
10280: hybrid_memory.process: pcm.access(0x1283a5d0, 4204672, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 44
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 44
10280: hybrid_memory.accessCompleted(0x1283a6a0, 30912, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 44
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283a770
10280: hybrid_memory.process: blocksLeftToWrite: 44
10280: hybrid_memory.process: dram.access(0x1283a770, 30976, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 35
10280: hybrid_memory.process: blocksLeftToWrite: 44
10280: hybrid_memory.process: pcm.access(0x1283a6a0, 4204736, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 43
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 43
10280: hybrid_memory.accessCompleted(0x1283a770, 30976, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 43
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283a3d0
10280: hybrid_memory.process: blocksLeftToWrite: 43
10280: hybrid_memory.process: dram.access(0x1283a3d0, 31040, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 36
10280: hybrid_memory.process: blocksLeftToWrite: 43
10280: hybrid_memory.process: pcm.access(0x1283a770, 4204800, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 42
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 42
10280: hybrid_memory.accessCompleted(0x1283a3d0, 31040, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 42
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283a4a0
10280: hybrid_memory.process: blocksLeftToWrite: 42
10280: hybrid_memory.process: dram.access(0x1283a4a0, 31104, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 37
10280: hybrid_memory.process: blocksLeftToWrite: 42
10280: hybrid_memory.process: pcm.access(0x1283a3d0, 4204864, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 41
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 41
10280: hybrid_memory.accessCompleted(0x1283a4a0, 31104, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 41
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12835060
10280: hybrid_memory.process: blocksLeftToWrite: 41
10280: hybrid_memory.process: dram.access(0x12835060, 31168, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 38
10280: hybrid_memory.process: blocksLeftToWrite: 41
10280: hybrid_memory.process: pcm.access(0x1283a4a0, 4204928, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 40
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 40
10280: hybrid_memory.accessCompleted(0x12835060, 31168, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 40
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12835170
10280: hybrid_memory.process: blocksLeftToWrite: 40
10280: hybrid_memory.process: dram.access(0x12835170, 31232, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 39
10280: hybrid_memory.process: blocksLeftToWrite: 40
10280: hybrid_memory.process: pcm.access(0x12835060, 4204992, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 39
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 39
10280: hybrid_memory.accessCompleted(0x12835170, 31232, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 39
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x12835280
10280: hybrid_memory.process: blocksLeftToWrite: 39
10280: hybrid_memory.process: dram.access(0x12835280, 31296, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 40
10280: hybrid_memory.process: blocksLeftToWrite: 39
10280: hybrid_memory.process: pcm.access(0x12835170, 4205056, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 38
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 38
10280: hybrid_memory.accessCompleted(0x12835280, 31296, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 38
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283b250
10280: hybrid_memory.process: blocksLeftToWrite: 38
10280: hybrid_memory.process: dram.access(0x1283b250, 31360, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 41
10280: hybrid_memory.process: blocksLeftToWrite: 38
10280: hybrid_memory.process: pcm.access(0x12835280, 4205120, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 37
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 37
10280: hybrid_memory.accessCompleted(0x1283b250, 31360, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 37
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283a840
10280: hybrid_memory.process: blocksLeftToWrite: 37
10280: hybrid_memory.process: dram.access(0x1283a840, 31424, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 42
10280: hybrid_memory.process: blocksLeftToWrite: 37
10280: hybrid_memory.process: pcm.access(0x1283b250, 4205184, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 36
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 36
10280: hybrid_memory.accessCompleted(0x1283a840, 31424, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 36
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283a950
10280: hybrid_memory.process: blocksLeftToWrite: 36
10280: hybrid_memory.process: dram.access(0x1283a950, 31488, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 43
10280: hybrid_memory.process: blocksLeftToWrite: 36
10280: hybrid_memory.process: pcm.access(0x1283a840, 4205248, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 35
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 35
10280: hybrid_memory.accessCompleted(0x1283a950, 31488, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 35
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283b320
10280: hybrid_memory.process: blocksLeftToWrite: 35
10280: hybrid_memory.process: dram.access(0x1283b320, 31552, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 44
10280: hybrid_memory.process: blocksLeftToWrite: 35
10280: hybrid_memory.process: pcm.access(0x1283a950, 4205312, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 34
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 34
10280: hybrid_memory.accessCompleted(0x1283b320, 31552, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 34
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283b3f0
10280: hybrid_memory.process: blocksLeftToWrite: 34
10280: hybrid_memory.process: dram.access(0x1283b3f0, 31616, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 45
10280: hybrid_memory.process: blocksLeftToWrite: 34
10280: hybrid_memory.process: pcm.access(0x1283b320, 4205376, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 33
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 33
10280: hybrid_memory.accessCompleted(0x1283b3f0, 31616, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 33
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283b6c0
10280: hybrid_memory.process: blocksLeftToWrite: 33
10280: hybrid_memory.process: dram.access(0x1283b6c0, 31680, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 46
10280: hybrid_memory.process: blocksLeftToWrite: 33
10280: hybrid_memory.process: pcm.access(0x1283b3f0, 4205440, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 32
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 32
10280: hybrid_memory.accessCompleted(0x1283b6c0, 31680, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 32
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283b050
10280: hybrid_memory.process: blocksLeftToWrite: 32
10280: hybrid_memory.process: dram.access(0x1283b050, 31744, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 47
10280: hybrid_memory.process: blocksLeftToWrite: 32
10280: hybrid_memory.process: pcm.access(0x1283b6c0, 4205504, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 31
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 31
10280: hybrid_memory.accessCompleted(0x1283b050, 31744, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 31
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283b120
10280: hybrid_memory.process: blocksLeftToWrite: 31
10280: hybrid_memory.process: dram.access(0x1283b120, 31808, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 48
10280: hybrid_memory.process: blocksLeftToWrite: 31
10280: hybrid_memory.process: pcm.access(0x1283b050, 4205568, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 30
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 30
10280: hybrid_memory.accessCompleted(0x1283b120, 31808, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 30
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283b790
10280: hybrid_memory.process: blocksLeftToWrite: 30
10280: hybrid_memory.process: dram.access(0x1283b790, 31872, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 49
10280: hybrid_memory.process: blocksLeftToWrite: 30
10280: hybrid_memory.process: pcm.access(0x1283b120, 4205632, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 29
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 29
10280: hybrid_memory.accessCompleted(0x1283b790, 31872, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 29
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283b8a0
10280: hybrid_memory.process: blocksLeftToWrite: 29
10280: hybrid_memory.process: dram.access(0x1283b8a0, 31936, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 50
10280: hybrid_memory.process: blocksLeftToWrite: 29
10280: hybrid_memory.process: pcm.access(0x1283b790, 4205696, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 28
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 28
10280: hybrid_memory.accessCompleted(0x1283b8a0, 31936, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 28
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283b9b0
10280: hybrid_memory.process: blocksLeftToWrite: 28
10280: hybrid_memory.process: dram.access(0x1283b9b0, 32000, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 51
10280: hybrid_memory.process: blocksLeftToWrite: 28
10280: hybrid_memory.process: pcm.access(0x1283b8a0, 4205760, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 27
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 27
10280: hybrid_memory.accessCompleted(0x1283b9b0, 32000, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 27
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283b4c0
10280: hybrid_memory.process: blocksLeftToWrite: 27
10280: hybrid_memory.process: dram.access(0x1283b4c0, 32064, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 52
10280: hybrid_memory.process: blocksLeftToWrite: 27
10280: hybrid_memory.process: pcm.access(0x1283b9b0, 4205824, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 26
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 26
10280: hybrid_memory.accessCompleted(0x1283b4c0, 32064, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 26
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283b5d0
10280: hybrid_memory.process: blocksLeftToWrite: 26
10280: hybrid_memory.process: dram.access(0x1283b5d0, 32128, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 53
10280: hybrid_memory.process: blocksLeftToWrite: 26
10280: hybrid_memory.process: pcm.access(0x1283b4c0, 4205888, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 25
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 25
10280: hybrid_memory.accessCompleted(0x1283b5d0, 32128, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 25
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283bd00
10280: hybrid_memory.process: blocksLeftToWrite: 25
10280: hybrid_memory.process: dram.access(0x1283bd00, 32192, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 54
10280: hybrid_memory.process: blocksLeftToWrite: 25
10280: hybrid_memory.process: pcm.access(0x1283b5d0, 4205952, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 24
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 24
10280: hybrid_memory.accessCompleted(0x1283bd00, 32192, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 24
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283be10
10280: hybrid_memory.process: blocksLeftToWrite: 24
10280: hybrid_memory.process: dram.access(0x1283be10, 32256, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 55
10280: hybrid_memory.process: blocksLeftToWrite: 24
10280: hybrid_memory.process: pcm.access(0x1283bd00, 4206016, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 23
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 23
10280: hybrid_memory.accessCompleted(0x1283be10, 32256, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 23
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283bf20
10280: hybrid_memory.process: blocksLeftToWrite: 23
10280: hybrid_memory.process: dram.access(0x1283bf20, 32320, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 56
10280: hybrid_memory.process: blocksLeftToWrite: 23
10280: hybrid_memory.process: pcm.access(0x1283be10, 4206080, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 22
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 22
10280: hybrid_memory.accessCompleted(0x1283bf20, 32320, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 22
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283ba80
10280: hybrid_memory.process: blocksLeftToWrite: 22
10280: hybrid_memory.process: dram.access(0x1283ba80, 32384, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 57
10280: hybrid_memory.process: blocksLeftToWrite: 22
10280: hybrid_memory.process: pcm.access(0x1283bf20, 4206144, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 21
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 21
10280: hybrid_memory.accessCompleted(0x1283ba80, 32384, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 21
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283bb90
10280: hybrid_memory.process: blocksLeftToWrite: 21
10280: hybrid_memory.process: dram.access(0x1283bb90, 32448, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 58
10280: hybrid_memory.process: blocksLeftToWrite: 21
10280: hybrid_memory.process: pcm.access(0x1283ba80, 4206208, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 20
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 20
10280: hybrid_memory.accessCompleted(0x1283bb90, 32448, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 20
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283c270
10280: hybrid_memory.process: blocksLeftToWrite: 20
10280: hybrid_memory.process: dram.access(0x1283c270, 32512, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 59
10280: hybrid_memory.process: blocksLeftToWrite: 20
10280: hybrid_memory.process: pcm.access(0x1283bb90, 4206272, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 19
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 19
10280: hybrid_memory.accessCompleted(0x1283c270, 32512, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 19
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283c380
10280: hybrid_memory.process: blocksLeftToWrite: 19
10280: hybrid_memory.process: dram.access(0x1283c380, 32576, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 60
10280: hybrid_memory.process: blocksLeftToWrite: 19
10280: hybrid_memory.process: pcm.access(0x1283c270, 4206336, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 18
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 18
10280: hybrid_memory.accessCompleted(0x1283c380, 32576, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 18
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283c490
10280: hybrid_memory.process: blocksLeftToWrite: 18
10280: hybrid_memory.process: dram.access(0x1283c490, 32640, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 61
10280: hybrid_memory.process: blocksLeftToWrite: 18
10280: hybrid_memory.process: pcm.access(0x1283c380, 4206400, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 17
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 17
10280: hybrid_memory.accessCompleted(0x1283c490, 32640, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 17
10280: hybrid_memory.process(): type: 1, page 7
10280: hybrid_memory.process: new memoryRequest: 0x1283c7a0
10280: hybrid_memory.process: blocksLeftToWrite: 17
10280: hybrid_memory.process: dram.access(0x1283c7a0, 32704, 64, read, data, 1)
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 62
10280: hybrid_memory.process: blocksLeftToWrite: 17
10280: hybrid_memory.process: pcm.access(0x1283c490, 4206464, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 16
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 16
10280: hybrid_memory.accessCompleted(0x1283c7a0, 32704, 64, read, dram)
10280: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 16
10280: hybrid_memory.process(): type: 2, page 7
10280: hybrid_memory.process: nextWriteBlock: 63
10280: hybrid_memory.process: blocksLeftToWrite: 16
10280: hybrid_memory.process: pcm.access(0x1283c7a0, 4206528, 64, write, data, 1
10280: hybrid_memory.process: not stalled
10280: hybrid_memory.process: blocksLeftToWrite: 15
10280: hybrid_memory.process: adding event: blocksLeftToWrite: 15
11275: hybrid_memory.accessCompleted(0x1282f630, 28672, 64, read, dram)
11275: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 15
11275: hybrid_memory.process(): type: 2, page 7
11275: hybrid_memory.process: nextWriteBlock: 0
11275: hybrid_memory.process: blocksLeftToWrite: 15
11275: hybrid_memory.process: pcm.access(0x1282f630, 4202496, 64, write, data, 1
11275: hybrid_memory.process: not stalled
11275: hybrid_memory.process: blocksLeftToWrite: 14
11275: hybrid_memory.process: adding event: blocksLeftToWrite: 14
11291: hybrid_memory.accessCompleted(0x1282f930, 28736, 64, read, dram)
11291: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 14
11291: hybrid_memory.process(): type: 2, page 7
11291: hybrid_memory.process: nextWriteBlock: 1
11291: hybrid_memory.process: blocksLeftToWrite: 14
11291: hybrid_memory.process: pcm.access(0x1282f930, 4202560, 64, write, data, 1
11291: hybrid_memory.process: not stalled
11291: hybrid_memory.process: blocksLeftToWrite: 13
11291: hybrid_memory.process: adding event: blocksLeftToWrite: 13
11307: hybrid_memory.accessCompleted(0x12831ad0, 28800, 64, read, dram)
11307: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 13
11307: hybrid_memory.process(): type: 2, page 7
11307: hybrid_memory.process: nextWriteBlock: 2
11307: hybrid_memory.process: blocksLeftToWrite: 13
11307: hybrid_memory.process: pcm.access(0x12831ad0, 4202624, 64, write, data, 1
11307: hybrid_memory.process: not stalled
11307: hybrid_memory.process: blocksLeftToWrite: 12
11307: hybrid_memory.process: adding event: blocksLeftToWrite: 12
11323: hybrid_memory.accessCompleted(0x2608a10, 28864, 64, read, dram)
11323: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 12
11323: hybrid_memory.process(): type: 2, page 7
11323: hybrid_memory.process: nextWriteBlock: 3
11323: hybrid_memory.process: blocksLeftToWrite: 12
11323: hybrid_memory.process: pcm.access(0x2608a10, 4202688, 64, write, data, 1
11323: hybrid_memory.process: not stalled
11323: hybrid_memory.process: blocksLeftToWrite: 11
11323: hybrid_memory.process: adding event: blocksLeftToWrite: 11
11339: hybrid_memory.accessCompleted(0x12833f30, 28928, 64, read, dram)
11339: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 11
11339: hybrid_memory.process(): type: 2, page 7
11339: hybrid_memory.process: nextWriteBlock: 4
11339: hybrid_memory.process: blocksLeftToWrite: 11
11339: hybrid_memory.process: pcm.access(0x12833f30, 4202752, 64, write, data, 1
11339: hybrid_memory.process: not stalled
11339: hybrid_memory.process: blocksLeftToWrite: 10
11339: hybrid_memory.process: adding event: blocksLeftToWrite: 10
11355: hybrid_memory.accessCompleted(0x2608710, 28992, 64, read, dram)
11355: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 10
11355: hybrid_memory.process(): type: 2, page 7
11355: hybrid_memory.process: nextWriteBlock: 5
11355: hybrid_memory.process: blocksLeftToWrite: 10
11355: hybrid_memory.process: pcm.access(0x2608710, 4202816, 64, write, data, 1
11355: hybrid_memory.process: not stalled
11355: hybrid_memory.process: blocksLeftToWrite: 9
11355: hybrid_memory.process: adding event: blocksLeftToWrite: 9
11371: hybrid_memory.accessCompleted(0x1282e390, 29056, 64, read, dram)
11371: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 9
11371: hybrid_memory.process(): type: 2, page 7
11371: hybrid_memory.process: nextWriteBlock: 6
11371: hybrid_memory.process: blocksLeftToWrite: 9
11371: hybrid_memory.process: pcm.access(0x1282e390, 4202880, 64, write, data, 1
11371: hybrid_memory.process: not stalled
11371: hybrid_memory.process: blocksLeftToWrite: 8
11371: hybrid_memory.process: adding event: blocksLeftToWrite: 8
11387: hybrid_memory.accessCompleted(0x1282e540, 29120, 64, read, dram)
11387: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 8
11387: hybrid_memory.process(): type: 2, page 7
11387: hybrid_memory.process: nextWriteBlock: 7
11387: hybrid_memory.process: blocksLeftToWrite: 8
11387: hybrid_memory.process: pcm.access(0x1282e540, 4202944, 64, write, data, 1
11387: hybrid_memory.process: not stalled
11387: hybrid_memory.process: blocksLeftToWrite: 7
11387: hybrid_memory.process: adding event: blocksLeftToWrite: 7
11403: hybrid_memory.accessCompleted(0x2608220, 29184, 64, read, dram)
11403: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 7
11403: hybrid_memory.process(): type: 2, page 7
11403: hybrid_memory.process: nextWriteBlock: 8
11403: hybrid_memory.process: blocksLeftToWrite: 7
11403: hybrid_memory.process: pcm.access(0x2608220, 4203008, 64, write, data, 1
11403: hybrid_memory.process: not stalled
11403: hybrid_memory.process: blocksLeftToWrite: 6
11403: hybrid_memory.process: adding event: blocksLeftToWrite: 6
11419: hybrid_memory.accessCompleted(0x128333b0, 29248, 64, read, dram)
11419: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 6
11419: hybrid_memory.process(): type: 2, page 7
11419: hybrid_memory.process: nextWriteBlock: 9
11419: hybrid_memory.process: blocksLeftToWrite: 6
11419: hybrid_memory.process: pcm.access(0x128333b0, 4203072, 64, write, data, 1
11419: hybrid_memory.process: not stalled
11419: hybrid_memory.process: blocksLeftToWrite: 5
11419: hybrid_memory.process: adding event: blocksLeftToWrite: 5
11435: hybrid_memory.accessCompleted(0x12832140, 29312, 64, read, dram)
11435: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 5
11435: hybrid_memory.process(): type: 2, page 7
11435: hybrid_memory.process: nextWriteBlock: 10
11435: hybrid_memory.process: blocksLeftToWrite: 5
11435: hybrid_memory.process: pcm.access(0x12832140, 4203136, 64, write, data, 1
11435: hybrid_memory.process: not stalled
11435: hybrid_memory.process: blocksLeftToWrite: 4
11435: hybrid_memory.process: adding event: blocksLeftToWrite: 4
11451: hybrid_memory.accessCompleted(0x12832290, 29376, 64, read, dram)
11451: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 4
11451: hybrid_memory.process(): type: 2, page 7
11451: hybrid_memory.process: nextWriteBlock: 11
11451: hybrid_memory.process: blocksLeftToWrite: 4
11451: hybrid_memory.process: pcm.access(0x12832290, 4203200, 64, write, data, 1
11451: hybrid_memory.process: not stalled
11451: hybrid_memory.process: blocksLeftToWrite: 3
11451: hybrid_memory.process: adding event: blocksLeftToWrite: 3
11467: hybrid_memory.accessCompleted(0x12832f20, 29440, 64, read, dram)
11467: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 3
11467: hybrid_memory.process(): type: 2, page 7
11467: hybrid_memory.process: nextWriteBlock: 12
11467: hybrid_memory.process: blocksLeftToWrite: 3
11467: hybrid_memory.process: pcm.access(0x12832f20, 4203264, 64, write, data, 1
11467: hybrid_memory.process: not stalled
11467: hybrid_memory.process: blocksLeftToWrite: 2
11467: hybrid_memory.process: adding event: blocksLeftToWrite: 2
11483: hybrid_memory.accessCompleted(0x128393a0, 29568, 64, read, dram)
11483: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 2
11483: hybrid_memory.process(): type: 2, page 7
11483: hybrid_memory.process: nextWriteBlock: 14
11483: hybrid_memory.process: blocksLeftToWrite: 2
11483: hybrid_memory.process: pcm.access(0x128393a0, 4203392, 64, write, data, 1
11483: hybrid_memory.process: not stalled
11483: hybrid_memory.process: blocksLeftToWrite: 1
11483: hybrid_memory.process: adding event: blocksLeftToWrite: 1
11499: hybrid_memory.accessCompleted(0x12838110, 29632, 64, read, dram)
11499: hybrid_memory.accessCompleted: adding event: blocksLeftToWrite: 1
11499: hybrid_memory.process(): type: 2, page 7
11499: hybrid_memory.process: nextWriteBlock: 15
11499: hybrid_memory.process: blocksLeftToWrite: 1
11499: hybrid_memory.process: pcm.access(0x12838110, 4203456, 64, write, data, 1
11499: hybrid_memory.process: not stalled
11499: hybrid_memory.process: blocksLeftToWrite: 0
11499: hybrid_memory.process: finish copy, src: dram, dest: pcm
11535: hybrid_memory.access(0x128338d0, 4202688, 64, write, data, 0, HybridMemoryManager)
11535: hybrid_memory.access(0x12833a20, 4202944, 64, write, data, 0, HybridMemoryManager)
11535: hybrid_memory.access(0x12833b70, 4202752, 64, write, data, 0, HybridMemoryManager)
11535: hybrid_memory.access(0x12834d80, 4202816, 64, write, data, 0, HybridMemoryManager)
11535: hybrid_memory.access(0x1283c270, 4202880, 64, write, data, 0, HybridMemoryManager)
11535: hybrid_memory.access(0x12834ed0, 4202496, 64, write, data, 0, HybridMemoryManager)
11535: hybrid_memory.access(0x2608470, 4202560, 64, write, data, 0, HybridMemoryManager)
11535: hybrid_memory.access(0x12833070, 4202624, 64, write, data, 0, HybridMemoryManager)
11570: hybrid_memory.access(0x12830760, 4203264, 64, write, data, 0, HybridMemoryManager)
11570: hybrid_memory.access(0x128308b0, 4203328, 64, write, data, 0, HybridMemoryManager)
11570: hybrid_memory.access(0x1283bf20, 4203392, 64, write, data, 0, HybridMemoryManager)
11570: hybrid_memory.access(0x1283be10, 4203456, 64, write, data, 0, HybridMemoryManager)
11570: hybrid_memory.access(0x128301c0, 4203008, 64, write, data, 0, HybridMemoryManager)
11570: hybrid_memory.access(0x12837a20, 4203072, 64, write, data, 0, HybridMemoryManager)
11570: hybrid_memory.access(0x1283bd00, 4203136, 64, write, data, 0, HybridMemoryManager)
11570: hybrid_memory.access(0x12838420, 4203200, 64, write, data, 0, HybridMemoryManager)
11605: hybrid_memory.access(0x12833580, 4203648, 64, write, data, 0, HybridMemoryManager)
11605: hybrid_memory.access(0x1283b8a0, 4203904, 64, write, data, 0, HybridMemoryManager)
11605: hybrid_memory.access(0x1283b790, 4203968, 64, write, data, 0, HybridMemoryManager)
11605: hybrid_memory.access(0x12839880, 4203712, 64, write, data, 0, HybridMemoryManager)
11605: hybrid_memory.access(0x1283b4c0, 4203776, 64, write, data, 0, HybridMemoryManager)
11605: hybrid_memory.access(0x1283a840, 4203840, 64, write, data, 0, HybridMemoryManager)
11605: hybrid_memory.access(0x1282ffd0, 4203520, 64, write, data, 0, HybridMemoryManager)
11605: hybrid_memory.access(0x12835350, 4203584, 64, write, data, 0, HybridMemoryManager)
11640: hybrid_memory.access(0x12835170, 4204032, 64, write, data, 0, HybridMemoryManager)
11640: hybrid_memory.access(0x128300a0, 4204288, 64, write, data, 0, HybridMemoryManager)
11640: hybrid_memory.access(0x12833c40, 4204416, 64, write, data, 0, HybridMemoryManager)
11640: hybrid_memory.access(0x1283b5d0, 4204480, 64, write, data, 0, HybridMemoryManager)
11640: hybrid_memory.access(0x1283b230, 4204352, 64, write, data, 0, HybridMemoryManager)
11640: hybrid_memory.access(0x12831340, 4204096, 64, write, data, 0, HybridMemoryManager)
11640: hybrid_memory.access(0x1282f1d0, 4204160, 64, write, data, 0, HybridMemoryManager)
11640: hybrid_memory.access(0x1282ece0, 4204224, 64, write, data, 0, HybridMemoryManager)
11675: hybrid_memory.access(0x12834040, 4204544, 64, write, data, 0, HybridMemoryManager)
11675: hybrid_memory.access(0x128382e0, 4204608, 64, write, data, 0, HybridMemoryManager)
11675: hybrid_memory.access(0x1282e910, 4204672, 64, write, data, 0, HybridMemoryManager)
11675: hybrid_memory.access(0x12833750, 4204864, 64, write, data, 0, HybridMemoryManager)
11675: hybrid_memory.access(0x128345c0, 4204992, 64, write, data, 0, HybridMemoryManager)
11675: hybrid_memory.access(0x12830570, 4204928, 64, write, data, 0, HybridMemoryManager)
11675: hybrid_memory.access(0x12838530, 4204736, 64, write, data, 0, HybridMemoryManager)
11675: hybrid_memory.access(0x1283b9b0, 4204800, 64, write, data, 0, HybridMemoryManager)
11710: hybrid_memory.access(0x1283bb80, 4205056, 64, write, data, 0, HybridMemoryManager)
11710: hybrid_memory.access(0x12839670, 4205376, 64, write, data, 0, HybridMemoryManager)
11710: hybrid_memory.access(0x12837bb0, 4205440, 64, write, data, 0, HybridMemoryManager)
11710: hybrid_memory.access(0x12831650, 4205504, 64, write, data, 0, HybridMemoryManager)
11710: hybrid_memory.access(0x128317e0, 4205120, 64, write, data, 0, HybridMemoryManager)
11710: hybrid_memory.access(0x12834430, 4205184, 64, write, data, 0, HybridMemoryManager)
11710: hybrid_memory.access(0x128318b0, 4205248, 64, write, data, 0, HybridMemoryManager)
11710: hybrid_memory.access(0x12839e90, 4205312, 64, write, data, 0, HybridMemoryManager)
11745: hybrid_memory.access(0x12839b50, 4206016, 64, write, data, 0, HybridMemoryManager)
11745: hybrid_memory.access(0x12839c20, 4205568, 64, write, data, 0, HybridMemoryManager)
11745: hybrid_memory.access(0x1283a020, 4205632, 64, write, data, 0, HybridMemoryManager)
11745: hybrid_memory.access(0x1283a170, 4205760, 64, write, data, 0, HybridMemoryManager)
11745: hybrid_memory.access(0x1283a300, 4205888, 64, write, data, 0, HybridMemoryManager)
11745: hybrid_memory.access(0x128372a0, 4205952, 64, write, data, 0, HybridMemoryManager)
11745: hybrid_memory.access(0x128373f0, 4205824, 64, write, data, 0, HybridMemoryManager)
11745: hybrid_memory.access(0x12837580, 4205696, 64, write, data, 0, HybridMemoryManager)
11780: hybrid_memory.access(0x1283b3f0, 4206336, 64, write, data, 0, HybridMemoryManager)
11780: hybrid_memory.access(0x12837910, 4206400, 64, write, data, 0, HybridMemoryManager)
11780: hybrid_memory.access(0x12837f10, 4206464, 64, write, data, 0, HybridMemoryManager)
11780: hybrid_memory.access(0x12838020, 4206528, 64, write, data, 0, HybridMemoryManager)
11780: hybrid_memory.access(0x12832540, 4206080, 64, write, data, 0, HybridMemoryManager)
11780: hybrid_memory.access(0x128326d0, 4206144, 64, write, data, 0, HybridMemoryManager)
11780: hybrid_memory.access(0x12832820, 4206208, 64, write, data, 0, HybridMemoryManager)
11780: hybrid_memory.access(0x128329b0, 4206272, 64, write, data, 0, HybridMemoryManager)
Between timestamps 0 and 10000000 executed 2806 events (3323.68 events per second)
#Final timestamp
final_timestamp 10000000

#Total number of events
total_events 2806

#Execution time in seconds
execution_time 0.84

#Event rate in events per second
event_rate 3323.51

#Number of cycles DRAM stalls critical requests
dram_critical_stall_time 0

#Number of cycles DRAM stalls on read requests
dram_read_stall_time 0

#Number of cycles DRAM stalls on write requests
dram_write_stall_time 0

#Number of cycles DRAM queue is stalled
dram_queue_stall_time 0

#Number of DRAM read requests
dram_read_requests 96

#Number of DRAM write requests
dram_write_requests 64

#Number of cycles DRAM read requests wait in the queue
dram_read_queue_time 18446744073709257115

#Number of cycles DRAM write requests wait in the queue
dram_write_queue_time 18446744073708911571

#Total number of cycles of DRAM read requests
dram_read_total_time 36421

#Total number of cycles of DRAM write requests
dram_write_total_time 35040

#Number of DRAM row buffer hits
dram_row_buffer_hits 122

#Number of DRAM row buffer misses
dram_row_buffer_misses 38

#Number of DRAM opens
dram_num_opens 38

#Number of DRAM accesses
dram_num_accesses 160

#Number of DRAM closes
dram_num_closes 37

#Number of DRAM read after read (RAR) hazards
dram_num_read_after_read 0

#Number of DRAM read after write (RAW) hazards
dram_num_read_after_write 49

#Number of DRAM write after read (WAR) hazards
dram_num_write_after_read 0

#Number of DRAM write after write (WAW) hazards
dram_num_write_after_write 0

#Number of cycles DRAM requests wait for lower priority requests
dram_wait_lower_priority_time 0

#Number of cycles DRAM requests wait for same priority requests
dram_wait_same_priority_time 7786

#Number of cycles DRAM requests wait for higher priority requests
dram_wait_higher_priority_time 13935

#Total number of DRAM requests
dram_requests 160

#Average number of cycles DRAM queue is stalled
dram_avg_queue_stall_time 0.00

#Total number of cycles DRAM stalls on requests
dram_total_stall_time 0

#Total number of cycles DRAM requests wait in the queue
dram_total_queue_time 18446744073708617070

#Number of cycles DRAM spends servicing read requests
dram_read_service_time 330922

#Number of cycles DRAM spends servicing write requests
dram_write_service_time 675085

#Total number of cycles DRAM spends servicing requests
dram_total_service_time 1006007

#Total number of cycles of DRAM requests
dram_total_time 71461

#Average number of cycles DRAM read requests spend in the queue
dram_avg_read_queue_time 192153584101138080.00

#Average number of cycles DRAM write requests spend in the queue
dram_avg_write_queue_time 288230376151701728.00

#Average number of cycles DRAM requests spend in the queue
dram_avg_queue_time 115292150460678864.00

#Average number of cycles DRAM spends servicing read requests
dram_avg_read_service_time 3447.10

#Average number of cycles DRAM spends servicing write requests
dram_avg_write_service_time 10548.20

#Average number of cycles DRAM spends servicing requests
dram_avg_service_time 6287.54

#Average number of cycles of DRAM read requests
dram_avg_read_time 379.39

#Average number of cycles of DRAM write requests
dram_avg_write_time 547.50

#Average number of cycles of DRAM requests
dram_avg_time 446.63

#Number of DRAM row buffer misses
dram_row_buffer_accesses 160

#Number of cycles requests for DRAM bank 0 spend in the queue
dram_bank_0_queue_time 18446744073708617070

#Number of cycles DRAM bank 0 spends opening rows for requests
dram_bank_0_open_time 1900

#Number of cycles DRAM bank 0 spends accessing rows for requests
dram_bank_0_access_time 3200

#Number of cycles DRAM bank 0 spends closing rows for requests
dram_bank_0_close_time 1850

#Number of DRAM bank 0 read requests
dram_bank_0_read_requests 96

#Number of DRAM bank 0 write requests
dram_bank_0_write_requests 64

#Number of cyclesDRAM bank 0 read requests wait in the queue
dram_bank_0_read_queue_time 18446744073709257115

#Number of cyclesDRAM bank 0 write requests wait in the queue
dram_bank_0_write_queue_time 18446744073708911571

#Total number of cycles of DRAM bank 0 read requests
dram_bank_0_read_total_time 36421

#Total number of cycles of DRAM bank 0 write requests
dram_bank_0_write_total_time 35040

#Number of DRAM bank 0 row buffer hits
dram_bank_0_row_buffer_hits 122

#Number of DRAM bank 0 row buffer misses
dram_bank_0_row_buffer_misses 38

#Number of DRAM bank 0 opens
dram_bank_0_num_opens 38

#Number of DRAM bank 0 accesses
dram_bank_0_num_accesses 160

#Number of DRAM bank 0 closes
dram_bank_0_num_closes 37

#Number of DRAM bank 0 read after read (RAR) hazards
dram_bank_0_num_read_after_read 0

#Number of DRAM bank 0 read after write (RAW) hazards
dram_bank_0_num_read_after_write 49

#Number of DRAM bank 0 write after read (WAR) hazards
dram_bank_0_num_write_after_read 0

#Number of DRAM bank 0 write after write (WAW) hazards
dram_bank_0_num_write_after_write 0

#Number of cycles DRAM bank 0 requests wait for lower priority requests
dram_bank_0_wait_lower_priority_time 0

#Number of cycles DRAM bank 0 requests wait for same priority requests
dram_bank_0_wait_same_priority_time 7786

#Number of cycles DRAM bank 0 requests wait for higher priority requests
dram_bank_0_wait_higher_priority_time 13935

#Number of cycles PCM stalls critical requests
pcm_critical_stall_time 0

#Number of cycles PCM stalls on read requests
pcm_read_stall_time 0

#Number of cycles PCM stalls on write requests
pcm_write_stall_time 0

#Number of cycles PCM queue is stalled
pcm_queue_stall_time 0

#Number of PCM read requests
pcm_read_requests 9

#Number of PCM write requests
pcm_write_requests 128

#Number of cycles PCM read requests wait in the queue
pcm_read_queue_time 0

#Number of cycles PCM write requests wait in the queue
pcm_write_queue_time 18446744073709219961

#Total number of cycles of PCM read requests
pcm_read_total_time 2790

#Total number of cycles of PCM write requests
pcm_write_total_time 231875

#Number of PCM row buffer hits
pcm_row_buffer_hits 37

#Number of PCM row buffer misses
pcm_row_buffer_misses 100

#Number of PCM opens
pcm_num_opens 100

#Number of PCM accesses
pcm_num_accesses 137

#Number of PCM closes
pcm_num_closes 99

#Number of PCM read after read (RAR) hazards
pcm_num_read_after_read 0

#Number of PCM read after write (RAW) hazards
pcm_num_read_after_write 0

#Number of PCM write after read (WAR) hazards
pcm_num_write_after_read 0

#Number of PCM write after write (WAW) hazards
pcm_num_write_after_write 0

#Number of cycles PCM requests wait for lower priority requests
pcm_wait_lower_priority_time 0

#Number of cycles PCM requests wait for same priority requests
pcm_wait_same_priority_time 0

#Number of cycles PCM requests wait for higher priority requests
pcm_wait_higher_priority_time 0

#Total number of PCM requests
pcm_requests 137

#Average number of cycles PCM queue is stalled
pcm_avg_queue_stall_time 0.00

#Total number of cycles PCM stalls on requests
pcm_total_stall_time 0

#Total number of cycles PCM requests wait in the queue
pcm_total_queue_time 18446744073709219961

#Number of cycles PCM spends servicing read requests
pcm_read_service_time 2790

#Number of cycles PCM spends servicing write requests
pcm_write_service_time 563530

#Total number of cycles PCM spends servicing requests
pcm_total_service_time 566320

#Total number of cycles of PCM requests
pcm_total_time 234665

#Average number of cycles PCM read requests spend in the queue
pcm_avg_read_queue_time 0.00

#Average number of cycles PCM write requests spend in the queue
pcm_avg_write_queue_time 144115188075853280.00

#Average number of cycles PCM requests spend in the queue
pcm_avg_queue_time 134647766961381168.00

#Average number of cycles PCM spends servicing read requests
pcm_avg_read_service_time 310.00

#Average number of cycles PCM spends servicing write requests
pcm_avg_write_service_time 4402.58

#Average number of cycles PCM spends servicing requests
pcm_avg_service_time 4133.72

#Average number of cycles of PCM read requests
pcm_avg_read_time 310.00

#Average number of cycles of PCM write requests
pcm_avg_write_time 1811.52

#Average number of cycles of PCM requests
pcm_avg_time 1712.88

#Number of PCM row buffer misses
pcm_row_buffer_accesses 137

#Number of cycles requests for PCM bank 0 spend in the queue
pcm_bank_0_queue_time 18446744073709540081

#Number of cycles PCM bank 0 spends opening rows for requests
pcm_bank_0_open_time 220

#Number of cycles PCM bank 0 spends accessing rows for requests
pcm_bank_0_access_time 100

#Number of cycles PCM bank 0 spends closing rows for requests
pcm_bank_0_close_time 0

#Number of PCM bank 0 read requests
pcm_bank_0_read_requests 0

#Number of PCM bank 0 write requests
pcm_bank_0_write_requests 2

#Number of cyclesPCM bank 0 read requests wait in the queue
pcm_bank_0_read_queue_time 0

#Number of cyclesPCM bank 0 write requests wait in the queue
pcm_bank_0_write_queue_time 18446744073709540081

#Total number of cycles of PCM bank 0 read requests
pcm_bank_0_read_total_time 0

#Total number of cycles of PCM bank 0 write requests
pcm_bank_0_write_total_time 2010

#Number of PCM bank 0 row buffer hits
pcm_bank_0_row_buffer_hits 1

#Number of PCM bank 0 row buffer misses
pcm_bank_0_row_buffer_misses 1

#Number of PCM bank 0 opens
pcm_bank_0_num_opens 1

#Number of PCM bank 0 accesses
pcm_bank_0_num_accesses 2

#Number of PCM bank 0 closes
pcm_bank_0_num_closes 1

#Number of PCM bank 0 read after read (RAR) hazards
pcm_bank_0_num_read_after_read 0

#Number of PCM bank 0 read after write (RAW) hazards
pcm_bank_0_num_read_after_write 0

#Number of PCM bank 0 write after read (WAR) hazards
pcm_bank_0_num_write_after_read 0

#Number of PCM bank 0 write after write (WAW) hazards
pcm_bank_0_num_write_after_write 0

#Number of cycles PCM bank 0 requests wait for lower priority requests
pcm_bank_0_wait_lower_priority_time 0

#Number of cycles PCM bank 0 requests wait for same priority requests
pcm_bank_0_wait_same_priority_time 0

#Number of cycles PCM bank 0 requests wait for higher priority requests
pcm_bank_0_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 1 spend in the queue
pcm_bank_1_queue_time 18446744073709540081

#Number of cycles PCM bank 1 spends opening rows for requests
pcm_bank_1_open_time 220

#Number of cycles PCM bank 1 spends accessing rows for requests
pcm_bank_1_access_time 100

#Number of cycles PCM bank 1 spends closing rows for requests
pcm_bank_1_close_time 0

#Number of PCM bank 1 read requests
pcm_bank_1_read_requests 0

#Number of PCM bank 1 write requests
pcm_bank_1_write_requests 2

#Number of cyclesPCM bank 1 read requests wait in the queue
pcm_bank_1_read_queue_time 0

#Number of cyclesPCM bank 1 write requests wait in the queue
pcm_bank_1_write_queue_time 18446744073709540081

#Total number of cycles of PCM bank 1 read requests
pcm_bank_1_read_total_time 0

#Total number of cycles of PCM bank 1 write requests
pcm_bank_1_write_total_time 2114

#Number of PCM bank 1 row buffer hits
pcm_bank_1_row_buffer_hits 1

#Number of PCM bank 1 row buffer misses
pcm_bank_1_row_buffer_misses 1

#Number of PCM bank 1 opens
pcm_bank_1_num_opens 1

#Number of PCM bank 1 accesses
pcm_bank_1_num_accesses 2

#Number of PCM bank 1 closes
pcm_bank_1_num_closes 1

#Number of PCM bank 1 read after read (RAR) hazards
pcm_bank_1_num_read_after_read 0

#Number of PCM bank 1 read after write (RAW) hazards
pcm_bank_1_num_read_after_write 0

#Number of PCM bank 1 write after read (WAR) hazards
pcm_bank_1_num_write_after_read 0

#Number of PCM bank 1 write after write (WAW) hazards
pcm_bank_1_num_write_after_write 0

#Number of cycles PCM bank 1 requests wait for lower priority requests
pcm_bank_1_wait_lower_priority_time 0

#Number of cycles PCM bank 1 requests wait for same priority requests
pcm_bank_1_wait_same_priority_time 0

#Number of cycles PCM bank 1 requests wait for higher priority requests
pcm_bank_1_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 2 spend in the queue
pcm_bank_2_queue_time 18446744073709540081

#Number of cycles PCM bank 2 spends opening rows for requests
pcm_bank_2_open_time 220

#Number of cycles PCM bank 2 spends accessing rows for requests
pcm_bank_2_access_time 100

#Number of cycles PCM bank 2 spends closing rows for requests
pcm_bank_2_close_time 0

#Number of PCM bank 2 read requests
pcm_bank_2_read_requests 0

#Number of PCM bank 2 write requests
pcm_bank_2_write_requests 2

#Number of cyclesPCM bank 2 read requests wait in the queue
pcm_bank_2_read_queue_time 0

#Number of cyclesPCM bank 2 write requests wait in the queue
pcm_bank_2_write_queue_time 18446744073709540081

#Total number of cycles of PCM bank 2 read requests
pcm_bank_2_read_total_time 0

#Total number of cycles of PCM bank 2 write requests
pcm_bank_2_write_total_time 2178

#Number of PCM bank 2 row buffer hits
pcm_bank_2_row_buffer_hits 1

#Number of PCM bank 2 row buffer misses
pcm_bank_2_row_buffer_misses 1

#Number of PCM bank 2 opens
pcm_bank_2_num_opens 1

#Number of PCM bank 2 accesses
pcm_bank_2_num_accesses 2

#Number of PCM bank 2 closes
pcm_bank_2_num_closes 1

#Number of PCM bank 2 read after read (RAR) hazards
pcm_bank_2_num_read_after_read 0

#Number of PCM bank 2 read after write (RAW) hazards
pcm_bank_2_num_read_after_write 0

#Number of PCM bank 2 write after read (WAR) hazards
pcm_bank_2_num_write_after_read 0

#Number of PCM bank 2 write after write (WAW) hazards
pcm_bank_2_num_write_after_write 0

#Number of cycles PCM bank 2 requests wait for lower priority requests
pcm_bank_2_wait_lower_priority_time 0

#Number of cycles PCM bank 2 requests wait for same priority requests
pcm_bank_2_wait_same_priority_time 0

#Number of cycles PCM bank 2 requests wait for higher priority requests
pcm_bank_2_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 3 spend in the queue
pcm_bank_3_queue_time 18446744073709540081

#Number of cycles PCM bank 3 spends opening rows for requests
pcm_bank_3_open_time 220

#Number of cycles PCM bank 3 spends accessing rows for requests
pcm_bank_3_access_time 100

#Number of cycles PCM bank 3 spends closing rows for requests
pcm_bank_3_close_time 0

#Number of PCM bank 3 read requests
pcm_bank_3_read_requests 0

#Number of PCM bank 3 write requests
pcm_bank_3_write_requests 2

#Number of cyclesPCM bank 3 read requests wait in the queue
pcm_bank_3_read_queue_time 0

#Number of cyclesPCM bank 3 write requests wait in the queue
pcm_bank_3_write_queue_time 18446744073709540081

#Total number of cycles of PCM bank 3 read requests
pcm_bank_3_read_total_time 0

#Total number of cycles of PCM bank 3 write requests
pcm_bank_3_write_total_time 4802

#Number of PCM bank 3 row buffer hits
pcm_bank_3_row_buffer_hits 1

#Number of PCM bank 3 row buffer misses
pcm_bank_3_row_buffer_misses 1

#Number of PCM bank 3 opens
pcm_bank_3_num_opens 1

#Number of PCM bank 3 accesses
pcm_bank_3_num_accesses 2

#Number of PCM bank 3 closes
pcm_bank_3_num_closes 1

#Number of PCM bank 3 read after read (RAR) hazards
pcm_bank_3_num_read_after_read 0

#Number of PCM bank 3 read after write (RAW) hazards
pcm_bank_3_num_read_after_write 0

#Number of PCM bank 3 write after read (WAR) hazards
pcm_bank_3_num_write_after_read 0

#Number of PCM bank 3 write after write (WAW) hazards
pcm_bank_3_num_write_after_write 0

#Number of cycles PCM bank 3 requests wait for lower priority requests
pcm_bank_3_wait_lower_priority_time 0

#Number of cycles PCM bank 3 requests wait for same priority requests
pcm_bank_3_wait_same_priority_time 0

#Number of cycles PCM bank 3 requests wait for higher priority requests
pcm_bank_3_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 4 spend in the queue
pcm_bank_4_queue_time 18446744073709540081

#Number of cycles PCM bank 4 spends opening rows for requests
pcm_bank_4_open_time 220

#Number of cycles PCM bank 4 spends accessing rows for requests
pcm_bank_4_access_time 100

#Number of cycles PCM bank 4 spends closing rows for requests
pcm_bank_4_close_time 0

#Number of PCM bank 4 read requests
pcm_bank_4_read_requests 0

#Number of PCM bank 4 write requests
pcm_bank_4_write_requests 2

#Number of cyclesPCM bank 4 read requests wait in the queue
pcm_bank_4_read_queue_time 0

#Number of cyclesPCM bank 4 write requests wait in the queue
pcm_bank_4_write_queue_time 18446744073709540081

#Total number of cycles of PCM bank 4 read requests
pcm_bank_4_read_total_time 0

#Total number of cycles of PCM bank 4 write requests
pcm_bank_4_write_total_time 4866

#Number of PCM bank 4 row buffer hits
pcm_bank_4_row_buffer_hits 1

#Number of PCM bank 4 row buffer misses
pcm_bank_4_row_buffer_misses 1

#Number of PCM bank 4 opens
pcm_bank_4_num_opens 1

#Number of PCM bank 4 accesses
pcm_bank_4_num_accesses 2

#Number of PCM bank 4 closes
pcm_bank_4_num_closes 1

#Number of PCM bank 4 read after read (RAR) hazards
pcm_bank_4_num_read_after_read 0

#Number of PCM bank 4 read after write (RAW) hazards
pcm_bank_4_num_read_after_write 0

#Number of PCM bank 4 write after read (WAR) hazards
pcm_bank_4_num_write_after_read 0

#Number of PCM bank 4 write after write (WAW) hazards
pcm_bank_4_num_write_after_write 0

#Number of cycles PCM bank 4 requests wait for lower priority requests
pcm_bank_4_wait_lower_priority_time 0

#Number of cycles PCM bank 4 requests wait for same priority requests
pcm_bank_4_wait_same_priority_time 0

#Number of cycles PCM bank 4 requests wait for higher priority requests
pcm_bank_4_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 5 spend in the queue
pcm_bank_5_queue_time 18446744073709540081

#Number of cycles PCM bank 5 spends opening rows for requests
pcm_bank_5_open_time 220

#Number of cycles PCM bank 5 spends accessing rows for requests
pcm_bank_5_access_time 100

#Number of cycles PCM bank 5 spends closing rows for requests
pcm_bank_5_close_time 0

#Number of PCM bank 5 read requests
pcm_bank_5_read_requests 0

#Number of PCM bank 5 write requests
pcm_bank_5_write_requests 2

#Number of cyclesPCM bank 5 read requests wait in the queue
pcm_bank_5_read_queue_time 0

#Number of cyclesPCM bank 5 write requests wait in the queue
pcm_bank_5_write_queue_time 18446744073709540081

#Total number of cycles of PCM bank 5 read requests
pcm_bank_5_read_total_time 0

#Total number of cycles of PCM bank 5 write requests
pcm_bank_5_write_total_time 4970

#Number of PCM bank 5 row buffer hits
pcm_bank_5_row_buffer_hits 1

#Number of PCM bank 5 row buffer misses
pcm_bank_5_row_buffer_misses 1

#Number of PCM bank 5 opens
pcm_bank_5_num_opens 1

#Number of PCM bank 5 accesses
pcm_bank_5_num_accesses 2

#Number of PCM bank 5 closes
pcm_bank_5_num_closes 1

#Number of PCM bank 5 read after read (RAR) hazards
pcm_bank_5_num_read_after_read 0

#Number of PCM bank 5 read after write (RAW) hazards
pcm_bank_5_num_read_after_write 0

#Number of PCM bank 5 write after read (WAR) hazards
pcm_bank_5_num_write_after_read 0

#Number of PCM bank 5 write after write (WAW) hazards
pcm_bank_5_num_write_after_write 0

#Number of cycles PCM bank 5 requests wait for lower priority requests
pcm_bank_5_wait_lower_priority_time 0

#Number of cycles PCM bank 5 requests wait for same priority requests
pcm_bank_5_wait_same_priority_time 0

#Number of cycles PCM bank 5 requests wait for higher priority requests
pcm_bank_5_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 6 spend in the queue
pcm_bank_6_queue_time 18446744073709540081

#Number of cycles PCM bank 6 spends opening rows for requests
pcm_bank_6_open_time 220

#Number of cycles PCM bank 6 spends accessing rows for requests
pcm_bank_6_access_time 100

#Number of cycles PCM bank 6 spends closing rows for requests
pcm_bank_6_close_time 0

#Number of PCM bank 6 read requests
pcm_bank_6_read_requests 0

#Number of PCM bank 6 write requests
pcm_bank_6_write_requests 2

#Number of cyclesPCM bank 6 read requests wait in the queue
pcm_bank_6_read_queue_time 0

#Number of cyclesPCM bank 6 write requests wait in the queue
pcm_bank_6_write_queue_time 18446744073709540081

#Total number of cycles of PCM bank 6 read requests
pcm_bank_6_read_total_time 0

#Total number of cycles of PCM bank 6 write requests
pcm_bank_6_write_total_time 5034

#Number of PCM bank 6 row buffer hits
pcm_bank_6_row_buffer_hits 1

#Number of PCM bank 6 row buffer misses
pcm_bank_6_row_buffer_misses 1

#Number of PCM bank 6 opens
pcm_bank_6_num_opens 1

#Number of PCM bank 6 accesses
pcm_bank_6_num_accesses 2

#Number of PCM bank 6 closes
pcm_bank_6_num_closes 1

#Number of PCM bank 6 read after read (RAR) hazards
pcm_bank_6_num_read_after_read 0

#Number of PCM bank 6 read after write (RAW) hazards
pcm_bank_6_num_read_after_write 0

#Number of PCM bank 6 write after read (WAR) hazards
pcm_bank_6_num_write_after_read 0

#Number of PCM bank 6 write after write (WAW) hazards
pcm_bank_6_num_write_after_write 0

#Number of cycles PCM bank 6 requests wait for lower priority requests
pcm_bank_6_wait_lower_priority_time 0

#Number of cycles PCM bank 6 requests wait for same priority requests
pcm_bank_6_wait_same_priority_time 0

#Number of cycles PCM bank 6 requests wait for higher priority requests
pcm_bank_6_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 7 spend in the queue
pcm_bank_7_queue_time 18446744073709540081

#Number of cycles PCM bank 7 spends opening rows for requests
pcm_bank_7_open_time 220

#Number of cycles PCM bank 7 spends accessing rows for requests
pcm_bank_7_access_time 100

#Number of cycles PCM bank 7 spends closing rows for requests
pcm_bank_7_close_time 0

#Number of PCM bank 7 read requests
pcm_bank_7_read_requests 0

#Number of PCM bank 7 write requests
pcm_bank_7_write_requests 2

#Number of cyclesPCM bank 7 read requests wait in the queue
pcm_bank_7_read_queue_time 0

#Number of cyclesPCM bank 7 write requests wait in the queue
pcm_bank_7_write_queue_time 18446744073709540081

#Total number of cycles of PCM bank 7 read requests
pcm_bank_7_read_total_time 0

#Total number of cycles of PCM bank 7 write requests
pcm_bank_7_write_total_time 5218

#Number of PCM bank 7 row buffer hits
pcm_bank_7_row_buffer_hits 1

#Number of PCM bank 7 row buffer misses
pcm_bank_7_row_buffer_misses 1

#Number of PCM bank 7 opens
pcm_bank_7_num_opens 1

#Number of PCM bank 7 accesses
pcm_bank_7_num_accesses 2

#Number of PCM bank 7 closes
pcm_bank_7_num_closes 1

#Number of PCM bank 7 read after read (RAR) hazards
pcm_bank_7_num_read_after_read 0

#Number of PCM bank 7 read after write (RAW) hazards
pcm_bank_7_num_read_after_write 0

#Number of PCM bank 7 write after read (WAR) hazards
pcm_bank_7_num_write_after_read 0

#Number of PCM bank 7 write after write (WAW) hazards
pcm_bank_7_num_write_after_write 0

#Number of cycles PCM bank 7 requests wait for lower priority requests
pcm_bank_7_wait_lower_priority_time 0

#Number of cycles PCM bank 7 requests wait for same priority requests
pcm_bank_7_wait_same_priority_time 0

#Number of cycles PCM bank 7 requests wait for higher priority requests
pcm_bank_7_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 8 spend in the queue
pcm_bank_8_queue_time 18446744073709540046

#Number of cycles PCM bank 8 spends opening rows for requests
pcm_bank_8_open_time 220

#Number of cycles PCM bank 8 spends accessing rows for requests
pcm_bank_8_access_time 100

#Number of cycles PCM bank 8 spends closing rows for requests
pcm_bank_8_close_time 0

#Number of PCM bank 8 read requests
pcm_bank_8_read_requests 0

#Number of PCM bank 8 write requests
pcm_bank_8_write_requests 2

#Number of cyclesPCM bank 8 read requests wait in the queue
pcm_bank_8_read_queue_time 0

#Number of cyclesPCM bank 8 write requests wait in the queue
pcm_bank_8_write_queue_time 18446744073709540046

#Total number of cycles of PCM bank 8 read requests
pcm_bank_8_read_total_time 0

#Total number of cycles of PCM bank 8 write requests
pcm_bank_8_write_total_time 5247

#Number of PCM bank 8 row buffer hits
pcm_bank_8_row_buffer_hits 1

#Number of PCM bank 8 row buffer misses
pcm_bank_8_row_buffer_misses 1

#Number of PCM bank 8 opens
pcm_bank_8_num_opens 1

#Number of PCM bank 8 accesses
pcm_bank_8_num_accesses 2

#Number of PCM bank 8 closes
pcm_bank_8_num_closes 1

#Number of PCM bank 8 read after read (RAR) hazards
pcm_bank_8_num_read_after_read 0

#Number of PCM bank 8 read after write (RAW) hazards
pcm_bank_8_num_read_after_write 0

#Number of PCM bank 8 write after read (WAR) hazards
pcm_bank_8_num_write_after_read 0

#Number of PCM bank 8 write after write (WAW) hazards
pcm_bank_8_num_write_after_write 0

#Number of cycles PCM bank 8 requests wait for lower priority requests
pcm_bank_8_wait_lower_priority_time 0

#Number of cycles PCM bank 8 requests wait for same priority requests
pcm_bank_8_wait_same_priority_time 0

#Number of cycles PCM bank 8 requests wait for higher priority requests
pcm_bank_8_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 9 spend in the queue
pcm_bank_9_queue_time 18446744073709540046

#Number of cycles PCM bank 9 spends opening rows for requests
pcm_bank_9_open_time 220

#Number of cycles PCM bank 9 spends accessing rows for requests
pcm_bank_9_access_time 100

#Number of cycles PCM bank 9 spends closing rows for requests
pcm_bank_9_close_time 0

#Number of PCM bank 9 read requests
pcm_bank_9_read_requests 0

#Number of PCM bank 9 write requests
pcm_bank_9_write_requests 2

#Number of cyclesPCM bank 9 read requests wait in the queue
pcm_bank_9_read_queue_time 0

#Number of cyclesPCM bank 9 write requests wait in the queue
pcm_bank_9_write_queue_time 18446744073709540046

#Total number of cycles of PCM bank 9 read requests
pcm_bank_9_read_total_time 0

#Total number of cycles of PCM bank 9 write requests
pcm_bank_9_write_total_time 5311

#Number of PCM bank 9 row buffer hits
pcm_bank_9_row_buffer_hits 1

#Number of PCM bank 9 row buffer misses
pcm_bank_9_row_buffer_misses 1

#Number of PCM bank 9 opens
pcm_bank_9_num_opens 1

#Number of PCM bank 9 accesses
pcm_bank_9_num_accesses 2

#Number of PCM bank 9 closes
pcm_bank_9_num_closes 1

#Number of PCM bank 9 read after read (RAR) hazards
pcm_bank_9_num_read_after_read 0

#Number of PCM bank 9 read after write (RAW) hazards
pcm_bank_9_num_read_after_write 0

#Number of PCM bank 9 write after read (WAR) hazards
pcm_bank_9_num_write_after_read 0

#Number of PCM bank 9 write after write (WAW) hazards
pcm_bank_9_num_write_after_write 0

#Number of cycles PCM bank 9 requests wait for lower priority requests
pcm_bank_9_wait_lower_priority_time 0

#Number of cycles PCM bank 9 requests wait for same priority requests
pcm_bank_9_wait_same_priority_time 0

#Number of cycles PCM bank 9 requests wait for higher priority requests
pcm_bank_9_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 10 spend in the queue
pcm_bank_10_queue_time 18446744073709540046

#Number of cycles PCM bank 10 spends opening rows for requests
pcm_bank_10_open_time 220

#Number of cycles PCM bank 10 spends accessing rows for requests
pcm_bank_10_access_time 100

#Number of cycles PCM bank 10 spends closing rows for requests
pcm_bank_10_close_time 0

#Number of PCM bank 10 read requests
pcm_bank_10_read_requests 0

#Number of PCM bank 10 write requests
pcm_bank_10_write_requests 2

#Number of cyclesPCM bank 10 read requests wait in the queue
pcm_bank_10_read_queue_time 0

#Number of cyclesPCM bank 10 write requests wait in the queue
pcm_bank_10_write_queue_time 18446744073709540046

#Total number of cycles of PCM bank 10 read requests
pcm_bank_10_read_total_time 0

#Total number of cycles of PCM bank 10 write requests
pcm_bank_10_write_total_time 5375

#Number of PCM bank 10 row buffer hits
pcm_bank_10_row_buffer_hits 1

#Number of PCM bank 10 row buffer misses
pcm_bank_10_row_buffer_misses 1

#Number of PCM bank 10 opens
pcm_bank_10_num_opens 1

#Number of PCM bank 10 accesses
pcm_bank_10_num_accesses 2

#Number of PCM bank 10 closes
pcm_bank_10_num_closes 1

#Number of PCM bank 10 read after read (RAR) hazards
pcm_bank_10_num_read_after_read 0

#Number of PCM bank 10 read after write (RAW) hazards
pcm_bank_10_num_read_after_write 0

#Number of PCM bank 10 write after read (WAR) hazards
pcm_bank_10_num_write_after_read 0

#Number of PCM bank 10 write after write (WAW) hazards
pcm_bank_10_num_write_after_write 0

#Number of cycles PCM bank 10 requests wait for lower priority requests
pcm_bank_10_wait_lower_priority_time 0

#Number of cycles PCM bank 10 requests wait for same priority requests
pcm_bank_10_wait_same_priority_time 0

#Number of cycles PCM bank 10 requests wait for higher priority requests
pcm_bank_10_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 11 spend in the queue
pcm_bank_11_queue_time 18446744073709540046

#Number of cycles PCM bank 11 spends opening rows for requests
pcm_bank_11_open_time 220

#Number of cycles PCM bank 11 spends accessing rows for requests
pcm_bank_11_access_time 100

#Number of cycles PCM bank 11 spends closing rows for requests
pcm_bank_11_close_time 0

#Number of PCM bank 11 read requests
pcm_bank_11_read_requests 0

#Number of PCM bank 11 write requests
pcm_bank_11_write_requests 2

#Number of cyclesPCM bank 11 read requests wait in the queue
pcm_bank_11_read_queue_time 0

#Number of cyclesPCM bank 11 write requests wait in the queue
pcm_bank_11_write_queue_time 18446744073709540046

#Total number of cycles of PCM bank 11 read requests
pcm_bank_11_read_total_time 0

#Total number of cycles of PCM bank 11 write requests
pcm_bank_11_write_total_time 5439

#Number of PCM bank 11 row buffer hits
pcm_bank_11_row_buffer_hits 1

#Number of PCM bank 11 row buffer misses
pcm_bank_11_row_buffer_misses 1

#Number of PCM bank 11 opens
pcm_bank_11_num_opens 1

#Number of PCM bank 11 accesses
pcm_bank_11_num_accesses 2

#Number of PCM bank 11 closes
pcm_bank_11_num_closes 1

#Number of PCM bank 11 read after read (RAR) hazards
pcm_bank_11_num_read_after_read 0

#Number of PCM bank 11 read after write (RAW) hazards
pcm_bank_11_num_read_after_write 0

#Number of PCM bank 11 write after read (WAR) hazards
pcm_bank_11_num_write_after_read 0

#Number of PCM bank 11 write after write (WAW) hazards
pcm_bank_11_num_write_after_write 0

#Number of cycles PCM bank 11 requests wait for lower priority requests
pcm_bank_11_wait_lower_priority_time 0

#Number of cycles PCM bank 11 requests wait for same priority requests
pcm_bank_11_wait_same_priority_time 0

#Number of cycles PCM bank 11 requests wait for higher priority requests
pcm_bank_11_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 12 spend in the queue
pcm_bank_12_queue_time 18446744073709540046

#Number of cycles PCM bank 12 spends opening rows for requests
pcm_bank_12_open_time 220

#Number of cycles PCM bank 12 spends accessing rows for requests
pcm_bank_12_access_time 100

#Number of cycles PCM bank 12 spends closing rows for requests
pcm_bank_12_close_time 0

#Number of PCM bank 12 read requests
pcm_bank_12_read_requests 0

#Number of PCM bank 12 write requests
pcm_bank_12_write_requests 2

#Number of cyclesPCM bank 12 read requests wait in the queue
pcm_bank_12_read_queue_time 0

#Number of cyclesPCM bank 12 write requests wait in the queue
pcm_bank_12_write_queue_time 18446744073709540046

#Total number of cycles of PCM bank 12 read requests
pcm_bank_12_read_total_time 0

#Total number of cycles of PCM bank 12 write requests
pcm_bank_12_write_total_time 5743

#Number of PCM bank 12 row buffer hits
pcm_bank_12_row_buffer_hits 1

#Number of PCM bank 12 row buffer misses
pcm_bank_12_row_buffer_misses 1

#Number of PCM bank 12 opens
pcm_bank_12_num_opens 1

#Number of PCM bank 12 accesses
pcm_bank_12_num_accesses 2

#Number of PCM bank 12 closes
pcm_bank_12_num_closes 1

#Number of PCM bank 12 read after read (RAR) hazards
pcm_bank_12_num_read_after_read 0

#Number of PCM bank 12 read after write (RAW) hazards
pcm_bank_12_num_read_after_write 0

#Number of PCM bank 12 write after read (WAR) hazards
pcm_bank_12_num_write_after_read 0

#Number of PCM bank 12 write after write (WAW) hazards
pcm_bank_12_num_write_after_write 0

#Number of cycles PCM bank 12 requests wait for lower priority requests
pcm_bank_12_wait_lower_priority_time 0

#Number of cycles PCM bank 12 requests wait for same priority requests
pcm_bank_12_wait_same_priority_time 0

#Number of cycles PCM bank 12 requests wait for higher priority requests
pcm_bank_12_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 13 spend in the queue
pcm_bank_13_queue_time 0

#Number of cycles PCM bank 13 spends opening rows for requests
pcm_bank_13_open_time 440

#Number of cycles PCM bank 13 spends accessing rows for requests
pcm_bank_13_access_time 100

#Number of cycles PCM bank 13 spends closing rows for requests
pcm_bank_13_close_time 0

#Number of PCM bank 13 read requests
pcm_bank_13_read_requests 0

#Number of PCM bank 13 write requests
pcm_bank_13_write_requests 2

#Number of cyclesPCM bank 13 read requests wait in the queue
pcm_bank_13_read_queue_time 0

#Number of cyclesPCM bank 13 write requests wait in the queue
pcm_bank_13_write_queue_time 0

#Total number of cycles of PCM bank 13 read requests
pcm_bank_13_read_total_time 0

#Total number of cycles of PCM bank 13 write requests
pcm_bank_13_write_total_time 2770

#Number of PCM bank 13 row buffer hits
pcm_bank_13_row_buffer_hits 0

#Number of PCM bank 13 row buffer misses
pcm_bank_13_row_buffer_misses 2

#Number of PCM bank 13 opens
pcm_bank_13_num_opens 2

#Number of PCM bank 13 accesses
pcm_bank_13_num_accesses 2

#Number of PCM bank 13 closes
pcm_bank_13_num_closes 2

#Number of PCM bank 13 read after read (RAR) hazards
pcm_bank_13_num_read_after_read 0

#Number of PCM bank 13 read after write (RAW) hazards
pcm_bank_13_num_read_after_write 0

#Number of PCM bank 13 write after read (WAR) hazards
pcm_bank_13_num_write_after_read 0

#Number of PCM bank 13 write after write (WAW) hazards
pcm_bank_13_num_write_after_write 0

#Number of cycles PCM bank 13 requests wait for lower priority requests
pcm_bank_13_wait_lower_priority_time 0

#Number of cycles PCM bank 13 requests wait for same priority requests
pcm_bank_13_wait_same_priority_time 0

#Number of cycles PCM bank 13 requests wait for higher priority requests
pcm_bank_13_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 14 spend in the queue
pcm_bank_14_queue_time 18446744073709540046

#Number of cycles PCM bank 14 spends opening rows for requests
pcm_bank_14_open_time 220

#Number of cycles PCM bank 14 spends accessing rows for requests
pcm_bank_14_access_time 100

#Number of cycles PCM bank 14 spends closing rows for requests
pcm_bank_14_close_time 0

#Number of PCM bank 14 read requests
pcm_bank_14_read_requests 0

#Number of PCM bank 14 write requests
pcm_bank_14_write_requests 2

#Number of cyclesPCM bank 14 read requests wait in the queue
pcm_bank_14_read_queue_time 0

#Number of cyclesPCM bank 14 write requests wait in the queue
pcm_bank_14_write_queue_time 18446744073709540046

#Total number of cycles of PCM bank 14 read requests
pcm_bank_14_read_total_time 0

#Total number of cycles of PCM bank 14 write requests
pcm_bank_14_write_total_time 5807

#Number of PCM bank 14 row buffer hits
pcm_bank_14_row_buffer_hits 1

#Number of PCM bank 14 row buffer misses
pcm_bank_14_row_buffer_misses 1

#Number of PCM bank 14 opens
pcm_bank_14_num_opens 1

#Number of PCM bank 14 accesses
pcm_bank_14_num_accesses 2

#Number of PCM bank 14 closes
pcm_bank_14_num_closes 1

#Number of PCM bank 14 read after read (RAR) hazards
pcm_bank_14_num_read_after_read 0

#Number of PCM bank 14 read after write (RAW) hazards
pcm_bank_14_num_read_after_write 0

#Number of PCM bank 14 write after read (WAR) hazards
pcm_bank_14_num_write_after_read 0

#Number of PCM bank 14 write after write (WAW) hazards
pcm_bank_14_num_write_after_write 0

#Number of cycles PCM bank 14 requests wait for lower priority requests
pcm_bank_14_wait_lower_priority_time 0

#Number of cycles PCM bank 14 requests wait for same priority requests
pcm_bank_14_wait_same_priority_time 0

#Number of cycles PCM bank 14 requests wait for higher priority requests
pcm_bank_14_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 15 spend in the queue
pcm_bank_15_queue_time 18446744073709540046

#Number of cycles PCM bank 15 spends opening rows for requests
pcm_bank_15_open_time 220

#Number of cycles PCM bank 15 spends accessing rows for requests
pcm_bank_15_access_time 100

#Number of cycles PCM bank 15 spends closing rows for requests
pcm_bank_15_close_time 0

#Number of PCM bank 15 read requests
pcm_bank_15_read_requests 1

#Number of PCM bank 15 write requests
pcm_bank_15_write_requests 2

#Number of cyclesPCM bank 15 read requests wait in the queue
pcm_bank_15_read_queue_time 0

#Number of cyclesPCM bank 15 write requests wait in the queue
pcm_bank_15_write_queue_time 18446744073709540046

#Total number of cycles of PCM bank 15 read requests
pcm_bank_15_read_total_time 310

#Total number of cycles of PCM bank 15 write requests
pcm_bank_15_write_total_time 1991

#Number of PCM bank 15 row buffer hits
pcm_bank_15_row_buffer_hits 2

#Number of PCM bank 15 row buffer misses
pcm_bank_15_row_buffer_misses 1

#Number of PCM bank 15 opens
pcm_bank_15_num_opens 1

#Number of PCM bank 15 accesses
pcm_bank_15_num_accesses 3

#Number of PCM bank 15 closes
pcm_bank_15_num_closes 1

#Number of PCM bank 15 read after read (RAR) hazards
pcm_bank_15_num_read_after_read 0

#Number of PCM bank 15 read after write (RAW) hazards
pcm_bank_15_num_read_after_write 0

#Number of PCM bank 15 write after read (WAR) hazards
pcm_bank_15_num_write_after_read 0

#Number of PCM bank 15 write after write (WAW) hazards
pcm_bank_15_num_write_after_write 0

#Number of cycles PCM bank 15 requests wait for lower priority requests
pcm_bank_15_wait_lower_priority_time 0

#Number of cycles PCM bank 15 requests wait for same priority requests
pcm_bank_15_wait_same_priority_time 0

#Number of cycles PCM bank 15 requests wait for higher priority requests
pcm_bank_15_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 16 spend in the queue
pcm_bank_16_queue_time 0

#Number of cycles PCM bank 16 spends opening rows for requests
pcm_bank_16_open_time 440

#Number of cycles PCM bank 16 spends accessing rows for requests
pcm_bank_16_access_time 100

#Number of cycles PCM bank 16 spends closing rows for requests
pcm_bank_16_close_time 0

#Number of PCM bank 16 read requests
pcm_bank_16_read_requests 1

#Number of PCM bank 16 write requests
pcm_bank_16_write_requests 2

#Number of cyclesPCM bank 16 read requests wait in the queue
pcm_bank_16_read_queue_time 0

#Number of cyclesPCM bank 16 write requests wait in the queue
pcm_bank_16_write_queue_time 0

#Total number of cycles of PCM bank 16 read requests
pcm_bank_16_read_total_time 310

#Total number of cycles of PCM bank 16 write requests
pcm_bank_16_write_total_time 2215

#Number of PCM bank 16 row buffer hits
pcm_bank_16_row_buffer_hits 1

#Number of PCM bank 16 row buffer misses
pcm_bank_16_row_buffer_misses 2

#Number of PCM bank 16 opens
pcm_bank_16_num_opens 2

#Number of PCM bank 16 accesses
pcm_bank_16_num_accesses 3

#Number of PCM bank 16 closes
pcm_bank_16_num_closes 2

#Number of PCM bank 16 read after read (RAR) hazards
pcm_bank_16_num_read_after_read 0

#Number of PCM bank 16 read after write (RAW) hazards
pcm_bank_16_num_read_after_write 0

#Number of PCM bank 16 write after read (WAR) hazards
pcm_bank_16_num_write_after_read 0

#Number of PCM bank 16 write after write (WAW) hazards
pcm_bank_16_num_write_after_write 0

#Number of cycles PCM bank 16 requests wait for lower priority requests
pcm_bank_16_wait_lower_priority_time 0

#Number of cycles PCM bank 16 requests wait for same priority requests
pcm_bank_16_wait_same_priority_time 0

#Number of cycles PCM bank 16 requests wait for higher priority requests
pcm_bank_16_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 17 spend in the queue
pcm_bank_17_queue_time 0

#Number of cycles PCM bank 17 spends opening rows for requests
pcm_bank_17_open_time 440

#Number of cycles PCM bank 17 spends accessing rows for requests
pcm_bank_17_access_time 100

#Number of cycles PCM bank 17 spends closing rows for requests
pcm_bank_17_close_time 0

#Number of PCM bank 17 read requests
pcm_bank_17_read_requests 1

#Number of PCM bank 17 write requests
pcm_bank_17_write_requests 2

#Number of cyclesPCM bank 17 read requests wait in the queue
pcm_bank_17_read_queue_time 0

#Number of cyclesPCM bank 17 write requests wait in the queue
pcm_bank_17_write_queue_time 0

#Total number of cycles of PCM bank 17 read requests
pcm_bank_17_read_total_time 310

#Total number of cycles of PCM bank 17 write requests
pcm_bank_17_write_total_time 2295

#Number of PCM bank 17 row buffer hits
pcm_bank_17_row_buffer_hits 1

#Number of PCM bank 17 row buffer misses
pcm_bank_17_row_buffer_misses 2

#Number of PCM bank 17 opens
pcm_bank_17_num_opens 2

#Number of PCM bank 17 accesses
pcm_bank_17_num_accesses 3

#Number of PCM bank 17 closes
pcm_bank_17_num_closes 2

#Number of PCM bank 17 read after read (RAR) hazards
pcm_bank_17_num_read_after_read 0

#Number of PCM bank 17 read after write (RAW) hazards
pcm_bank_17_num_read_after_write 0

#Number of PCM bank 17 write after read (WAR) hazards
pcm_bank_17_num_write_after_read 0

#Number of PCM bank 17 write after write (WAW) hazards
pcm_bank_17_num_write_after_write 0

#Number of cycles PCM bank 17 requests wait for lower priority requests
pcm_bank_17_wait_lower_priority_time 0

#Number of cycles PCM bank 17 requests wait for same priority requests
pcm_bank_17_wait_same_priority_time 0

#Number of cycles PCM bank 17 requests wait for higher priority requests
pcm_bank_17_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 18 spend in the queue
pcm_bank_18_queue_time 0

#Number of cycles PCM bank 18 spends opening rows for requests
pcm_bank_18_open_time 440

#Number of cycles PCM bank 18 spends accessing rows for requests
pcm_bank_18_access_time 100

#Number of cycles PCM bank 18 spends closing rows for requests
pcm_bank_18_close_time 0

#Number of PCM bank 18 read requests
pcm_bank_18_read_requests 1

#Number of PCM bank 18 write requests
pcm_bank_18_write_requests 2

#Number of cyclesPCM bank 18 read requests wait in the queue
pcm_bank_18_read_queue_time 0

#Number of cyclesPCM bank 18 write requests wait in the queue
pcm_bank_18_write_queue_time 0

#Total number of cycles of PCM bank 18 read requests
pcm_bank_18_read_total_time 310

#Total number of cycles of PCM bank 18 write requests
pcm_bank_18_write_total_time 2415

#Number of PCM bank 18 row buffer hits
pcm_bank_18_row_buffer_hits 1

#Number of PCM bank 18 row buffer misses
pcm_bank_18_row_buffer_misses 2

#Number of PCM bank 18 opens
pcm_bank_18_num_opens 2

#Number of PCM bank 18 accesses
pcm_bank_18_num_accesses 3

#Number of PCM bank 18 closes
pcm_bank_18_num_closes 2

#Number of PCM bank 18 read after read (RAR) hazards
pcm_bank_18_num_read_after_read 0

#Number of PCM bank 18 read after write (RAW) hazards
pcm_bank_18_num_read_after_write 0

#Number of PCM bank 18 write after read (WAR) hazards
pcm_bank_18_num_write_after_read 0

#Number of PCM bank 18 write after write (WAW) hazards
pcm_bank_18_num_write_after_write 0

#Number of cycles PCM bank 18 requests wait for lower priority requests
pcm_bank_18_wait_lower_priority_time 0

#Number of cycles PCM bank 18 requests wait for same priority requests
pcm_bank_18_wait_same_priority_time 0

#Number of cycles PCM bank 18 requests wait for higher priority requests
pcm_bank_18_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 19 spend in the queue
pcm_bank_19_queue_time 0

#Number of cycles PCM bank 19 spends opening rows for requests
pcm_bank_19_open_time 440

#Number of cycles PCM bank 19 spends accessing rows for requests
pcm_bank_19_access_time 100

#Number of cycles PCM bank 19 spends closing rows for requests
pcm_bank_19_close_time 0

#Number of PCM bank 19 read requests
pcm_bank_19_read_requests 1

#Number of PCM bank 19 write requests
pcm_bank_19_write_requests 2

#Number of cyclesPCM bank 19 read requests wait in the queue
pcm_bank_19_read_queue_time 0

#Number of cyclesPCM bank 19 write requests wait in the queue
pcm_bank_19_write_queue_time 0

#Total number of cycles of PCM bank 19 read requests
pcm_bank_19_read_total_time 310

#Total number of cycles of PCM bank 19 write requests
pcm_bank_19_write_total_time 2295

#Number of PCM bank 19 row buffer hits
pcm_bank_19_row_buffer_hits 1

#Number of PCM bank 19 row buffer misses
pcm_bank_19_row_buffer_misses 2

#Number of PCM bank 19 opens
pcm_bank_19_num_opens 2

#Number of PCM bank 19 accesses
pcm_bank_19_num_accesses 3

#Number of PCM bank 19 closes
pcm_bank_19_num_closes 2

#Number of PCM bank 19 read after read (RAR) hazards
pcm_bank_19_num_read_after_read 0

#Number of PCM bank 19 read after write (RAW) hazards
pcm_bank_19_num_read_after_write 0

#Number of PCM bank 19 write after read (WAR) hazards
pcm_bank_19_num_write_after_read 0

#Number of PCM bank 19 write after write (WAW) hazards
pcm_bank_19_num_write_after_write 0

#Number of cycles PCM bank 19 requests wait for lower priority requests
pcm_bank_19_wait_lower_priority_time 0

#Number of cycles PCM bank 19 requests wait for same priority requests
pcm_bank_19_wait_same_priority_time 0

#Number of cycles PCM bank 19 requests wait for higher priority requests
pcm_bank_19_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 20 spend in the queue
pcm_bank_20_queue_time 18446744073709540011

#Number of cycles PCM bank 20 spends opening rows for requests
pcm_bank_20_open_time 220

#Number of cycles PCM bank 20 spends accessing rows for requests
pcm_bank_20_access_time 100

#Number of cycles PCM bank 20 spends closing rows for requests
pcm_bank_20_close_time 0

#Number of PCM bank 20 read requests
pcm_bank_20_read_requests 0

#Number of PCM bank 20 write requests
pcm_bank_20_write_requests 2

#Number of cyclesPCM bank 20 read requests wait in the queue
pcm_bank_20_read_queue_time 0

#Number of cyclesPCM bank 20 write requests wait in the queue
pcm_bank_20_write_queue_time 18446744073709540011

#Total number of cycles of PCM bank 20 read requests
pcm_bank_20_read_total_time 0

#Total number of cycles of PCM bank 20 write requests
pcm_bank_20_write_total_time 3015

#Number of PCM bank 20 row buffer hits
pcm_bank_20_row_buffer_hits 1

#Number of PCM bank 20 row buffer misses
pcm_bank_20_row_buffer_misses 1

#Number of PCM bank 20 opens
pcm_bank_20_num_opens 1

#Number of PCM bank 20 accesses
pcm_bank_20_num_accesses 2

#Number of PCM bank 20 closes
pcm_bank_20_num_closes 1

#Number of PCM bank 20 read after read (RAR) hazards
pcm_bank_20_num_read_after_read 0

#Number of PCM bank 20 read after write (RAW) hazards
pcm_bank_20_num_read_after_write 0

#Number of PCM bank 20 write after read (WAR) hazards
pcm_bank_20_num_write_after_read 0

#Number of PCM bank 20 write after write (WAW) hazards
pcm_bank_20_num_write_after_write 0

#Number of cycles PCM bank 20 requests wait for lower priority requests
pcm_bank_20_wait_lower_priority_time 0

#Number of cycles PCM bank 20 requests wait for same priority requests
pcm_bank_20_wait_same_priority_time 0

#Number of cycles PCM bank 20 requests wait for higher priority requests
pcm_bank_20_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 21 spend in the queue
pcm_bank_21_queue_time 18446744073709540011

#Number of cycles PCM bank 21 spends opening rows for requests
pcm_bank_21_open_time 220

#Number of cycles PCM bank 21 spends accessing rows for requests
pcm_bank_21_access_time 100

#Number of cycles PCM bank 21 spends closing rows for requests
pcm_bank_21_close_time 0

#Number of PCM bank 21 read requests
pcm_bank_21_read_requests 0

#Number of PCM bank 21 write requests
pcm_bank_21_write_requests 2

#Number of cyclesPCM bank 21 read requests wait in the queue
pcm_bank_21_read_queue_time 0

#Number of cyclesPCM bank 21 write requests wait in the queue
pcm_bank_21_write_queue_time 18446744073709540011

#Total number of cycles of PCM bank 21 read requests
pcm_bank_21_read_total_time 0

#Total number of cycles of PCM bank 21 write requests
pcm_bank_21_write_total_time 3095

#Number of PCM bank 21 row buffer hits
pcm_bank_21_row_buffer_hits 1

#Number of PCM bank 21 row buffer misses
pcm_bank_21_row_buffer_misses 1

#Number of PCM bank 21 opens
pcm_bank_21_num_opens 1

#Number of PCM bank 21 accesses
pcm_bank_21_num_accesses 2

#Number of PCM bank 21 closes
pcm_bank_21_num_closes 1

#Number of PCM bank 21 read after read (RAR) hazards
pcm_bank_21_num_read_after_read 0

#Number of PCM bank 21 read after write (RAW) hazards
pcm_bank_21_num_read_after_write 0

#Number of PCM bank 21 write after read (WAR) hazards
pcm_bank_21_num_write_after_read 0

#Number of PCM bank 21 write after write (WAW) hazards
pcm_bank_21_num_write_after_write 0

#Number of cycles PCM bank 21 requests wait for lower priority requests
pcm_bank_21_wait_lower_priority_time 0

#Number of cycles PCM bank 21 requests wait for same priority requests
pcm_bank_21_wait_same_priority_time 0

#Number of cycles PCM bank 21 requests wait for higher priority requests
pcm_bank_21_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 22 spend in the queue
pcm_bank_22_queue_time 18446744073709540011

#Number of cycles PCM bank 22 spends opening rows for requests
pcm_bank_22_open_time 220

#Number of cycles PCM bank 22 spends accessing rows for requests
pcm_bank_22_access_time 100

#Number of cycles PCM bank 22 spends closing rows for requests
pcm_bank_22_close_time 0

#Number of PCM bank 22 read requests
pcm_bank_22_read_requests 0

#Number of PCM bank 22 write requests
pcm_bank_22_write_requests 2

#Number of cyclesPCM bank 22 read requests wait in the queue
pcm_bank_22_read_queue_time 0

#Number of cyclesPCM bank 22 write requests wait in the queue
pcm_bank_22_write_queue_time 18446744073709540011

#Total number of cycles of PCM bank 22 read requests
pcm_bank_22_read_total_time 0

#Total number of cycles of PCM bank 22 write requests
pcm_bank_22_write_total_time 2935

#Number of PCM bank 22 row buffer hits
pcm_bank_22_row_buffer_hits 1

#Number of PCM bank 22 row buffer misses
pcm_bank_22_row_buffer_misses 1

#Number of PCM bank 22 opens
pcm_bank_22_num_opens 1

#Number of PCM bank 22 accesses
pcm_bank_22_num_accesses 2

#Number of PCM bank 22 closes
pcm_bank_22_num_closes 1

#Number of PCM bank 22 read after read (RAR) hazards
pcm_bank_22_num_read_after_read 0

#Number of PCM bank 22 read after write (RAW) hazards
pcm_bank_22_num_read_after_write 0

#Number of PCM bank 22 write after read (WAR) hazards
pcm_bank_22_num_write_after_read 0

#Number of PCM bank 22 write after write (WAW) hazards
pcm_bank_22_num_write_after_write 0

#Number of cycles PCM bank 22 requests wait for lower priority requests
pcm_bank_22_wait_lower_priority_time 0

#Number of cycles PCM bank 22 requests wait for same priority requests
pcm_bank_22_wait_same_priority_time 0

#Number of cycles PCM bank 22 requests wait for higher priority requests
pcm_bank_22_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 23 spend in the queue
pcm_bank_23_queue_time 0

#Number of cycles PCM bank 23 spends opening rows for requests
pcm_bank_23_open_time 440

#Number of cycles PCM bank 23 spends accessing rows for requests
pcm_bank_23_access_time 100

#Number of cycles PCM bank 23 spends closing rows for requests
pcm_bank_23_close_time 0

#Number of PCM bank 23 read requests
pcm_bank_23_read_requests 1

#Number of PCM bank 23 write requests
pcm_bank_23_write_requests 2

#Number of cyclesPCM bank 23 read requests wait in the queue
pcm_bank_23_read_queue_time 0

#Number of cyclesPCM bank 23 write requests wait in the queue
pcm_bank_23_write_queue_time 0

#Total number of cycles of PCM bank 23 read requests
pcm_bank_23_read_total_time 310

#Total number of cycles of PCM bank 23 write requests
pcm_bank_23_write_total_time 2455

#Number of PCM bank 23 row buffer hits
pcm_bank_23_row_buffer_hits 1

#Number of PCM bank 23 row buffer misses
pcm_bank_23_row_buffer_misses 2

#Number of PCM bank 23 opens
pcm_bank_23_num_opens 2

#Number of PCM bank 23 accesses
pcm_bank_23_num_accesses 3

#Number of PCM bank 23 closes
pcm_bank_23_num_closes 2

#Number of PCM bank 23 read after read (RAR) hazards
pcm_bank_23_num_read_after_read 0

#Number of PCM bank 23 read after write (RAW) hazards
pcm_bank_23_num_read_after_write 0

#Number of PCM bank 23 write after read (WAR) hazards
pcm_bank_23_num_write_after_read 0

#Number of PCM bank 23 write after write (WAW) hazards
pcm_bank_23_num_write_after_write 0

#Number of cycles PCM bank 23 requests wait for lower priority requests
pcm_bank_23_wait_lower_priority_time 0

#Number of cycles PCM bank 23 requests wait for same priority requests
pcm_bank_23_wait_same_priority_time 0

#Number of cycles PCM bank 23 requests wait for higher priority requests
pcm_bank_23_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 24 spend in the queue
pcm_bank_24_queue_time 0

#Number of cycles PCM bank 24 spends opening rows for requests
pcm_bank_24_open_time 440

#Number of cycles PCM bank 24 spends accessing rows for requests
pcm_bank_24_access_time 100

#Number of cycles PCM bank 24 spends closing rows for requests
pcm_bank_24_close_time 0

#Number of PCM bank 24 read requests
pcm_bank_24_read_requests 1

#Number of PCM bank 24 write requests
pcm_bank_24_write_requests 2

#Number of cyclesPCM bank 24 read requests wait in the queue
pcm_bank_24_read_queue_time 0

#Number of cyclesPCM bank 24 write requests wait in the queue
pcm_bank_24_write_queue_time 0

#Total number of cycles of PCM bank 24 read requests
pcm_bank_24_read_total_time 310

#Total number of cycles of PCM bank 24 write requests
pcm_bank_24_write_total_time 2660

#Number of PCM bank 24 row buffer hits
pcm_bank_24_row_buffer_hits 1

#Number of PCM bank 24 row buffer misses
pcm_bank_24_row_buffer_misses 2

#Number of PCM bank 24 opens
pcm_bank_24_num_opens 2

#Number of PCM bank 24 accesses
pcm_bank_24_num_accesses 3

#Number of PCM bank 24 closes
pcm_bank_24_num_closes 2

#Number of PCM bank 24 read after read (RAR) hazards
pcm_bank_24_num_read_after_read 0

#Number of PCM bank 24 read after write (RAW) hazards
pcm_bank_24_num_read_after_write 0

#Number of PCM bank 24 write after read (WAR) hazards
pcm_bank_24_num_write_after_read 0

#Number of PCM bank 24 write after write (WAW) hazards
pcm_bank_24_num_write_after_write 0

#Number of cycles PCM bank 24 requests wait for lower priority requests
pcm_bank_24_wait_lower_priority_time 0

#Number of cycles PCM bank 24 requests wait for same priority requests
pcm_bank_24_wait_same_priority_time 0

#Number of cycles PCM bank 24 requests wait for higher priority requests
pcm_bank_24_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 25 spend in the queue
pcm_bank_25_queue_time 0

#Number of cycles PCM bank 25 spends opening rows for requests
pcm_bank_25_open_time 440

#Number of cycles PCM bank 25 spends accessing rows for requests
pcm_bank_25_access_time 100

#Number of cycles PCM bank 25 spends closing rows for requests
pcm_bank_25_close_time 0

#Number of PCM bank 25 read requests
pcm_bank_25_read_requests 1

#Number of PCM bank 25 write requests
pcm_bank_25_write_requests 2

#Number of cyclesPCM bank 25 read requests wait in the queue
pcm_bank_25_read_queue_time 0

#Number of cyclesPCM bank 25 write requests wait in the queue
pcm_bank_25_write_queue_time 0

#Total number of cycles of PCM bank 25 read requests
pcm_bank_25_read_total_time 310

#Total number of cycles of PCM bank 25 write requests
pcm_bank_25_write_total_time 2580

#Number of PCM bank 25 row buffer hits
pcm_bank_25_row_buffer_hits 1

#Number of PCM bank 25 row buffer misses
pcm_bank_25_row_buffer_misses 2

#Number of PCM bank 25 opens
pcm_bank_25_num_opens 2

#Number of PCM bank 25 accesses
pcm_bank_25_num_accesses 3

#Number of PCM bank 25 closes
pcm_bank_25_num_closes 2

#Number of PCM bank 25 read after read (RAR) hazards
pcm_bank_25_num_read_after_read 0

#Number of PCM bank 25 read after write (RAW) hazards
pcm_bank_25_num_read_after_write 0

#Number of PCM bank 25 write after read (WAR) hazards
pcm_bank_25_num_write_after_read 0

#Number of PCM bank 25 write after write (WAW) hazards
pcm_bank_25_num_write_after_write 0

#Number of cycles PCM bank 25 requests wait for lower priority requests
pcm_bank_25_wait_lower_priority_time 0

#Number of cycles PCM bank 25 requests wait for same priority requests
pcm_bank_25_wait_same_priority_time 0

#Number of cycles PCM bank 25 requests wait for higher priority requests
pcm_bank_25_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 26 spend in the queue
pcm_bank_26_queue_time 410

#Number of cycles PCM bank 26 spends opening rows for requests
pcm_bank_26_open_time 440

#Number of cycles PCM bank 26 spends accessing rows for requests
pcm_bank_26_access_time 100

#Number of cycles PCM bank 26 spends closing rows for requests
pcm_bank_26_close_time 0

#Number of PCM bank 26 read requests
pcm_bank_26_read_requests 0

#Number of PCM bank 26 write requests
pcm_bank_26_write_requests 2

#Number of cyclesPCM bank 26 read requests wait in the queue
pcm_bank_26_read_queue_time 0

#Number of cyclesPCM bank 26 write requests wait in the queue
pcm_bank_26_write_queue_time 410

#Total number of cycles of PCM bank 26 read requests
pcm_bank_26_read_total_time 0

#Total number of cycles of PCM bank 26 write requests
pcm_bank_26_write_total_time 4260

#Number of PCM bank 26 row buffer hits
pcm_bank_26_row_buffer_hits 0

#Number of PCM bank 26 row buffer misses
pcm_bank_26_row_buffer_misses 2

#Number of PCM bank 26 opens
pcm_bank_26_num_opens 2

#Number of PCM bank 26 accesses
pcm_bank_26_num_accesses 2

#Number of PCM bank 26 closes
pcm_bank_26_num_closes 2

#Number of PCM bank 26 read after read (RAR) hazards
pcm_bank_26_num_read_after_read 0

#Number of PCM bank 26 read after write (RAW) hazards
pcm_bank_26_num_read_after_write 0

#Number of PCM bank 26 write after read (WAR) hazards
pcm_bank_26_num_write_after_read 0

#Number of PCM bank 26 write after write (WAW) hazards
pcm_bank_26_num_write_after_write 0

#Number of cycles PCM bank 26 requests wait for lower priority requests
pcm_bank_26_wait_lower_priority_time 0

#Number of cycles PCM bank 26 requests wait for same priority requests
pcm_bank_26_wait_same_priority_time 0

#Number of cycles PCM bank 26 requests wait for higher priority requests
pcm_bank_26_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 27 spend in the queue
pcm_bank_27_queue_time 330

#Number of cycles PCM bank 27 spends opening rows for requests
pcm_bank_27_open_time 440

#Number of cycles PCM bank 27 spends accessing rows for requests
pcm_bank_27_access_time 100

#Number of cycles PCM bank 27 spends closing rows for requests
pcm_bank_27_close_time 0

#Number of PCM bank 27 read requests
pcm_bank_27_read_requests 0

#Number of PCM bank 27 write requests
pcm_bank_27_write_requests 2

#Number of cyclesPCM bank 27 read requests wait in the queue
pcm_bank_27_read_queue_time 0

#Number of cyclesPCM bank 27 write requests wait in the queue
pcm_bank_27_write_queue_time 330

#Total number of cycles of PCM bank 27 read requests
pcm_bank_27_read_total_time 0

#Total number of cycles of PCM bank 27 write requests
pcm_bank_27_write_total_time 4100

#Number of PCM bank 27 row buffer hits
pcm_bank_27_row_buffer_hits 0

#Number of PCM bank 27 row buffer misses
pcm_bank_27_row_buffer_misses 2

#Number of PCM bank 27 opens
pcm_bank_27_num_opens 2

#Number of PCM bank 27 accesses
pcm_bank_27_num_accesses 2

#Number of PCM bank 27 closes
pcm_bank_27_num_closes 2

#Number of PCM bank 27 read after read (RAR) hazards
pcm_bank_27_num_read_after_read 0

#Number of PCM bank 27 read after write (RAW) hazards
pcm_bank_27_num_read_after_write 0

#Number of PCM bank 27 write after read (WAR) hazards
pcm_bank_27_num_write_after_read 0

#Number of PCM bank 27 write after write (WAW) hazards
pcm_bank_27_num_write_after_write 0

#Number of cycles PCM bank 27 requests wait for lower priority requests
pcm_bank_27_wait_lower_priority_time 0

#Number of cycles PCM bank 27 requests wait for same priority requests
pcm_bank_27_wait_same_priority_time 0

#Number of cycles PCM bank 27 requests wait for higher priority requests
pcm_bank_27_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 28 spend in the queue
pcm_bank_28_queue_time 170

#Number of cycles PCM bank 28 spends opening rows for requests
pcm_bank_28_open_time 440

#Number of cycles PCM bank 28 spends accessing rows for requests
pcm_bank_28_access_time 100

#Number of cycles PCM bank 28 spends closing rows for requests
pcm_bank_28_close_time 0

#Number of PCM bank 28 read requests
pcm_bank_28_read_requests 0

#Number of PCM bank 28 write requests
pcm_bank_28_write_requests 2

#Number of cyclesPCM bank 28 read requests wait in the queue
pcm_bank_28_read_queue_time 0

#Number of cyclesPCM bank 28 write requests wait in the queue
pcm_bank_28_write_queue_time 170

#Total number of cycles of PCM bank 28 read requests
pcm_bank_28_read_total_time 0

#Total number of cycles of PCM bank 28 write requests
pcm_bank_28_write_total_time 3780

#Number of PCM bank 28 row buffer hits
pcm_bank_28_row_buffer_hits 0

#Number of PCM bank 28 row buffer misses
pcm_bank_28_row_buffer_misses 2

#Number of PCM bank 28 opens
pcm_bank_28_num_opens 2

#Number of PCM bank 28 accesses
pcm_bank_28_num_accesses 2

#Number of PCM bank 28 closes
pcm_bank_28_num_closes 2

#Number of PCM bank 28 read after read (RAR) hazards
pcm_bank_28_num_read_after_read 0

#Number of PCM bank 28 read after write (RAW) hazards
pcm_bank_28_num_read_after_write 0

#Number of PCM bank 28 write after read (WAR) hazards
pcm_bank_28_num_write_after_read 0

#Number of PCM bank 28 write after write (WAW) hazards
pcm_bank_28_num_write_after_write 0

#Number of cycles PCM bank 28 requests wait for lower priority requests
pcm_bank_28_wait_lower_priority_time 0

#Number of cycles PCM bank 28 requests wait for same priority requests
pcm_bank_28_wait_same_priority_time 0

#Number of cycles PCM bank 28 requests wait for higher priority requests
pcm_bank_28_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 29 spend in the queue
pcm_bank_29_queue_time 0

#Number of cycles PCM bank 29 spends opening rows for requests
pcm_bank_29_open_time 440

#Number of cycles PCM bank 29 spends accessing rows for requests
pcm_bank_29_access_time 100

#Number of cycles PCM bank 29 spends closing rows for requests
pcm_bank_29_close_time 0

#Number of PCM bank 29 read requests
pcm_bank_29_read_requests 0

#Number of PCM bank 29 write requests
pcm_bank_29_write_requests 2

#Number of cyclesPCM bank 29 read requests wait in the queue
pcm_bank_29_read_queue_time 0

#Number of cyclesPCM bank 29 write requests wait in the queue
pcm_bank_29_write_queue_time 0

#Total number of cycles of PCM bank 29 read requests
pcm_bank_29_read_total_time 0

#Total number of cycles of PCM bank 29 write requests
pcm_bank_29_write_total_time 3020

#Number of PCM bank 29 row buffer hits
pcm_bank_29_row_buffer_hits 0

#Number of PCM bank 29 row buffer misses
pcm_bank_29_row_buffer_misses 2

#Number of PCM bank 29 opens
pcm_bank_29_num_opens 2

#Number of PCM bank 29 accesses
pcm_bank_29_num_accesses 2

#Number of PCM bank 29 closes
pcm_bank_29_num_closes 2

#Number of PCM bank 29 read after read (RAR) hazards
pcm_bank_29_num_read_after_read 0

#Number of PCM bank 29 read after write (RAW) hazards
pcm_bank_29_num_read_after_write 0

#Number of PCM bank 29 write after read (WAR) hazards
pcm_bank_29_num_write_after_read 0

#Number of PCM bank 29 write after write (WAW) hazards
pcm_bank_29_num_write_after_write 0

#Number of cycles PCM bank 29 requests wait for lower priority requests
pcm_bank_29_wait_lower_priority_time 0

#Number of cycles PCM bank 29 requests wait for same priority requests
pcm_bank_29_wait_same_priority_time 0

#Number of cycles PCM bank 29 requests wait for higher priority requests
pcm_bank_29_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 30 spend in the queue
pcm_bank_30_queue_time 0

#Number of cycles PCM bank 30 spends opening rows for requests
pcm_bank_30_open_time 440

#Number of cycles PCM bank 30 spends accessing rows for requests
pcm_bank_30_access_time 100

#Number of cycles PCM bank 30 spends closing rows for requests
pcm_bank_30_close_time 0

#Number of PCM bank 30 read requests
pcm_bank_30_read_requests 0

#Number of PCM bank 30 write requests
pcm_bank_30_write_requests 2

#Number of cyclesPCM bank 30 read requests wait in the queue
pcm_bank_30_read_queue_time 0

#Number of cyclesPCM bank 30 write requests wait in the queue
pcm_bank_30_write_queue_time 0

#Total number of cycles of PCM bank 30 read requests
pcm_bank_30_read_total_time 0

#Total number of cycles of PCM bank 30 write requests
pcm_bank_30_write_total_time 2900

#Number of PCM bank 30 row buffer hits
pcm_bank_30_row_buffer_hits 0

#Number of PCM bank 30 row buffer misses
pcm_bank_30_row_buffer_misses 2

#Number of PCM bank 30 opens
pcm_bank_30_num_opens 2

#Number of PCM bank 30 accesses
pcm_bank_30_num_accesses 2

#Number of PCM bank 30 closes
pcm_bank_30_num_closes 2

#Number of PCM bank 30 read after read (RAR) hazards
pcm_bank_30_num_read_after_read 0

#Number of PCM bank 30 read after write (RAW) hazards
pcm_bank_30_num_read_after_write 0

#Number of PCM bank 30 write after read (WAR) hazards
pcm_bank_30_num_write_after_read 0

#Number of PCM bank 30 write after write (WAW) hazards
pcm_bank_30_num_write_after_write 0

#Number of cycles PCM bank 30 requests wait for lower priority requests
pcm_bank_30_wait_lower_priority_time 0

#Number of cycles PCM bank 30 requests wait for same priority requests
pcm_bank_30_wait_same_priority_time 0

#Number of cycles PCM bank 30 requests wait for higher priority requests
pcm_bank_30_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 31 spend in the queue
pcm_bank_31_queue_time 0

#Number of cycles PCM bank 31 spends opening rows for requests
pcm_bank_31_open_time 440

#Number of cycles PCM bank 31 spends accessing rows for requests
pcm_bank_31_access_time 100

#Number of cycles PCM bank 31 spends closing rows for requests
pcm_bank_31_close_time 0

#Number of PCM bank 31 read requests
pcm_bank_31_read_requests 0

#Number of PCM bank 31 write requests
pcm_bank_31_write_requests 2

#Number of cyclesPCM bank 31 read requests wait in the queue
pcm_bank_31_read_queue_time 0

#Number of cyclesPCM bank 31 write requests wait in the queue
pcm_bank_31_write_queue_time 0

#Total number of cycles of PCM bank 31 read requests
pcm_bank_31_read_total_time 0

#Total number of cycles of PCM bank 31 write requests
pcm_bank_31_write_total_time 2820

#Number of PCM bank 31 row buffer hits
pcm_bank_31_row_buffer_hits 0

#Number of PCM bank 31 row buffer misses
pcm_bank_31_row_buffer_misses 2

#Number of PCM bank 31 opens
pcm_bank_31_num_opens 2

#Number of PCM bank 31 accesses
pcm_bank_31_num_accesses 2

#Number of PCM bank 31 closes
pcm_bank_31_num_closes 2

#Number of PCM bank 31 read after read (RAR) hazards
pcm_bank_31_num_read_after_read 0

#Number of PCM bank 31 read after write (RAW) hazards
pcm_bank_31_num_read_after_write 0

#Number of PCM bank 31 write after read (WAR) hazards
pcm_bank_31_num_write_after_read 0

#Number of PCM bank 31 write after write (WAW) hazards
pcm_bank_31_num_write_after_write 0

#Number of cycles PCM bank 31 requests wait for lower priority requests
pcm_bank_31_wait_lower_priority_time 0

#Number of cycles PCM bank 31 requests wait for same priority requests
pcm_bank_31_wait_same_priority_time 0

#Number of cycles PCM bank 31 requests wait for higher priority requests
pcm_bank_31_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 32 spend in the queue
pcm_bank_32_queue_time 18446744073709539941

#Number of cycles PCM bank 32 spends opening rows for requests
pcm_bank_32_open_time 220

#Number of cycles PCM bank 32 spends accessing rows for requests
pcm_bank_32_access_time 100

#Number of cycles PCM bank 32 spends closing rows for requests
pcm_bank_32_close_time 0

#Number of PCM bank 32 read requests
pcm_bank_32_read_requests 0

#Number of PCM bank 32 write requests
pcm_bank_32_write_requests 2

#Number of cyclesPCM bank 32 read requests wait in the queue
pcm_bank_32_read_queue_time 0

#Number of cyclesPCM bank 32 write requests wait in the queue
pcm_bank_32_write_queue_time 18446744073709539941

#Total number of cycles of PCM bank 32 read requests
pcm_bank_32_read_total_time 0

#Total number of cycles of PCM bank 32 write requests
pcm_bank_32_write_total_time 3145

#Number of PCM bank 32 row buffer hits
pcm_bank_32_row_buffer_hits 1

#Number of PCM bank 32 row buffer misses
pcm_bank_32_row_buffer_misses 1

#Number of PCM bank 32 opens
pcm_bank_32_num_opens 1

#Number of PCM bank 32 accesses
pcm_bank_32_num_accesses 2

#Number of PCM bank 32 closes
pcm_bank_32_num_closes 1

#Number of PCM bank 32 read after read (RAR) hazards
pcm_bank_32_num_read_after_read 0

#Number of PCM bank 32 read after write (RAW) hazards
pcm_bank_32_num_read_after_write 0

#Number of PCM bank 32 write after read (WAR) hazards
pcm_bank_32_num_write_after_read 0

#Number of PCM bank 32 write after write (WAW) hazards
pcm_bank_32_num_write_after_write 0

#Number of cycles PCM bank 32 requests wait for lower priority requests
pcm_bank_32_wait_lower_priority_time 0

#Number of cycles PCM bank 32 requests wait for same priority requests
pcm_bank_32_wait_same_priority_time 0

#Number of cycles PCM bank 32 requests wait for higher priority requests
pcm_bank_32_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 33 spend in the queue
pcm_bank_33_queue_time 0

#Number of cycles PCM bank 33 spends opening rows for requests
pcm_bank_33_open_time 440

#Number of cycles PCM bank 33 spends accessing rows for requests
pcm_bank_33_access_time 100

#Number of cycles PCM bank 33 spends closing rows for requests
pcm_bank_33_close_time 0

#Number of PCM bank 33 read requests
pcm_bank_33_read_requests 0

#Number of PCM bank 33 write requests
pcm_bank_33_write_requests 2

#Number of cyclesPCM bank 33 read requests wait in the queue
pcm_bank_33_read_queue_time 0

#Number of cyclesPCM bank 33 write requests wait in the queue
pcm_bank_33_write_queue_time 0

#Total number of cycles of PCM bank 33 read requests
pcm_bank_33_read_total_time 0

#Total number of cycles of PCM bank 33 write requests
pcm_bank_33_write_total_time 2785

#Number of PCM bank 33 row buffer hits
pcm_bank_33_row_buffer_hits 0

#Number of PCM bank 33 row buffer misses
pcm_bank_33_row_buffer_misses 2

#Number of PCM bank 33 opens
pcm_bank_33_num_opens 2

#Number of PCM bank 33 accesses
pcm_bank_33_num_accesses 2

#Number of PCM bank 33 closes
pcm_bank_33_num_closes 2

#Number of PCM bank 33 read after read (RAR) hazards
pcm_bank_33_num_read_after_read 0

#Number of PCM bank 33 read after write (RAW) hazards
pcm_bank_33_num_read_after_write 0

#Number of PCM bank 33 write after read (WAR) hazards
pcm_bank_33_num_write_after_read 0

#Number of PCM bank 33 write after write (WAW) hazards
pcm_bank_33_num_write_after_write 0

#Number of cycles PCM bank 33 requests wait for lower priority requests
pcm_bank_33_wait_lower_priority_time 0

#Number of cycles PCM bank 33 requests wait for same priority requests
pcm_bank_33_wait_same_priority_time 0

#Number of cycles PCM bank 33 requests wait for higher priority requests
pcm_bank_33_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 34 spend in the queue
pcm_bank_34_queue_time 18446744073709539941

#Number of cycles PCM bank 34 spends opening rows for requests
pcm_bank_34_open_time 220

#Number of cycles PCM bank 34 spends accessing rows for requests
pcm_bank_34_access_time 100

#Number of cycles PCM bank 34 spends closing rows for requests
pcm_bank_34_close_time 0

#Number of PCM bank 34 read requests
pcm_bank_34_read_requests 0

#Number of PCM bank 34 write requests
pcm_bank_34_write_requests 2

#Number of cyclesPCM bank 34 read requests wait in the queue
pcm_bank_34_read_queue_time 0

#Number of cyclesPCM bank 34 write requests wait in the queue
pcm_bank_34_write_queue_time 18446744073709539941

#Total number of cycles of PCM bank 34 read requests
pcm_bank_34_read_total_time 0

#Total number of cycles of PCM bank 34 write requests
pcm_bank_34_write_total_time 3505

#Number of PCM bank 34 row buffer hits
pcm_bank_34_row_buffer_hits 1

#Number of PCM bank 34 row buffer misses
pcm_bank_34_row_buffer_misses 1

#Number of PCM bank 34 opens
pcm_bank_34_num_opens 1

#Number of PCM bank 34 accesses
pcm_bank_34_num_accesses 2

#Number of PCM bank 34 closes
pcm_bank_34_num_closes 1

#Number of PCM bank 34 read after read (RAR) hazards
pcm_bank_34_num_read_after_read 0

#Number of PCM bank 34 read after write (RAW) hazards
pcm_bank_34_num_read_after_write 0

#Number of PCM bank 34 write after read (WAR) hazards
pcm_bank_34_num_write_after_read 0

#Number of PCM bank 34 write after write (WAW) hazards
pcm_bank_34_num_write_after_write 0

#Number of cycles PCM bank 34 requests wait for lower priority requests
pcm_bank_34_wait_lower_priority_time 0

#Number of cycles PCM bank 34 requests wait for same priority requests
pcm_bank_34_wait_same_priority_time 0

#Number of cycles PCM bank 34 requests wait for higher priority requests
pcm_bank_34_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 35 spend in the queue
pcm_bank_35_queue_time 18446744073709539941

#Number of cycles PCM bank 35 spends opening rows for requests
pcm_bank_35_open_time 220

#Number of cycles PCM bank 35 spends accessing rows for requests
pcm_bank_35_access_time 100

#Number of cycles PCM bank 35 spends closing rows for requests
pcm_bank_35_close_time 0

#Number of PCM bank 35 read requests
pcm_bank_35_read_requests 0

#Number of PCM bank 35 write requests
pcm_bank_35_write_requests 2

#Number of cyclesPCM bank 35 read requests wait in the queue
pcm_bank_35_read_queue_time 0

#Number of cyclesPCM bank 35 write requests wait in the queue
pcm_bank_35_write_queue_time 18446744073709539941

#Total number of cycles of PCM bank 35 read requests
pcm_bank_35_read_total_time 0

#Total number of cycles of PCM bank 35 write requests
pcm_bank_35_write_total_time 3225

#Number of PCM bank 35 row buffer hits
pcm_bank_35_row_buffer_hits 1

#Number of PCM bank 35 row buffer misses
pcm_bank_35_row_buffer_misses 1

#Number of PCM bank 35 opens
pcm_bank_35_num_opens 1

#Number of PCM bank 35 accesses
pcm_bank_35_num_accesses 2

#Number of PCM bank 35 closes
pcm_bank_35_num_closes 1

#Number of PCM bank 35 read after read (RAR) hazards
pcm_bank_35_num_read_after_read 0

#Number of PCM bank 35 read after write (RAW) hazards
pcm_bank_35_num_read_after_write 0

#Number of PCM bank 35 write after read (WAR) hazards
pcm_bank_35_num_write_after_read 0

#Number of PCM bank 35 write after write (WAW) hazards
pcm_bank_35_num_write_after_write 0

#Number of cycles PCM bank 35 requests wait for lower priority requests
pcm_bank_35_wait_lower_priority_time 0

#Number of cycles PCM bank 35 requests wait for same priority requests
pcm_bank_35_wait_same_priority_time 0

#Number of cycles PCM bank 35 requests wait for higher priority requests
pcm_bank_35_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 36 spend in the queue
pcm_bank_36_queue_time 18446744073709539941

#Number of cycles PCM bank 36 spends opening rows for requests
pcm_bank_36_open_time 220

#Number of cycles PCM bank 36 spends accessing rows for requests
pcm_bank_36_access_time 100

#Number of cycles PCM bank 36 spends closing rows for requests
pcm_bank_36_close_time 0

#Number of PCM bank 36 read requests
pcm_bank_36_read_requests 0

#Number of PCM bank 36 write requests
pcm_bank_36_write_requests 2

#Number of cyclesPCM bank 36 read requests wait in the queue
pcm_bank_36_read_queue_time 0

#Number of cyclesPCM bank 36 write requests wait in the queue
pcm_bank_36_write_queue_time 18446744073709539941

#Total number of cycles of PCM bank 36 read requests
pcm_bank_36_read_total_time 0

#Total number of cycles of PCM bank 36 write requests
pcm_bank_36_write_total_time 3225

#Number of PCM bank 36 row buffer hits
pcm_bank_36_row_buffer_hits 1

#Number of PCM bank 36 row buffer misses
pcm_bank_36_row_buffer_misses 1

#Number of PCM bank 36 opens
pcm_bank_36_num_opens 1

#Number of PCM bank 36 accesses
pcm_bank_36_num_accesses 2

#Number of PCM bank 36 closes
pcm_bank_36_num_closes 1

#Number of PCM bank 36 read after read (RAR) hazards
pcm_bank_36_num_read_after_read 0

#Number of PCM bank 36 read after write (RAW) hazards
pcm_bank_36_num_read_after_write 0

#Number of PCM bank 36 write after read (WAR) hazards
pcm_bank_36_num_write_after_read 0

#Number of PCM bank 36 write after write (WAW) hazards
pcm_bank_36_num_write_after_write 0

#Number of cycles PCM bank 36 requests wait for lower priority requests
pcm_bank_36_wait_lower_priority_time 0

#Number of cycles PCM bank 36 requests wait for same priority requests
pcm_bank_36_wait_same_priority_time 0

#Number of cycles PCM bank 36 requests wait for higher priority requests
pcm_bank_36_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 37 spend in the queue
pcm_bank_37_queue_time 18446744073709539941

#Number of cycles PCM bank 37 spends opening rows for requests
pcm_bank_37_open_time 220

#Number of cycles PCM bank 37 spends accessing rows for requests
pcm_bank_37_access_time 100

#Number of cycles PCM bank 37 spends closing rows for requests
pcm_bank_37_close_time 0

#Number of PCM bank 37 read requests
pcm_bank_37_read_requests 0

#Number of PCM bank 37 write requests
pcm_bank_37_write_requests 2

#Number of cyclesPCM bank 37 read requests wait in the queue
pcm_bank_37_read_queue_time 0

#Number of cyclesPCM bank 37 write requests wait in the queue
pcm_bank_37_write_queue_time 18446744073709539941

#Total number of cycles of PCM bank 37 read requests
pcm_bank_37_read_total_time 0

#Total number of cycles of PCM bank 37 write requests
pcm_bank_37_write_total_time 3465

#Number of PCM bank 37 row buffer hits
pcm_bank_37_row_buffer_hits 1

#Number of PCM bank 37 row buffer misses
pcm_bank_37_row_buffer_misses 1

#Number of PCM bank 37 opens
pcm_bank_37_num_opens 1

#Number of PCM bank 37 accesses
pcm_bank_37_num_accesses 2

#Number of PCM bank 37 closes
pcm_bank_37_num_closes 1

#Number of PCM bank 37 read after read (RAR) hazards
pcm_bank_37_num_read_after_read 0

#Number of PCM bank 37 read after write (RAW) hazards
pcm_bank_37_num_read_after_write 0

#Number of PCM bank 37 write after read (WAR) hazards
pcm_bank_37_num_write_after_read 0

#Number of PCM bank 37 write after write (WAW) hazards
pcm_bank_37_num_write_after_write 0

#Number of cycles PCM bank 37 requests wait for lower priority requests
pcm_bank_37_wait_lower_priority_time 0

#Number of cycles PCM bank 37 requests wait for same priority requests
pcm_bank_37_wait_same_priority_time 0

#Number of cycles PCM bank 37 requests wait for higher priority requests
pcm_bank_37_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 38 spend in the queue
pcm_bank_38_queue_time 18446744073709539941

#Number of cycles PCM bank 38 spends opening rows for requests
pcm_bank_38_open_time 220

#Number of cycles PCM bank 38 spends accessing rows for requests
pcm_bank_38_access_time 100

#Number of cycles PCM bank 38 spends closing rows for requests
pcm_bank_38_close_time 0

#Number of PCM bank 38 read requests
pcm_bank_38_read_requests 0

#Number of PCM bank 38 write requests
pcm_bank_38_write_requests 2

#Number of cyclesPCM bank 38 read requests wait in the queue
pcm_bank_38_read_queue_time 0

#Number of cyclesPCM bank 38 write requests wait in the queue
pcm_bank_38_write_queue_time 18446744073709539941

#Total number of cycles of PCM bank 38 read requests
pcm_bank_38_read_total_time 0

#Total number of cycles of PCM bank 38 write requests
pcm_bank_38_write_total_time 3465

#Number of PCM bank 38 row buffer hits
pcm_bank_38_row_buffer_hits 1

#Number of PCM bank 38 row buffer misses
pcm_bank_38_row_buffer_misses 1

#Number of PCM bank 38 opens
pcm_bank_38_num_opens 1

#Number of PCM bank 38 accesses
pcm_bank_38_num_accesses 2

#Number of PCM bank 38 closes
pcm_bank_38_num_closes 1

#Number of PCM bank 38 read after read (RAR) hazards
pcm_bank_38_num_read_after_read 0

#Number of PCM bank 38 read after write (RAW) hazards
pcm_bank_38_num_read_after_write 0

#Number of PCM bank 38 write after read (WAR) hazards
pcm_bank_38_num_write_after_read 0

#Number of PCM bank 38 write after write (WAW) hazards
pcm_bank_38_num_write_after_write 0

#Number of cycles PCM bank 38 requests wait for lower priority requests
pcm_bank_38_wait_lower_priority_time 0

#Number of cycles PCM bank 38 requests wait for same priority requests
pcm_bank_38_wait_same_priority_time 0

#Number of cycles PCM bank 38 requests wait for higher priority requests
pcm_bank_38_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 39 spend in the queue
pcm_bank_39_queue_time 575

#Number of cycles PCM bank 39 spends opening rows for requests
pcm_bank_39_open_time 440

#Number of cycles PCM bank 39 spends accessing rows for requests
pcm_bank_39_access_time 100

#Number of cycles PCM bank 39 spends closing rows for requests
pcm_bank_39_close_time 0

#Number of PCM bank 39 read requests
pcm_bank_39_read_requests 0

#Number of PCM bank 39 write requests
pcm_bank_39_write_requests 2

#Number of cyclesPCM bank 39 read requests wait in the queue
pcm_bank_39_read_queue_time 0

#Number of cyclesPCM bank 39 write requests wait in the queue
pcm_bank_39_write_queue_time 575

#Total number of cycles of PCM bank 39 read requests
pcm_bank_39_read_total_time 0

#Total number of cycles of PCM bank 39 write requests
pcm_bank_39_write_total_time 4625

#Number of PCM bank 39 row buffer hits
pcm_bank_39_row_buffer_hits 0

#Number of PCM bank 39 row buffer misses
pcm_bank_39_row_buffer_misses 2

#Number of PCM bank 39 opens
pcm_bank_39_num_opens 2

#Number of PCM bank 39 accesses
pcm_bank_39_num_accesses 2

#Number of PCM bank 39 closes
pcm_bank_39_num_closes 2

#Number of PCM bank 39 read after read (RAR) hazards
pcm_bank_39_num_read_after_read 0

#Number of PCM bank 39 read after write (RAW) hazards
pcm_bank_39_num_read_after_write 0

#Number of PCM bank 39 write after read (WAR) hazards
pcm_bank_39_num_write_after_read 0

#Number of PCM bank 39 write after write (WAW) hazards
pcm_bank_39_num_write_after_write 0

#Number of cycles PCM bank 39 requests wait for lower priority requests
pcm_bank_39_wait_lower_priority_time 0

#Number of cycles PCM bank 39 requests wait for same priority requests
pcm_bank_39_wait_same_priority_time 0

#Number of cycles PCM bank 39 requests wait for higher priority requests
pcm_bank_39_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 40 spend in the queue
pcm_bank_40_queue_time 500

#Number of cycles PCM bank 40 spends opening rows for requests
pcm_bank_40_open_time 440

#Number of cycles PCM bank 40 spends accessing rows for requests
pcm_bank_40_access_time 100

#Number of cycles PCM bank 40 spends closing rows for requests
pcm_bank_40_close_time 0

#Number of PCM bank 40 read requests
pcm_bank_40_read_requests 0

#Number of PCM bank 40 write requests
pcm_bank_40_write_requests 2

#Number of cyclesPCM bank 40 read requests wait in the queue
pcm_bank_40_read_queue_time 0

#Number of cyclesPCM bank 40 write requests wait in the queue
pcm_bank_40_write_queue_time 500

#Total number of cycles of PCM bank 40 read requests
pcm_bank_40_read_total_time 0

#Total number of cycles of PCM bank 40 write requests
pcm_bank_40_write_total_time 4510

#Number of PCM bank 40 row buffer hits
pcm_bank_40_row_buffer_hits 0

#Number of PCM bank 40 row buffer misses
pcm_bank_40_row_buffer_misses 2

#Number of PCM bank 40 opens
pcm_bank_40_num_opens 2

#Number of PCM bank 40 accesses
pcm_bank_40_num_accesses 2

#Number of PCM bank 40 closes
pcm_bank_40_num_closes 2

#Number of PCM bank 40 read after read (RAR) hazards
pcm_bank_40_num_read_after_read 0

#Number of PCM bank 40 read after write (RAW) hazards
pcm_bank_40_num_read_after_write 0

#Number of PCM bank 40 write after read (WAR) hazards
pcm_bank_40_num_write_after_read 0

#Number of PCM bank 40 write after write (WAW) hazards
pcm_bank_40_num_write_after_write 0

#Number of cycles PCM bank 40 requests wait for lower priority requests
pcm_bank_40_wait_lower_priority_time 0

#Number of cycles PCM bank 40 requests wait for same priority requests
pcm_bank_40_wait_same_priority_time 0

#Number of cycles PCM bank 40 requests wait for higher priority requests
pcm_bank_40_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 41 spend in the queue
pcm_bank_41_queue_time 18446744073709539906

#Number of cycles PCM bank 41 spends opening rows for requests
pcm_bank_41_open_time 220

#Number of cycles PCM bank 41 spends accessing rows for requests
pcm_bank_41_access_time 100

#Number of cycles PCM bank 41 spends closing rows for requests
pcm_bank_41_close_time 0

#Number of PCM bank 41 read requests
pcm_bank_41_read_requests 0

#Number of PCM bank 41 write requests
pcm_bank_41_write_requests 2

#Number of cyclesPCM bank 41 read requests wait in the queue
pcm_bank_41_read_queue_time 0

#Number of cyclesPCM bank 41 write requests wait in the queue
pcm_bank_41_write_queue_time 18446744073709539906

#Total number of cycles of PCM bank 41 read requests
pcm_bank_41_read_total_time 0

#Total number of cycles of PCM bank 41 write requests
pcm_bank_41_write_total_time 3710

#Number of PCM bank 41 row buffer hits
pcm_bank_41_row_buffer_hits 1

#Number of PCM bank 41 row buffer misses
pcm_bank_41_row_buffer_misses 1

#Number of PCM bank 41 opens
pcm_bank_41_num_opens 1

#Number of PCM bank 41 accesses
pcm_bank_41_num_accesses 2

#Number of PCM bank 41 closes
pcm_bank_41_num_closes 1

#Number of PCM bank 41 read after read (RAR) hazards
pcm_bank_41_num_read_after_read 0

#Number of PCM bank 41 read after write (RAW) hazards
pcm_bank_41_num_read_after_write 0

#Number of PCM bank 41 write after read (WAR) hazards
pcm_bank_41_num_write_after_read 0

#Number of PCM bank 41 write after write (WAW) hazards
pcm_bank_41_num_write_after_write 0

#Number of cycles PCM bank 41 requests wait for lower priority requests
pcm_bank_41_wait_lower_priority_time 0

#Number of cycles PCM bank 41 requests wait for same priority requests
pcm_bank_41_wait_same_priority_time 0

#Number of cycles PCM bank 41 requests wait for higher priority requests
pcm_bank_41_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 42 spend in the queue
pcm_bank_42_queue_time 460

#Number of cycles PCM bank 42 spends opening rows for requests
pcm_bank_42_open_time 440

#Number of cycles PCM bank 42 spends accessing rows for requests
pcm_bank_42_access_time 100

#Number of cycles PCM bank 42 spends closing rows for requests
pcm_bank_42_close_time 0

#Number of PCM bank 42 read requests
pcm_bank_42_read_requests 0

#Number of PCM bank 42 write requests
pcm_bank_42_write_requests 2

#Number of cyclesPCM bank 42 read requests wait in the queue
pcm_bank_42_read_queue_time 0

#Number of cyclesPCM bank 42 write requests wait in the queue
pcm_bank_42_write_queue_time 460

#Total number of cycles of PCM bank 42 read requests
pcm_bank_42_read_total_time 0

#Total number of cycles of PCM bank 42 write requests
pcm_bank_42_write_total_time 4430

#Number of PCM bank 42 row buffer hits
pcm_bank_42_row_buffer_hits 0

#Number of PCM bank 42 row buffer misses
pcm_bank_42_row_buffer_misses 2

#Number of PCM bank 42 opens
pcm_bank_42_num_opens 2

#Number of PCM bank 42 accesses
pcm_bank_42_num_accesses 2

#Number of PCM bank 42 closes
pcm_bank_42_num_closes 2

#Number of PCM bank 42 read after read (RAR) hazards
pcm_bank_42_num_read_after_read 0

#Number of PCM bank 42 read after write (RAW) hazards
pcm_bank_42_num_read_after_write 0

#Number of PCM bank 42 write after read (WAR) hazards
pcm_bank_42_num_write_after_read 0

#Number of PCM bank 42 write after write (WAW) hazards
pcm_bank_42_num_write_after_write 0

#Number of cycles PCM bank 42 requests wait for lower priority requests
pcm_bank_42_wait_lower_priority_time 0

#Number of cycles PCM bank 42 requests wait for same priority requests
pcm_bank_42_wait_same_priority_time 0

#Number of cycles PCM bank 42 requests wait for higher priority requests
pcm_bank_42_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 43 spend in the queue
pcm_bank_43_queue_time 420

#Number of cycles PCM bank 43 spends opening rows for requests
pcm_bank_43_open_time 440

#Number of cycles PCM bank 43 spends accessing rows for requests
pcm_bank_43_access_time 100

#Number of cycles PCM bank 43 spends closing rows for requests
pcm_bank_43_close_time 0

#Number of PCM bank 43 read requests
pcm_bank_43_read_requests 0

#Number of PCM bank 43 write requests
pcm_bank_43_write_requests 2

#Number of cyclesPCM bank 43 read requests wait in the queue
pcm_bank_43_read_queue_time 0

#Number of cyclesPCM bank 43 write requests wait in the queue
pcm_bank_43_write_queue_time 420

#Total number of cycles of PCM bank 43 read requests
pcm_bank_43_read_total_time 0

#Total number of cycles of PCM bank 43 write requests
pcm_bank_43_write_total_time 4350

#Number of PCM bank 43 row buffer hits
pcm_bank_43_row_buffer_hits 0

#Number of PCM bank 43 row buffer misses
pcm_bank_43_row_buffer_misses 2

#Number of PCM bank 43 opens
pcm_bank_43_num_opens 2

#Number of PCM bank 43 accesses
pcm_bank_43_num_accesses 2

#Number of PCM bank 43 closes
pcm_bank_43_num_closes 2

#Number of PCM bank 43 read after read (RAR) hazards
pcm_bank_43_num_read_after_read 0

#Number of PCM bank 43 read after write (RAW) hazards
pcm_bank_43_num_read_after_write 0

#Number of PCM bank 43 write after read (WAR) hazards
pcm_bank_43_num_write_after_read 0

#Number of PCM bank 43 write after write (WAW) hazards
pcm_bank_43_num_write_after_write 0

#Number of cycles PCM bank 43 requests wait for lower priority requests
pcm_bank_43_wait_lower_priority_time 0

#Number of cycles PCM bank 43 requests wait for same priority requests
pcm_bank_43_wait_same_priority_time 0

#Number of cycles PCM bank 43 requests wait for higher priority requests
pcm_bank_43_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 44 spend in the queue
pcm_bank_44_queue_time 380

#Number of cycles PCM bank 44 spends opening rows for requests
pcm_bank_44_open_time 440

#Number of cycles PCM bank 44 spends accessing rows for requests
pcm_bank_44_access_time 100

#Number of cycles PCM bank 44 spends closing rows for requests
pcm_bank_44_close_time 0

#Number of PCM bank 44 read requests
pcm_bank_44_read_requests 0

#Number of PCM bank 44 write requests
pcm_bank_44_write_requests 2

#Number of cyclesPCM bank 44 read requests wait in the queue
pcm_bank_44_read_queue_time 0

#Number of cyclesPCM bank 44 write requests wait in the queue
pcm_bank_44_write_queue_time 380

#Total number of cycles of PCM bank 44 read requests
pcm_bank_44_read_total_time 0

#Total number of cycles of PCM bank 44 write requests
pcm_bank_44_write_total_time 4270

#Number of PCM bank 44 row buffer hits
pcm_bank_44_row_buffer_hits 0

#Number of PCM bank 44 row buffer misses
pcm_bank_44_row_buffer_misses 2

#Number of PCM bank 44 opens
pcm_bank_44_num_opens 2

#Number of PCM bank 44 accesses
pcm_bank_44_num_accesses 2

#Number of PCM bank 44 closes
pcm_bank_44_num_closes 2

#Number of PCM bank 44 read after read (RAR) hazards
pcm_bank_44_num_read_after_read 0

#Number of PCM bank 44 read after write (RAW) hazards
pcm_bank_44_num_read_after_write 0

#Number of PCM bank 44 write after read (WAR) hazards
pcm_bank_44_num_write_after_read 0

#Number of PCM bank 44 write after write (WAW) hazards
pcm_bank_44_num_write_after_write 0

#Number of cycles PCM bank 44 requests wait for lower priority requests
pcm_bank_44_wait_lower_priority_time 0

#Number of cycles PCM bank 44 requests wait for same priority requests
pcm_bank_44_wait_same_priority_time 0

#Number of cycles PCM bank 44 requests wait for higher priority requests
pcm_bank_44_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 45 spend in the queue
pcm_bank_45_queue_time 18446744073709539906

#Number of cycles PCM bank 45 spends opening rows for requests
pcm_bank_45_open_time 220

#Number of cycles PCM bank 45 spends accessing rows for requests
pcm_bank_45_access_time 100

#Number of cycles PCM bank 45 spends closing rows for requests
pcm_bank_45_close_time 0

#Number of PCM bank 45 read requests
pcm_bank_45_read_requests 0

#Number of PCM bank 45 write requests
pcm_bank_45_write_requests 2

#Number of cyclesPCM bank 45 read requests wait in the queue
pcm_bank_45_read_queue_time 0

#Number of cyclesPCM bank 45 write requests wait in the queue
pcm_bank_45_write_queue_time 18446744073709539906

#Total number of cycles of PCM bank 45 read requests
pcm_bank_45_read_total_time 0

#Total number of cycles of PCM bank 45 write requests
pcm_bank_45_write_total_time 3390

#Number of PCM bank 45 row buffer hits
pcm_bank_45_row_buffer_hits 1

#Number of PCM bank 45 row buffer misses
pcm_bank_45_row_buffer_misses 1

#Number of PCM bank 45 opens
pcm_bank_45_num_opens 1

#Number of PCM bank 45 accesses
pcm_bank_45_num_accesses 2

#Number of PCM bank 45 closes
pcm_bank_45_num_closes 1

#Number of PCM bank 45 read after read (RAR) hazards
pcm_bank_45_num_read_after_read 0

#Number of PCM bank 45 read after write (RAW) hazards
pcm_bank_45_num_read_after_write 0

#Number of PCM bank 45 write after read (WAR) hazards
pcm_bank_45_num_write_after_read 0

#Number of PCM bank 45 write after write (WAW) hazards
pcm_bank_45_num_write_after_write 0

#Number of cycles PCM bank 45 requests wait for lower priority requests
pcm_bank_45_wait_lower_priority_time 0

#Number of cycles PCM bank 45 requests wait for same priority requests
pcm_bank_45_wait_same_priority_time 0

#Number of cycles PCM bank 45 requests wait for higher priority requests
pcm_bank_45_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 46 spend in the queue
pcm_bank_46_queue_time 18446744073709539906

#Number of cycles PCM bank 46 spends opening rows for requests
pcm_bank_46_open_time 220

#Number of cycles PCM bank 46 spends accessing rows for requests
pcm_bank_46_access_time 100

#Number of cycles PCM bank 46 spends closing rows for requests
pcm_bank_46_close_time 0

#Number of PCM bank 46 read requests
pcm_bank_46_read_requests 0

#Number of PCM bank 46 write requests
pcm_bank_46_write_requests 2

#Number of cyclesPCM bank 46 read requests wait in the queue
pcm_bank_46_read_queue_time 0

#Number of cyclesPCM bank 46 write requests wait in the queue
pcm_bank_46_write_queue_time 18446744073709539906

#Total number of cycles of PCM bank 46 read requests
pcm_bank_46_read_total_time 0

#Total number of cycles of PCM bank 46 write requests
pcm_bank_46_write_total_time 3270

#Number of PCM bank 46 row buffer hits
pcm_bank_46_row_buffer_hits 1

#Number of PCM bank 46 row buffer misses
pcm_bank_46_row_buffer_misses 1

#Number of PCM bank 46 opens
pcm_bank_46_num_opens 1

#Number of PCM bank 46 accesses
pcm_bank_46_num_accesses 2

#Number of PCM bank 46 closes
pcm_bank_46_num_closes 1

#Number of PCM bank 46 read after read (RAR) hazards
pcm_bank_46_num_read_after_read 0

#Number of PCM bank 46 read after write (RAW) hazards
pcm_bank_46_num_read_after_write 0

#Number of PCM bank 46 write after read (WAR) hazards
pcm_bank_46_num_write_after_read 0

#Number of PCM bank 46 write after write (WAW) hazards
pcm_bank_46_num_write_after_write 0

#Number of cycles PCM bank 46 requests wait for lower priority requests
pcm_bank_46_wait_lower_priority_time 0

#Number of cycles PCM bank 46 requests wait for same priority requests
pcm_bank_46_wait_same_priority_time 0

#Number of cycles PCM bank 46 requests wait for higher priority requests
pcm_bank_46_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 47 spend in the queue
pcm_bank_47_queue_time 18446744073709539906

#Number of cycles PCM bank 47 spends opening rows for requests
pcm_bank_47_open_time 220

#Number of cycles PCM bank 47 spends accessing rows for requests
pcm_bank_47_access_time 100

#Number of cycles PCM bank 47 spends closing rows for requests
pcm_bank_47_close_time 0

#Number of PCM bank 47 read requests
pcm_bank_47_read_requests 0

#Number of PCM bank 47 write requests
pcm_bank_47_write_requests 2

#Number of cyclesPCM bank 47 read requests wait in the queue
pcm_bank_47_read_queue_time 0

#Number of cyclesPCM bank 47 write requests wait in the queue
pcm_bank_47_write_queue_time 18446744073709539906

#Total number of cycles of PCM bank 47 read requests
pcm_bank_47_read_total_time 0

#Total number of cycles of PCM bank 47 write requests
pcm_bank_47_write_total_time 3350

#Number of PCM bank 47 row buffer hits
pcm_bank_47_row_buffer_hits 1

#Number of PCM bank 47 row buffer misses
pcm_bank_47_row_buffer_misses 1

#Number of PCM bank 47 opens
pcm_bank_47_num_opens 1

#Number of PCM bank 47 accesses
pcm_bank_47_num_accesses 2

#Number of PCM bank 47 closes
pcm_bank_47_num_closes 1

#Number of PCM bank 47 read after read (RAR) hazards
pcm_bank_47_num_read_after_read 0

#Number of PCM bank 47 read after write (RAW) hazards
pcm_bank_47_num_read_after_write 0

#Number of PCM bank 47 write after read (WAR) hazards
pcm_bank_47_num_write_after_read 0

#Number of PCM bank 47 write after write (WAW) hazards
pcm_bank_47_num_write_after_write 0

#Number of cycles PCM bank 47 requests wait for lower priority requests
pcm_bank_47_wait_lower_priority_time 0

#Number of cycles PCM bank 47 requests wait for same priority requests
pcm_bank_47_wait_same_priority_time 0

#Number of cycles PCM bank 47 requests wait for higher priority requests
pcm_bank_47_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 48 spend in the queue
pcm_bank_48_queue_time 545

#Number of cycles PCM bank 48 spends opening rows for requests
pcm_bank_48_open_time 440

#Number of cycles PCM bank 48 spends accessing rows for requests
pcm_bank_48_access_time 100

#Number of cycles PCM bank 48 spends closing rows for requests
pcm_bank_48_close_time 0

#Number of PCM bank 48 read requests
pcm_bank_48_read_requests 0

#Number of PCM bank 48 write requests
pcm_bank_48_write_requests 2

#Number of cyclesPCM bank 48 read requests wait in the queue
pcm_bank_48_read_queue_time 0

#Number of cyclesPCM bank 48 write requests wait in the queue
pcm_bank_48_write_queue_time 545

#Total number of cycles of PCM bank 48 read requests
pcm_bank_48_read_total_time 0

#Total number of cycles of PCM bank 48 write requests
pcm_bank_48_write_total_time 4635

#Number of PCM bank 48 row buffer hits
pcm_bank_48_row_buffer_hits 0

#Number of PCM bank 48 row buffer misses
pcm_bank_48_row_buffer_misses 2

#Number of PCM bank 48 opens
pcm_bank_48_num_opens 2

#Number of PCM bank 48 accesses
pcm_bank_48_num_accesses 2

#Number of PCM bank 48 closes
pcm_bank_48_num_closes 2

#Number of PCM bank 48 read after read (RAR) hazards
pcm_bank_48_num_read_after_read 0

#Number of PCM bank 48 read after write (RAW) hazards
pcm_bank_48_num_read_after_write 0

#Number of PCM bank 48 write after read (WAR) hazards
pcm_bank_48_num_write_after_read 0

#Number of PCM bank 48 write after write (WAW) hazards
pcm_bank_48_num_write_after_write 0

#Number of cycles PCM bank 48 requests wait for lower priority requests
pcm_bank_48_wait_lower_priority_time 0

#Number of cycles PCM bank 48 requests wait for same priority requests
pcm_bank_48_wait_same_priority_time 0

#Number of cycles PCM bank 48 requests wait for higher priority requests
pcm_bank_48_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 49 spend in the queue
pcm_bank_49_queue_time 585

#Number of cycles PCM bank 49 spends opening rows for requests
pcm_bank_49_open_time 440

#Number of cycles PCM bank 49 spends accessing rows for requests
pcm_bank_49_access_time 100

#Number of cycles PCM bank 49 spends closing rows for requests
pcm_bank_49_close_time 0

#Number of PCM bank 49 read requests
pcm_bank_49_read_requests 0

#Number of PCM bank 49 write requests
pcm_bank_49_write_requests 2

#Number of cyclesPCM bank 49 read requests wait in the queue
pcm_bank_49_read_queue_time 0

#Number of cyclesPCM bank 49 write requests wait in the queue
pcm_bank_49_write_queue_time 585

#Total number of cycles of PCM bank 49 read requests
pcm_bank_49_read_total_time 0

#Total number of cycles of PCM bank 49 write requests
pcm_bank_49_write_total_time 4715

#Number of PCM bank 49 row buffer hits
pcm_bank_49_row_buffer_hits 0

#Number of PCM bank 49 row buffer misses
pcm_bank_49_row_buffer_misses 2

#Number of PCM bank 49 opens
pcm_bank_49_num_opens 2

#Number of PCM bank 49 accesses
pcm_bank_49_num_accesses 2

#Number of PCM bank 49 closes
pcm_bank_49_num_closes 2

#Number of PCM bank 49 read after read (RAR) hazards
pcm_bank_49_num_read_after_read 0

#Number of PCM bank 49 read after write (RAW) hazards
pcm_bank_49_num_read_after_write 0

#Number of PCM bank 49 write after read (WAR) hazards
pcm_bank_49_num_write_after_read 0

#Number of PCM bank 49 write after write (WAW) hazards
pcm_bank_49_num_write_after_write 0

#Number of cycles PCM bank 49 requests wait for lower priority requests
pcm_bank_49_wait_lower_priority_time 0

#Number of cycles PCM bank 49 requests wait for same priority requests
pcm_bank_49_wait_same_priority_time 0

#Number of cycles PCM bank 49 requests wait for higher priority requests
pcm_bank_49_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 50 spend in the queue
pcm_bank_50_queue_time 185

#Number of cycles PCM bank 50 spends opening rows for requests
pcm_bank_50_open_time 440

#Number of cycles PCM bank 50 spends accessing rows for requests
pcm_bank_50_access_time 100

#Number of cycles PCM bank 50 spends closing rows for requests
pcm_bank_50_close_time 0

#Number of PCM bank 50 read requests
pcm_bank_50_read_requests 0

#Number of PCM bank 50 write requests
pcm_bank_50_write_requests 2

#Number of cyclesPCM bank 50 read requests wait in the queue
pcm_bank_50_read_queue_time 0

#Number of cyclesPCM bank 50 write requests wait in the queue
pcm_bank_50_write_queue_time 185

#Total number of cycles of PCM bank 50 read requests
pcm_bank_50_read_total_time 0

#Total number of cycles of PCM bank 50 write requests
pcm_bank_50_write_total_time 3915

#Number of PCM bank 50 row buffer hits
pcm_bank_50_row_buffer_hits 0

#Number of PCM bank 50 row buffer misses
pcm_bank_50_row_buffer_misses 2

#Number of PCM bank 50 opens
pcm_bank_50_num_opens 2

#Number of PCM bank 50 accesses
pcm_bank_50_num_accesses 2

#Number of PCM bank 50 closes
pcm_bank_50_num_closes 2

#Number of PCM bank 50 read after read (RAR) hazards
pcm_bank_50_num_read_after_read 0

#Number of PCM bank 50 read after write (RAW) hazards
pcm_bank_50_num_read_after_write 0

#Number of PCM bank 50 write after read (WAR) hazards
pcm_bank_50_num_write_after_read 0

#Number of PCM bank 50 write after write (WAW) hazards
pcm_bank_50_num_write_after_write 0

#Number of cycles PCM bank 50 requests wait for lower priority requests
pcm_bank_50_wait_lower_priority_time 0

#Number of cycles PCM bank 50 requests wait for same priority requests
pcm_bank_50_wait_same_priority_time 0

#Number of cycles PCM bank 50 requests wait for higher priority requests
pcm_bank_50_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 51 spend in the queue
pcm_bank_51_queue_time 145

#Number of cycles PCM bank 51 spends opening rows for requests
pcm_bank_51_open_time 440

#Number of cycles PCM bank 51 spends accessing rows for requests
pcm_bank_51_access_time 100

#Number of cycles PCM bank 51 spends closing rows for requests
pcm_bank_51_close_time 0

#Number of PCM bank 51 read requests
pcm_bank_51_read_requests 0

#Number of PCM bank 51 write requests
pcm_bank_51_write_requests 2

#Number of cyclesPCM bank 51 read requests wait in the queue
pcm_bank_51_read_queue_time 0

#Number of cyclesPCM bank 51 write requests wait in the queue
pcm_bank_51_write_queue_time 145

#Total number of cycles of PCM bank 51 read requests
pcm_bank_51_read_total_time 0

#Total number of cycles of PCM bank 51 write requests
pcm_bank_51_write_total_time 3835

#Number of PCM bank 51 row buffer hits
pcm_bank_51_row_buffer_hits 0

#Number of PCM bank 51 row buffer misses
pcm_bank_51_row_buffer_misses 2

#Number of PCM bank 51 opens
pcm_bank_51_num_opens 2

#Number of PCM bank 51 accesses
pcm_bank_51_num_accesses 2

#Number of PCM bank 51 closes
pcm_bank_51_num_closes 2

#Number of PCM bank 51 read after read (RAR) hazards
pcm_bank_51_num_read_after_read 0

#Number of PCM bank 51 read after write (RAW) hazards
pcm_bank_51_num_read_after_write 0

#Number of PCM bank 51 write after read (WAR) hazards
pcm_bank_51_num_write_after_read 0

#Number of PCM bank 51 write after write (WAW) hazards
pcm_bank_51_num_write_after_write 0

#Number of cycles PCM bank 51 requests wait for lower priority requests
pcm_bank_51_wait_lower_priority_time 0

#Number of cycles PCM bank 51 requests wait for same priority requests
pcm_bank_51_wait_same_priority_time 0

#Number of cycles PCM bank 51 requests wait for higher priority requests
pcm_bank_51_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 52 spend in the queue
pcm_bank_52_queue_time 105

#Number of cycles PCM bank 52 spends opening rows for requests
pcm_bank_52_open_time 440

#Number of cycles PCM bank 52 spends accessing rows for requests
pcm_bank_52_access_time 100

#Number of cycles PCM bank 52 spends closing rows for requests
pcm_bank_52_close_time 0

#Number of PCM bank 52 read requests
pcm_bank_52_read_requests 0

#Number of PCM bank 52 write requests
pcm_bank_52_write_requests 2

#Number of cyclesPCM bank 52 read requests wait in the queue
pcm_bank_52_read_queue_time 0

#Number of cyclesPCM bank 52 write requests wait in the queue
pcm_bank_52_write_queue_time 105

#Total number of cycles of PCM bank 52 read requests
pcm_bank_52_read_total_time 0

#Total number of cycles of PCM bank 52 write requests
pcm_bank_52_write_total_time 3755

#Number of PCM bank 52 row buffer hits
pcm_bank_52_row_buffer_hits 0

#Number of PCM bank 52 row buffer misses
pcm_bank_52_row_buffer_misses 2

#Number of PCM bank 52 opens
pcm_bank_52_num_opens 2

#Number of PCM bank 52 accesses
pcm_bank_52_num_accesses 2

#Number of PCM bank 52 closes
pcm_bank_52_num_closes 2

#Number of PCM bank 52 read after read (RAR) hazards
pcm_bank_52_num_read_after_read 0

#Number of PCM bank 52 read after write (RAW) hazards
pcm_bank_52_num_read_after_write 0

#Number of PCM bank 52 write after read (WAR) hazards
pcm_bank_52_num_write_after_read 0

#Number of PCM bank 52 write after write (WAW) hazards
pcm_bank_52_num_write_after_write 0

#Number of cycles PCM bank 52 requests wait for lower priority requests
pcm_bank_52_wait_lower_priority_time 0

#Number of cycles PCM bank 52 requests wait for same priority requests
pcm_bank_52_wait_same_priority_time 0

#Number of cycles PCM bank 52 requests wait for higher priority requests
pcm_bank_52_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 53 spend in the queue
pcm_bank_53_queue_time 265

#Number of cycles PCM bank 53 spends opening rows for requests
pcm_bank_53_open_time 440

#Number of cycles PCM bank 53 spends accessing rows for requests
pcm_bank_53_access_time 100

#Number of cycles PCM bank 53 spends closing rows for requests
pcm_bank_53_close_time 0

#Number of PCM bank 53 read requests
pcm_bank_53_read_requests 0

#Number of PCM bank 53 write requests
pcm_bank_53_write_requests 2

#Number of cyclesPCM bank 53 read requests wait in the queue
pcm_bank_53_read_queue_time 0

#Number of cyclesPCM bank 53 write requests wait in the queue
pcm_bank_53_write_queue_time 265

#Total number of cycles of PCM bank 53 read requests
pcm_bank_53_read_total_time 0

#Total number of cycles of PCM bank 53 write requests
pcm_bank_53_write_total_time 4075

#Number of PCM bank 53 row buffer hits
pcm_bank_53_row_buffer_hits 0

#Number of PCM bank 53 row buffer misses
pcm_bank_53_row_buffer_misses 2

#Number of PCM bank 53 opens
pcm_bank_53_num_opens 2

#Number of PCM bank 53 accesses
pcm_bank_53_num_accesses 2

#Number of PCM bank 53 closes
pcm_bank_53_num_closes 2

#Number of PCM bank 53 read after read (RAR) hazards
pcm_bank_53_num_read_after_read 0

#Number of PCM bank 53 read after write (RAW) hazards
pcm_bank_53_num_read_after_write 0

#Number of PCM bank 53 write after read (WAR) hazards
pcm_bank_53_num_write_after_read 0

#Number of PCM bank 53 write after write (WAW) hazards
pcm_bank_53_num_write_after_write 0

#Number of cycles PCM bank 53 requests wait for lower priority requests
pcm_bank_53_wait_lower_priority_time 0

#Number of cycles PCM bank 53 requests wait for same priority requests
pcm_bank_53_wait_same_priority_time 0

#Number of cycles PCM bank 53 requests wait for higher priority requests
pcm_bank_53_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 54 spend in the queue
pcm_bank_54_queue_time 25

#Number of cycles PCM bank 54 spends opening rows for requests
pcm_bank_54_open_time 440

#Number of cycles PCM bank 54 spends accessing rows for requests
pcm_bank_54_access_time 100

#Number of cycles PCM bank 54 spends closing rows for requests
pcm_bank_54_close_time 0

#Number of PCM bank 54 read requests
pcm_bank_54_read_requests 0

#Number of PCM bank 54 write requests
pcm_bank_54_write_requests 2

#Number of cyclesPCM bank 54 read requests wait in the queue
pcm_bank_54_read_queue_time 0

#Number of cyclesPCM bank 54 write requests wait in the queue
pcm_bank_54_write_queue_time 25

#Total number of cycles of PCM bank 54 read requests
pcm_bank_54_read_total_time 0

#Total number of cycles of PCM bank 54 write requests
pcm_bank_54_write_total_time 3315

#Number of PCM bank 54 row buffer hits
pcm_bank_54_row_buffer_hits 0

#Number of PCM bank 54 row buffer misses
pcm_bank_54_row_buffer_misses 2

#Number of PCM bank 54 opens
pcm_bank_54_num_opens 2

#Number of PCM bank 54 accesses
pcm_bank_54_num_accesses 2

#Number of PCM bank 54 closes
pcm_bank_54_num_closes 2

#Number of PCM bank 54 read after read (RAR) hazards
pcm_bank_54_num_read_after_read 0

#Number of PCM bank 54 read after write (RAW) hazards
pcm_bank_54_num_read_after_write 0

#Number of PCM bank 54 write after read (WAR) hazards
pcm_bank_54_num_write_after_read 0

#Number of PCM bank 54 write after write (WAW) hazards
pcm_bank_54_num_write_after_write 0

#Number of cycles PCM bank 54 requests wait for lower priority requests
pcm_bank_54_wait_lower_priority_time 0

#Number of cycles PCM bank 54 requests wait for same priority requests
pcm_bank_54_wait_same_priority_time 0

#Number of cycles PCM bank 54 requests wait for higher priority requests
pcm_bank_54_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 55 spend in the queue
pcm_bank_55_queue_time 0

#Number of cycles PCM bank 55 spends opening rows for requests
pcm_bank_55_open_time 440

#Number of cycles PCM bank 55 spends accessing rows for requests
pcm_bank_55_access_time 100

#Number of cycles PCM bank 55 spends closing rows for requests
pcm_bank_55_close_time 0

#Number of PCM bank 55 read requests
pcm_bank_55_read_requests 0

#Number of PCM bank 55 write requests
pcm_bank_55_write_requests 2

#Number of cyclesPCM bank 55 read requests wait in the queue
pcm_bank_55_read_queue_time 0

#Number of cyclesPCM bank 55 write requests wait in the queue
pcm_bank_55_write_queue_time 0

#Total number of cycles of PCM bank 55 read requests
pcm_bank_55_read_total_time 0

#Total number of cycles of PCM bank 55 write requests
pcm_bank_55_write_total_time 3235

#Number of PCM bank 55 row buffer hits
pcm_bank_55_row_buffer_hits 0

#Number of PCM bank 55 row buffer misses
pcm_bank_55_row_buffer_misses 2

#Number of PCM bank 55 opens
pcm_bank_55_num_opens 2

#Number of PCM bank 55 accesses
pcm_bank_55_num_accesses 2

#Number of PCM bank 55 closes
pcm_bank_55_num_closes 2

#Number of PCM bank 55 read after read (RAR) hazards
pcm_bank_55_num_read_after_read 0

#Number of PCM bank 55 read after write (RAW) hazards
pcm_bank_55_num_read_after_write 0

#Number of PCM bank 55 write after read (WAR) hazards
pcm_bank_55_num_write_after_read 0

#Number of PCM bank 55 write after write (WAW) hazards
pcm_bank_55_num_write_after_write 0

#Number of cycles PCM bank 55 requests wait for lower priority requests
pcm_bank_55_wait_lower_priority_time 0

#Number of cycles PCM bank 55 requests wait for same priority requests
pcm_bank_55_wait_same_priority_time 0

#Number of cycles PCM bank 55 requests wait for higher priority requests
pcm_bank_55_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 56 spend in the queue
pcm_bank_56_queue_time 0

#Number of cycles PCM bank 56 spends opening rows for requests
pcm_bank_56_open_time 440

#Number of cycles PCM bank 56 spends accessing rows for requests
pcm_bank_56_access_time 100

#Number of cycles PCM bank 56 spends closing rows for requests
pcm_bank_56_close_time 0

#Number of PCM bank 56 read requests
pcm_bank_56_read_requests 0

#Number of PCM bank 56 write requests
pcm_bank_56_write_requests 2

#Number of cyclesPCM bank 56 read requests wait in the queue
pcm_bank_56_read_queue_time 0

#Number of cyclesPCM bank 56 write requests wait in the queue
pcm_bank_56_write_queue_time 0

#Total number of cycles of PCM bank 56 read requests
pcm_bank_56_read_total_time 0

#Total number of cycles of PCM bank 56 write requests
pcm_bank_56_write_total_time 3400

#Number of PCM bank 56 row buffer hits
pcm_bank_56_row_buffer_hits 0

#Number of PCM bank 56 row buffer misses
pcm_bank_56_row_buffer_misses 2

#Number of PCM bank 56 opens
pcm_bank_56_num_opens 2

#Number of PCM bank 56 accesses
pcm_bank_56_num_accesses 2

#Number of PCM bank 56 closes
pcm_bank_56_num_closes 2

#Number of PCM bank 56 read after read (RAR) hazards
pcm_bank_56_num_read_after_read 0

#Number of PCM bank 56 read after write (RAW) hazards
pcm_bank_56_num_read_after_write 0

#Number of PCM bank 56 write after read (WAR) hazards
pcm_bank_56_num_write_after_read 0

#Number of PCM bank 56 write after write (WAW) hazards
pcm_bank_56_num_write_after_write 0

#Number of cycles PCM bank 56 requests wait for lower priority requests
pcm_bank_56_wait_lower_priority_time 0

#Number of cycles PCM bank 56 requests wait for same priority requests
pcm_bank_56_wait_same_priority_time 0

#Number of cycles PCM bank 56 requests wait for higher priority requests
pcm_bank_56_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 57 spend in the queue
pcm_bank_57_queue_time 0

#Number of cycles PCM bank 57 spends opening rows for requests
pcm_bank_57_open_time 440

#Number of cycles PCM bank 57 spends accessing rows for requests
pcm_bank_57_access_time 100

#Number of cycles PCM bank 57 spends closing rows for requests
pcm_bank_57_close_time 0

#Number of PCM bank 57 read requests
pcm_bank_57_read_requests 0

#Number of PCM bank 57 write requests
pcm_bank_57_write_requests 2

#Number of cyclesPCM bank 57 read requests wait in the queue
pcm_bank_57_read_queue_time 0

#Number of cyclesPCM bank 57 write requests wait in the queue
pcm_bank_57_write_queue_time 0

#Total number of cycles of PCM bank 57 read requests
pcm_bank_57_read_total_time 0

#Total number of cycles of PCM bank 57 write requests
pcm_bank_57_write_total_time 3400

#Number of PCM bank 57 row buffer hits
pcm_bank_57_row_buffer_hits 0

#Number of PCM bank 57 row buffer misses
pcm_bank_57_row_buffer_misses 2

#Number of PCM bank 57 opens
pcm_bank_57_num_opens 2

#Number of PCM bank 57 accesses
pcm_bank_57_num_accesses 2

#Number of PCM bank 57 closes
pcm_bank_57_num_closes 2

#Number of PCM bank 57 read after read (RAR) hazards
pcm_bank_57_num_read_after_read 0

#Number of PCM bank 57 read after write (RAW) hazards
pcm_bank_57_num_read_after_write 0

#Number of PCM bank 57 write after read (WAR) hazards
pcm_bank_57_num_write_after_read 0

#Number of PCM bank 57 write after write (WAW) hazards
pcm_bank_57_num_write_after_write 0

#Number of cycles PCM bank 57 requests wait for lower priority requests
pcm_bank_57_wait_lower_priority_time 0

#Number of cycles PCM bank 57 requests wait for same priority requests
pcm_bank_57_wait_same_priority_time 0

#Number of cycles PCM bank 57 requests wait for higher priority requests
pcm_bank_57_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 58 spend in the queue
pcm_bank_58_queue_time 0

#Number of cycles PCM bank 58 spends opening rows for requests
pcm_bank_58_open_time 440

#Number of cycles PCM bank 58 spends accessing rows for requests
pcm_bank_58_access_time 100

#Number of cycles PCM bank 58 spends closing rows for requests
pcm_bank_58_close_time 0

#Number of PCM bank 58 read requests
pcm_bank_58_read_requests 0

#Number of PCM bank 58 write requests
pcm_bank_58_write_requests 2

#Number of cyclesPCM bank 58 read requests wait in the queue
pcm_bank_58_read_queue_time 0

#Number of cyclesPCM bank 58 write requests wait in the queue
pcm_bank_58_write_queue_time 0

#Total number of cycles of PCM bank 58 read requests
pcm_bank_58_read_total_time 0

#Total number of cycles of PCM bank 58 write requests
pcm_bank_58_write_total_time 3320

#Number of PCM bank 58 row buffer hits
pcm_bank_58_row_buffer_hits 0

#Number of PCM bank 58 row buffer misses
pcm_bank_58_row_buffer_misses 2

#Number of PCM bank 58 opens
pcm_bank_58_num_opens 2

#Number of PCM bank 58 accesses
pcm_bank_58_num_accesses 2

#Number of PCM bank 58 closes
pcm_bank_58_num_closes 2

#Number of PCM bank 58 read after read (RAR) hazards
pcm_bank_58_num_read_after_read 0

#Number of PCM bank 58 read after write (RAW) hazards
pcm_bank_58_num_read_after_write 0

#Number of PCM bank 58 write after read (WAR) hazards
pcm_bank_58_num_write_after_read 0

#Number of PCM bank 58 write after write (WAW) hazards
pcm_bank_58_num_write_after_write 0

#Number of cycles PCM bank 58 requests wait for lower priority requests
pcm_bank_58_wait_lower_priority_time 0

#Number of cycles PCM bank 58 requests wait for same priority requests
pcm_bank_58_wait_same_priority_time 0

#Number of cycles PCM bank 58 requests wait for higher priority requests
pcm_bank_58_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 59 spend in the queue
pcm_bank_59_queue_time 0

#Number of cycles PCM bank 59 spends opening rows for requests
pcm_bank_59_open_time 440

#Number of cycles PCM bank 59 spends accessing rows for requests
pcm_bank_59_access_time 100

#Number of cycles PCM bank 59 spends closing rows for requests
pcm_bank_59_close_time 0

#Number of PCM bank 59 read requests
pcm_bank_59_read_requests 0

#Number of PCM bank 59 write requests
pcm_bank_59_write_requests 2

#Number of cyclesPCM bank 59 read requests wait in the queue
pcm_bank_59_read_queue_time 0

#Number of cyclesPCM bank 59 write requests wait in the queue
pcm_bank_59_write_queue_time 0

#Total number of cycles of PCM bank 59 read requests
pcm_bank_59_read_total_time 0

#Total number of cycles of PCM bank 59 write requests
pcm_bank_59_write_total_time 3040

#Number of PCM bank 59 row buffer hits
pcm_bank_59_row_buffer_hits 0

#Number of PCM bank 59 row buffer misses
pcm_bank_59_row_buffer_misses 2

#Number of PCM bank 59 opens
pcm_bank_59_num_opens 2

#Number of PCM bank 59 accesses
pcm_bank_59_num_accesses 2

#Number of PCM bank 59 closes
pcm_bank_59_num_closes 2

#Number of PCM bank 59 read after read (RAR) hazards
pcm_bank_59_num_read_after_read 0

#Number of PCM bank 59 read after write (RAW) hazards
pcm_bank_59_num_read_after_write 0

#Number of PCM bank 59 write after read (WAR) hazards
pcm_bank_59_num_write_after_read 0

#Number of PCM bank 59 write after write (WAW) hazards
pcm_bank_59_num_write_after_write 0

#Number of cycles PCM bank 59 requests wait for lower priority requests
pcm_bank_59_wait_lower_priority_time 0

#Number of cycles PCM bank 59 requests wait for same priority requests
pcm_bank_59_wait_same_priority_time 0

#Number of cycles PCM bank 59 requests wait for higher priority requests
pcm_bank_59_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 60 spend in the queue
pcm_bank_60_queue_time 0

#Number of cycles PCM bank 60 spends opening rows for requests
pcm_bank_60_open_time 440

#Number of cycles PCM bank 60 spends accessing rows for requests
pcm_bank_60_access_time 100

#Number of cycles PCM bank 60 spends closing rows for requests
pcm_bank_60_close_time 0

#Number of PCM bank 60 read requests
pcm_bank_60_read_requests 0

#Number of PCM bank 60 write requests
pcm_bank_60_write_requests 2

#Number of cyclesPCM bank 60 read requests wait in the queue
pcm_bank_60_read_queue_time 0

#Number of cyclesPCM bank 60 write requests wait in the queue
pcm_bank_60_write_queue_time 0

#Total number of cycles of PCM bank 60 read requests
pcm_bank_60_read_total_time 0

#Total number of cycles of PCM bank 60 write requests
pcm_bank_60_write_total_time 3040

#Number of PCM bank 60 row buffer hits
pcm_bank_60_row_buffer_hits 0

#Number of PCM bank 60 row buffer misses
pcm_bank_60_row_buffer_misses 2

#Number of PCM bank 60 opens
pcm_bank_60_num_opens 2

#Number of PCM bank 60 accesses
pcm_bank_60_num_accesses 2

#Number of PCM bank 60 closes
pcm_bank_60_num_closes 2

#Number of PCM bank 60 read after read (RAR) hazards
pcm_bank_60_num_read_after_read 0

#Number of PCM bank 60 read after write (RAW) hazards
pcm_bank_60_num_read_after_write 0

#Number of PCM bank 60 write after read (WAR) hazards
pcm_bank_60_num_write_after_read 0

#Number of PCM bank 60 write after write (WAW) hazards
pcm_bank_60_num_write_after_write 0

#Number of cycles PCM bank 60 requests wait for lower priority requests
pcm_bank_60_wait_lower_priority_time 0

#Number of cycles PCM bank 60 requests wait for same priority requests
pcm_bank_60_wait_same_priority_time 0

#Number of cycles PCM bank 60 requests wait for higher priority requests
pcm_bank_60_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 61 spend in the queue
pcm_bank_61_queue_time 0

#Number of cycles PCM bank 61 spends opening rows for requests
pcm_bank_61_open_time 440

#Number of cycles PCM bank 61 spends accessing rows for requests
pcm_bank_61_access_time 100

#Number of cycles PCM bank 61 spends closing rows for requests
pcm_bank_61_close_time 0

#Number of PCM bank 61 read requests
pcm_bank_61_read_requests 0

#Number of PCM bank 61 write requests
pcm_bank_61_write_requests 2

#Number of cyclesPCM bank 61 read requests wait in the queue
pcm_bank_61_read_queue_time 0

#Number of cyclesPCM bank 61 write requests wait in the queue
pcm_bank_61_write_queue_time 0

#Total number of cycles of PCM bank 61 read requests
pcm_bank_61_read_total_time 0

#Total number of cycles of PCM bank 61 write requests
pcm_bank_61_write_total_time 3000

#Number of PCM bank 61 row buffer hits
pcm_bank_61_row_buffer_hits 0

#Number of PCM bank 61 row buffer misses
pcm_bank_61_row_buffer_misses 2

#Number of PCM bank 61 opens
pcm_bank_61_num_opens 2

#Number of PCM bank 61 accesses
pcm_bank_61_num_accesses 2

#Number of PCM bank 61 closes
pcm_bank_61_num_closes 2

#Number of PCM bank 61 read after read (RAR) hazards
pcm_bank_61_num_read_after_read 0

#Number of PCM bank 61 read after write (RAW) hazards
pcm_bank_61_num_read_after_write 0

#Number of PCM bank 61 write after read (WAR) hazards
pcm_bank_61_num_write_after_read 0

#Number of PCM bank 61 write after write (WAW) hazards
pcm_bank_61_num_write_after_write 0

#Number of cycles PCM bank 61 requests wait for lower priority requests
pcm_bank_61_wait_lower_priority_time 0

#Number of cycles PCM bank 61 requests wait for same priority requests
pcm_bank_61_wait_same_priority_time 0

#Number of cycles PCM bank 61 requests wait for higher priority requests
pcm_bank_61_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 62 spend in the queue
pcm_bank_62_queue_time 18446744073709539836

#Number of cycles PCM bank 62 spends opening rows for requests
pcm_bank_62_open_time 220

#Number of cycles PCM bank 62 spends accessing rows for requests
pcm_bank_62_access_time 100

#Number of cycles PCM bank 62 spends closing rows for requests
pcm_bank_62_close_time 0

#Number of PCM bank 62 read requests
pcm_bank_62_read_requests 0

#Number of PCM bank 62 write requests
pcm_bank_62_write_requests 2

#Number of cyclesPCM bank 62 read requests wait in the queue
pcm_bank_62_read_queue_time 0

#Number of cyclesPCM bank 62 write requests wait in the queue
pcm_bank_62_write_queue_time 18446744073709539836

#Total number of cycles of PCM bank 62 read requests
pcm_bank_62_read_total_time 0

#Total number of cycles of PCM bank 62 write requests
pcm_bank_62_write_total_time 3800

#Number of PCM bank 62 row buffer hits
pcm_bank_62_row_buffer_hits 1

#Number of PCM bank 62 row buffer misses
pcm_bank_62_row_buffer_misses 1

#Number of PCM bank 62 opens
pcm_bank_62_num_opens 1

#Number of PCM bank 62 accesses
pcm_bank_62_num_accesses 2

#Number of PCM bank 62 closes
pcm_bank_62_num_closes 1

#Number of PCM bank 62 read after read (RAR) hazards
pcm_bank_62_num_read_after_read 0

#Number of PCM bank 62 read after write (RAW) hazards
pcm_bank_62_num_read_after_write 0

#Number of PCM bank 62 write after read (WAR) hazards
pcm_bank_62_num_write_after_read 0

#Number of PCM bank 62 write after write (WAW) hazards
pcm_bank_62_num_write_after_write 0

#Number of cycles PCM bank 62 requests wait for lower priority requests
pcm_bank_62_wait_lower_priority_time 0

#Number of cycles PCM bank 62 requests wait for same priority requests
pcm_bank_62_wait_same_priority_time 0

#Number of cycles PCM bank 62 requests wait for higher priority requests
pcm_bank_62_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 63 spend in the queue
pcm_bank_63_queue_time 0

#Number of cycles PCM bank 63 spends opening rows for requests
pcm_bank_63_open_time 440

#Number of cycles PCM bank 63 spends accessing rows for requests
pcm_bank_63_access_time 100

#Number of cycles PCM bank 63 spends closing rows for requests
pcm_bank_63_close_time 0

#Number of PCM bank 63 read requests
pcm_bank_63_read_requests 0

#Number of PCM bank 63 write requests
pcm_bank_63_write_requests 2

#Number of cyclesPCM bank 63 read requests wait in the queue
pcm_bank_63_read_queue_time 0

#Number of cyclesPCM bank 63 write requests wait in the queue
pcm_bank_63_write_queue_time 0

#Total number of cycles of PCM bank 63 read requests
pcm_bank_63_read_total_time 0

#Total number of cycles of PCM bank 63 write requests
pcm_bank_63_write_total_time 2960

#Number of PCM bank 63 row buffer hits
pcm_bank_63_row_buffer_hits 0

#Number of PCM bank 63 row buffer misses
pcm_bank_63_row_buffer_misses 2

#Number of PCM bank 63 opens
pcm_bank_63_num_opens 2

#Number of PCM bank 63 accesses
pcm_bank_63_num_accesses 2

#Number of PCM bank 63 closes
pcm_bank_63_num_closes 2

#Number of PCM bank 63 read after read (RAR) hazards
pcm_bank_63_num_read_after_read 0

#Number of PCM bank 63 read after write (RAW) hazards
pcm_bank_63_num_read_after_write 0

#Number of PCM bank 63 write after read (WAR) hazards
pcm_bank_63_num_write_after_read 0

#Number of PCM bank 63 write after write (WAW) hazards
pcm_bank_63_num_write_after_write 0

#Number of cycles PCM bank 63 requests wait for lower priority requests
pcm_bank_63_wait_lower_priority_time 0

#Number of cycles PCM bank 63 requests wait for same priority requests
pcm_bank_63_wait_same_priority_time 0

#Number of cycles PCM bank 63 requests wait for higher priority requests
pcm_bank_63_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 64 spend in the queue
pcm_bank_64_queue_time 0

#Number of cycles PCM bank 64 spends opening rows for requests
pcm_bank_64_open_time 0

#Number of cycles PCM bank 64 spends accessing rows for requests
pcm_bank_64_access_time 0

#Number of cycles PCM bank 64 spends closing rows for requests
pcm_bank_64_close_time 0

#Number of PCM bank 64 read requests
pcm_bank_64_read_requests 0

#Number of PCM bank 64 write requests
pcm_bank_64_write_requests 0

#Number of cyclesPCM bank 64 read requests wait in the queue
pcm_bank_64_read_queue_time 0

#Number of cyclesPCM bank 64 write requests wait in the queue
pcm_bank_64_write_queue_time 0

#Total number of cycles of PCM bank 64 read requests
pcm_bank_64_read_total_time 0

#Total number of cycles of PCM bank 64 write requests
pcm_bank_64_write_total_time 0

#Number of PCM bank 64 row buffer hits
pcm_bank_64_row_buffer_hits 0

#Number of PCM bank 64 row buffer misses
pcm_bank_64_row_buffer_misses 0

#Number of PCM bank 64 opens
pcm_bank_64_num_opens 0

#Number of PCM bank 64 accesses
pcm_bank_64_num_accesses 0

#Number of PCM bank 64 closes
pcm_bank_64_num_closes 0

#Number of PCM bank 64 read after read (RAR) hazards
pcm_bank_64_num_read_after_read 0

#Number of PCM bank 64 read after write (RAW) hazards
pcm_bank_64_num_read_after_write 0

#Number of PCM bank 64 write after read (WAR) hazards
pcm_bank_64_num_write_after_read 0

#Number of PCM bank 64 write after write (WAW) hazards
pcm_bank_64_num_write_after_write 0

#Number of cycles PCM bank 64 requests wait for lower priority requests
pcm_bank_64_wait_lower_priority_time 0

#Number of cycles PCM bank 64 requests wait for same priority requests
pcm_bank_64_wait_same_priority_time 0

#Number of cycles PCM bank 64 requests wait for higher priority requests
pcm_bank_64_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 65 spend in the queue
pcm_bank_65_queue_time 0

#Number of cycles PCM bank 65 spends opening rows for requests
pcm_bank_65_open_time 0

#Number of cycles PCM bank 65 spends accessing rows for requests
pcm_bank_65_access_time 0

#Number of cycles PCM bank 65 spends closing rows for requests
pcm_bank_65_close_time 0

#Number of PCM bank 65 read requests
pcm_bank_65_read_requests 0

#Number of PCM bank 65 write requests
pcm_bank_65_write_requests 0

#Number of cyclesPCM bank 65 read requests wait in the queue
pcm_bank_65_read_queue_time 0

#Number of cyclesPCM bank 65 write requests wait in the queue
pcm_bank_65_write_queue_time 0

#Total number of cycles of PCM bank 65 read requests
pcm_bank_65_read_total_time 0

#Total number of cycles of PCM bank 65 write requests
pcm_bank_65_write_total_time 0

#Number of PCM bank 65 row buffer hits
pcm_bank_65_row_buffer_hits 0

#Number of PCM bank 65 row buffer misses
pcm_bank_65_row_buffer_misses 0

#Number of PCM bank 65 opens
pcm_bank_65_num_opens 0

#Number of PCM bank 65 accesses
pcm_bank_65_num_accesses 0

#Number of PCM bank 65 closes
pcm_bank_65_num_closes 0

#Number of PCM bank 65 read after read (RAR) hazards
pcm_bank_65_num_read_after_read 0

#Number of PCM bank 65 read after write (RAW) hazards
pcm_bank_65_num_read_after_write 0

#Number of PCM bank 65 write after read (WAR) hazards
pcm_bank_65_num_write_after_read 0

#Number of PCM bank 65 write after write (WAW) hazards
pcm_bank_65_num_write_after_write 0

#Number of cycles PCM bank 65 requests wait for lower priority requests
pcm_bank_65_wait_lower_priority_time 0

#Number of cycles PCM bank 65 requests wait for same priority requests
pcm_bank_65_wait_same_priority_time 0

#Number of cycles PCM bank 65 requests wait for higher priority requests
pcm_bank_65_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 66 spend in the queue
pcm_bank_66_queue_time 0

#Number of cycles PCM bank 66 spends opening rows for requests
pcm_bank_66_open_time 0

#Number of cycles PCM bank 66 spends accessing rows for requests
pcm_bank_66_access_time 0

#Number of cycles PCM bank 66 spends closing rows for requests
pcm_bank_66_close_time 0

#Number of PCM bank 66 read requests
pcm_bank_66_read_requests 0

#Number of PCM bank 66 write requests
pcm_bank_66_write_requests 0

#Number of cyclesPCM bank 66 read requests wait in the queue
pcm_bank_66_read_queue_time 0

#Number of cyclesPCM bank 66 write requests wait in the queue
pcm_bank_66_write_queue_time 0

#Total number of cycles of PCM bank 66 read requests
pcm_bank_66_read_total_time 0

#Total number of cycles of PCM bank 66 write requests
pcm_bank_66_write_total_time 0

#Number of PCM bank 66 row buffer hits
pcm_bank_66_row_buffer_hits 0

#Number of PCM bank 66 row buffer misses
pcm_bank_66_row_buffer_misses 0

#Number of PCM bank 66 opens
pcm_bank_66_num_opens 0

#Number of PCM bank 66 accesses
pcm_bank_66_num_accesses 0

#Number of PCM bank 66 closes
pcm_bank_66_num_closes 0

#Number of PCM bank 66 read after read (RAR) hazards
pcm_bank_66_num_read_after_read 0

#Number of PCM bank 66 read after write (RAW) hazards
pcm_bank_66_num_read_after_write 0

#Number of PCM bank 66 write after read (WAR) hazards
pcm_bank_66_num_write_after_read 0

#Number of PCM bank 66 write after write (WAW) hazards
pcm_bank_66_num_write_after_write 0

#Number of cycles PCM bank 66 requests wait for lower priority requests
pcm_bank_66_wait_lower_priority_time 0

#Number of cycles PCM bank 66 requests wait for same priority requests
pcm_bank_66_wait_same_priority_time 0

#Number of cycles PCM bank 66 requests wait for higher priority requests
pcm_bank_66_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 67 spend in the queue
pcm_bank_67_queue_time 0

#Number of cycles PCM bank 67 spends opening rows for requests
pcm_bank_67_open_time 0

#Number of cycles PCM bank 67 spends accessing rows for requests
pcm_bank_67_access_time 0

#Number of cycles PCM bank 67 spends closing rows for requests
pcm_bank_67_close_time 0

#Number of PCM bank 67 read requests
pcm_bank_67_read_requests 0

#Number of PCM bank 67 write requests
pcm_bank_67_write_requests 0

#Number of cyclesPCM bank 67 read requests wait in the queue
pcm_bank_67_read_queue_time 0

#Number of cyclesPCM bank 67 write requests wait in the queue
pcm_bank_67_write_queue_time 0

#Total number of cycles of PCM bank 67 read requests
pcm_bank_67_read_total_time 0

#Total number of cycles of PCM bank 67 write requests
pcm_bank_67_write_total_time 0

#Number of PCM bank 67 row buffer hits
pcm_bank_67_row_buffer_hits 0

#Number of PCM bank 67 row buffer misses
pcm_bank_67_row_buffer_misses 0

#Number of PCM bank 67 opens
pcm_bank_67_num_opens 0

#Number of PCM bank 67 accesses
pcm_bank_67_num_accesses 0

#Number of PCM bank 67 closes
pcm_bank_67_num_closes 0

#Number of PCM bank 67 read after read (RAR) hazards
pcm_bank_67_num_read_after_read 0

#Number of PCM bank 67 read after write (RAW) hazards
pcm_bank_67_num_read_after_write 0

#Number of PCM bank 67 write after read (WAR) hazards
pcm_bank_67_num_write_after_read 0

#Number of PCM bank 67 write after write (WAW) hazards
pcm_bank_67_num_write_after_write 0

#Number of cycles PCM bank 67 requests wait for lower priority requests
pcm_bank_67_wait_lower_priority_time 0

#Number of cycles PCM bank 67 requests wait for same priority requests
pcm_bank_67_wait_same_priority_time 0

#Number of cycles PCM bank 67 requests wait for higher priority requests
pcm_bank_67_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 68 spend in the queue
pcm_bank_68_queue_time 0

#Number of cycles PCM bank 68 spends opening rows for requests
pcm_bank_68_open_time 220

#Number of cycles PCM bank 68 spends accessing rows for requests
pcm_bank_68_access_time 0

#Number of cycles PCM bank 68 spends closing rows for requests
pcm_bank_68_close_time 0

#Number of PCM bank 68 read requests
pcm_bank_68_read_requests 1

#Number of PCM bank 68 write requests
pcm_bank_68_write_requests 0

#Number of cyclesPCM bank 68 read requests wait in the queue
pcm_bank_68_read_queue_time 0

#Number of cyclesPCM bank 68 write requests wait in the queue
pcm_bank_68_write_queue_time 0

#Total number of cycles of PCM bank 68 read requests
pcm_bank_68_read_total_time 310

#Total number of cycles of PCM bank 68 write requests
pcm_bank_68_write_total_time 0

#Number of PCM bank 68 row buffer hits
pcm_bank_68_row_buffer_hits 0

#Number of PCM bank 68 row buffer misses
pcm_bank_68_row_buffer_misses 1

#Number of PCM bank 68 opens
pcm_bank_68_num_opens 1

#Number of PCM bank 68 accesses
pcm_bank_68_num_accesses 1

#Number of PCM bank 68 closes
pcm_bank_68_num_closes 0

#Number of PCM bank 68 read after read (RAR) hazards
pcm_bank_68_num_read_after_read 0

#Number of PCM bank 68 read after write (RAW) hazards
pcm_bank_68_num_read_after_write 0

#Number of PCM bank 68 write after read (WAR) hazards
pcm_bank_68_num_write_after_read 0

#Number of PCM bank 68 write after write (WAW) hazards
pcm_bank_68_num_write_after_write 0

#Number of cycles PCM bank 68 requests wait for lower priority requests
pcm_bank_68_wait_lower_priority_time 0

#Number of cycles PCM bank 68 requests wait for same priority requests
pcm_bank_68_wait_same_priority_time 0

#Number of cycles PCM bank 68 requests wait for higher priority requests
pcm_bank_68_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 69 spend in the queue
pcm_bank_69_queue_time 0

#Number of cycles PCM bank 69 spends opening rows for requests
pcm_bank_69_open_time 0

#Number of cycles PCM bank 69 spends accessing rows for requests
pcm_bank_69_access_time 0

#Number of cycles PCM bank 69 spends closing rows for requests
pcm_bank_69_close_time 0

#Number of PCM bank 69 read requests
pcm_bank_69_read_requests 0

#Number of PCM bank 69 write requests
pcm_bank_69_write_requests 0

#Number of cyclesPCM bank 69 read requests wait in the queue
pcm_bank_69_read_queue_time 0

#Number of cyclesPCM bank 69 write requests wait in the queue
pcm_bank_69_write_queue_time 0

#Total number of cycles of PCM bank 69 read requests
pcm_bank_69_read_total_time 0

#Total number of cycles of PCM bank 69 write requests
pcm_bank_69_write_total_time 0

#Number of PCM bank 69 row buffer hits
pcm_bank_69_row_buffer_hits 0

#Number of PCM bank 69 row buffer misses
pcm_bank_69_row_buffer_misses 0

#Number of PCM bank 69 opens
pcm_bank_69_num_opens 0

#Number of PCM bank 69 accesses
pcm_bank_69_num_accesses 0

#Number of PCM bank 69 closes
pcm_bank_69_num_closes 0

#Number of PCM bank 69 read after read (RAR) hazards
pcm_bank_69_num_read_after_read 0

#Number of PCM bank 69 read after write (RAW) hazards
pcm_bank_69_num_read_after_write 0

#Number of PCM bank 69 write after read (WAR) hazards
pcm_bank_69_num_write_after_read 0

#Number of PCM bank 69 write after write (WAW) hazards
pcm_bank_69_num_write_after_write 0

#Number of cycles PCM bank 69 requests wait for lower priority requests
pcm_bank_69_wait_lower_priority_time 0

#Number of cycles PCM bank 69 requests wait for same priority requests
pcm_bank_69_wait_same_priority_time 0

#Number of cycles PCM bank 69 requests wait for higher priority requests
pcm_bank_69_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 70 spend in the queue
pcm_bank_70_queue_time 0

#Number of cycles PCM bank 70 spends opening rows for requests
pcm_bank_70_open_time 0

#Number of cycles PCM bank 70 spends accessing rows for requests
pcm_bank_70_access_time 0

#Number of cycles PCM bank 70 spends closing rows for requests
pcm_bank_70_close_time 0

#Number of PCM bank 70 read requests
pcm_bank_70_read_requests 0

#Number of PCM bank 70 write requests
pcm_bank_70_write_requests 0

#Number of cyclesPCM bank 70 read requests wait in the queue
pcm_bank_70_read_queue_time 0

#Number of cyclesPCM bank 70 write requests wait in the queue
pcm_bank_70_write_queue_time 0

#Total number of cycles of PCM bank 70 read requests
pcm_bank_70_read_total_time 0

#Total number of cycles of PCM bank 70 write requests
pcm_bank_70_write_total_time 0

#Number of PCM bank 70 row buffer hits
pcm_bank_70_row_buffer_hits 0

#Number of PCM bank 70 row buffer misses
pcm_bank_70_row_buffer_misses 0

#Number of PCM bank 70 opens
pcm_bank_70_num_opens 0

#Number of PCM bank 70 accesses
pcm_bank_70_num_accesses 0

#Number of PCM bank 70 closes
pcm_bank_70_num_closes 0

#Number of PCM bank 70 read after read (RAR) hazards
pcm_bank_70_num_read_after_read 0

#Number of PCM bank 70 read after write (RAW) hazards
pcm_bank_70_num_read_after_write 0

#Number of PCM bank 70 write after read (WAR) hazards
pcm_bank_70_num_write_after_read 0

#Number of PCM bank 70 write after write (WAW) hazards
pcm_bank_70_num_write_after_write 0

#Number of cycles PCM bank 70 requests wait for lower priority requests
pcm_bank_70_wait_lower_priority_time 0

#Number of cycles PCM bank 70 requests wait for same priority requests
pcm_bank_70_wait_same_priority_time 0

#Number of cycles PCM bank 70 requests wait for higher priority requests
pcm_bank_70_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 71 spend in the queue
pcm_bank_71_queue_time 0

#Number of cycles PCM bank 71 spends opening rows for requests
pcm_bank_71_open_time 0

#Number of cycles PCM bank 71 spends accessing rows for requests
pcm_bank_71_access_time 0

#Number of cycles PCM bank 71 spends closing rows for requests
pcm_bank_71_close_time 0

#Number of PCM bank 71 read requests
pcm_bank_71_read_requests 0

#Number of PCM bank 71 write requests
pcm_bank_71_write_requests 0

#Number of cyclesPCM bank 71 read requests wait in the queue
pcm_bank_71_read_queue_time 0

#Number of cyclesPCM bank 71 write requests wait in the queue
pcm_bank_71_write_queue_time 0

#Total number of cycles of PCM bank 71 read requests
pcm_bank_71_read_total_time 0

#Total number of cycles of PCM bank 71 write requests
pcm_bank_71_write_total_time 0

#Number of PCM bank 71 row buffer hits
pcm_bank_71_row_buffer_hits 0

#Number of PCM bank 71 row buffer misses
pcm_bank_71_row_buffer_misses 0

#Number of PCM bank 71 opens
pcm_bank_71_num_opens 0

#Number of PCM bank 71 accesses
pcm_bank_71_num_accesses 0

#Number of PCM bank 71 closes
pcm_bank_71_num_closes 0

#Number of PCM bank 71 read after read (RAR) hazards
pcm_bank_71_num_read_after_read 0

#Number of PCM bank 71 read after write (RAW) hazards
pcm_bank_71_num_read_after_write 0

#Number of PCM bank 71 write after read (WAR) hazards
pcm_bank_71_num_write_after_read 0

#Number of PCM bank 71 write after write (WAW) hazards
pcm_bank_71_num_write_after_write 0

#Number of cycles PCM bank 71 requests wait for lower priority requests
pcm_bank_71_wait_lower_priority_time 0

#Number of cycles PCM bank 71 requests wait for same priority requests
pcm_bank_71_wait_same_priority_time 0

#Number of cycles PCM bank 71 requests wait for higher priority requests
pcm_bank_71_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 72 spend in the queue
pcm_bank_72_queue_time 0

#Number of cycles PCM bank 72 spends opening rows for requests
pcm_bank_72_open_time 0

#Number of cycles PCM bank 72 spends accessing rows for requests
pcm_bank_72_access_time 0

#Number of cycles PCM bank 72 spends closing rows for requests
pcm_bank_72_close_time 0

#Number of PCM bank 72 read requests
pcm_bank_72_read_requests 0

#Number of PCM bank 72 write requests
pcm_bank_72_write_requests 0

#Number of cyclesPCM bank 72 read requests wait in the queue
pcm_bank_72_read_queue_time 0

#Number of cyclesPCM bank 72 write requests wait in the queue
pcm_bank_72_write_queue_time 0

#Total number of cycles of PCM bank 72 read requests
pcm_bank_72_read_total_time 0

#Total number of cycles of PCM bank 72 write requests
pcm_bank_72_write_total_time 0

#Number of PCM bank 72 row buffer hits
pcm_bank_72_row_buffer_hits 0

#Number of PCM bank 72 row buffer misses
pcm_bank_72_row_buffer_misses 0

#Number of PCM bank 72 opens
pcm_bank_72_num_opens 0

#Number of PCM bank 72 accesses
pcm_bank_72_num_accesses 0

#Number of PCM bank 72 closes
pcm_bank_72_num_closes 0

#Number of PCM bank 72 read after read (RAR) hazards
pcm_bank_72_num_read_after_read 0

#Number of PCM bank 72 read after write (RAW) hazards
pcm_bank_72_num_read_after_write 0

#Number of PCM bank 72 write after read (WAR) hazards
pcm_bank_72_num_write_after_read 0

#Number of PCM bank 72 write after write (WAW) hazards
pcm_bank_72_num_write_after_write 0

#Number of cycles PCM bank 72 requests wait for lower priority requests
pcm_bank_72_wait_lower_priority_time 0

#Number of cycles PCM bank 72 requests wait for same priority requests
pcm_bank_72_wait_same_priority_time 0

#Number of cycles PCM bank 72 requests wait for higher priority requests
pcm_bank_72_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 73 spend in the queue
pcm_bank_73_queue_time 0

#Number of cycles PCM bank 73 spends opening rows for requests
pcm_bank_73_open_time 0

#Number of cycles PCM bank 73 spends accessing rows for requests
pcm_bank_73_access_time 0

#Number of cycles PCM bank 73 spends closing rows for requests
pcm_bank_73_close_time 0

#Number of PCM bank 73 read requests
pcm_bank_73_read_requests 0

#Number of PCM bank 73 write requests
pcm_bank_73_write_requests 0

#Number of cyclesPCM bank 73 read requests wait in the queue
pcm_bank_73_read_queue_time 0

#Number of cyclesPCM bank 73 write requests wait in the queue
pcm_bank_73_write_queue_time 0

#Total number of cycles of PCM bank 73 read requests
pcm_bank_73_read_total_time 0

#Total number of cycles of PCM bank 73 write requests
pcm_bank_73_write_total_time 0

#Number of PCM bank 73 row buffer hits
pcm_bank_73_row_buffer_hits 0

#Number of PCM bank 73 row buffer misses
pcm_bank_73_row_buffer_misses 0

#Number of PCM bank 73 opens
pcm_bank_73_num_opens 0

#Number of PCM bank 73 accesses
pcm_bank_73_num_accesses 0

#Number of PCM bank 73 closes
pcm_bank_73_num_closes 0

#Number of PCM bank 73 read after read (RAR) hazards
pcm_bank_73_num_read_after_read 0

#Number of PCM bank 73 read after write (RAW) hazards
pcm_bank_73_num_read_after_write 0

#Number of PCM bank 73 write after read (WAR) hazards
pcm_bank_73_num_write_after_read 0

#Number of PCM bank 73 write after write (WAW) hazards
pcm_bank_73_num_write_after_write 0

#Number of cycles PCM bank 73 requests wait for lower priority requests
pcm_bank_73_wait_lower_priority_time 0

#Number of cycles PCM bank 73 requests wait for same priority requests
pcm_bank_73_wait_same_priority_time 0

#Number of cycles PCM bank 73 requests wait for higher priority requests
pcm_bank_73_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 74 spend in the queue
pcm_bank_74_queue_time 0

#Number of cycles PCM bank 74 spends opening rows for requests
pcm_bank_74_open_time 0

#Number of cycles PCM bank 74 spends accessing rows for requests
pcm_bank_74_access_time 0

#Number of cycles PCM bank 74 spends closing rows for requests
pcm_bank_74_close_time 0

#Number of PCM bank 74 read requests
pcm_bank_74_read_requests 0

#Number of PCM bank 74 write requests
pcm_bank_74_write_requests 0

#Number of cyclesPCM bank 74 read requests wait in the queue
pcm_bank_74_read_queue_time 0

#Number of cyclesPCM bank 74 write requests wait in the queue
pcm_bank_74_write_queue_time 0

#Total number of cycles of PCM bank 74 read requests
pcm_bank_74_read_total_time 0

#Total number of cycles of PCM bank 74 write requests
pcm_bank_74_write_total_time 0

#Number of PCM bank 74 row buffer hits
pcm_bank_74_row_buffer_hits 0

#Number of PCM bank 74 row buffer misses
pcm_bank_74_row_buffer_misses 0

#Number of PCM bank 74 opens
pcm_bank_74_num_opens 0

#Number of PCM bank 74 accesses
pcm_bank_74_num_accesses 0

#Number of PCM bank 74 closes
pcm_bank_74_num_closes 0

#Number of PCM bank 74 read after read (RAR) hazards
pcm_bank_74_num_read_after_read 0

#Number of PCM bank 74 read after write (RAW) hazards
pcm_bank_74_num_read_after_write 0

#Number of PCM bank 74 write after read (WAR) hazards
pcm_bank_74_num_write_after_read 0

#Number of PCM bank 74 write after write (WAW) hazards
pcm_bank_74_num_write_after_write 0

#Number of cycles PCM bank 74 requests wait for lower priority requests
pcm_bank_74_wait_lower_priority_time 0

#Number of cycles PCM bank 74 requests wait for same priority requests
pcm_bank_74_wait_same_priority_time 0

#Number of cycles PCM bank 74 requests wait for higher priority requests
pcm_bank_74_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 75 spend in the queue
pcm_bank_75_queue_time 0

#Number of cycles PCM bank 75 spends opening rows for requests
pcm_bank_75_open_time 0

#Number of cycles PCM bank 75 spends accessing rows for requests
pcm_bank_75_access_time 0

#Number of cycles PCM bank 75 spends closing rows for requests
pcm_bank_75_close_time 0

#Number of PCM bank 75 read requests
pcm_bank_75_read_requests 0

#Number of PCM bank 75 write requests
pcm_bank_75_write_requests 0

#Number of cyclesPCM bank 75 read requests wait in the queue
pcm_bank_75_read_queue_time 0

#Number of cyclesPCM bank 75 write requests wait in the queue
pcm_bank_75_write_queue_time 0

#Total number of cycles of PCM bank 75 read requests
pcm_bank_75_read_total_time 0

#Total number of cycles of PCM bank 75 write requests
pcm_bank_75_write_total_time 0

#Number of PCM bank 75 row buffer hits
pcm_bank_75_row_buffer_hits 0

#Number of PCM bank 75 row buffer misses
pcm_bank_75_row_buffer_misses 0

#Number of PCM bank 75 opens
pcm_bank_75_num_opens 0

#Number of PCM bank 75 accesses
pcm_bank_75_num_accesses 0

#Number of PCM bank 75 closes
pcm_bank_75_num_closes 0

#Number of PCM bank 75 read after read (RAR) hazards
pcm_bank_75_num_read_after_read 0

#Number of PCM bank 75 read after write (RAW) hazards
pcm_bank_75_num_read_after_write 0

#Number of PCM bank 75 write after read (WAR) hazards
pcm_bank_75_num_write_after_read 0

#Number of PCM bank 75 write after write (WAW) hazards
pcm_bank_75_num_write_after_write 0

#Number of cycles PCM bank 75 requests wait for lower priority requests
pcm_bank_75_wait_lower_priority_time 0

#Number of cycles PCM bank 75 requests wait for same priority requests
pcm_bank_75_wait_same_priority_time 0

#Number of cycles PCM bank 75 requests wait for higher priority requests
pcm_bank_75_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 76 spend in the queue
pcm_bank_76_queue_time 0

#Number of cycles PCM bank 76 spends opening rows for requests
pcm_bank_76_open_time 0

#Number of cycles PCM bank 76 spends accessing rows for requests
pcm_bank_76_access_time 0

#Number of cycles PCM bank 76 spends closing rows for requests
pcm_bank_76_close_time 0

#Number of PCM bank 76 read requests
pcm_bank_76_read_requests 0

#Number of PCM bank 76 write requests
pcm_bank_76_write_requests 0

#Number of cyclesPCM bank 76 read requests wait in the queue
pcm_bank_76_read_queue_time 0

#Number of cyclesPCM bank 76 write requests wait in the queue
pcm_bank_76_write_queue_time 0

#Total number of cycles of PCM bank 76 read requests
pcm_bank_76_read_total_time 0

#Total number of cycles of PCM bank 76 write requests
pcm_bank_76_write_total_time 0

#Number of PCM bank 76 row buffer hits
pcm_bank_76_row_buffer_hits 0

#Number of PCM bank 76 row buffer misses
pcm_bank_76_row_buffer_misses 0

#Number of PCM bank 76 opens
pcm_bank_76_num_opens 0

#Number of PCM bank 76 accesses
pcm_bank_76_num_accesses 0

#Number of PCM bank 76 closes
pcm_bank_76_num_closes 0

#Number of PCM bank 76 read after read (RAR) hazards
pcm_bank_76_num_read_after_read 0

#Number of PCM bank 76 read after write (RAW) hazards
pcm_bank_76_num_read_after_write 0

#Number of PCM bank 76 write after read (WAR) hazards
pcm_bank_76_num_write_after_read 0

#Number of PCM bank 76 write after write (WAW) hazards
pcm_bank_76_num_write_after_write 0

#Number of cycles PCM bank 76 requests wait for lower priority requests
pcm_bank_76_wait_lower_priority_time 0

#Number of cycles PCM bank 76 requests wait for same priority requests
pcm_bank_76_wait_same_priority_time 0

#Number of cycles PCM bank 76 requests wait for higher priority requests
pcm_bank_76_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 77 spend in the queue
pcm_bank_77_queue_time 0

#Number of cycles PCM bank 77 spends opening rows for requests
pcm_bank_77_open_time 0

#Number of cycles PCM bank 77 spends accessing rows for requests
pcm_bank_77_access_time 0

#Number of cycles PCM bank 77 spends closing rows for requests
pcm_bank_77_close_time 0

#Number of PCM bank 77 read requests
pcm_bank_77_read_requests 0

#Number of PCM bank 77 write requests
pcm_bank_77_write_requests 0

#Number of cyclesPCM bank 77 read requests wait in the queue
pcm_bank_77_read_queue_time 0

#Number of cyclesPCM bank 77 write requests wait in the queue
pcm_bank_77_write_queue_time 0

#Total number of cycles of PCM bank 77 read requests
pcm_bank_77_read_total_time 0

#Total number of cycles of PCM bank 77 write requests
pcm_bank_77_write_total_time 0

#Number of PCM bank 77 row buffer hits
pcm_bank_77_row_buffer_hits 0

#Number of PCM bank 77 row buffer misses
pcm_bank_77_row_buffer_misses 0

#Number of PCM bank 77 opens
pcm_bank_77_num_opens 0

#Number of PCM bank 77 accesses
pcm_bank_77_num_accesses 0

#Number of PCM bank 77 closes
pcm_bank_77_num_closes 0

#Number of PCM bank 77 read after read (RAR) hazards
pcm_bank_77_num_read_after_read 0

#Number of PCM bank 77 read after write (RAW) hazards
pcm_bank_77_num_read_after_write 0

#Number of PCM bank 77 write after read (WAR) hazards
pcm_bank_77_num_write_after_read 0

#Number of PCM bank 77 write after write (WAW) hazards
pcm_bank_77_num_write_after_write 0

#Number of cycles PCM bank 77 requests wait for lower priority requests
pcm_bank_77_wait_lower_priority_time 0

#Number of cycles PCM bank 77 requests wait for same priority requests
pcm_bank_77_wait_same_priority_time 0

#Number of cycles PCM bank 77 requests wait for higher priority requests
pcm_bank_77_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 78 spend in the queue
pcm_bank_78_queue_time 0

#Number of cycles PCM bank 78 spends opening rows for requests
pcm_bank_78_open_time 0

#Number of cycles PCM bank 78 spends accessing rows for requests
pcm_bank_78_access_time 0

#Number of cycles PCM bank 78 spends closing rows for requests
pcm_bank_78_close_time 0

#Number of PCM bank 78 read requests
pcm_bank_78_read_requests 0

#Number of PCM bank 78 write requests
pcm_bank_78_write_requests 0

#Number of cyclesPCM bank 78 read requests wait in the queue
pcm_bank_78_read_queue_time 0

#Number of cyclesPCM bank 78 write requests wait in the queue
pcm_bank_78_write_queue_time 0

#Total number of cycles of PCM bank 78 read requests
pcm_bank_78_read_total_time 0

#Total number of cycles of PCM bank 78 write requests
pcm_bank_78_write_total_time 0

#Number of PCM bank 78 row buffer hits
pcm_bank_78_row_buffer_hits 0

#Number of PCM bank 78 row buffer misses
pcm_bank_78_row_buffer_misses 0

#Number of PCM bank 78 opens
pcm_bank_78_num_opens 0

#Number of PCM bank 78 accesses
pcm_bank_78_num_accesses 0

#Number of PCM bank 78 closes
pcm_bank_78_num_closes 0

#Number of PCM bank 78 read after read (RAR) hazards
pcm_bank_78_num_read_after_read 0

#Number of PCM bank 78 read after write (RAW) hazards
pcm_bank_78_num_read_after_write 0

#Number of PCM bank 78 write after read (WAR) hazards
pcm_bank_78_num_write_after_read 0

#Number of PCM bank 78 write after write (WAW) hazards
pcm_bank_78_num_write_after_write 0

#Number of cycles PCM bank 78 requests wait for lower priority requests
pcm_bank_78_wait_lower_priority_time 0

#Number of cycles PCM bank 78 requests wait for same priority requests
pcm_bank_78_wait_same_priority_time 0

#Number of cycles PCM bank 78 requests wait for higher priority requests
pcm_bank_78_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 79 spend in the queue
pcm_bank_79_queue_time 0

#Number of cycles PCM bank 79 spends opening rows for requests
pcm_bank_79_open_time 0

#Number of cycles PCM bank 79 spends accessing rows for requests
pcm_bank_79_access_time 0

#Number of cycles PCM bank 79 spends closing rows for requests
pcm_bank_79_close_time 0

#Number of PCM bank 79 read requests
pcm_bank_79_read_requests 0

#Number of PCM bank 79 write requests
pcm_bank_79_write_requests 0

#Number of cyclesPCM bank 79 read requests wait in the queue
pcm_bank_79_read_queue_time 0

#Number of cyclesPCM bank 79 write requests wait in the queue
pcm_bank_79_write_queue_time 0

#Total number of cycles of PCM bank 79 read requests
pcm_bank_79_read_total_time 0

#Total number of cycles of PCM bank 79 write requests
pcm_bank_79_write_total_time 0

#Number of PCM bank 79 row buffer hits
pcm_bank_79_row_buffer_hits 0

#Number of PCM bank 79 row buffer misses
pcm_bank_79_row_buffer_misses 0

#Number of PCM bank 79 opens
pcm_bank_79_num_opens 0

#Number of PCM bank 79 accesses
pcm_bank_79_num_accesses 0

#Number of PCM bank 79 closes
pcm_bank_79_num_closes 0

#Number of PCM bank 79 read after read (RAR) hazards
pcm_bank_79_num_read_after_read 0

#Number of PCM bank 79 read after write (RAW) hazards
pcm_bank_79_num_read_after_write 0

#Number of PCM bank 79 write after read (WAR) hazards
pcm_bank_79_num_write_after_read 0

#Number of PCM bank 79 write after write (WAW) hazards
pcm_bank_79_num_write_after_write 0

#Number of cycles PCM bank 79 requests wait for lower priority requests
pcm_bank_79_wait_lower_priority_time 0

#Number of cycles PCM bank 79 requests wait for same priority requests
pcm_bank_79_wait_same_priority_time 0

#Number of cycles PCM bank 79 requests wait for higher priority requests
pcm_bank_79_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 80 spend in the queue
pcm_bank_80_queue_time 0

#Number of cycles PCM bank 80 spends opening rows for requests
pcm_bank_80_open_time 0

#Number of cycles PCM bank 80 spends accessing rows for requests
pcm_bank_80_access_time 0

#Number of cycles PCM bank 80 spends closing rows for requests
pcm_bank_80_close_time 0

#Number of PCM bank 80 read requests
pcm_bank_80_read_requests 0

#Number of PCM bank 80 write requests
pcm_bank_80_write_requests 0

#Number of cyclesPCM bank 80 read requests wait in the queue
pcm_bank_80_read_queue_time 0

#Number of cyclesPCM bank 80 write requests wait in the queue
pcm_bank_80_write_queue_time 0

#Total number of cycles of PCM bank 80 read requests
pcm_bank_80_read_total_time 0

#Total number of cycles of PCM bank 80 write requests
pcm_bank_80_write_total_time 0

#Number of PCM bank 80 row buffer hits
pcm_bank_80_row_buffer_hits 0

#Number of PCM bank 80 row buffer misses
pcm_bank_80_row_buffer_misses 0

#Number of PCM bank 80 opens
pcm_bank_80_num_opens 0

#Number of PCM bank 80 accesses
pcm_bank_80_num_accesses 0

#Number of PCM bank 80 closes
pcm_bank_80_num_closes 0

#Number of PCM bank 80 read after read (RAR) hazards
pcm_bank_80_num_read_after_read 0

#Number of PCM bank 80 read after write (RAW) hazards
pcm_bank_80_num_read_after_write 0

#Number of PCM bank 80 write after read (WAR) hazards
pcm_bank_80_num_write_after_read 0

#Number of PCM bank 80 write after write (WAW) hazards
pcm_bank_80_num_write_after_write 0

#Number of cycles PCM bank 80 requests wait for lower priority requests
pcm_bank_80_wait_lower_priority_time 0

#Number of cycles PCM bank 80 requests wait for same priority requests
pcm_bank_80_wait_same_priority_time 0

#Number of cycles PCM bank 80 requests wait for higher priority requests
pcm_bank_80_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 81 spend in the queue
pcm_bank_81_queue_time 0

#Number of cycles PCM bank 81 spends opening rows for requests
pcm_bank_81_open_time 0

#Number of cycles PCM bank 81 spends accessing rows for requests
pcm_bank_81_access_time 0

#Number of cycles PCM bank 81 spends closing rows for requests
pcm_bank_81_close_time 0

#Number of PCM bank 81 read requests
pcm_bank_81_read_requests 0

#Number of PCM bank 81 write requests
pcm_bank_81_write_requests 0

#Number of cyclesPCM bank 81 read requests wait in the queue
pcm_bank_81_read_queue_time 0

#Number of cyclesPCM bank 81 write requests wait in the queue
pcm_bank_81_write_queue_time 0

#Total number of cycles of PCM bank 81 read requests
pcm_bank_81_read_total_time 0

#Total number of cycles of PCM bank 81 write requests
pcm_bank_81_write_total_time 0

#Number of PCM bank 81 row buffer hits
pcm_bank_81_row_buffer_hits 0

#Number of PCM bank 81 row buffer misses
pcm_bank_81_row_buffer_misses 0

#Number of PCM bank 81 opens
pcm_bank_81_num_opens 0

#Number of PCM bank 81 accesses
pcm_bank_81_num_accesses 0

#Number of PCM bank 81 closes
pcm_bank_81_num_closes 0

#Number of PCM bank 81 read after read (RAR) hazards
pcm_bank_81_num_read_after_read 0

#Number of PCM bank 81 read after write (RAW) hazards
pcm_bank_81_num_read_after_write 0

#Number of PCM bank 81 write after read (WAR) hazards
pcm_bank_81_num_write_after_read 0

#Number of PCM bank 81 write after write (WAW) hazards
pcm_bank_81_num_write_after_write 0

#Number of cycles PCM bank 81 requests wait for lower priority requests
pcm_bank_81_wait_lower_priority_time 0

#Number of cycles PCM bank 81 requests wait for same priority requests
pcm_bank_81_wait_same_priority_time 0

#Number of cycles PCM bank 81 requests wait for higher priority requests
pcm_bank_81_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 82 spend in the queue
pcm_bank_82_queue_time 0

#Number of cycles PCM bank 82 spends opening rows for requests
pcm_bank_82_open_time 0

#Number of cycles PCM bank 82 spends accessing rows for requests
pcm_bank_82_access_time 0

#Number of cycles PCM bank 82 spends closing rows for requests
pcm_bank_82_close_time 0

#Number of PCM bank 82 read requests
pcm_bank_82_read_requests 0

#Number of PCM bank 82 write requests
pcm_bank_82_write_requests 0

#Number of cyclesPCM bank 82 read requests wait in the queue
pcm_bank_82_read_queue_time 0

#Number of cyclesPCM bank 82 write requests wait in the queue
pcm_bank_82_write_queue_time 0

#Total number of cycles of PCM bank 82 read requests
pcm_bank_82_read_total_time 0

#Total number of cycles of PCM bank 82 write requests
pcm_bank_82_write_total_time 0

#Number of PCM bank 82 row buffer hits
pcm_bank_82_row_buffer_hits 0

#Number of PCM bank 82 row buffer misses
pcm_bank_82_row_buffer_misses 0

#Number of PCM bank 82 opens
pcm_bank_82_num_opens 0

#Number of PCM bank 82 accesses
pcm_bank_82_num_accesses 0

#Number of PCM bank 82 closes
pcm_bank_82_num_closes 0

#Number of PCM bank 82 read after read (RAR) hazards
pcm_bank_82_num_read_after_read 0

#Number of PCM bank 82 read after write (RAW) hazards
pcm_bank_82_num_read_after_write 0

#Number of PCM bank 82 write after read (WAR) hazards
pcm_bank_82_num_write_after_read 0

#Number of PCM bank 82 write after write (WAW) hazards
pcm_bank_82_num_write_after_write 0

#Number of cycles PCM bank 82 requests wait for lower priority requests
pcm_bank_82_wait_lower_priority_time 0

#Number of cycles PCM bank 82 requests wait for same priority requests
pcm_bank_82_wait_same_priority_time 0

#Number of cycles PCM bank 82 requests wait for higher priority requests
pcm_bank_82_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 83 spend in the queue
pcm_bank_83_queue_time 0

#Number of cycles PCM bank 83 spends opening rows for requests
pcm_bank_83_open_time 0

#Number of cycles PCM bank 83 spends accessing rows for requests
pcm_bank_83_access_time 0

#Number of cycles PCM bank 83 spends closing rows for requests
pcm_bank_83_close_time 0

#Number of PCM bank 83 read requests
pcm_bank_83_read_requests 0

#Number of PCM bank 83 write requests
pcm_bank_83_write_requests 0

#Number of cyclesPCM bank 83 read requests wait in the queue
pcm_bank_83_read_queue_time 0

#Number of cyclesPCM bank 83 write requests wait in the queue
pcm_bank_83_write_queue_time 0

#Total number of cycles of PCM bank 83 read requests
pcm_bank_83_read_total_time 0

#Total number of cycles of PCM bank 83 write requests
pcm_bank_83_write_total_time 0

#Number of PCM bank 83 row buffer hits
pcm_bank_83_row_buffer_hits 0

#Number of PCM bank 83 row buffer misses
pcm_bank_83_row_buffer_misses 0

#Number of PCM bank 83 opens
pcm_bank_83_num_opens 0

#Number of PCM bank 83 accesses
pcm_bank_83_num_accesses 0

#Number of PCM bank 83 closes
pcm_bank_83_num_closes 0

#Number of PCM bank 83 read after read (RAR) hazards
pcm_bank_83_num_read_after_read 0

#Number of PCM bank 83 read after write (RAW) hazards
pcm_bank_83_num_read_after_write 0

#Number of PCM bank 83 write after read (WAR) hazards
pcm_bank_83_num_write_after_read 0

#Number of PCM bank 83 write after write (WAW) hazards
pcm_bank_83_num_write_after_write 0

#Number of cycles PCM bank 83 requests wait for lower priority requests
pcm_bank_83_wait_lower_priority_time 0

#Number of cycles PCM bank 83 requests wait for same priority requests
pcm_bank_83_wait_same_priority_time 0

#Number of cycles PCM bank 83 requests wait for higher priority requests
pcm_bank_83_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 84 spend in the queue
pcm_bank_84_queue_time 0

#Number of cycles PCM bank 84 spends opening rows for requests
pcm_bank_84_open_time 0

#Number of cycles PCM bank 84 spends accessing rows for requests
pcm_bank_84_access_time 0

#Number of cycles PCM bank 84 spends closing rows for requests
pcm_bank_84_close_time 0

#Number of PCM bank 84 read requests
pcm_bank_84_read_requests 0

#Number of PCM bank 84 write requests
pcm_bank_84_write_requests 0

#Number of cyclesPCM bank 84 read requests wait in the queue
pcm_bank_84_read_queue_time 0

#Number of cyclesPCM bank 84 write requests wait in the queue
pcm_bank_84_write_queue_time 0

#Total number of cycles of PCM bank 84 read requests
pcm_bank_84_read_total_time 0

#Total number of cycles of PCM bank 84 write requests
pcm_bank_84_write_total_time 0

#Number of PCM bank 84 row buffer hits
pcm_bank_84_row_buffer_hits 0

#Number of PCM bank 84 row buffer misses
pcm_bank_84_row_buffer_misses 0

#Number of PCM bank 84 opens
pcm_bank_84_num_opens 0

#Number of PCM bank 84 accesses
pcm_bank_84_num_accesses 0

#Number of PCM bank 84 closes
pcm_bank_84_num_closes 0

#Number of PCM bank 84 read after read (RAR) hazards
pcm_bank_84_num_read_after_read 0

#Number of PCM bank 84 read after write (RAW) hazards
pcm_bank_84_num_read_after_write 0

#Number of PCM bank 84 write after read (WAR) hazards
pcm_bank_84_num_write_after_read 0

#Number of PCM bank 84 write after write (WAW) hazards
pcm_bank_84_num_write_after_write 0

#Number of cycles PCM bank 84 requests wait for lower priority requests
pcm_bank_84_wait_lower_priority_time 0

#Number of cycles PCM bank 84 requests wait for same priority requests
pcm_bank_84_wait_same_priority_time 0

#Number of cycles PCM bank 84 requests wait for higher priority requests
pcm_bank_84_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 85 spend in the queue
pcm_bank_85_queue_time 0

#Number of cycles PCM bank 85 spends opening rows for requests
pcm_bank_85_open_time 0

#Number of cycles PCM bank 85 spends accessing rows for requests
pcm_bank_85_access_time 0

#Number of cycles PCM bank 85 spends closing rows for requests
pcm_bank_85_close_time 0

#Number of PCM bank 85 read requests
pcm_bank_85_read_requests 0

#Number of PCM bank 85 write requests
pcm_bank_85_write_requests 0

#Number of cyclesPCM bank 85 read requests wait in the queue
pcm_bank_85_read_queue_time 0

#Number of cyclesPCM bank 85 write requests wait in the queue
pcm_bank_85_write_queue_time 0

#Total number of cycles of PCM bank 85 read requests
pcm_bank_85_read_total_time 0

#Total number of cycles of PCM bank 85 write requests
pcm_bank_85_write_total_time 0

#Number of PCM bank 85 row buffer hits
pcm_bank_85_row_buffer_hits 0

#Number of PCM bank 85 row buffer misses
pcm_bank_85_row_buffer_misses 0

#Number of PCM bank 85 opens
pcm_bank_85_num_opens 0

#Number of PCM bank 85 accesses
pcm_bank_85_num_accesses 0

#Number of PCM bank 85 closes
pcm_bank_85_num_closes 0

#Number of PCM bank 85 read after read (RAR) hazards
pcm_bank_85_num_read_after_read 0

#Number of PCM bank 85 read after write (RAW) hazards
pcm_bank_85_num_read_after_write 0

#Number of PCM bank 85 write after read (WAR) hazards
pcm_bank_85_num_write_after_read 0

#Number of PCM bank 85 write after write (WAW) hazards
pcm_bank_85_num_write_after_write 0

#Number of cycles PCM bank 85 requests wait for lower priority requests
pcm_bank_85_wait_lower_priority_time 0

#Number of cycles PCM bank 85 requests wait for same priority requests
pcm_bank_85_wait_same_priority_time 0

#Number of cycles PCM bank 85 requests wait for higher priority requests
pcm_bank_85_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 86 spend in the queue
pcm_bank_86_queue_time 0

#Number of cycles PCM bank 86 spends opening rows for requests
pcm_bank_86_open_time 0

#Number of cycles PCM bank 86 spends accessing rows for requests
pcm_bank_86_access_time 0

#Number of cycles PCM bank 86 spends closing rows for requests
pcm_bank_86_close_time 0

#Number of PCM bank 86 read requests
pcm_bank_86_read_requests 0

#Number of PCM bank 86 write requests
pcm_bank_86_write_requests 0

#Number of cyclesPCM bank 86 read requests wait in the queue
pcm_bank_86_read_queue_time 0

#Number of cyclesPCM bank 86 write requests wait in the queue
pcm_bank_86_write_queue_time 0

#Total number of cycles of PCM bank 86 read requests
pcm_bank_86_read_total_time 0

#Total number of cycles of PCM bank 86 write requests
pcm_bank_86_write_total_time 0

#Number of PCM bank 86 row buffer hits
pcm_bank_86_row_buffer_hits 0

#Number of PCM bank 86 row buffer misses
pcm_bank_86_row_buffer_misses 0

#Number of PCM bank 86 opens
pcm_bank_86_num_opens 0

#Number of PCM bank 86 accesses
pcm_bank_86_num_accesses 0

#Number of PCM bank 86 closes
pcm_bank_86_num_closes 0

#Number of PCM bank 86 read after read (RAR) hazards
pcm_bank_86_num_read_after_read 0

#Number of PCM bank 86 read after write (RAW) hazards
pcm_bank_86_num_read_after_write 0

#Number of PCM bank 86 write after read (WAR) hazards
pcm_bank_86_num_write_after_read 0

#Number of PCM bank 86 write after write (WAW) hazards
pcm_bank_86_num_write_after_write 0

#Number of cycles PCM bank 86 requests wait for lower priority requests
pcm_bank_86_wait_lower_priority_time 0

#Number of cycles PCM bank 86 requests wait for same priority requests
pcm_bank_86_wait_same_priority_time 0

#Number of cycles PCM bank 86 requests wait for higher priority requests
pcm_bank_86_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 87 spend in the queue
pcm_bank_87_queue_time 0

#Number of cycles PCM bank 87 spends opening rows for requests
pcm_bank_87_open_time 0

#Number of cycles PCM bank 87 spends accessing rows for requests
pcm_bank_87_access_time 0

#Number of cycles PCM bank 87 spends closing rows for requests
pcm_bank_87_close_time 0

#Number of PCM bank 87 read requests
pcm_bank_87_read_requests 0

#Number of PCM bank 87 write requests
pcm_bank_87_write_requests 0

#Number of cyclesPCM bank 87 read requests wait in the queue
pcm_bank_87_read_queue_time 0

#Number of cyclesPCM bank 87 write requests wait in the queue
pcm_bank_87_write_queue_time 0

#Total number of cycles of PCM bank 87 read requests
pcm_bank_87_read_total_time 0

#Total number of cycles of PCM bank 87 write requests
pcm_bank_87_write_total_time 0

#Number of PCM bank 87 row buffer hits
pcm_bank_87_row_buffer_hits 0

#Number of PCM bank 87 row buffer misses
pcm_bank_87_row_buffer_misses 0

#Number of PCM bank 87 opens
pcm_bank_87_num_opens 0

#Number of PCM bank 87 accesses
pcm_bank_87_num_accesses 0

#Number of PCM bank 87 closes
pcm_bank_87_num_closes 0

#Number of PCM bank 87 read after read (RAR) hazards
pcm_bank_87_num_read_after_read 0

#Number of PCM bank 87 read after write (RAW) hazards
pcm_bank_87_num_read_after_write 0

#Number of PCM bank 87 write after read (WAR) hazards
pcm_bank_87_num_write_after_read 0

#Number of PCM bank 87 write after write (WAW) hazards
pcm_bank_87_num_write_after_write 0

#Number of cycles PCM bank 87 requests wait for lower priority requests
pcm_bank_87_wait_lower_priority_time 0

#Number of cycles PCM bank 87 requests wait for same priority requests
pcm_bank_87_wait_same_priority_time 0

#Number of cycles PCM bank 87 requests wait for higher priority requests
pcm_bank_87_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 88 spend in the queue
pcm_bank_88_queue_time 0

#Number of cycles PCM bank 88 spends opening rows for requests
pcm_bank_88_open_time 0

#Number of cycles PCM bank 88 spends accessing rows for requests
pcm_bank_88_access_time 0

#Number of cycles PCM bank 88 spends closing rows for requests
pcm_bank_88_close_time 0

#Number of PCM bank 88 read requests
pcm_bank_88_read_requests 0

#Number of PCM bank 88 write requests
pcm_bank_88_write_requests 0

#Number of cyclesPCM bank 88 read requests wait in the queue
pcm_bank_88_read_queue_time 0

#Number of cyclesPCM bank 88 write requests wait in the queue
pcm_bank_88_write_queue_time 0

#Total number of cycles of PCM bank 88 read requests
pcm_bank_88_read_total_time 0

#Total number of cycles of PCM bank 88 write requests
pcm_bank_88_write_total_time 0

#Number of PCM bank 88 row buffer hits
pcm_bank_88_row_buffer_hits 0

#Number of PCM bank 88 row buffer misses
pcm_bank_88_row_buffer_misses 0

#Number of PCM bank 88 opens
pcm_bank_88_num_opens 0

#Number of PCM bank 88 accesses
pcm_bank_88_num_accesses 0

#Number of PCM bank 88 closes
pcm_bank_88_num_closes 0

#Number of PCM bank 88 read after read (RAR) hazards
pcm_bank_88_num_read_after_read 0

#Number of PCM bank 88 read after write (RAW) hazards
pcm_bank_88_num_read_after_write 0

#Number of PCM bank 88 write after read (WAR) hazards
pcm_bank_88_num_write_after_read 0

#Number of PCM bank 88 write after write (WAW) hazards
pcm_bank_88_num_write_after_write 0

#Number of cycles PCM bank 88 requests wait for lower priority requests
pcm_bank_88_wait_lower_priority_time 0

#Number of cycles PCM bank 88 requests wait for same priority requests
pcm_bank_88_wait_same_priority_time 0

#Number of cycles PCM bank 88 requests wait for higher priority requests
pcm_bank_88_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 89 spend in the queue
pcm_bank_89_queue_time 0

#Number of cycles PCM bank 89 spends opening rows for requests
pcm_bank_89_open_time 0

#Number of cycles PCM bank 89 spends accessing rows for requests
pcm_bank_89_access_time 0

#Number of cycles PCM bank 89 spends closing rows for requests
pcm_bank_89_close_time 0

#Number of PCM bank 89 read requests
pcm_bank_89_read_requests 0

#Number of PCM bank 89 write requests
pcm_bank_89_write_requests 0

#Number of cyclesPCM bank 89 read requests wait in the queue
pcm_bank_89_read_queue_time 0

#Number of cyclesPCM bank 89 write requests wait in the queue
pcm_bank_89_write_queue_time 0

#Total number of cycles of PCM bank 89 read requests
pcm_bank_89_read_total_time 0

#Total number of cycles of PCM bank 89 write requests
pcm_bank_89_write_total_time 0

#Number of PCM bank 89 row buffer hits
pcm_bank_89_row_buffer_hits 0

#Number of PCM bank 89 row buffer misses
pcm_bank_89_row_buffer_misses 0

#Number of PCM bank 89 opens
pcm_bank_89_num_opens 0

#Number of PCM bank 89 accesses
pcm_bank_89_num_accesses 0

#Number of PCM bank 89 closes
pcm_bank_89_num_closes 0

#Number of PCM bank 89 read after read (RAR) hazards
pcm_bank_89_num_read_after_read 0

#Number of PCM bank 89 read after write (RAW) hazards
pcm_bank_89_num_read_after_write 0

#Number of PCM bank 89 write after read (WAR) hazards
pcm_bank_89_num_write_after_read 0

#Number of PCM bank 89 write after write (WAW) hazards
pcm_bank_89_num_write_after_write 0

#Number of cycles PCM bank 89 requests wait for lower priority requests
pcm_bank_89_wait_lower_priority_time 0

#Number of cycles PCM bank 89 requests wait for same priority requests
pcm_bank_89_wait_same_priority_time 0

#Number of cycles PCM bank 89 requests wait for higher priority requests
pcm_bank_89_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 90 spend in the queue
pcm_bank_90_queue_time 0

#Number of cycles PCM bank 90 spends opening rows for requests
pcm_bank_90_open_time 0

#Number of cycles PCM bank 90 spends accessing rows for requests
pcm_bank_90_access_time 0

#Number of cycles PCM bank 90 spends closing rows for requests
pcm_bank_90_close_time 0

#Number of PCM bank 90 read requests
pcm_bank_90_read_requests 0

#Number of PCM bank 90 write requests
pcm_bank_90_write_requests 0

#Number of cyclesPCM bank 90 read requests wait in the queue
pcm_bank_90_read_queue_time 0

#Number of cyclesPCM bank 90 write requests wait in the queue
pcm_bank_90_write_queue_time 0

#Total number of cycles of PCM bank 90 read requests
pcm_bank_90_read_total_time 0

#Total number of cycles of PCM bank 90 write requests
pcm_bank_90_write_total_time 0

#Number of PCM bank 90 row buffer hits
pcm_bank_90_row_buffer_hits 0

#Number of PCM bank 90 row buffer misses
pcm_bank_90_row_buffer_misses 0

#Number of PCM bank 90 opens
pcm_bank_90_num_opens 0

#Number of PCM bank 90 accesses
pcm_bank_90_num_accesses 0

#Number of PCM bank 90 closes
pcm_bank_90_num_closes 0

#Number of PCM bank 90 read after read (RAR) hazards
pcm_bank_90_num_read_after_read 0

#Number of PCM bank 90 read after write (RAW) hazards
pcm_bank_90_num_read_after_write 0

#Number of PCM bank 90 write after read (WAR) hazards
pcm_bank_90_num_write_after_read 0

#Number of PCM bank 90 write after write (WAW) hazards
pcm_bank_90_num_write_after_write 0

#Number of cycles PCM bank 90 requests wait for lower priority requests
pcm_bank_90_wait_lower_priority_time 0

#Number of cycles PCM bank 90 requests wait for same priority requests
pcm_bank_90_wait_same_priority_time 0

#Number of cycles PCM bank 90 requests wait for higher priority requests
pcm_bank_90_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 91 spend in the queue
pcm_bank_91_queue_time 0

#Number of cycles PCM bank 91 spends opening rows for requests
pcm_bank_91_open_time 0

#Number of cycles PCM bank 91 spends accessing rows for requests
pcm_bank_91_access_time 0

#Number of cycles PCM bank 91 spends closing rows for requests
pcm_bank_91_close_time 0

#Number of PCM bank 91 read requests
pcm_bank_91_read_requests 0

#Number of PCM bank 91 write requests
pcm_bank_91_write_requests 0

#Number of cyclesPCM bank 91 read requests wait in the queue
pcm_bank_91_read_queue_time 0

#Number of cyclesPCM bank 91 write requests wait in the queue
pcm_bank_91_write_queue_time 0

#Total number of cycles of PCM bank 91 read requests
pcm_bank_91_read_total_time 0

#Total number of cycles of PCM bank 91 write requests
pcm_bank_91_write_total_time 0

#Number of PCM bank 91 row buffer hits
pcm_bank_91_row_buffer_hits 0

#Number of PCM bank 91 row buffer misses
pcm_bank_91_row_buffer_misses 0

#Number of PCM bank 91 opens
pcm_bank_91_num_opens 0

#Number of PCM bank 91 accesses
pcm_bank_91_num_accesses 0

#Number of PCM bank 91 closes
pcm_bank_91_num_closes 0

#Number of PCM bank 91 read after read (RAR) hazards
pcm_bank_91_num_read_after_read 0

#Number of PCM bank 91 read after write (RAW) hazards
pcm_bank_91_num_read_after_write 0

#Number of PCM bank 91 write after read (WAR) hazards
pcm_bank_91_num_write_after_read 0

#Number of PCM bank 91 write after write (WAW) hazards
pcm_bank_91_num_write_after_write 0

#Number of cycles PCM bank 91 requests wait for lower priority requests
pcm_bank_91_wait_lower_priority_time 0

#Number of cycles PCM bank 91 requests wait for same priority requests
pcm_bank_91_wait_same_priority_time 0

#Number of cycles PCM bank 91 requests wait for higher priority requests
pcm_bank_91_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 92 spend in the queue
pcm_bank_92_queue_time 0

#Number of cycles PCM bank 92 spends opening rows for requests
pcm_bank_92_open_time 0

#Number of cycles PCM bank 92 spends accessing rows for requests
pcm_bank_92_access_time 0

#Number of cycles PCM bank 92 spends closing rows for requests
pcm_bank_92_close_time 0

#Number of PCM bank 92 read requests
pcm_bank_92_read_requests 0

#Number of PCM bank 92 write requests
pcm_bank_92_write_requests 0

#Number of cyclesPCM bank 92 read requests wait in the queue
pcm_bank_92_read_queue_time 0

#Number of cyclesPCM bank 92 write requests wait in the queue
pcm_bank_92_write_queue_time 0

#Total number of cycles of PCM bank 92 read requests
pcm_bank_92_read_total_time 0

#Total number of cycles of PCM bank 92 write requests
pcm_bank_92_write_total_time 0

#Number of PCM bank 92 row buffer hits
pcm_bank_92_row_buffer_hits 0

#Number of PCM bank 92 row buffer misses
pcm_bank_92_row_buffer_misses 0

#Number of PCM bank 92 opens
pcm_bank_92_num_opens 0

#Number of PCM bank 92 accesses
pcm_bank_92_num_accesses 0

#Number of PCM bank 92 closes
pcm_bank_92_num_closes 0

#Number of PCM bank 92 read after read (RAR) hazards
pcm_bank_92_num_read_after_read 0

#Number of PCM bank 92 read after write (RAW) hazards
pcm_bank_92_num_read_after_write 0

#Number of PCM bank 92 write after read (WAR) hazards
pcm_bank_92_num_write_after_read 0

#Number of PCM bank 92 write after write (WAW) hazards
pcm_bank_92_num_write_after_write 0

#Number of cycles PCM bank 92 requests wait for lower priority requests
pcm_bank_92_wait_lower_priority_time 0

#Number of cycles PCM bank 92 requests wait for same priority requests
pcm_bank_92_wait_same_priority_time 0

#Number of cycles PCM bank 92 requests wait for higher priority requests
pcm_bank_92_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 93 spend in the queue
pcm_bank_93_queue_time 0

#Number of cycles PCM bank 93 spends opening rows for requests
pcm_bank_93_open_time 0

#Number of cycles PCM bank 93 spends accessing rows for requests
pcm_bank_93_access_time 0

#Number of cycles PCM bank 93 spends closing rows for requests
pcm_bank_93_close_time 0

#Number of PCM bank 93 read requests
pcm_bank_93_read_requests 0

#Number of PCM bank 93 write requests
pcm_bank_93_write_requests 0

#Number of cyclesPCM bank 93 read requests wait in the queue
pcm_bank_93_read_queue_time 0

#Number of cyclesPCM bank 93 write requests wait in the queue
pcm_bank_93_write_queue_time 0

#Total number of cycles of PCM bank 93 read requests
pcm_bank_93_read_total_time 0

#Total number of cycles of PCM bank 93 write requests
pcm_bank_93_write_total_time 0

#Number of PCM bank 93 row buffer hits
pcm_bank_93_row_buffer_hits 0

#Number of PCM bank 93 row buffer misses
pcm_bank_93_row_buffer_misses 0

#Number of PCM bank 93 opens
pcm_bank_93_num_opens 0

#Number of PCM bank 93 accesses
pcm_bank_93_num_accesses 0

#Number of PCM bank 93 closes
pcm_bank_93_num_closes 0

#Number of PCM bank 93 read after read (RAR) hazards
pcm_bank_93_num_read_after_read 0

#Number of PCM bank 93 read after write (RAW) hazards
pcm_bank_93_num_read_after_write 0

#Number of PCM bank 93 write after read (WAR) hazards
pcm_bank_93_num_write_after_read 0

#Number of PCM bank 93 write after write (WAW) hazards
pcm_bank_93_num_write_after_write 0

#Number of cycles PCM bank 93 requests wait for lower priority requests
pcm_bank_93_wait_lower_priority_time 0

#Number of cycles PCM bank 93 requests wait for same priority requests
pcm_bank_93_wait_same_priority_time 0

#Number of cycles PCM bank 93 requests wait for higher priority requests
pcm_bank_93_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 94 spend in the queue
pcm_bank_94_queue_time 0

#Number of cycles PCM bank 94 spends opening rows for requests
pcm_bank_94_open_time 0

#Number of cycles PCM bank 94 spends accessing rows for requests
pcm_bank_94_access_time 0

#Number of cycles PCM bank 94 spends closing rows for requests
pcm_bank_94_close_time 0

#Number of PCM bank 94 read requests
pcm_bank_94_read_requests 0

#Number of PCM bank 94 write requests
pcm_bank_94_write_requests 0

#Number of cyclesPCM bank 94 read requests wait in the queue
pcm_bank_94_read_queue_time 0

#Number of cyclesPCM bank 94 write requests wait in the queue
pcm_bank_94_write_queue_time 0

#Total number of cycles of PCM bank 94 read requests
pcm_bank_94_read_total_time 0

#Total number of cycles of PCM bank 94 write requests
pcm_bank_94_write_total_time 0

#Number of PCM bank 94 row buffer hits
pcm_bank_94_row_buffer_hits 0

#Number of PCM bank 94 row buffer misses
pcm_bank_94_row_buffer_misses 0

#Number of PCM bank 94 opens
pcm_bank_94_num_opens 0

#Number of PCM bank 94 accesses
pcm_bank_94_num_accesses 0

#Number of PCM bank 94 closes
pcm_bank_94_num_closes 0

#Number of PCM bank 94 read after read (RAR) hazards
pcm_bank_94_num_read_after_read 0

#Number of PCM bank 94 read after write (RAW) hazards
pcm_bank_94_num_read_after_write 0

#Number of PCM bank 94 write after read (WAR) hazards
pcm_bank_94_num_write_after_read 0

#Number of PCM bank 94 write after write (WAW) hazards
pcm_bank_94_num_write_after_write 0

#Number of cycles PCM bank 94 requests wait for lower priority requests
pcm_bank_94_wait_lower_priority_time 0

#Number of cycles PCM bank 94 requests wait for same priority requests
pcm_bank_94_wait_same_priority_time 0

#Number of cycles PCM bank 94 requests wait for higher priority requests
pcm_bank_94_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 95 spend in the queue
pcm_bank_95_queue_time 0

#Number of cycles PCM bank 95 spends opening rows for requests
pcm_bank_95_open_time 0

#Number of cycles PCM bank 95 spends accessing rows for requests
pcm_bank_95_access_time 0

#Number of cycles PCM bank 95 spends closing rows for requests
pcm_bank_95_close_time 0

#Number of PCM bank 95 read requests
pcm_bank_95_read_requests 0

#Number of PCM bank 95 write requests
pcm_bank_95_write_requests 0

#Number of cyclesPCM bank 95 read requests wait in the queue
pcm_bank_95_read_queue_time 0

#Number of cyclesPCM bank 95 write requests wait in the queue
pcm_bank_95_write_queue_time 0

#Total number of cycles of PCM bank 95 read requests
pcm_bank_95_read_total_time 0

#Total number of cycles of PCM bank 95 write requests
pcm_bank_95_write_total_time 0

#Number of PCM bank 95 row buffer hits
pcm_bank_95_row_buffer_hits 0

#Number of PCM bank 95 row buffer misses
pcm_bank_95_row_buffer_misses 0

#Number of PCM bank 95 opens
pcm_bank_95_num_opens 0

#Number of PCM bank 95 accesses
pcm_bank_95_num_accesses 0

#Number of PCM bank 95 closes
pcm_bank_95_num_closes 0

#Number of PCM bank 95 read after read (RAR) hazards
pcm_bank_95_num_read_after_read 0

#Number of PCM bank 95 read after write (RAW) hazards
pcm_bank_95_num_read_after_write 0

#Number of PCM bank 95 write after read (WAR) hazards
pcm_bank_95_num_write_after_read 0

#Number of PCM bank 95 write after write (WAW) hazards
pcm_bank_95_num_write_after_write 0

#Number of cycles PCM bank 95 requests wait for lower priority requests
pcm_bank_95_wait_lower_priority_time 0

#Number of cycles PCM bank 95 requests wait for same priority requests
pcm_bank_95_wait_same_priority_time 0

#Number of cycles PCM bank 95 requests wait for higher priority requests
pcm_bank_95_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 96 spend in the queue
pcm_bank_96_queue_time 0

#Number of cycles PCM bank 96 spends opening rows for requests
pcm_bank_96_open_time 0

#Number of cycles PCM bank 96 spends accessing rows for requests
pcm_bank_96_access_time 0

#Number of cycles PCM bank 96 spends closing rows for requests
pcm_bank_96_close_time 0

#Number of PCM bank 96 read requests
pcm_bank_96_read_requests 0

#Number of PCM bank 96 write requests
pcm_bank_96_write_requests 0

#Number of cyclesPCM bank 96 read requests wait in the queue
pcm_bank_96_read_queue_time 0

#Number of cyclesPCM bank 96 write requests wait in the queue
pcm_bank_96_write_queue_time 0

#Total number of cycles of PCM bank 96 read requests
pcm_bank_96_read_total_time 0

#Total number of cycles of PCM bank 96 write requests
pcm_bank_96_write_total_time 0

#Number of PCM bank 96 row buffer hits
pcm_bank_96_row_buffer_hits 0

#Number of PCM bank 96 row buffer misses
pcm_bank_96_row_buffer_misses 0

#Number of PCM bank 96 opens
pcm_bank_96_num_opens 0

#Number of PCM bank 96 accesses
pcm_bank_96_num_accesses 0

#Number of PCM bank 96 closes
pcm_bank_96_num_closes 0

#Number of PCM bank 96 read after read (RAR) hazards
pcm_bank_96_num_read_after_read 0

#Number of PCM bank 96 read after write (RAW) hazards
pcm_bank_96_num_read_after_write 0

#Number of PCM bank 96 write after read (WAR) hazards
pcm_bank_96_num_write_after_read 0

#Number of PCM bank 96 write after write (WAW) hazards
pcm_bank_96_num_write_after_write 0

#Number of cycles PCM bank 96 requests wait for lower priority requests
pcm_bank_96_wait_lower_priority_time 0

#Number of cycles PCM bank 96 requests wait for same priority requests
pcm_bank_96_wait_same_priority_time 0

#Number of cycles PCM bank 96 requests wait for higher priority requests
pcm_bank_96_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 97 spend in the queue
pcm_bank_97_queue_time 0

#Number of cycles PCM bank 97 spends opening rows for requests
pcm_bank_97_open_time 0

#Number of cycles PCM bank 97 spends accessing rows for requests
pcm_bank_97_access_time 0

#Number of cycles PCM bank 97 spends closing rows for requests
pcm_bank_97_close_time 0

#Number of PCM bank 97 read requests
pcm_bank_97_read_requests 0

#Number of PCM bank 97 write requests
pcm_bank_97_write_requests 0

#Number of cyclesPCM bank 97 read requests wait in the queue
pcm_bank_97_read_queue_time 0

#Number of cyclesPCM bank 97 write requests wait in the queue
pcm_bank_97_write_queue_time 0

#Total number of cycles of PCM bank 97 read requests
pcm_bank_97_read_total_time 0

#Total number of cycles of PCM bank 97 write requests
pcm_bank_97_write_total_time 0

#Number of PCM bank 97 row buffer hits
pcm_bank_97_row_buffer_hits 0

#Number of PCM bank 97 row buffer misses
pcm_bank_97_row_buffer_misses 0

#Number of PCM bank 97 opens
pcm_bank_97_num_opens 0

#Number of PCM bank 97 accesses
pcm_bank_97_num_accesses 0

#Number of PCM bank 97 closes
pcm_bank_97_num_closes 0

#Number of PCM bank 97 read after read (RAR) hazards
pcm_bank_97_num_read_after_read 0

#Number of PCM bank 97 read after write (RAW) hazards
pcm_bank_97_num_read_after_write 0

#Number of PCM bank 97 write after read (WAR) hazards
pcm_bank_97_num_write_after_read 0

#Number of PCM bank 97 write after write (WAW) hazards
pcm_bank_97_num_write_after_write 0

#Number of cycles PCM bank 97 requests wait for lower priority requests
pcm_bank_97_wait_lower_priority_time 0

#Number of cycles PCM bank 97 requests wait for same priority requests
pcm_bank_97_wait_same_priority_time 0

#Number of cycles PCM bank 97 requests wait for higher priority requests
pcm_bank_97_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 98 spend in the queue
pcm_bank_98_queue_time 0

#Number of cycles PCM bank 98 spends opening rows for requests
pcm_bank_98_open_time 0

#Number of cycles PCM bank 98 spends accessing rows for requests
pcm_bank_98_access_time 0

#Number of cycles PCM bank 98 spends closing rows for requests
pcm_bank_98_close_time 0

#Number of PCM bank 98 read requests
pcm_bank_98_read_requests 0

#Number of PCM bank 98 write requests
pcm_bank_98_write_requests 0

#Number of cyclesPCM bank 98 read requests wait in the queue
pcm_bank_98_read_queue_time 0

#Number of cyclesPCM bank 98 write requests wait in the queue
pcm_bank_98_write_queue_time 0

#Total number of cycles of PCM bank 98 read requests
pcm_bank_98_read_total_time 0

#Total number of cycles of PCM bank 98 write requests
pcm_bank_98_write_total_time 0

#Number of PCM bank 98 row buffer hits
pcm_bank_98_row_buffer_hits 0

#Number of PCM bank 98 row buffer misses
pcm_bank_98_row_buffer_misses 0

#Number of PCM bank 98 opens
pcm_bank_98_num_opens 0

#Number of PCM bank 98 accesses
pcm_bank_98_num_accesses 0

#Number of PCM bank 98 closes
pcm_bank_98_num_closes 0

#Number of PCM bank 98 read after read (RAR) hazards
pcm_bank_98_num_read_after_read 0

#Number of PCM bank 98 read after write (RAW) hazards
pcm_bank_98_num_read_after_write 0

#Number of PCM bank 98 write after read (WAR) hazards
pcm_bank_98_num_write_after_read 0

#Number of PCM bank 98 write after write (WAW) hazards
pcm_bank_98_num_write_after_write 0

#Number of cycles PCM bank 98 requests wait for lower priority requests
pcm_bank_98_wait_lower_priority_time 0

#Number of cycles PCM bank 98 requests wait for same priority requests
pcm_bank_98_wait_same_priority_time 0

#Number of cycles PCM bank 98 requests wait for higher priority requests
pcm_bank_98_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 99 spend in the queue
pcm_bank_99_queue_time 0

#Number of cycles PCM bank 99 spends opening rows for requests
pcm_bank_99_open_time 0

#Number of cycles PCM bank 99 spends accessing rows for requests
pcm_bank_99_access_time 0

#Number of cycles PCM bank 99 spends closing rows for requests
pcm_bank_99_close_time 0

#Number of PCM bank 99 read requests
pcm_bank_99_read_requests 0

#Number of PCM bank 99 write requests
pcm_bank_99_write_requests 0

#Number of cyclesPCM bank 99 read requests wait in the queue
pcm_bank_99_read_queue_time 0

#Number of cyclesPCM bank 99 write requests wait in the queue
pcm_bank_99_write_queue_time 0

#Total number of cycles of PCM bank 99 read requests
pcm_bank_99_read_total_time 0

#Total number of cycles of PCM bank 99 write requests
pcm_bank_99_write_total_time 0

#Number of PCM bank 99 row buffer hits
pcm_bank_99_row_buffer_hits 0

#Number of PCM bank 99 row buffer misses
pcm_bank_99_row_buffer_misses 0

#Number of PCM bank 99 opens
pcm_bank_99_num_opens 0

#Number of PCM bank 99 accesses
pcm_bank_99_num_accesses 0

#Number of PCM bank 99 closes
pcm_bank_99_num_closes 0

#Number of PCM bank 99 read after read (RAR) hazards
pcm_bank_99_num_read_after_read 0

#Number of PCM bank 99 read after write (RAW) hazards
pcm_bank_99_num_read_after_write 0

#Number of PCM bank 99 write after read (WAR) hazards
pcm_bank_99_num_write_after_read 0

#Number of PCM bank 99 write after write (WAW) hazards
pcm_bank_99_num_write_after_write 0

#Number of cycles PCM bank 99 requests wait for lower priority requests
pcm_bank_99_wait_lower_priority_time 0

#Number of cycles PCM bank 99 requests wait for same priority requests
pcm_bank_99_wait_same_priority_time 0

#Number of cycles PCM bank 99 requests wait for higher priority requests
pcm_bank_99_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 100 spend in the queue
pcm_bank_100_queue_time 0

#Number of cycles PCM bank 100 spends opening rows for requests
pcm_bank_100_open_time 0

#Number of cycles PCM bank 100 spends accessing rows for requests
pcm_bank_100_access_time 0

#Number of cycles PCM bank 100 spends closing rows for requests
pcm_bank_100_close_time 0

#Number of PCM bank 100 read requests
pcm_bank_100_read_requests 0

#Number of PCM bank 100 write requests
pcm_bank_100_write_requests 0

#Number of cyclesPCM bank 100 read requests wait in the queue
pcm_bank_100_read_queue_time 0

#Number of cyclesPCM bank 100 write requests wait in the queue
pcm_bank_100_write_queue_time 0

#Total number of cycles of PCM bank 100 read requests
pcm_bank_100_read_total_time 0

#Total number of cycles of PCM bank 100 write requests
pcm_bank_100_write_total_time 0

#Number of PCM bank 100 row buffer hits
pcm_bank_100_row_buffer_hits 0

#Number of PCM bank 100 row buffer misses
pcm_bank_100_row_buffer_misses 0

#Number of PCM bank 100 opens
pcm_bank_100_num_opens 0

#Number of PCM bank 100 accesses
pcm_bank_100_num_accesses 0

#Number of PCM bank 100 closes
pcm_bank_100_num_closes 0

#Number of PCM bank 100 read after read (RAR) hazards
pcm_bank_100_num_read_after_read 0

#Number of PCM bank 100 read after write (RAW) hazards
pcm_bank_100_num_read_after_write 0

#Number of PCM bank 100 write after read (WAR) hazards
pcm_bank_100_num_write_after_read 0

#Number of PCM bank 100 write after write (WAW) hazards
pcm_bank_100_num_write_after_write 0

#Number of cycles PCM bank 100 requests wait for lower priority requests
pcm_bank_100_wait_lower_priority_time 0

#Number of cycles PCM bank 100 requests wait for same priority requests
pcm_bank_100_wait_same_priority_time 0

#Number of cycles PCM bank 100 requests wait for higher priority requests
pcm_bank_100_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 101 spend in the queue
pcm_bank_101_queue_time 0

#Number of cycles PCM bank 101 spends opening rows for requests
pcm_bank_101_open_time 0

#Number of cycles PCM bank 101 spends accessing rows for requests
pcm_bank_101_access_time 0

#Number of cycles PCM bank 101 spends closing rows for requests
pcm_bank_101_close_time 0

#Number of PCM bank 101 read requests
pcm_bank_101_read_requests 0

#Number of PCM bank 101 write requests
pcm_bank_101_write_requests 0

#Number of cyclesPCM bank 101 read requests wait in the queue
pcm_bank_101_read_queue_time 0

#Number of cyclesPCM bank 101 write requests wait in the queue
pcm_bank_101_write_queue_time 0

#Total number of cycles of PCM bank 101 read requests
pcm_bank_101_read_total_time 0

#Total number of cycles of PCM bank 101 write requests
pcm_bank_101_write_total_time 0

#Number of PCM bank 101 row buffer hits
pcm_bank_101_row_buffer_hits 0

#Number of PCM bank 101 row buffer misses
pcm_bank_101_row_buffer_misses 0

#Number of PCM bank 101 opens
pcm_bank_101_num_opens 0

#Number of PCM bank 101 accesses
pcm_bank_101_num_accesses 0

#Number of PCM bank 101 closes
pcm_bank_101_num_closes 0

#Number of PCM bank 101 read after read (RAR) hazards
pcm_bank_101_num_read_after_read 0

#Number of PCM bank 101 read after write (RAW) hazards
pcm_bank_101_num_read_after_write 0

#Number of PCM bank 101 write after read (WAR) hazards
pcm_bank_101_num_write_after_read 0

#Number of PCM bank 101 write after write (WAW) hazards
pcm_bank_101_num_write_after_write 0

#Number of cycles PCM bank 101 requests wait for lower priority requests
pcm_bank_101_wait_lower_priority_time 0

#Number of cycles PCM bank 101 requests wait for same priority requests
pcm_bank_101_wait_same_priority_time 0

#Number of cycles PCM bank 101 requests wait for higher priority requests
pcm_bank_101_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 102 spend in the queue
pcm_bank_102_queue_time 0

#Number of cycles PCM bank 102 spends opening rows for requests
pcm_bank_102_open_time 0

#Number of cycles PCM bank 102 spends accessing rows for requests
pcm_bank_102_access_time 0

#Number of cycles PCM bank 102 spends closing rows for requests
pcm_bank_102_close_time 0

#Number of PCM bank 102 read requests
pcm_bank_102_read_requests 0

#Number of PCM bank 102 write requests
pcm_bank_102_write_requests 0

#Number of cyclesPCM bank 102 read requests wait in the queue
pcm_bank_102_read_queue_time 0

#Number of cyclesPCM bank 102 write requests wait in the queue
pcm_bank_102_write_queue_time 0

#Total number of cycles of PCM bank 102 read requests
pcm_bank_102_read_total_time 0

#Total number of cycles of PCM bank 102 write requests
pcm_bank_102_write_total_time 0

#Number of PCM bank 102 row buffer hits
pcm_bank_102_row_buffer_hits 0

#Number of PCM bank 102 row buffer misses
pcm_bank_102_row_buffer_misses 0

#Number of PCM bank 102 opens
pcm_bank_102_num_opens 0

#Number of PCM bank 102 accesses
pcm_bank_102_num_accesses 0

#Number of PCM bank 102 closes
pcm_bank_102_num_closes 0

#Number of PCM bank 102 read after read (RAR) hazards
pcm_bank_102_num_read_after_read 0

#Number of PCM bank 102 read after write (RAW) hazards
pcm_bank_102_num_read_after_write 0

#Number of PCM bank 102 write after read (WAR) hazards
pcm_bank_102_num_write_after_read 0

#Number of PCM bank 102 write after write (WAW) hazards
pcm_bank_102_num_write_after_write 0

#Number of cycles PCM bank 102 requests wait for lower priority requests
pcm_bank_102_wait_lower_priority_time 0

#Number of cycles PCM bank 102 requests wait for same priority requests
pcm_bank_102_wait_same_priority_time 0

#Number of cycles PCM bank 102 requests wait for higher priority requests
pcm_bank_102_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 103 spend in the queue
pcm_bank_103_queue_time 0

#Number of cycles PCM bank 103 spends opening rows for requests
pcm_bank_103_open_time 0

#Number of cycles PCM bank 103 spends accessing rows for requests
pcm_bank_103_access_time 0

#Number of cycles PCM bank 103 spends closing rows for requests
pcm_bank_103_close_time 0

#Number of PCM bank 103 read requests
pcm_bank_103_read_requests 0

#Number of PCM bank 103 write requests
pcm_bank_103_write_requests 0

#Number of cyclesPCM bank 103 read requests wait in the queue
pcm_bank_103_read_queue_time 0

#Number of cyclesPCM bank 103 write requests wait in the queue
pcm_bank_103_write_queue_time 0

#Total number of cycles of PCM bank 103 read requests
pcm_bank_103_read_total_time 0

#Total number of cycles of PCM bank 103 write requests
pcm_bank_103_write_total_time 0

#Number of PCM bank 103 row buffer hits
pcm_bank_103_row_buffer_hits 0

#Number of PCM bank 103 row buffer misses
pcm_bank_103_row_buffer_misses 0

#Number of PCM bank 103 opens
pcm_bank_103_num_opens 0

#Number of PCM bank 103 accesses
pcm_bank_103_num_accesses 0

#Number of PCM bank 103 closes
pcm_bank_103_num_closes 0

#Number of PCM bank 103 read after read (RAR) hazards
pcm_bank_103_num_read_after_read 0

#Number of PCM bank 103 read after write (RAW) hazards
pcm_bank_103_num_read_after_write 0

#Number of PCM bank 103 write after read (WAR) hazards
pcm_bank_103_num_write_after_read 0

#Number of PCM bank 103 write after write (WAW) hazards
pcm_bank_103_num_write_after_write 0

#Number of cycles PCM bank 103 requests wait for lower priority requests
pcm_bank_103_wait_lower_priority_time 0

#Number of cycles PCM bank 103 requests wait for same priority requests
pcm_bank_103_wait_same_priority_time 0

#Number of cycles PCM bank 103 requests wait for higher priority requests
pcm_bank_103_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 104 spend in the queue
pcm_bank_104_queue_time 0

#Number of cycles PCM bank 104 spends opening rows for requests
pcm_bank_104_open_time 0

#Number of cycles PCM bank 104 spends accessing rows for requests
pcm_bank_104_access_time 0

#Number of cycles PCM bank 104 spends closing rows for requests
pcm_bank_104_close_time 0

#Number of PCM bank 104 read requests
pcm_bank_104_read_requests 0

#Number of PCM bank 104 write requests
pcm_bank_104_write_requests 0

#Number of cyclesPCM bank 104 read requests wait in the queue
pcm_bank_104_read_queue_time 0

#Number of cyclesPCM bank 104 write requests wait in the queue
pcm_bank_104_write_queue_time 0

#Total number of cycles of PCM bank 104 read requests
pcm_bank_104_read_total_time 0

#Total number of cycles of PCM bank 104 write requests
pcm_bank_104_write_total_time 0

#Number of PCM bank 104 row buffer hits
pcm_bank_104_row_buffer_hits 0

#Number of PCM bank 104 row buffer misses
pcm_bank_104_row_buffer_misses 0

#Number of PCM bank 104 opens
pcm_bank_104_num_opens 0

#Number of PCM bank 104 accesses
pcm_bank_104_num_accesses 0

#Number of PCM bank 104 closes
pcm_bank_104_num_closes 0

#Number of PCM bank 104 read after read (RAR) hazards
pcm_bank_104_num_read_after_read 0

#Number of PCM bank 104 read after write (RAW) hazards
pcm_bank_104_num_read_after_write 0

#Number of PCM bank 104 write after read (WAR) hazards
pcm_bank_104_num_write_after_read 0

#Number of PCM bank 104 write after write (WAW) hazards
pcm_bank_104_num_write_after_write 0

#Number of cycles PCM bank 104 requests wait for lower priority requests
pcm_bank_104_wait_lower_priority_time 0

#Number of cycles PCM bank 104 requests wait for same priority requests
pcm_bank_104_wait_same_priority_time 0

#Number of cycles PCM bank 104 requests wait for higher priority requests
pcm_bank_104_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 105 spend in the queue
pcm_bank_105_queue_time 0

#Number of cycles PCM bank 105 spends opening rows for requests
pcm_bank_105_open_time 0

#Number of cycles PCM bank 105 spends accessing rows for requests
pcm_bank_105_access_time 0

#Number of cycles PCM bank 105 spends closing rows for requests
pcm_bank_105_close_time 0

#Number of PCM bank 105 read requests
pcm_bank_105_read_requests 0

#Number of PCM bank 105 write requests
pcm_bank_105_write_requests 0

#Number of cyclesPCM bank 105 read requests wait in the queue
pcm_bank_105_read_queue_time 0

#Number of cyclesPCM bank 105 write requests wait in the queue
pcm_bank_105_write_queue_time 0

#Total number of cycles of PCM bank 105 read requests
pcm_bank_105_read_total_time 0

#Total number of cycles of PCM bank 105 write requests
pcm_bank_105_write_total_time 0

#Number of PCM bank 105 row buffer hits
pcm_bank_105_row_buffer_hits 0

#Number of PCM bank 105 row buffer misses
pcm_bank_105_row_buffer_misses 0

#Number of PCM bank 105 opens
pcm_bank_105_num_opens 0

#Number of PCM bank 105 accesses
pcm_bank_105_num_accesses 0

#Number of PCM bank 105 closes
pcm_bank_105_num_closes 0

#Number of PCM bank 105 read after read (RAR) hazards
pcm_bank_105_num_read_after_read 0

#Number of PCM bank 105 read after write (RAW) hazards
pcm_bank_105_num_read_after_write 0

#Number of PCM bank 105 write after read (WAR) hazards
pcm_bank_105_num_write_after_read 0

#Number of PCM bank 105 write after write (WAW) hazards
pcm_bank_105_num_write_after_write 0

#Number of cycles PCM bank 105 requests wait for lower priority requests
pcm_bank_105_wait_lower_priority_time 0

#Number of cycles PCM bank 105 requests wait for same priority requests
pcm_bank_105_wait_same_priority_time 0

#Number of cycles PCM bank 105 requests wait for higher priority requests
pcm_bank_105_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 106 spend in the queue
pcm_bank_106_queue_time 0

#Number of cycles PCM bank 106 spends opening rows for requests
pcm_bank_106_open_time 0

#Number of cycles PCM bank 106 spends accessing rows for requests
pcm_bank_106_access_time 0

#Number of cycles PCM bank 106 spends closing rows for requests
pcm_bank_106_close_time 0

#Number of PCM bank 106 read requests
pcm_bank_106_read_requests 0

#Number of PCM bank 106 write requests
pcm_bank_106_write_requests 0

#Number of cyclesPCM bank 106 read requests wait in the queue
pcm_bank_106_read_queue_time 0

#Number of cyclesPCM bank 106 write requests wait in the queue
pcm_bank_106_write_queue_time 0

#Total number of cycles of PCM bank 106 read requests
pcm_bank_106_read_total_time 0

#Total number of cycles of PCM bank 106 write requests
pcm_bank_106_write_total_time 0

#Number of PCM bank 106 row buffer hits
pcm_bank_106_row_buffer_hits 0

#Number of PCM bank 106 row buffer misses
pcm_bank_106_row_buffer_misses 0

#Number of PCM bank 106 opens
pcm_bank_106_num_opens 0

#Number of PCM bank 106 accesses
pcm_bank_106_num_accesses 0

#Number of PCM bank 106 closes
pcm_bank_106_num_closes 0

#Number of PCM bank 106 read after read (RAR) hazards
pcm_bank_106_num_read_after_read 0

#Number of PCM bank 106 read after write (RAW) hazards
pcm_bank_106_num_read_after_write 0

#Number of PCM bank 106 write after read (WAR) hazards
pcm_bank_106_num_write_after_read 0

#Number of PCM bank 106 write after write (WAW) hazards
pcm_bank_106_num_write_after_write 0

#Number of cycles PCM bank 106 requests wait for lower priority requests
pcm_bank_106_wait_lower_priority_time 0

#Number of cycles PCM bank 106 requests wait for same priority requests
pcm_bank_106_wait_same_priority_time 0

#Number of cycles PCM bank 106 requests wait for higher priority requests
pcm_bank_106_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 107 spend in the queue
pcm_bank_107_queue_time 0

#Number of cycles PCM bank 107 spends opening rows for requests
pcm_bank_107_open_time 0

#Number of cycles PCM bank 107 spends accessing rows for requests
pcm_bank_107_access_time 0

#Number of cycles PCM bank 107 spends closing rows for requests
pcm_bank_107_close_time 0

#Number of PCM bank 107 read requests
pcm_bank_107_read_requests 0

#Number of PCM bank 107 write requests
pcm_bank_107_write_requests 0

#Number of cyclesPCM bank 107 read requests wait in the queue
pcm_bank_107_read_queue_time 0

#Number of cyclesPCM bank 107 write requests wait in the queue
pcm_bank_107_write_queue_time 0

#Total number of cycles of PCM bank 107 read requests
pcm_bank_107_read_total_time 0

#Total number of cycles of PCM bank 107 write requests
pcm_bank_107_write_total_time 0

#Number of PCM bank 107 row buffer hits
pcm_bank_107_row_buffer_hits 0

#Number of PCM bank 107 row buffer misses
pcm_bank_107_row_buffer_misses 0

#Number of PCM bank 107 opens
pcm_bank_107_num_opens 0

#Number of PCM bank 107 accesses
pcm_bank_107_num_accesses 0

#Number of PCM bank 107 closes
pcm_bank_107_num_closes 0

#Number of PCM bank 107 read after read (RAR) hazards
pcm_bank_107_num_read_after_read 0

#Number of PCM bank 107 read after write (RAW) hazards
pcm_bank_107_num_read_after_write 0

#Number of PCM bank 107 write after read (WAR) hazards
pcm_bank_107_num_write_after_read 0

#Number of PCM bank 107 write after write (WAW) hazards
pcm_bank_107_num_write_after_write 0

#Number of cycles PCM bank 107 requests wait for lower priority requests
pcm_bank_107_wait_lower_priority_time 0

#Number of cycles PCM bank 107 requests wait for same priority requests
pcm_bank_107_wait_same_priority_time 0

#Number of cycles PCM bank 107 requests wait for higher priority requests
pcm_bank_107_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 108 spend in the queue
pcm_bank_108_queue_time 0

#Number of cycles PCM bank 108 spends opening rows for requests
pcm_bank_108_open_time 0

#Number of cycles PCM bank 108 spends accessing rows for requests
pcm_bank_108_access_time 0

#Number of cycles PCM bank 108 spends closing rows for requests
pcm_bank_108_close_time 0

#Number of PCM bank 108 read requests
pcm_bank_108_read_requests 0

#Number of PCM bank 108 write requests
pcm_bank_108_write_requests 0

#Number of cyclesPCM bank 108 read requests wait in the queue
pcm_bank_108_read_queue_time 0

#Number of cyclesPCM bank 108 write requests wait in the queue
pcm_bank_108_write_queue_time 0

#Total number of cycles of PCM bank 108 read requests
pcm_bank_108_read_total_time 0

#Total number of cycles of PCM bank 108 write requests
pcm_bank_108_write_total_time 0

#Number of PCM bank 108 row buffer hits
pcm_bank_108_row_buffer_hits 0

#Number of PCM bank 108 row buffer misses
pcm_bank_108_row_buffer_misses 0

#Number of PCM bank 108 opens
pcm_bank_108_num_opens 0

#Number of PCM bank 108 accesses
pcm_bank_108_num_accesses 0

#Number of PCM bank 108 closes
pcm_bank_108_num_closes 0

#Number of PCM bank 108 read after read (RAR) hazards
pcm_bank_108_num_read_after_read 0

#Number of PCM bank 108 read after write (RAW) hazards
pcm_bank_108_num_read_after_write 0

#Number of PCM bank 108 write after read (WAR) hazards
pcm_bank_108_num_write_after_read 0

#Number of PCM bank 108 write after write (WAW) hazards
pcm_bank_108_num_write_after_write 0

#Number of cycles PCM bank 108 requests wait for lower priority requests
pcm_bank_108_wait_lower_priority_time 0

#Number of cycles PCM bank 108 requests wait for same priority requests
pcm_bank_108_wait_same_priority_time 0

#Number of cycles PCM bank 108 requests wait for higher priority requests
pcm_bank_108_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 109 spend in the queue
pcm_bank_109_queue_time 0

#Number of cycles PCM bank 109 spends opening rows for requests
pcm_bank_109_open_time 0

#Number of cycles PCM bank 109 spends accessing rows for requests
pcm_bank_109_access_time 0

#Number of cycles PCM bank 109 spends closing rows for requests
pcm_bank_109_close_time 0

#Number of PCM bank 109 read requests
pcm_bank_109_read_requests 0

#Number of PCM bank 109 write requests
pcm_bank_109_write_requests 0

#Number of cyclesPCM bank 109 read requests wait in the queue
pcm_bank_109_read_queue_time 0

#Number of cyclesPCM bank 109 write requests wait in the queue
pcm_bank_109_write_queue_time 0

#Total number of cycles of PCM bank 109 read requests
pcm_bank_109_read_total_time 0

#Total number of cycles of PCM bank 109 write requests
pcm_bank_109_write_total_time 0

#Number of PCM bank 109 row buffer hits
pcm_bank_109_row_buffer_hits 0

#Number of PCM bank 109 row buffer misses
pcm_bank_109_row_buffer_misses 0

#Number of PCM bank 109 opens
pcm_bank_109_num_opens 0

#Number of PCM bank 109 accesses
pcm_bank_109_num_accesses 0

#Number of PCM bank 109 closes
pcm_bank_109_num_closes 0

#Number of PCM bank 109 read after read (RAR) hazards
pcm_bank_109_num_read_after_read 0

#Number of PCM bank 109 read after write (RAW) hazards
pcm_bank_109_num_read_after_write 0

#Number of PCM bank 109 write after read (WAR) hazards
pcm_bank_109_num_write_after_read 0

#Number of PCM bank 109 write after write (WAW) hazards
pcm_bank_109_num_write_after_write 0

#Number of cycles PCM bank 109 requests wait for lower priority requests
pcm_bank_109_wait_lower_priority_time 0

#Number of cycles PCM bank 109 requests wait for same priority requests
pcm_bank_109_wait_same_priority_time 0

#Number of cycles PCM bank 109 requests wait for higher priority requests
pcm_bank_109_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 110 spend in the queue
pcm_bank_110_queue_time 0

#Number of cycles PCM bank 110 spends opening rows for requests
pcm_bank_110_open_time 0

#Number of cycles PCM bank 110 spends accessing rows for requests
pcm_bank_110_access_time 0

#Number of cycles PCM bank 110 spends closing rows for requests
pcm_bank_110_close_time 0

#Number of PCM bank 110 read requests
pcm_bank_110_read_requests 0

#Number of PCM bank 110 write requests
pcm_bank_110_write_requests 0

#Number of cyclesPCM bank 110 read requests wait in the queue
pcm_bank_110_read_queue_time 0

#Number of cyclesPCM bank 110 write requests wait in the queue
pcm_bank_110_write_queue_time 0

#Total number of cycles of PCM bank 110 read requests
pcm_bank_110_read_total_time 0

#Total number of cycles of PCM bank 110 write requests
pcm_bank_110_write_total_time 0

#Number of PCM bank 110 row buffer hits
pcm_bank_110_row_buffer_hits 0

#Number of PCM bank 110 row buffer misses
pcm_bank_110_row_buffer_misses 0

#Number of PCM bank 110 opens
pcm_bank_110_num_opens 0

#Number of PCM bank 110 accesses
pcm_bank_110_num_accesses 0

#Number of PCM bank 110 closes
pcm_bank_110_num_closes 0

#Number of PCM bank 110 read after read (RAR) hazards
pcm_bank_110_num_read_after_read 0

#Number of PCM bank 110 read after write (RAW) hazards
pcm_bank_110_num_read_after_write 0

#Number of PCM bank 110 write after read (WAR) hazards
pcm_bank_110_num_write_after_read 0

#Number of PCM bank 110 write after write (WAW) hazards
pcm_bank_110_num_write_after_write 0

#Number of cycles PCM bank 110 requests wait for lower priority requests
pcm_bank_110_wait_lower_priority_time 0

#Number of cycles PCM bank 110 requests wait for same priority requests
pcm_bank_110_wait_same_priority_time 0

#Number of cycles PCM bank 110 requests wait for higher priority requests
pcm_bank_110_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 111 spend in the queue
pcm_bank_111_queue_time 0

#Number of cycles PCM bank 111 spends opening rows for requests
pcm_bank_111_open_time 0

#Number of cycles PCM bank 111 spends accessing rows for requests
pcm_bank_111_access_time 0

#Number of cycles PCM bank 111 spends closing rows for requests
pcm_bank_111_close_time 0

#Number of PCM bank 111 read requests
pcm_bank_111_read_requests 0

#Number of PCM bank 111 write requests
pcm_bank_111_write_requests 0

#Number of cyclesPCM bank 111 read requests wait in the queue
pcm_bank_111_read_queue_time 0

#Number of cyclesPCM bank 111 write requests wait in the queue
pcm_bank_111_write_queue_time 0

#Total number of cycles of PCM bank 111 read requests
pcm_bank_111_read_total_time 0

#Total number of cycles of PCM bank 111 write requests
pcm_bank_111_write_total_time 0

#Number of PCM bank 111 row buffer hits
pcm_bank_111_row_buffer_hits 0

#Number of PCM bank 111 row buffer misses
pcm_bank_111_row_buffer_misses 0

#Number of PCM bank 111 opens
pcm_bank_111_num_opens 0

#Number of PCM bank 111 accesses
pcm_bank_111_num_accesses 0

#Number of PCM bank 111 closes
pcm_bank_111_num_closes 0

#Number of PCM bank 111 read after read (RAR) hazards
pcm_bank_111_num_read_after_read 0

#Number of PCM bank 111 read after write (RAW) hazards
pcm_bank_111_num_read_after_write 0

#Number of PCM bank 111 write after read (WAR) hazards
pcm_bank_111_num_write_after_read 0

#Number of PCM bank 111 write after write (WAW) hazards
pcm_bank_111_num_write_after_write 0

#Number of cycles PCM bank 111 requests wait for lower priority requests
pcm_bank_111_wait_lower_priority_time 0

#Number of cycles PCM bank 111 requests wait for same priority requests
pcm_bank_111_wait_same_priority_time 0

#Number of cycles PCM bank 111 requests wait for higher priority requests
pcm_bank_111_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 112 spend in the queue
pcm_bank_112_queue_time 0

#Number of cycles PCM bank 112 spends opening rows for requests
pcm_bank_112_open_time 0

#Number of cycles PCM bank 112 spends accessing rows for requests
pcm_bank_112_access_time 0

#Number of cycles PCM bank 112 spends closing rows for requests
pcm_bank_112_close_time 0

#Number of PCM bank 112 read requests
pcm_bank_112_read_requests 0

#Number of PCM bank 112 write requests
pcm_bank_112_write_requests 0

#Number of cyclesPCM bank 112 read requests wait in the queue
pcm_bank_112_read_queue_time 0

#Number of cyclesPCM bank 112 write requests wait in the queue
pcm_bank_112_write_queue_time 0

#Total number of cycles of PCM bank 112 read requests
pcm_bank_112_read_total_time 0

#Total number of cycles of PCM bank 112 write requests
pcm_bank_112_write_total_time 0

#Number of PCM bank 112 row buffer hits
pcm_bank_112_row_buffer_hits 0

#Number of PCM bank 112 row buffer misses
pcm_bank_112_row_buffer_misses 0

#Number of PCM bank 112 opens
pcm_bank_112_num_opens 0

#Number of PCM bank 112 accesses
pcm_bank_112_num_accesses 0

#Number of PCM bank 112 closes
pcm_bank_112_num_closes 0

#Number of PCM bank 112 read after read (RAR) hazards
pcm_bank_112_num_read_after_read 0

#Number of PCM bank 112 read after write (RAW) hazards
pcm_bank_112_num_read_after_write 0

#Number of PCM bank 112 write after read (WAR) hazards
pcm_bank_112_num_write_after_read 0

#Number of PCM bank 112 write after write (WAW) hazards
pcm_bank_112_num_write_after_write 0

#Number of cycles PCM bank 112 requests wait for lower priority requests
pcm_bank_112_wait_lower_priority_time 0

#Number of cycles PCM bank 112 requests wait for same priority requests
pcm_bank_112_wait_same_priority_time 0

#Number of cycles PCM bank 112 requests wait for higher priority requests
pcm_bank_112_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 113 spend in the queue
pcm_bank_113_queue_time 0

#Number of cycles PCM bank 113 spends opening rows for requests
pcm_bank_113_open_time 0

#Number of cycles PCM bank 113 spends accessing rows for requests
pcm_bank_113_access_time 0

#Number of cycles PCM bank 113 spends closing rows for requests
pcm_bank_113_close_time 0

#Number of PCM bank 113 read requests
pcm_bank_113_read_requests 0

#Number of PCM bank 113 write requests
pcm_bank_113_write_requests 0

#Number of cyclesPCM bank 113 read requests wait in the queue
pcm_bank_113_read_queue_time 0

#Number of cyclesPCM bank 113 write requests wait in the queue
pcm_bank_113_write_queue_time 0

#Total number of cycles of PCM bank 113 read requests
pcm_bank_113_read_total_time 0

#Total number of cycles of PCM bank 113 write requests
pcm_bank_113_write_total_time 0

#Number of PCM bank 113 row buffer hits
pcm_bank_113_row_buffer_hits 0

#Number of PCM bank 113 row buffer misses
pcm_bank_113_row_buffer_misses 0

#Number of PCM bank 113 opens
pcm_bank_113_num_opens 0

#Number of PCM bank 113 accesses
pcm_bank_113_num_accesses 0

#Number of PCM bank 113 closes
pcm_bank_113_num_closes 0

#Number of PCM bank 113 read after read (RAR) hazards
pcm_bank_113_num_read_after_read 0

#Number of PCM bank 113 read after write (RAW) hazards
pcm_bank_113_num_read_after_write 0

#Number of PCM bank 113 write after read (WAR) hazards
pcm_bank_113_num_write_after_read 0

#Number of PCM bank 113 write after write (WAW) hazards
pcm_bank_113_num_write_after_write 0

#Number of cycles PCM bank 113 requests wait for lower priority requests
pcm_bank_113_wait_lower_priority_time 0

#Number of cycles PCM bank 113 requests wait for same priority requests
pcm_bank_113_wait_same_priority_time 0

#Number of cycles PCM bank 113 requests wait for higher priority requests
pcm_bank_113_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 114 spend in the queue
pcm_bank_114_queue_time 0

#Number of cycles PCM bank 114 spends opening rows for requests
pcm_bank_114_open_time 0

#Number of cycles PCM bank 114 spends accessing rows for requests
pcm_bank_114_access_time 0

#Number of cycles PCM bank 114 spends closing rows for requests
pcm_bank_114_close_time 0

#Number of PCM bank 114 read requests
pcm_bank_114_read_requests 0

#Number of PCM bank 114 write requests
pcm_bank_114_write_requests 0

#Number of cyclesPCM bank 114 read requests wait in the queue
pcm_bank_114_read_queue_time 0

#Number of cyclesPCM bank 114 write requests wait in the queue
pcm_bank_114_write_queue_time 0

#Total number of cycles of PCM bank 114 read requests
pcm_bank_114_read_total_time 0

#Total number of cycles of PCM bank 114 write requests
pcm_bank_114_write_total_time 0

#Number of PCM bank 114 row buffer hits
pcm_bank_114_row_buffer_hits 0

#Number of PCM bank 114 row buffer misses
pcm_bank_114_row_buffer_misses 0

#Number of PCM bank 114 opens
pcm_bank_114_num_opens 0

#Number of PCM bank 114 accesses
pcm_bank_114_num_accesses 0

#Number of PCM bank 114 closes
pcm_bank_114_num_closes 0

#Number of PCM bank 114 read after read (RAR) hazards
pcm_bank_114_num_read_after_read 0

#Number of PCM bank 114 read after write (RAW) hazards
pcm_bank_114_num_read_after_write 0

#Number of PCM bank 114 write after read (WAR) hazards
pcm_bank_114_num_write_after_read 0

#Number of PCM bank 114 write after write (WAW) hazards
pcm_bank_114_num_write_after_write 0

#Number of cycles PCM bank 114 requests wait for lower priority requests
pcm_bank_114_wait_lower_priority_time 0

#Number of cycles PCM bank 114 requests wait for same priority requests
pcm_bank_114_wait_same_priority_time 0

#Number of cycles PCM bank 114 requests wait for higher priority requests
pcm_bank_114_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 115 spend in the queue
pcm_bank_115_queue_time 0

#Number of cycles PCM bank 115 spends opening rows for requests
pcm_bank_115_open_time 0

#Number of cycles PCM bank 115 spends accessing rows for requests
pcm_bank_115_access_time 0

#Number of cycles PCM bank 115 spends closing rows for requests
pcm_bank_115_close_time 0

#Number of PCM bank 115 read requests
pcm_bank_115_read_requests 0

#Number of PCM bank 115 write requests
pcm_bank_115_write_requests 0

#Number of cyclesPCM bank 115 read requests wait in the queue
pcm_bank_115_read_queue_time 0

#Number of cyclesPCM bank 115 write requests wait in the queue
pcm_bank_115_write_queue_time 0

#Total number of cycles of PCM bank 115 read requests
pcm_bank_115_read_total_time 0

#Total number of cycles of PCM bank 115 write requests
pcm_bank_115_write_total_time 0

#Number of PCM bank 115 row buffer hits
pcm_bank_115_row_buffer_hits 0

#Number of PCM bank 115 row buffer misses
pcm_bank_115_row_buffer_misses 0

#Number of PCM bank 115 opens
pcm_bank_115_num_opens 0

#Number of PCM bank 115 accesses
pcm_bank_115_num_accesses 0

#Number of PCM bank 115 closes
pcm_bank_115_num_closes 0

#Number of PCM bank 115 read after read (RAR) hazards
pcm_bank_115_num_read_after_read 0

#Number of PCM bank 115 read after write (RAW) hazards
pcm_bank_115_num_read_after_write 0

#Number of PCM bank 115 write after read (WAR) hazards
pcm_bank_115_num_write_after_read 0

#Number of PCM bank 115 write after write (WAW) hazards
pcm_bank_115_num_write_after_write 0

#Number of cycles PCM bank 115 requests wait for lower priority requests
pcm_bank_115_wait_lower_priority_time 0

#Number of cycles PCM bank 115 requests wait for same priority requests
pcm_bank_115_wait_same_priority_time 0

#Number of cycles PCM bank 115 requests wait for higher priority requests
pcm_bank_115_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 116 spend in the queue
pcm_bank_116_queue_time 0

#Number of cycles PCM bank 116 spends opening rows for requests
pcm_bank_116_open_time 0

#Number of cycles PCM bank 116 spends accessing rows for requests
pcm_bank_116_access_time 0

#Number of cycles PCM bank 116 spends closing rows for requests
pcm_bank_116_close_time 0

#Number of PCM bank 116 read requests
pcm_bank_116_read_requests 0

#Number of PCM bank 116 write requests
pcm_bank_116_write_requests 0

#Number of cyclesPCM bank 116 read requests wait in the queue
pcm_bank_116_read_queue_time 0

#Number of cyclesPCM bank 116 write requests wait in the queue
pcm_bank_116_write_queue_time 0

#Total number of cycles of PCM bank 116 read requests
pcm_bank_116_read_total_time 0

#Total number of cycles of PCM bank 116 write requests
pcm_bank_116_write_total_time 0

#Number of PCM bank 116 row buffer hits
pcm_bank_116_row_buffer_hits 0

#Number of PCM bank 116 row buffer misses
pcm_bank_116_row_buffer_misses 0

#Number of PCM bank 116 opens
pcm_bank_116_num_opens 0

#Number of PCM bank 116 accesses
pcm_bank_116_num_accesses 0

#Number of PCM bank 116 closes
pcm_bank_116_num_closes 0

#Number of PCM bank 116 read after read (RAR) hazards
pcm_bank_116_num_read_after_read 0

#Number of PCM bank 116 read after write (RAW) hazards
pcm_bank_116_num_read_after_write 0

#Number of PCM bank 116 write after read (WAR) hazards
pcm_bank_116_num_write_after_read 0

#Number of PCM bank 116 write after write (WAW) hazards
pcm_bank_116_num_write_after_write 0

#Number of cycles PCM bank 116 requests wait for lower priority requests
pcm_bank_116_wait_lower_priority_time 0

#Number of cycles PCM bank 116 requests wait for same priority requests
pcm_bank_116_wait_same_priority_time 0

#Number of cycles PCM bank 116 requests wait for higher priority requests
pcm_bank_116_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 117 spend in the queue
pcm_bank_117_queue_time 0

#Number of cycles PCM bank 117 spends opening rows for requests
pcm_bank_117_open_time 0

#Number of cycles PCM bank 117 spends accessing rows for requests
pcm_bank_117_access_time 0

#Number of cycles PCM bank 117 spends closing rows for requests
pcm_bank_117_close_time 0

#Number of PCM bank 117 read requests
pcm_bank_117_read_requests 0

#Number of PCM bank 117 write requests
pcm_bank_117_write_requests 0

#Number of cyclesPCM bank 117 read requests wait in the queue
pcm_bank_117_read_queue_time 0

#Number of cyclesPCM bank 117 write requests wait in the queue
pcm_bank_117_write_queue_time 0

#Total number of cycles of PCM bank 117 read requests
pcm_bank_117_read_total_time 0

#Total number of cycles of PCM bank 117 write requests
pcm_bank_117_write_total_time 0

#Number of PCM bank 117 row buffer hits
pcm_bank_117_row_buffer_hits 0

#Number of PCM bank 117 row buffer misses
pcm_bank_117_row_buffer_misses 0

#Number of PCM bank 117 opens
pcm_bank_117_num_opens 0

#Number of PCM bank 117 accesses
pcm_bank_117_num_accesses 0

#Number of PCM bank 117 closes
pcm_bank_117_num_closes 0

#Number of PCM bank 117 read after read (RAR) hazards
pcm_bank_117_num_read_after_read 0

#Number of PCM bank 117 read after write (RAW) hazards
pcm_bank_117_num_read_after_write 0

#Number of PCM bank 117 write after read (WAR) hazards
pcm_bank_117_num_write_after_read 0

#Number of PCM bank 117 write after write (WAW) hazards
pcm_bank_117_num_write_after_write 0

#Number of cycles PCM bank 117 requests wait for lower priority requests
pcm_bank_117_wait_lower_priority_time 0

#Number of cycles PCM bank 117 requests wait for same priority requests
pcm_bank_117_wait_same_priority_time 0

#Number of cycles PCM bank 117 requests wait for higher priority requests
pcm_bank_117_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 118 spend in the queue
pcm_bank_118_queue_time 0

#Number of cycles PCM bank 118 spends opening rows for requests
pcm_bank_118_open_time 0

#Number of cycles PCM bank 118 spends accessing rows for requests
pcm_bank_118_access_time 0

#Number of cycles PCM bank 118 spends closing rows for requests
pcm_bank_118_close_time 0

#Number of PCM bank 118 read requests
pcm_bank_118_read_requests 0

#Number of PCM bank 118 write requests
pcm_bank_118_write_requests 0

#Number of cyclesPCM bank 118 read requests wait in the queue
pcm_bank_118_read_queue_time 0

#Number of cyclesPCM bank 118 write requests wait in the queue
pcm_bank_118_write_queue_time 0

#Total number of cycles of PCM bank 118 read requests
pcm_bank_118_read_total_time 0

#Total number of cycles of PCM bank 118 write requests
pcm_bank_118_write_total_time 0

#Number of PCM bank 118 row buffer hits
pcm_bank_118_row_buffer_hits 0

#Number of PCM bank 118 row buffer misses
pcm_bank_118_row_buffer_misses 0

#Number of PCM bank 118 opens
pcm_bank_118_num_opens 0

#Number of PCM bank 118 accesses
pcm_bank_118_num_accesses 0

#Number of PCM bank 118 closes
pcm_bank_118_num_closes 0

#Number of PCM bank 118 read after read (RAR) hazards
pcm_bank_118_num_read_after_read 0

#Number of PCM bank 118 read after write (RAW) hazards
pcm_bank_118_num_read_after_write 0

#Number of PCM bank 118 write after read (WAR) hazards
pcm_bank_118_num_write_after_read 0

#Number of PCM bank 118 write after write (WAW) hazards
pcm_bank_118_num_write_after_write 0

#Number of cycles PCM bank 118 requests wait for lower priority requests
pcm_bank_118_wait_lower_priority_time 0

#Number of cycles PCM bank 118 requests wait for same priority requests
pcm_bank_118_wait_same_priority_time 0

#Number of cycles PCM bank 118 requests wait for higher priority requests
pcm_bank_118_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 119 spend in the queue
pcm_bank_119_queue_time 0

#Number of cycles PCM bank 119 spends opening rows for requests
pcm_bank_119_open_time 0

#Number of cycles PCM bank 119 spends accessing rows for requests
pcm_bank_119_access_time 0

#Number of cycles PCM bank 119 spends closing rows for requests
pcm_bank_119_close_time 0

#Number of PCM bank 119 read requests
pcm_bank_119_read_requests 0

#Number of PCM bank 119 write requests
pcm_bank_119_write_requests 0

#Number of cyclesPCM bank 119 read requests wait in the queue
pcm_bank_119_read_queue_time 0

#Number of cyclesPCM bank 119 write requests wait in the queue
pcm_bank_119_write_queue_time 0

#Total number of cycles of PCM bank 119 read requests
pcm_bank_119_read_total_time 0

#Total number of cycles of PCM bank 119 write requests
pcm_bank_119_write_total_time 0

#Number of PCM bank 119 row buffer hits
pcm_bank_119_row_buffer_hits 0

#Number of PCM bank 119 row buffer misses
pcm_bank_119_row_buffer_misses 0

#Number of PCM bank 119 opens
pcm_bank_119_num_opens 0

#Number of PCM bank 119 accesses
pcm_bank_119_num_accesses 0

#Number of PCM bank 119 closes
pcm_bank_119_num_closes 0

#Number of PCM bank 119 read after read (RAR) hazards
pcm_bank_119_num_read_after_read 0

#Number of PCM bank 119 read after write (RAW) hazards
pcm_bank_119_num_read_after_write 0

#Number of PCM bank 119 write after read (WAR) hazards
pcm_bank_119_num_write_after_read 0

#Number of PCM bank 119 write after write (WAW) hazards
pcm_bank_119_num_write_after_write 0

#Number of cycles PCM bank 119 requests wait for lower priority requests
pcm_bank_119_wait_lower_priority_time 0

#Number of cycles PCM bank 119 requests wait for same priority requests
pcm_bank_119_wait_same_priority_time 0

#Number of cycles PCM bank 119 requests wait for higher priority requests
pcm_bank_119_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 120 spend in the queue
pcm_bank_120_queue_time 0

#Number of cycles PCM bank 120 spends opening rows for requests
pcm_bank_120_open_time 0

#Number of cycles PCM bank 120 spends accessing rows for requests
pcm_bank_120_access_time 0

#Number of cycles PCM bank 120 spends closing rows for requests
pcm_bank_120_close_time 0

#Number of PCM bank 120 read requests
pcm_bank_120_read_requests 0

#Number of PCM bank 120 write requests
pcm_bank_120_write_requests 0

#Number of cyclesPCM bank 120 read requests wait in the queue
pcm_bank_120_read_queue_time 0

#Number of cyclesPCM bank 120 write requests wait in the queue
pcm_bank_120_write_queue_time 0

#Total number of cycles of PCM bank 120 read requests
pcm_bank_120_read_total_time 0

#Total number of cycles of PCM bank 120 write requests
pcm_bank_120_write_total_time 0

#Number of PCM bank 120 row buffer hits
pcm_bank_120_row_buffer_hits 0

#Number of PCM bank 120 row buffer misses
pcm_bank_120_row_buffer_misses 0

#Number of PCM bank 120 opens
pcm_bank_120_num_opens 0

#Number of PCM bank 120 accesses
pcm_bank_120_num_accesses 0

#Number of PCM bank 120 closes
pcm_bank_120_num_closes 0

#Number of PCM bank 120 read after read (RAR) hazards
pcm_bank_120_num_read_after_read 0

#Number of PCM bank 120 read after write (RAW) hazards
pcm_bank_120_num_read_after_write 0

#Number of PCM bank 120 write after read (WAR) hazards
pcm_bank_120_num_write_after_read 0

#Number of PCM bank 120 write after write (WAW) hazards
pcm_bank_120_num_write_after_write 0

#Number of cycles PCM bank 120 requests wait for lower priority requests
pcm_bank_120_wait_lower_priority_time 0

#Number of cycles PCM bank 120 requests wait for same priority requests
pcm_bank_120_wait_same_priority_time 0

#Number of cycles PCM bank 120 requests wait for higher priority requests
pcm_bank_120_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 121 spend in the queue
pcm_bank_121_queue_time 0

#Number of cycles PCM bank 121 spends opening rows for requests
pcm_bank_121_open_time 0

#Number of cycles PCM bank 121 spends accessing rows for requests
pcm_bank_121_access_time 0

#Number of cycles PCM bank 121 spends closing rows for requests
pcm_bank_121_close_time 0

#Number of PCM bank 121 read requests
pcm_bank_121_read_requests 0

#Number of PCM bank 121 write requests
pcm_bank_121_write_requests 0

#Number of cyclesPCM bank 121 read requests wait in the queue
pcm_bank_121_read_queue_time 0

#Number of cyclesPCM bank 121 write requests wait in the queue
pcm_bank_121_write_queue_time 0

#Total number of cycles of PCM bank 121 read requests
pcm_bank_121_read_total_time 0

#Total number of cycles of PCM bank 121 write requests
pcm_bank_121_write_total_time 0

#Number of PCM bank 121 row buffer hits
pcm_bank_121_row_buffer_hits 0

#Number of PCM bank 121 row buffer misses
pcm_bank_121_row_buffer_misses 0

#Number of PCM bank 121 opens
pcm_bank_121_num_opens 0

#Number of PCM bank 121 accesses
pcm_bank_121_num_accesses 0

#Number of PCM bank 121 closes
pcm_bank_121_num_closes 0

#Number of PCM bank 121 read after read (RAR) hazards
pcm_bank_121_num_read_after_read 0

#Number of PCM bank 121 read after write (RAW) hazards
pcm_bank_121_num_read_after_write 0

#Number of PCM bank 121 write after read (WAR) hazards
pcm_bank_121_num_write_after_read 0

#Number of PCM bank 121 write after write (WAW) hazards
pcm_bank_121_num_write_after_write 0

#Number of cycles PCM bank 121 requests wait for lower priority requests
pcm_bank_121_wait_lower_priority_time 0

#Number of cycles PCM bank 121 requests wait for same priority requests
pcm_bank_121_wait_same_priority_time 0

#Number of cycles PCM bank 121 requests wait for higher priority requests
pcm_bank_121_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 122 spend in the queue
pcm_bank_122_queue_time 0

#Number of cycles PCM bank 122 spends opening rows for requests
pcm_bank_122_open_time 0

#Number of cycles PCM bank 122 spends accessing rows for requests
pcm_bank_122_access_time 0

#Number of cycles PCM bank 122 spends closing rows for requests
pcm_bank_122_close_time 0

#Number of PCM bank 122 read requests
pcm_bank_122_read_requests 0

#Number of PCM bank 122 write requests
pcm_bank_122_write_requests 0

#Number of cyclesPCM bank 122 read requests wait in the queue
pcm_bank_122_read_queue_time 0

#Number of cyclesPCM bank 122 write requests wait in the queue
pcm_bank_122_write_queue_time 0

#Total number of cycles of PCM bank 122 read requests
pcm_bank_122_read_total_time 0

#Total number of cycles of PCM bank 122 write requests
pcm_bank_122_write_total_time 0

#Number of PCM bank 122 row buffer hits
pcm_bank_122_row_buffer_hits 0

#Number of PCM bank 122 row buffer misses
pcm_bank_122_row_buffer_misses 0

#Number of PCM bank 122 opens
pcm_bank_122_num_opens 0

#Number of PCM bank 122 accesses
pcm_bank_122_num_accesses 0

#Number of PCM bank 122 closes
pcm_bank_122_num_closes 0

#Number of PCM bank 122 read after read (RAR) hazards
pcm_bank_122_num_read_after_read 0

#Number of PCM bank 122 read after write (RAW) hazards
pcm_bank_122_num_read_after_write 0

#Number of PCM bank 122 write after read (WAR) hazards
pcm_bank_122_num_write_after_read 0

#Number of PCM bank 122 write after write (WAW) hazards
pcm_bank_122_num_write_after_write 0

#Number of cycles PCM bank 122 requests wait for lower priority requests
pcm_bank_122_wait_lower_priority_time 0

#Number of cycles PCM bank 122 requests wait for same priority requests
pcm_bank_122_wait_same_priority_time 0

#Number of cycles PCM bank 122 requests wait for higher priority requests
pcm_bank_122_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 123 spend in the queue
pcm_bank_123_queue_time 0

#Number of cycles PCM bank 123 spends opening rows for requests
pcm_bank_123_open_time 0

#Number of cycles PCM bank 123 spends accessing rows for requests
pcm_bank_123_access_time 0

#Number of cycles PCM bank 123 spends closing rows for requests
pcm_bank_123_close_time 0

#Number of PCM bank 123 read requests
pcm_bank_123_read_requests 0

#Number of PCM bank 123 write requests
pcm_bank_123_write_requests 0

#Number of cyclesPCM bank 123 read requests wait in the queue
pcm_bank_123_read_queue_time 0

#Number of cyclesPCM bank 123 write requests wait in the queue
pcm_bank_123_write_queue_time 0

#Total number of cycles of PCM bank 123 read requests
pcm_bank_123_read_total_time 0

#Total number of cycles of PCM bank 123 write requests
pcm_bank_123_write_total_time 0

#Number of PCM bank 123 row buffer hits
pcm_bank_123_row_buffer_hits 0

#Number of PCM bank 123 row buffer misses
pcm_bank_123_row_buffer_misses 0

#Number of PCM bank 123 opens
pcm_bank_123_num_opens 0

#Number of PCM bank 123 accesses
pcm_bank_123_num_accesses 0

#Number of PCM bank 123 closes
pcm_bank_123_num_closes 0

#Number of PCM bank 123 read after read (RAR) hazards
pcm_bank_123_num_read_after_read 0

#Number of PCM bank 123 read after write (RAW) hazards
pcm_bank_123_num_read_after_write 0

#Number of PCM bank 123 write after read (WAR) hazards
pcm_bank_123_num_write_after_read 0

#Number of PCM bank 123 write after write (WAW) hazards
pcm_bank_123_num_write_after_write 0

#Number of cycles PCM bank 123 requests wait for lower priority requests
pcm_bank_123_wait_lower_priority_time 0

#Number of cycles PCM bank 123 requests wait for same priority requests
pcm_bank_123_wait_same_priority_time 0

#Number of cycles PCM bank 123 requests wait for higher priority requests
pcm_bank_123_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 124 spend in the queue
pcm_bank_124_queue_time 0

#Number of cycles PCM bank 124 spends opening rows for requests
pcm_bank_124_open_time 0

#Number of cycles PCM bank 124 spends accessing rows for requests
pcm_bank_124_access_time 0

#Number of cycles PCM bank 124 spends closing rows for requests
pcm_bank_124_close_time 0

#Number of PCM bank 124 read requests
pcm_bank_124_read_requests 0

#Number of PCM bank 124 write requests
pcm_bank_124_write_requests 0

#Number of cyclesPCM bank 124 read requests wait in the queue
pcm_bank_124_read_queue_time 0

#Number of cyclesPCM bank 124 write requests wait in the queue
pcm_bank_124_write_queue_time 0

#Total number of cycles of PCM bank 124 read requests
pcm_bank_124_read_total_time 0

#Total number of cycles of PCM bank 124 write requests
pcm_bank_124_write_total_time 0

#Number of PCM bank 124 row buffer hits
pcm_bank_124_row_buffer_hits 0

#Number of PCM bank 124 row buffer misses
pcm_bank_124_row_buffer_misses 0

#Number of PCM bank 124 opens
pcm_bank_124_num_opens 0

#Number of PCM bank 124 accesses
pcm_bank_124_num_accesses 0

#Number of PCM bank 124 closes
pcm_bank_124_num_closes 0

#Number of PCM bank 124 read after read (RAR) hazards
pcm_bank_124_num_read_after_read 0

#Number of PCM bank 124 read after write (RAW) hazards
pcm_bank_124_num_read_after_write 0

#Number of PCM bank 124 write after read (WAR) hazards
pcm_bank_124_num_write_after_read 0

#Number of PCM bank 124 write after write (WAW) hazards
pcm_bank_124_num_write_after_write 0

#Number of cycles PCM bank 124 requests wait for lower priority requests
pcm_bank_124_wait_lower_priority_time 0

#Number of cycles PCM bank 124 requests wait for same priority requests
pcm_bank_124_wait_same_priority_time 0

#Number of cycles PCM bank 124 requests wait for higher priority requests
pcm_bank_124_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 125 spend in the queue
pcm_bank_125_queue_time 0

#Number of cycles PCM bank 125 spends opening rows for requests
pcm_bank_125_open_time 0

#Number of cycles PCM bank 125 spends accessing rows for requests
pcm_bank_125_access_time 0

#Number of cycles PCM bank 125 spends closing rows for requests
pcm_bank_125_close_time 0

#Number of PCM bank 125 read requests
pcm_bank_125_read_requests 0

#Number of PCM bank 125 write requests
pcm_bank_125_write_requests 0

#Number of cyclesPCM bank 125 read requests wait in the queue
pcm_bank_125_read_queue_time 0

#Number of cyclesPCM bank 125 write requests wait in the queue
pcm_bank_125_write_queue_time 0

#Total number of cycles of PCM bank 125 read requests
pcm_bank_125_read_total_time 0

#Total number of cycles of PCM bank 125 write requests
pcm_bank_125_write_total_time 0

#Number of PCM bank 125 row buffer hits
pcm_bank_125_row_buffer_hits 0

#Number of PCM bank 125 row buffer misses
pcm_bank_125_row_buffer_misses 0

#Number of PCM bank 125 opens
pcm_bank_125_num_opens 0

#Number of PCM bank 125 accesses
pcm_bank_125_num_accesses 0

#Number of PCM bank 125 closes
pcm_bank_125_num_closes 0

#Number of PCM bank 125 read after read (RAR) hazards
pcm_bank_125_num_read_after_read 0

#Number of PCM bank 125 read after write (RAW) hazards
pcm_bank_125_num_read_after_write 0

#Number of PCM bank 125 write after read (WAR) hazards
pcm_bank_125_num_write_after_read 0

#Number of PCM bank 125 write after write (WAW) hazards
pcm_bank_125_num_write_after_write 0

#Number of cycles PCM bank 125 requests wait for lower priority requests
pcm_bank_125_wait_lower_priority_time 0

#Number of cycles PCM bank 125 requests wait for same priority requests
pcm_bank_125_wait_same_priority_time 0

#Number of cycles PCM bank 125 requests wait for higher priority requests
pcm_bank_125_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 126 spend in the queue
pcm_bank_126_queue_time 0

#Number of cycles PCM bank 126 spends opening rows for requests
pcm_bank_126_open_time 0

#Number of cycles PCM bank 126 spends accessing rows for requests
pcm_bank_126_access_time 0

#Number of cycles PCM bank 126 spends closing rows for requests
pcm_bank_126_close_time 0

#Number of PCM bank 126 read requests
pcm_bank_126_read_requests 0

#Number of PCM bank 126 write requests
pcm_bank_126_write_requests 0

#Number of cyclesPCM bank 126 read requests wait in the queue
pcm_bank_126_read_queue_time 0

#Number of cyclesPCM bank 126 write requests wait in the queue
pcm_bank_126_write_queue_time 0

#Total number of cycles of PCM bank 126 read requests
pcm_bank_126_read_total_time 0

#Total number of cycles of PCM bank 126 write requests
pcm_bank_126_write_total_time 0

#Number of PCM bank 126 row buffer hits
pcm_bank_126_row_buffer_hits 0

#Number of PCM bank 126 row buffer misses
pcm_bank_126_row_buffer_misses 0

#Number of PCM bank 126 opens
pcm_bank_126_num_opens 0

#Number of PCM bank 126 accesses
pcm_bank_126_num_accesses 0

#Number of PCM bank 126 closes
pcm_bank_126_num_closes 0

#Number of PCM bank 126 read after read (RAR) hazards
pcm_bank_126_num_read_after_read 0

#Number of PCM bank 126 read after write (RAW) hazards
pcm_bank_126_num_read_after_write 0

#Number of PCM bank 126 write after read (WAR) hazards
pcm_bank_126_num_write_after_read 0

#Number of PCM bank 126 write after write (WAW) hazards
pcm_bank_126_num_write_after_write 0

#Number of cycles PCM bank 126 requests wait for lower priority requests
pcm_bank_126_wait_lower_priority_time 0

#Number of cycles PCM bank 126 requests wait for same priority requests
pcm_bank_126_wait_same_priority_time 0

#Number of cycles PCM bank 126 requests wait for higher priority requests
pcm_bank_126_wait_higher_priority_time 0

#Number of cycles requests for PCM bank 127 spend in the queue
pcm_bank_127_queue_time 0

#Number of cycles PCM bank 127 spends opening rows for requests
pcm_bank_127_open_time 0

#Number of cycles PCM bank 127 spends accessing rows for requests
pcm_bank_127_access_time 0

#Number of cycles PCM bank 127 spends closing rows for requests
pcm_bank_127_close_time 0

#Number of PCM bank 127 read requests
pcm_bank_127_read_requests 0

#Number of PCM bank 127 write requests
pcm_bank_127_write_requests 0

#Number of cyclesPCM bank 127 read requests wait in the queue
pcm_bank_127_read_queue_time 0

#Number of cyclesPCM bank 127 write requests wait in the queue
pcm_bank_127_write_queue_time 0

#Total number of cycles of PCM bank 127 read requests
pcm_bank_127_read_total_time 0

#Total number of cycles of PCM bank 127 write requests
pcm_bank_127_write_total_time 0

#Number of PCM bank 127 row buffer hits
pcm_bank_127_row_buffer_hits 0

#Number of PCM bank 127 row buffer misses
pcm_bank_127_row_buffer_misses 0

#Number of PCM bank 127 opens
pcm_bank_127_num_opens 0

#Number of PCM bank 127 accesses
pcm_bank_127_num_accesses 0

#Number of PCM bank 127 closes
pcm_bank_127_num_closes 0

#Number of PCM bank 127 read after read (RAR) hazards
pcm_bank_127_num_read_after_read 0

#Number of PCM bank 127 read after write (RAW) hazards
pcm_bank_127_num_read_after_write 0

#Number of PCM bank 127 write after read (WAR) hazards
pcm_bank_127_num_write_after_read 0

#Number of PCM bank 127 write after write (WAW) hazards
pcm_bank_127_num_write_after_write 0

#Number of cycles PCM bank 127 requests wait for lower priority requests
pcm_bank_127_wait_lower_priority_time 0

#Number of cycles PCM bank 127 requests wait for same priority requests
pcm_bank_127_wait_same_priority_time 0

#Number of cycles PCM bank 127 requests wait for higher priority requests
pcm_bank_127_wait_higher_priority_time 0

#Number of DRAM reads seen by the Hybrid Memory
hybrid_memory_dram_reads 81

#Number of DRAM writes seen by the Hybrid Memory
hybrid_memory_dram_writes 64

#Number of DRAM accesses seen by the Hybrid Memory
hybrid_memory_dram_accesses 145

#Number of PCM reads seen by the Hybrid Memory
hybrid_memory_pcm_reads 9

#Number of PCM writes seen by the Hybrid Memory
hybrid_memory_pcm_writes 64

#Number of PCM accesses seen by the Hybrid Memory
hybrid_memory_pcm_accesses 73

#Number of total reads seen by the Hybrid Memory
hybrid_memory_total_reads 90

#Number of total writes seen by the Hybrid Memory
hybrid_memory_total_writes 128

#Number of total accesses seen by the Hybrid Memory
hybrid_memory_total_accesses 218

#Fraction of DRAM reads seen by the Hybrid Memory
hybrid_memory_fraction_dram_reads 0.90

#Fraction of PCM reads seen by the Hybrid Memory
hybrid_memory_fraction_pcm_reads 0.10

#Fraction of DRAM writes seen by the Hybrid Memory
hybrid_memory_fraction_dram_writes 0.50

#Fraction of PCM writes seen by the Hybrid Memory
hybrid_memory_fraction_pcm_writes 0.50

#Fraction of DRAM accesses seen by the Hybrid Memory
hybrid_memory_fraction_dram_accesses 0.67

#Fraction of PCM accesses seen by the Hybrid Memory
hybrid_memory_fraction_pcm_accesses 0.33

#Number of reads to the Hybrid Memory served by DRAM
hybrid_memory_reads_from_dram 81

#Number of reads to the Hybrid Memory served by PCM
hybrid_memory_reads_from_pcm 9

#Number of reads to the Hybrid Memory served by the buffer
hybrid_memory_reads_from_buffer 0

#Number of writes to the Hybrid Memory served by DRAM
hybrid_memory_writes_to_dram 64

#Number of writes to the Hybrid Memory served by PCM
hybrid_memory_writes_to_pcm 64

#Number of writes to the Hybrid Memory served by the buffer
hybrid_memory_writes_to_buffer 0

#Number of cycles servicing DRAM reads as seen by the Hybrid Memory
hybrid_memory_dram_read_time 19816

#Number of cycles servicing DRAM writes as seen by the Hybrid Memory
hybrid_memory_dram_write_time 0

#Number of cycles servicing DRAM accesses as seen by the Hybrid Memory
hybrid_memory_dram_access_time 19816

#Number of cycles servicing PCM reads as seen by the Hybrid Memory
hybrid_memory_pcm_read_time 2790

#Number of cycles servicing PCM writes as seen by the Hybrid Memory
hybrid_memory_pcm_write_time 0

#Number of cycles servicing PCM accesses as seen by the Hybrid Memory
hybrid_memory_pcm_access_time 2790

#Number of cycles servicing all accesses as seen by the Hybrid Memory
hybrid_memory_total_access_time 22606

#Average number of cycles servicing DRAM reads as seen by the Hybrid Memory
hybrid_memory_avg_dram_read_time 244.64

#Average number of cycles servicing DRAM writes as seen by the Hybrid Memory
hybrid_memory_avg_dram_write_time 0.00

#Average number of cycles servicing DRAM accesses as seen by the Hybrid Memory
hybrid_memory_avg_dram_access_time 136.66

#Average number of cycles servicing PCM reads as seen by the Hybrid Memory
hybrid_memory_avg_pcm_read_time 310.00

#Average number of cycles servicing PCM writes as seen by the Hybrid Memory
hybrid_memory_avg_pcm_write_time 0.00

#Average number of cycles servicing PCM accesses as seen by the Hybrid Memory
hybrid_memory_avg_pcm_access_time 38.22

#Average number of cycles servicing all accesses as seen by the Hybrid Memory
hybrid_memory_avg_access_time 103.70

#Number of DRAM reads due to page copies by the Hybrid Memory
hybrid_memory_dram_copy_reads 64

#Number of DRAM writes due to page copies by the Hybrid Memory
hybrid_memory_dram_copy_writes 0

#Number of DRAM accesses due to page copies by the Hybrid Memory
hybrid_memory_dram_copy_accesses 64

#Number of PCM reads due to page copies by the Hybrid Memory
hybrid_memory_pcm_copy_reads 0

#Number of PCM writes due to page copies by the Hybrid Memory
hybrid_memory_pcm_copy_writes 64

#Number of PCM accesses due to page copies by the Hybrid Memory
hybrid_memory_pcm_copy_accesses 64

#Number of total accesses due to page copies by the Hybrid Memory
hybrid_memory_total_copy_accesses 128

#Number of cycles servicing DRAM reads due to page copies by the Hybrid Memory
hybrid_memory_dram_copy_read_time 16605

#Number of cycles servicing DRAM writes due to page copies by the Hybrid Memory
hybrid_memory_dram_copy_write_time 0

#Number of cycles servicing DRAM accesses due to page copies by the Hybrid Memory
hybrid_memory_dram_copy_access_time 16605

#Number of cycles servicing PCM reads due to page copies by the Hybrid Memory
hybrid_memory_pcm_copy_read_time 0

#Number of cycles servicing PCM writes due to page copies by the Hybrid Memory
hybrid_memory_pcm_copy_write_time 0

#Number of cycles servicing PCM accesses due to page copies by the Hybrid Memory
hybrid_memory_pcm_copy_access_time 0

#Number of cycles servicing all accesses due to page copies by the Hybrid Memory
hybrid_memory_total_copy_access_time 16605

#Average number of cycles servicing DRAM reads due to page copies by the Hybrid Memory
hybrid_memory_avg_dram_copy_read_time 259.45

#Average number of cycles servicing DRAM writes due to page copies by the Hybrid Memory
hybrid_memory_avg_dram_copy_write_time -nan

#Average number of cycles servicing DRAM accesses due to page copies by the Hybrid Memory
hybrid_memory_avg_dram_copy_access_time 259.45

#Average number of cycles servicing PCM reads due to page copies by the Hybrid Memory
hybrid_memory_avg_pcm_copy_read_time -nan

#Average number of cycles servicing PCM writes due to page copies by the Hybrid Memory
hybrid_memory_avg_pcm_copy_write_time 0.00

#Average number of cycles servicing PCM accesses due to page copies by the Hybrid Memory
hybrid_memory_avg_pcm_copy_access_time 0.00

#Average number of cycles servicing all accesses due to page copies by the Hybrid Memory
hybrid_memory_avg_access_copy_time 129.73

#Number of DRAM pages copied by Hybrid Memory
hybrid_memory_dram_page_copies 0

#Number of PCM pages copied by Hybrid Memory
hybrid_memory_pcm_page_copies 1

#Number of cycles copying DRAM pages by Hybrid Memory
hybrid_memory_dram_page_copy_time 0

#Number of cycles copying PCM pages by Hybrid Memory
hybrid_memory_pcm_page_copy_time 1219

#Number of DRAM reads seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_dram_reads_per_pid_size 1

#Number of DRAM reads seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_dram_reads_per_pid_size_0 81

#Number of DRAM writes seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_dram_writes_per_pid_size 1

#Number of DRAM writes seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_dram_writes_per_pid_size_0 64

#Number of DRAM accesses seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_dram_accesses_per_pid_size 1

#Number of DRAM accesses seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_dram_accesses_per_pid_size_0 145

#Number of PCM reads seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_pcm_reads_per_pid_size 1

#Number of PCM reads seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_pcm_reads_per_pid_size_0 9

#Number of PCM writes seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_pcm_writes_per_pid_size 1

#Number of PCM writes seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_pcm_writes_per_pid_size_0 0

#Number of PCM accesses seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_pcm_accesses_per_pid_size 1

#Number of PCM accesses seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_pcm_accesses_per_pid_size_0 9

#Number of total reads seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_total_reads_per_pid_size 1

#Number of total reads seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_total_reads_per_pid_size_0 90

#Number of total writes seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_total_writes_per_pid_size 1

#Number of total writes seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_total_writes_per_pid_size_0 64

#Number of total accesses seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_total_accesses_per_pid_size 1

#Number of total accesses seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_total_accesses_per_pid_size_0 154

#Fraction of DRAM reads seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_fraction_dram_reads_per_pid_size 1

#Fraction of DRAM reads seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_fraction_dram_reads_per_pid_size_0 0.90

#Fraction of PCM reads seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_fraction_pcm_reads_per_pid_size 1

#Fraction of PCM reads seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_fraction_pcm_reads_per_pid_size_0 0.10

#Fraction of DRAM writes seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_fraction_dram_writes_per_pid_size 1

#Fraction of DRAM writes seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_fraction_dram_writes_per_pid_size_0 1.00

#Fraction of PCM writes seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_fraction_pcm_writes_per_pid_size 1

#Fraction of PCM writes seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_fraction_pcm_writes_per_pid_size_0 0.00

#Fraction of DRAM accesses seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_fraction_dram_accesses_per_pid_size 1

#Fraction of DRAM accesses seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_fraction_dram_accesses_per_pid_size_0 0.94

#Fraction of PCM accesses seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_fraction_pcm_accesses_per_pid_size 1

#Fraction of PCM accesses seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_fraction_pcm_accesses_per_pid_size_0 0.06

#Number of cycles servicing DRAM reads as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_dram_read_time_per_pid_size 1

#Number of cycles servicing DRAM reads as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_dram_read_time_per_pid_size_0 19816

#Number of cycles servicing DRAM writes as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_dram_write_time_per_pid_size 1

#Number of cycles servicing DRAM writes as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_dram_write_time_per_pid_size_0 0

#Number of cycles servicing DRAM accesses as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_dram_access_time_per_pid_size 1

#Number of cycles servicing DRAM accesses as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_dram_access_time_per_pid_size_0 19816

#Number of cycles servicing DRAM reads as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_pcm_read_time_per_pid_size 1

#Number of cycles servicing DRAM reads as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_pcm_read_time_per_pid_size_0 2790

#Number of cycles servicing DRAM writes as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_pcm_write_time_per_pid_size 1

#Number of cycles servicing DRAM writes as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_pcm_write_time_per_pid_size_0 0

#Number of cycles servicing DRAM accesses as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_pcm_access_time_per_pid_size 1

#Number of cycles servicing DRAM accesses as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_pcm_access_time_per_pid_size_0 2790

#Number of cycles servicing all accesses as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_total_access_time_per_pid_size 1

#Number of cycles servicing all accesses as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_total_access_time_per_pid_size_0 22606

#Average number of cycles servicing DRAM reads as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_avg_dram_read_time_per_pid_size 1

#Average number of cycles servicing DRAM reads as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_avg_dram_read_time_per_pid_size_0 244.64

#Average number of cycles servicing DRAM writes as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_avg_dram_write_time_per_pid_size 1

#Average number of cycles servicing DRAM writes as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_avg_dram_write_time_per_pid_size_0 0.00

#Average number of cycles servicing DRAM accesses as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_avg_dram_access_time_per_pid_size 1

#Average number of cycles servicing DRAM accesses as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_avg_dram_access_time_per_pid_size_0 136.66

#Average number of cycles servicing PCM reads as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_avg_pcm_read_time_per_pid_size 1

#Average number of cycles servicing PCM reads as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_avg_pcm_read_time_per_pid_size_0 310.00

#Average number of cycles servicing PCM writes as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_avg_pcm_write_time_per_pid_size 1

#Average number of cycles servicing PCM writes as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_avg_pcm_write_time_per_pid_size_0 -nan

#Average number of cycles servicing PCM accesses as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_avg_pcm_access_time_per_pid_size 1

#Average number of cycles servicing PCM accesses as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_avg_pcm_access_time_per_pid_size_0 310.00

#Average number of cycles servicing all accesses as seen by the Hybrid Memory from process (number of generated statistics)
hybrid_memory_avg_access_time_per_pid_size 1

#Average number of cycles servicing all accesses as seen by the Hybrid Memory from process (number of generated statistics) 0
hybrid_memory_avg_access_time_per_pid_size_0 146.79

#Number of Shared L2 Cache hits
L2_all_hits 0

#Number of Shared L2 Cache misses without eviction
L2_misses_without_eviction 90

#Number of Shared L2 Cache misses with eviction
L2_misses_with_eviction 0

#Number of Shared L2 Cache misses with writeback
L2_misses_with_writeback 0

#Number of Shared L2 Cache misses without free block
L2_misses_without_free_block 0

#Number of Shared L2 Cache data load hits
L2_data_load_hits 0

#Number of Shared L2 Cache data load misses
L2_data_load_misses 60

#Number of Shared L2 Cache data store hits
L2_data_store_hits 0

#Number of Shared L2 Cache data store misses
L2_data_store_misses 0

#Number of Shared L2 Cache instruction load hits
L2_instr_load_hits 0

#Number of Shared L2 Cache instruction load misses
L2_instr_load_misses 30

#Number of Shared L2 Cache flushes without eviction
L2_flushes_without_eviction 126

#Number of Shared L2 Cache flushes with eviction
L2_flushes_with_eviction 2

#Number of Shared L2 Cache flushes with writeback
L2_flushes_with_writeback 0

#Number of Shared L2 Cache tag change hits
L2_tag_change_hits 0

#Number of Shared L2 Cache tag change misses
L2_tag_change_misses 0

#Number of Shared L2 Cache misses
L2_all_misses 90

#Number of Shared L2 Cache accesses
L2_accesses 90

#Shared L2 Cache hit rate
L2_hit_rate 0.00

#Shared L2 Cache miss rate
L2_miss_rate 1.00

#Number of cycles of Shared L2 Cache read requests
L2_read_access_time 22606

#Number of Shared L2 Cache misses from flush
L2_misses_from_flush 0

#Number of Shared L2 Cache writebacks from flush
L2_writebacks_from_flush 0

#Number of full DRAM migrations
manager_dram_full_migrations 0

#Number of partial DRAM migrations (rolledback)
manager_dram_partial_migrations 0

#Number of DRAM migrations (full and partial)
manager_dram_migrations 0

#Number of full PCM migrations
manager_pcm_full_migrations 1

#Number of partial PCM migrations (result of rollback)
manager_pcm_partial_migrations 0

#Number of PCM migrations (full and partial)
manager_pcm_migrations 1

#Total number of full migrations
manager_total_full_migrations 1

#Total number of partial migrations (each rollbacks is counted twice)
manager_total_partial_migrations 0

#Total number of migrations
manager_total_migrations 1

#Sum of the number of ongoing migration each time a new migration starts
manager_migration_entries_sum 1

#Number of migrations started
manager_migration_entries_count 1

#Average number of ongoing migrations
manager_avg_migration_entries 1.00

#Number of clean flushed blocks
manager_clean_flushed_blocks 0

#Number of dirty flushed blocks
manager_dirty_flushed_blocks 128

#Number of tag changes
manager_tag_changes 0

#Number of cycles migrating pages to DRAM (full migration)
manager_dram_full_migration_time 0

#Number of cycles migrating pages to DRAM (partial migration)
manager_dram_partial_migration_time 0

#Number of cycles migrating pages to DRAM (full and partial migration)
manager_dram_migration_time 0

#Number of cycles migrating pages to PCM (full migration)
manager_pcm_full_migration_time 1780

#Number of cycles migrating pages to PCM (partial migration)
manager_pcm_partial_migration_time 0

#Number of cycles migrating pages to PCM (full and partial migration)
manager_pcm_migration_time 1780

#Number of cycles migrating pages (full migration)
manager_full_migration_time 1780

#Number of cycles migrating pages (partial migration)
manager_partial_migration_time 0

#Total number of cycles migrating all pages (full and partial migration)
manager_total_migration_time 1780

#Number of cycles flushing the cache before migrations to DRAM
manager_dram_flush_before_time 0

#Number of cycles flushing the cache before migrations to PCM
manager_pcm_flush_before_time 280

#Number of cycles flushing the cache before migrations
manager_flush_before_time 280

#Number of cycles flushing the cache after migrations to DRAM
manager_dram_flush_after_time 0

#Number of cycles flushing the cache after migrations to PCM
manager_pcm_flush_after_time 280

#Number of cycles flushing the cache after migrations
manager_flush_after_time 280

#Number of cycles flushing the cache due to migrations to DRAM
manager_dram_flush_time 0

#Number of cycles flushing the cache due to migrations to PCM
manager_pcm_flush_time 560

#Total number of cycles flushing the cache
manager_total_flush_time 560

#Number of cycles copying pages during migrations to DRAM
manager_dram_copy_time 0

#Number of cycles copying pages during migrations to PCM
manager_pcm_copy_time 1219

#Number of cycles copying pages during migrations
manager_copy_time 1219

#Number of cycles the migration policy (demotion) is idle
manager_idle_time 10000

#Average number of cycles per migration to DRAM
manager_avg_dram_migration_time -nan

#Average number of cycles per migration to PCM
manager_avg_pcm_migration_time 1780.00

#Average number of cycles per migration
manager_avg_migration_time 1780.00

#Average number of cycles flushing the cache before each migration to DRAM
manager_avg_dram_flush_before_time -nan

#Average number of cycles flushing the cache before each migration to PCM
manager_avg_pcm_flush_before_time 280.00

#Average number of cycles flushing the cache per migration
manager_avg_flush_before_time 280.00

#Average number of cycles flushing the cache after each migration to DRAM
manager_avg_dram_flush_after_time -nan

#Average number of cycles flushing the cache after each migration to PCM
manager_avg_pcm_flush_after_time 280.00

#Average number of cycles flushing the cache per migration
manager_avg_flush_after_time 280.00

#Average number of cycles flushing the cache per DRAM migration
manager_avg_dram_flush_time -nan

#Average number of cycles flushing the cache per PCM migration
manager_avg_pcm_flush_time 560.00

#Average number of cycles flushing the cache per migration
manager_avg_flush_time 560.00

#Average number of cycles copying pages per DRAM migration
manager_avg_dram_copy_time -nan

#Average number of cycles copying pages per PCM migration
manager_avg_pcm_copy_time 1219.00

#Average number of cycles copying pages per migration
manager_avg_copy_time 1219.00

#Size of DRAM memory available to the memory manager
manager_dram_memory_size 4194304

#Size of DRAM memory used by the memory manager
manager_dram_memory_size_used 28672

#Size of PCM memory available to the memory manager
manager_pcm_memory_size 34359738368

#Size of PCM memory used by the memory manager
manager_pcm_memory_size_used 12288

#Size of DRAM memory at start of simulation
manager_dram_memory_size_initial 0

#Size of PCM memory at start of simulation
manager_pcm_memory_size_initial 0

#Total size of DRAM and PCM memory at start of simulation
manager_total_memory_size_initial 0

#Size of DRAM memory used by process (number of generated statistics)
manager_dram_memory_size_per_pid_size 1

#Size of DRAM memory used by process (number of generated statistics) 0
manager_dram_memory_size_per_pid_size_0 28672

#Size of PCM memory used by process (number of generated statistics)
manager_pcm_memory_size_per_pid_size 1

#Size of PCM memory used by process (number of generated statistics) 0
manager_pcm_memory_size_per_pid_size_0 12288

#Size of total memory used by process (number of generated statistics)
manager_total_memory_size_per_pid_size 1

#Size of total memory used by process (number of generated statistics) 0
manager_total_memory_size_per_pid_size_0 40960

#Number of DRAM migrations by process (number of generated statistics)
manager_dram_migrations_per_pid_size 1

#Number of DRAM migrations by process (number of generated statistics) 0
manager_dram_migrations_per_pid_size_0 0

#Number of PCM migrations by process (number of generated statistics)
manager_pcm_migrations_per_pid_size 1

#Number of PCM migrations by process (number of generated statistics) 0
manager_pcm_migrations_per_pid_size_0 1

#Number of total migrations by process (number of generated statistics)
manager_total_migrations_per_pid_size 1

#Number of total migrations by process (number of generated statistics) 0
manager_total_migrations_per_pid_size_0 1

#Number of Instruction L1 Cache 0 hits
instr_L1_0_all_hits 292

#Number of Instruction L1 Cache 0 misses without eviction
instr_L1_0_misses_without_eviction 30

#Number of Instruction L1 Cache 0 misses with eviction
instr_L1_0_misses_with_eviction 0

#Number of Instruction L1 Cache 0 misses with writeback
instr_L1_0_misses_with_writeback 0

#Number of Instruction L1 Cache 0 misses without free block
instr_L1_0_misses_without_free_block 0

#Number of Instruction L1 Cache 0 data load hits
instr_L1_0_data_load_hits 0

#Number of Instruction L1 Cache 0 data load misses
instr_L1_0_data_load_misses 0

#Number of Instruction L1 Cache 0 data store hits
instr_L1_0_data_store_hits 0

#Number of Instruction L1 Cache 0 data store misses
instr_L1_0_data_store_misses 0

#Number of Instruction L1 Cache 0 instruction load hits
instr_L1_0_instr_load_hits 292

#Number of Instruction L1 Cache 0 instruction load misses
instr_L1_0_instr_load_misses 30

#Number of Instruction L1 Cache 0 flushes without eviction
instr_L1_0_flushes_without_eviction 126

#Number of Instruction L1 Cache 0 flushes with eviction
instr_L1_0_flushes_with_eviction 2

#Number of Instruction L1 Cache 0 flushes with writeback
instr_L1_0_flushes_with_writeback 0

#Number of Instruction L1 Cache 0 tag change hits
instr_L1_0_tag_change_hits 0

#Number of Instruction L1 Cache 0 tag change misses
instr_L1_0_tag_change_misses 0

#Number of Instruction L1 Cache 0 misses
instr_L1_0_all_misses 30

#Number of Instruction L1 Cache 0 accesses
instr_L1_0_accesses 322

#Instruction L1 Cache 0 hit rate
instr_L1_0_hit_rate 0.91

#Instruction L1 Cache 0 miss rate
instr_L1_0_miss_rate 0.09

#Number of cycles of Instruction L1 Cache 0 read requests
instr_L1_0_read_access_time 9048

#Number of Instruction L1 Cache 0 misses from flush
instr_L1_0_misses_from_flush 0

#Number of Instruction L1 Cache 0 writebacks from flush
instr_L1_0_writebacks_from_flush 0

#Number of Data L1 Cache 0 hits
data_L1_0_all_hits 82

#Number of Data L1 Cache 0 misses without eviction
data_L1_0_misses_without_eviction 60

#Number of Data L1 Cache 0 misses with eviction
data_L1_0_misses_with_eviction 0

#Number of Data L1 Cache 0 misses with writeback
data_L1_0_misses_with_writeback 0

#Number of Data L1 Cache 0 misses without free block
data_L1_0_misses_without_free_block 0

#Number of Data L1 Cache 0 data load hits
data_L1_0_data_load_hits 67

#Number of Data L1 Cache 0 data load misses
data_L1_0_data_load_misses 37

#Number of Data L1 Cache 0 data store hits
data_L1_0_data_store_hits 15

#Number of Data L1 Cache 0 data store misses
data_L1_0_data_store_misses 23

#Number of Data L1 Cache 0 instruction load hits
data_L1_0_instr_load_hits 0

#Number of Data L1 Cache 0 instruction load misses
data_L1_0_instr_load_misses 0

#Number of Data L1 Cache 0 flushes without eviction
data_L1_0_flushes_without_eviction 128

#Number of Data L1 Cache 0 flushes with eviction
data_L1_0_flushes_with_eviction 0

#Number of Data L1 Cache 0 flushes with writeback
data_L1_0_flushes_with_writeback 0

#Number of Data L1 Cache 0 tag change hits
data_L1_0_tag_change_hits 0

#Number of Data L1 Cache 0 tag change misses
data_L1_0_tag_change_misses 0

#Number of Data L1 Cache 0 misses
data_L1_0_all_misses 60

#Number of Data L1 Cache 0 accesses
data_L1_0_accesses 142

#Data L1 Cache 0 hit rate
data_L1_0_hit_rate 0.58

#Data L1 Cache 0 miss rate
data_L1_0_miss_rate 0.42

#Number of cycles of Data L1 Cache 0 read requests
data_L1_0_read_access_time 16438

#Number of Data L1 Cache 0 misses from flush
data_L1_0_misses_from_flush 0

#Number of Data L1 Cache 0 writebacks from flush
data_L1_0_writebacks_from_flush 0

#Number of CPU 0 instructions executed
cpu_0_instructions_executed 1001

#Total number of CPU 0 cycles
cpu_0_total_time 9798

#Number of CPU 0 instruction reads
cpu_0_instruction_reads 1031

#Number of CPU 0 data reads
cpu_0_data_reads 246

#Number of CPU 0 data writes
cpu_0_data_writes 82

#Number of CPU 0 sleep cycles
cpu_0_sleep_cycles 0

#Number of CPU 0 access cycles
cpu_0_access_cycles 0

#Number of CPU 0 pause cycles
cpu_0_pause_cycles 0

#CPU 0 IPC
cpu_0_ipc 0.10

#Number of cycles of CPU 0 instruction requests
cpu_0_instr_total_time 23483

#Number of cycles CPU 0 instruction requests wait for requests to the same block in the L1
cpu_0_instr_L1_wait_time 3449825

#Number of cycles CPU 0 instruction requests wait for requests to the same block in the L2
cpu_0_instr_L2_wait_time 0

#Number of cycles CPU 0 instruction requests pause at CPU
cpu_0_instr_cpu_pause_time 0

#Number of cycles CPU 0 instruction requests stall at CPU
cpu_0_instr_cpu_stall_time 0

#Number of cycles CPU 0 instruction requests spend on L1 tag access
cpu_0_instr_L1_tag_time 0

#Number of cycles CPU 0 instruction requests stall at L1
cpu_0_instr_L1_stall_time 0

#Number of cycles CPU 0 instruction requests spend on L2 tag access
cpu_0_instr_L2_tag_time 960

#Number of cycles CPU 0 instruction requests stall at L2
cpu_0_instr_L2_stall_time 0

#Number of cycles CPU 0 instruction requests wait in the DRAM queue
cpu_0_instr_dram_queue_time 0

#Number of cycles CPU 0 instruction requests wait closing DRAM banks
cpu_0_instr_dram_close_time 2806

#Number of cycles of CPU 0 instruction requests spend opening DRAM banks
cpu_0_instr_dram_open_time 650

#Number of cycles CPU 0 instruction requests spend accessing DRAM banks
cpu_0_instr_dram_access_time 700

#Number of cycles CPU 0 instruction requests wait in the DRAM bus queue
cpu_0_instr_dram_bus_queue_time 1100

#Number of cycles CPU 0 instruction requests spend in the DRAM bus
cpu_0_instr_dram_bus_time 0

#Number of cycles CPU 0 instruction requests wait in the PCM queue
cpu_0_instr_pcm_queue_time 352

#Number of cycles CPU 0 instruction requests wait closing PCM banks
cpu_0_instr_pcm_close_time 0

#Number of cycles of CPU 0 instruction requests spend opening PCM banks
cpu_0_instr_pcm_open_time 0

#Number of cycles CPU 0 instruction requests spend accessing PCM banks
cpu_0_instr_pcm_access_time 1760

#Number of cycles CPU 0 instruction requests wait in the PCM bus queue
cpu_0_instr_pcm_bus_queue_time 400

#Number of cycles CPU 0 instruction requests spend in the PCM bus
cpu_0_instr_pcm_bus_time 0

#Number of CPU 0 instruction L1 requests (ignoring reads that wait for other requests)
cpu_0_instr_L1_count 0

#Number of CPU 0 instruction L2 requests (ignoring reads that wait for other requests)
cpu_0_instr_L2_count 30

#Number of CPU 0 instruction requests that close a DRAM row
cpu_0_instr_dram_close_count 13

#Number of CPU 0 instruction requests that open a DRAM row
cpu_0_instr_dram_open_count 14

#Number of CPU 0 instruction requests that access a DRAM row
cpu_0_instr_dram_access_count 22

#Number of CPU 0 instruction requests that close a PCM row
cpu_0_instr_pcm_close_count 0

#Number of CPU 0 instruction requests that open a PCM row
cpu_0_instr_pcm_open_count 8

#Number of CPU 0 instruction requests that access a PCM row
cpu_0_instr_pcm_access_count 8

#Number of cycles of CPU 0 data requests
cpu_0_data_total_time 35644

#Number of cycles CPU 0 data requests wait for requests to the same block in the L1
cpu_0_data_L1_wait_time 86676

#Number of cycles CPU 0 data requests wait for requests to the same block in the L2
cpu_0_data_L2_wait_time 0

#Number of cycles CPU 0 data requests pause at CPU
cpu_0_data_cpu_pause_time 0

#Number of cycles CPU 0 data requests stall at CPU
cpu_0_data_cpu_stall_time 593

#Number of cycles CPU 0 data requests spend on L1 tag access
cpu_0_data_L1_tag_time 312

#Number of cycles CPU 0 data requests stall at L1
cpu_0_data_L1_stall_time 0

#Number of cycles CPU 0 data requests spend on L2 tag access
cpu_0_data_L2_tag_time 1184

#Number of cycles CPU 0 data requests stall at L2
cpu_0_data_L2_stall_time 0

#Number of cycles CPU 0 data requests wait in the DRAM queue
cpu_0_data_dram_queue_time 0

#Number of cycles CPU 0 data requests wait closing DRAM banks
cpu_0_data_dram_close_time 4753

#Number of cycles of CPU 0 data requests spend opening DRAM banks
cpu_0_data_dram_open_time 650

#Number of cycles CPU 0 data requests spend accessing DRAM banks
cpu_0_data_dram_access_time 650

#Number of cycles CPU 0 data requests wait in the DRAM bus queue
cpu_0_data_dram_bus_queue_time 1850

#Number of cycles CPU 0 data requests spend in the DRAM bus
cpu_0_data_dram_bus_time 0

#Number of cycles CPU 0 data requests wait in the PCM queue
cpu_0_data_pcm_queue_time 592

#Number of cycles CPU 0 data requests wait closing PCM banks
cpu_0_data_pcm_close_time 0

#Number of cycles of CPU 0 data requests spend opening PCM banks
cpu_0_data_pcm_open_time 0

#Number of cycles CPU 0 data requests spend accessing PCM banks
cpu_0_data_pcm_access_time 0

#Number of cycles CPU 0 data requests wait in the PCM bus queue
cpu_0_data_pcm_bus_queue_time 0

#Number of cycles CPU 0 data requests spend in the PCM bus
cpu_0_data_pcm_bus_time 0

#Number of CPU 0 data L1 requests (ignoring reads that wait for other requests)
cpu_0_data_L1_count 104

#Number of CPU 0 data L2 requests (ignoring reads that wait for other requests)
cpu_0_data_L2_count 37

#Number of CPU 0 data requests that close a DRAM row
cpu_0_data_dram_close_count 13

#Number of CPU 0 data requests that open a DRAM row
cpu_0_data_dram_open_count 13

#Number of CPU 0 data requests that access a DRAM row
cpu_0_data_dram_access_count 37

#Number of CPU 0 data requests that close a PCM row
cpu_0_data_pcm_close_count 0

#Number of CPU 0 data requests that open a PCM row
cpu_0_data_pcm_open_count 0

#Number of CPU 0 data requests that access a PCM row
cpu_0_data_pcm_access_count 0

33: hybrid_memory.access(0x109902b0, 3264, 64, read, instr, 0, L2)
33: hybrid_memory.access(0x10990630, 7168, 64, read, instr, 0, L2)
149: hybrid_memory.accessCompleted(0x109902b0, 3264, 64, read, dram)
185: hybrid_memory.access(0x1098bd50, 8704, 64, read, data, 0, L2)
315: hybrid_memory.accessCompleted(0x10990630, 7168, 64, read, dram)
349: hybrid_memory.access(0x10991430, 7232, 64, read, instr, 0, L2)
353: hybrid_memory.access(0x1099fa90, 8640, 64, read, data, 0, L2)
481: hybrid_memory.accessCompleted(0x1098bd50, 8704, 64, read, dram)
497: hybrid_memory.accessCompleted(0x1099fa90, 8640, 64, read, dram)
663: hybrid_memory.accessCompleted(0x10991430, 7232, 64, read, dram)
698: hybrid_memory.access(0x10992bb0, 7296, 64, read, instr, 0, L2)
701: hybrid_memory.access(0x1099e390, 15936, 64, read, data, 0, L2)
701: hybrid_memory.access(0x1099f830, 16384, 64, read, data, 0, L2)
701: hybrid_memory.access(0x1098bd50, 15488, 64, read, data, 0, L2)
702: hybrid_memory.access(0x1099f930, 18880, 64, read, data, 0, L2)
764: hybrid_memory.accessCompleted(0x10992bb0, 7296, 64, read, dram)
799: hybrid_memory.access(0x10993d30, 7360, 64, read, instr, 0, L2)
930: hybrid_memory.accessCompleted(0x1099e390, 15936, 64, read, dram)
946: hybrid_memory.accessCompleted(0x1098bd50, 15488, 64, read, dram)
1112: hybrid_memory.accessCompleted(0x1099f830, 16384, 64, read, dram)
1128: hybrid_memory.accessCompleted(0x1099f930, 18880, 64, read, dram)
1294: hybrid_memory.accessCompleted(0x10993d30, 7360, 64, read, dram)
1331: hybrid_memory.access(0x1099e390, 19072, 64, read, data, 0, L2)
1332: hybrid_memory.access(0x10996670, 7872, 64, read, instr, 0, L2)
1332: hybrid_memory.access(0x1098bd50, 16000, 64, read, data, 0, L2)
1333: hybrid_memory.access(0x1099f830, 18944, 64, read, data, 0, L2)
1497: hybrid_memory.accessCompleted(0x1099e390, 19072, 64, read, dram)
1513: hybrid_memory.accessCompleted(0x1099f830, 18944, 64, read, dram)
1679: hybrid_memory.accessCompleted(0x10996670, 7872, 64, read, dram)
1712: hybrid_memory.access(0x10996d70, 7936, 64, read, instr, 0, L2)
1845: hybrid_memory.accessCompleted(0x1098bd50, 16000, 64, read, dram)
2011: hybrid_memory.accessCompleted(0x10996d70, 7936, 64, read, dram)
2044: hybrid_memory.access(0x10997470, 20544, 64, read, instr, 0, L2)
2210: hybrid_memory.accessCompleted(0x10997470, 20544, 64, read, dram)
2247: hybrid_memory.access(0x1099e390, 19520, 64, read, data, 0, L2)
2249: hybrid_memory.access(0x1098bd50, 19008, 64, read, data, 0, L2)
2252: hybrid_memory.access(0x1099fec0, 16064, 64, read, data, 0, L2)
2260: hybrid_memory.access(0x778790, 16128, 64, read, data, 0, L2)
2263: hybrid_memory.access(0x109a1880, 19136, 64, read, data, 0, L2)
2268: hybrid_memory.access(0x109a1d30, 16192, 64, read, data, 0, L2)
2269: hybrid_memory.access(0x10995070, 7424, 64, read, instr, 0, L2)
2413: hybrid_memory.accessCompleted(0x1099e390, 19520, 64, read, dram)
2429: hybrid_memory.accessCompleted(0x1098bd50, 19008, 64, read, dram)
2445: hybrid_memory.accessCompleted(0x109a1880, 19136, 64, read, dram)
2611: hybrid_memory.accessCompleted(0x1099fec0, 16064, 64, read, dram)
2627: hybrid_memory.accessCompleted(0x778790, 16128, 64, read, dram)
2643: hybrid_memory.accessCompleted(0x109a1d30, 16192, 64, read, dram)
2809: hybrid_memory.accessCompleted(0x10995070, 7424, 64, read, dram)
2845: hybrid_memory.access(0x109a2230, 19264, 64, read, data, 0, L2)
2848: hybrid_memory.access(0x1099e390, 19200, 64, read, data, 0, L2)
2852: hybrid_memory.access(0x109a20e0, 19328, 64, read, data, 0, L2)
2852: hybrid_memory.access(0x1099f830, 16256, 64, read, data, 0, L2)
2855: hybrid_memory.access(0x1099b5f0, 7488, 64, read, instr, 0, L2)
3011: hybrid_memory.accessCompleted(0x109a2230, 19264, 64, read, dram)
3027: hybrid_memory.accessCompleted(0x1099e390, 19200, 64, read, dram)
3043: hybrid_memory.accessCompleted(0x109a20e0, 19328, 64, read, dram)
3209: hybrid_memory.accessCompleted(0x1099f830, 16256, 64, read, dram)
3375: hybrid_memory.accessCompleted(0x1099b5f0, 7488, 64, read, dram)
3411: hybrid_memory.access(0x1099d1f0, 7552, 64, read, instr, 0, L2)
3477: hybrid_memory.accessCompleted(0x1099d1f0, 7552, 64, read, dram)
3513: hybrid_memory.access(0x10990df0, 7616, 64, read, instr, 0, L2)
3579: hybrid_memory.accessCompleted(0x10990df0, 7616, 64, read, dram)
3613: hybrid_memory.access(0x10991cf0, 7680, 64, read, instr, 0, L2)
3679: hybrid_memory.accessCompleted(0x10991cf0, 7680, 64, read, dram)
3714: hybrid_memory.access(0x10992d70, 8000, 64, read, instr, 0, L2)
3780: hybrid_memory.accessCompleted(0x10992d70, 8000, 64, read, dram)
3815: hybrid_memory.access(0x109945f0, 8064, 64, read, instr, 0, L2)
3881: hybrid_memory.accessCompleted(0x109945f0, 8064, 64, read, dram)
3918: hybrid_memory.access(0x109964b0, 8128, 64, read, instr, 0, L2)
3921: hybrid_memory.access(0x1099e390, 2176, 64, read, data, 0, L2)
3984: hybrid_memory.accessCompleted(0x109964b0, 8128, 64, read, dram)
4021: hybrid_memory.access(0x109a2230, 15744, 64, read, data, 0, L2)
4021: hybrid_memory.access(0x109a2330, 2240, 64, read, data, 0, L2)
4027: hybrid_memory.access(0x109a0d90, 2304, 64, read, data, 0, L2)
4034: hybrid_memory.access(0x109a2bb0, 2368, 64, read, data, 0, L2)
4038: hybrid_memory.access(0x109a33b0, 15808, 64, read, data, 0, L2)
4150: hybrid_memory.accessCompleted(0x1099e390, 2176, 64, read, dram)
4166: hybrid_memory.accessCompleted(0x109a2330, 2240, 64, read, dram)
4182: hybrid_memory.accessCompleted(0x109a0d90, 2304, 64, read, dram)
4198: hybrid_memory.accessCompleted(0x109a2bb0, 2368, 64, read, dram)
4202: hybrid_memory.access(0x109a1b00, 2432, 64, read, data, 0, L2)
4203: hybrid_memory.access(0x10993b70, 20480, 64, read, instr, 0, L2)
4364: hybrid_memory.accessCompleted(0x109a2230, 15744, 64, read, dram)
4380: hybrid_memory.accessCompleted(0x109a33b0, 15808, 64, read, dram)
4546: hybrid_memory.accessCompleted(0x109a1b00, 2432, 64, read, dram)
4712: hybrid_memory.accessCompleted(0x10993b70, 20480, 64, read, dram)
4749: hybrid_memory.access(0x10996130, 20608, 64, read, instr, 0, L2)
4750: hybrid_memory.access(0x778910, 1088, 64, read, data, 0, L2)
4752: hybrid_memory.access(0x109a2f20, 26112, 64, read, data, 0, L2)
4815: hybrid_memory.accessCompleted(0x10996130, 20608, 64, read, dram)
4851: hybrid_memory.access(0x109a3140, 16320, 64, read, data, 0, L2)
4855: hybrid_memory.access(0x1099f930, 1024, 64, read, data, 0, L2)
4858: hybrid_memory.access(0x109a2330, 2496, 64, read, data, 0, L2)
4863: hybrid_memory.access(0x109a1e30, 1152, 64, read, data, 0, L2)
4870: hybrid_memory.access(0x778780, 1472, 64, read, data, 0, L2)
4870: hybrid_memory.access(0x109a0d90, 1408, 64, read, data, 0, L2)
4874: hybrid_memory.access(0x109a3900, 2560, 64, read, data, 0, L2)
4877: hybrid_memory.access(0x109a3010, 1216, 64, read, data, 0, L2)
4981: hybrid_memory.accessCompleted(0x778910, 1088, 64, read, dram)
4997: hybrid_memory.accessCompleted(0x1099f930, 1024, 64, read, dram)
5013: hybrid_memory.accessCompleted(0x109a2330, 2496, 64, read, dram)
5029: hybrid_memory.accessCompleted(0x109a1e30, 1152, 64, read, dram)
5045: hybrid_memory.accessCompleted(0x778780, 1472, 64, read, dram)
5061: hybrid_memory.accessCompleted(0x109a0d90, 1408, 64, read, dram)
5077: hybrid_memory.accessCompleted(0x109a3900, 2560, 64, read, dram)
5093: hybrid_memory.accessCompleted(0x109a3010, 1216, 64, read, dram)
5259: hybrid_memory.accessCompleted(0x109a2f20, 26112, 64, read, dram)
5307: hybrid_memory.access(0x1099beb0, 7744, 64, read, instr, 0, L2)
5307: hybrid_memory.access(0x1099c170, 31872, 64, read, instr, 0, L2)
5425: hybrid_memory.accessCompleted(0x109a3140, 16320, 64, read, dram)
5591: hybrid_memory.accessCompleted(0x1099beb0, 7744, 64, read, dram)
5627: hybrid_memory.access(0x109a3010, 19648, 64, read, data, 0, L2)
5627: hybrid_memory.access(0x109a2f20, 8576, 64, read, data, 0, L2)
5757: hybrid_memory.accessCompleted(0x1099c170, 31872, 64, read, dram)
5793: hybrid_memory.access(0x1099dff0, 31936, 64, read, instr, 0, L2)
5794: hybrid_memory.access(0x109a2cd0, 640, 64, read, data, 0, L2)
5923: hybrid_memory.accessCompleted(0x109a3010, 19648, 64, read, dram)
6089: hybrid_memory.accessCompleted(0x109a2f20, 8576, 64, read, dram)
6255: hybrid_memory.accessCompleted(0x1099dff0, 31936, 64, read, dram)
6291: hybrid_memory.access(0x109916b0, 7808, 64, read, instr, 0, L2)
6294: hybrid_memory.access(0x778910, 19712, 64, read, data, 0, L2)
6421: hybrid_memory.accessCompleted(0x109a2cd0, 640, 64, read, dram)
6587: hybrid_memory.accessCompleted(0x109916b0, 7808, 64, read, dram)
6621: hybrid_memory.access(0x10992770, 4195264, 64, read, instr, 0, L2)
6625: hybrid_memory.access(0x1099fe70, 18816, 64, read, data, 0, L2)
6753: hybrid_memory.accessCompleted(0x778910, 19712, 64, read, dram)
6769: hybrid_memory.accessCompleted(0x1099fe70, 18816, 64, read, dram)
6931: hybrid_memory.accessCompleted(0x10992770, 4195264, 64, read, pcm)
6966: hybrid_memory.access(0x109939b0, 4195328, 64, read, instr, 0, L2)
33: hybrid_memory.access(0x109902b0, 3264, 64, read, instr, 0, L2)
33: hybrid_memory.access(0x10990630, 7168, 64, read, instr, 0, L2)
149: hybrid_memory.accessCompleted(0x109902b0, 3264, 64, read, dram)
185: hybrid_memory.access(0x1098bd50, 8704, 64, read, data, 0, L2)
315: hybrid_memory.accessCompleted(0x10990630, 7168, 64, read, dram)
349: hybrid_memory.access(0x10991430, 7232, 64, read, instr, 0, L2)
353: hybrid_memory.access(0x1099fa90, 8640, 64, read, data, 0, L2)
481: hybrid_memory.accessCompleted(0x1098bd50, 8704, 64, read, dram)
497: hybrid_memory.accessCompleted(0x1099fa90, 8640, 64, read, dram)
663: hybrid_memory.accessCompleted(0x10991430, 7232, 64, read, dram)
698: hybrid_memory.access(0x10992bb0, 7296, 64, read, instr, 0, L2)
701: hybrid_memory.access(0x1099e390, 15936, 64, read, data, 0, L2)
701: hybrid_memory.access(0x1099f830, 16384, 64, read, data, 0, L2)
701: hybrid_memory.access(0x1098bd50, 15488, 64, read, data, 0, L2)
702: hybrid_memory.access(0x1099f930, 18880, 64, read, data, 0, L2)
764: hybrid_memory.accessCompleted(0x10992bb0, 7296, 64, read, dram)
799: hybrid_memory.access(0x10993d30, 7360, 64, read, instr, 0, L2)
930: hybrid_memory.accessCompleted(0x1099e390, 15936, 64, read, dram)
946: hybrid_memory.accessCompleted(0x1098bd50, 15488, 64, read, dram)
1112: hybrid_memory.accessCompleted(0x1099f830, 16384, 64, read, dram)
1128: hybrid_memory.accessCompleted(0x1099f930, 18880, 64, read, dram)
1294: hybrid_memory.accessCompleted(0x10993d30, 7360, 64, read, dram)
1331: hybrid_memory.access(0x1099e390, 19072, 64, read, data, 0, L2)
1332: hybrid_memory.access(0x10996670, 7872, 64, read, instr, 0, L2)
1332: hybrid_memory.access(0x1098bd50, 16000, 64, read, data, 0, L2)
1333: hybrid_memory.access(0x1099f830, 18944, 64, read, data, 0, L2)
1497: hybrid_memory.accessCompleted(0x1099e390, 19072, 64, read, dram)
1513: hybrid_memory.accessCompleted(0x1099f830, 18944, 64, read, dram)
1679: hybrid_memory.accessCompleted(0x10996670, 7872, 64, read, dram)
1712: hybrid_memory.access(0x10996d70, 7936, 64, read, instr, 0, L2)
1845: hybrid_memory.accessCompleted(0x1098bd50, 16000, 64, read, dram)
2011: hybrid_memory.accessCompleted(0x10996d70, 7936, 64, read, dram)
2044: hybrid_memory.access(0x10997470, 20544, 64, read, instr, 0, L2)
2210: hybrid_memory.accessCompleted(0x10997470, 20544, 64, read, dram)
2247: hybrid_memory.access(0x1099e390, 19520, 64, read, data, 0, L2)
2249: hybrid_memory.access(0x1098bd50, 19008, 64, read, data, 0, L2)
2252: hybrid_memory.access(0x1099fec0, 16064, 64, read, data, 0, L2)
2260: hybrid_memory.access(0x778790, 16128, 64, read, data, 0, L2)
2263: hybrid_memory.access(0x109a1880, 19136, 64, read, data, 0, L2)
2268: hybrid_memory.access(0x109a1d30, 16192, 64, read, data, 0, L2)
2269: hybrid_memory.access(0x10995070, 7424, 64, read, instr, 0, L2)
2413: hybrid_memory.accessCompleted(0x1099e390, 19520, 64, read, dram)
2429: hybrid_memory.accessCompleted(0x1098bd50, 19008, 64, read, dram)
2445: hybrid_memory.accessCompleted(0x109a1880, 19136, 64, read, dram)
2611: hybrid_memory.accessCompleted(0x1099fec0, 16064, 64, read, dram)
2627: hybrid_memory.accessCompleted(0x778790, 16128, 64, read, dram)
2643: hybrid_memory.accessCompleted(0x109a1d30, 16192, 64, read, dram)
2809: hybrid_memory.accessCompleted(0x10995070, 7424, 64, read, dram)
2845: hybrid_memory.access(0x109a2230, 19264, 64, read, data, 0, L2)
2848: hybrid_memory.access(0x1099e390, 19200, 64, read, data, 0, L2)
2852: hybrid_memory.access(0x109a20e0, 19328, 64, read, data, 0, L2)
2852: hybrid_memory.access(0x1099f830, 16256, 64, read, data, 0, L2)
2855: hybrid_memory.access(0x1099b5f0, 7488, 64, read, instr, 0, L2)
3011: hybrid_memory.accessCompleted(0x109a2230, 19264, 64, read, dram)
3027: hybrid_memory.accessCompleted(0x1099e390, 19200, 64, read, dram)
3043: hybrid_memory.accessCompleted(0x109a20e0, 19328, 64, read, dram)
3209: hybrid_memory.accessCompleted(0x1099f830, 16256, 64, read, dram)
3375: hybrid_memory.accessCompleted(0x1099b5f0, 7488, 64, read, dram)
3411: hybrid_memory.access(0x1099d1f0, 7552, 64, read, instr, 0, L2)
3477: hybrid_memory.accessCompleted(0x1099d1f0, 7552, 64, read, dram)
3513: hybrid_memory.access(0x10990df0, 7616, 64, read, instr, 0, L2)
3579: hybrid_memory.accessCompleted(0x10990df0, 7616, 64, read, dram)
3613: hybrid_memory.access(0x10991cf0, 7680, 64, read, instr, 0, L2)
3679: hybrid_memory.accessCompleted(0x10991cf0, 7680, 64, read, dram)
3714: hybrid_memory.access(0x10992d70, 8000, 64, read, instr, 0, L2)
3780: hybrid_memory.accessCompleted(0x10992d70, 8000, 64, read, dram)
3815: hybrid_memory.access(0x109945f0, 8064, 64, read, instr, 0, L2)
3881: hybrid_memory.accessCompleted(0x109945f0, 8064, 64, read, dram)
3918: hybrid_memory.access(0x109964b0, 8128, 64, read, instr, 0, L2)
3921: hybrid_memory.access(0x1099e390, 2176, 64, read, data, 0, L2)
3984: hybrid_memory.accessCompleted(0x109964b0, 8128, 64, read, dram)
4021: hybrid_memory.access(0x109a2230, 15744, 64, read, data, 0, L2)
4021: hybrid_memory.access(0x109a2330, 2240, 64, read, data, 0, L2)
4027: hybrid_memory.access(0x109a0d90, 2304, 64, read, data, 0, L2)
4034: hybrid_memory.access(0x109a2bb0, 2368, 64, read, data, 0, L2)
4038: hybrid_memory.access(0x109a33b0, 15808, 64, read, data, 0, L2)
4150: hybrid_memory.accessCompleted(0x1099e390, 2176, 64, read, dram)
4166: hybrid_memory.accessCompleted(0x109a2330, 2240, 64, read, dram)
4182: hybrid_memory.accessCompleted(0x109a0d90, 2304, 64, read, dram)
4198: hybrid_memory.accessCompleted(0x109a2bb0, 2368, 64, read, dram)
4202: hybrid_memory.access(0x109a1b00, 2432, 64, read, data, 0, L2)
4203: hybrid_memory.access(0x10993b70, 20480, 64, read, instr, 0, L2)
4364: hybrid_memory.accessCompleted(0x109a2230, 15744, 64, read, dram)
4380: hybrid_memory.accessCompleted(0x109a33b0, 15808, 64, read, dram)
4546: hybrid_memory.accessCompleted(0x109a1b00, 2432, 64, read, dram)
4712: hybrid_memory.accessCompleted(0x10993b70, 20480, 64, read, dram)
4749: hybrid_memory.access(0x10996130, 20608, 64, read, instr, 0, L2)
4750: hybrid_memory.access(0x778910, 1088, 64, read, data, 0, L2)
4752: hybrid_memory.access(0x109a2f20, 26112, 64, read, data, 0, L2)
4815: hybrid_memory.accessCompleted(0x10996130, 20608, 64, read, dram)
4851: hybrid_memory.access(0x109a3140, 16320, 64, read, data, 0, L2)
4855: hybrid_memory.access(0x1099f930, 1024, 64, read, data, 0, L2)
4858: hybrid_memory.access(0x109a2330, 2496, 64, read, data, 0, L2)
4863: hybrid_memory.access(0x109a1e30, 1152, 64, read, data, 0, L2)
4870: hybrid_memory.access(0x778780, 1472, 64, read, data, 0, L2)
4870: hybrid_memory.access(0x109a0d90, 1408, 64, read, data, 0, L2)
4874: hybrid_memory.access(0x109a3900, 2560, 64, read, data, 0, L2)
4877: hybrid_memory.access(0x109a3010, 1216, 64, read, data, 0, L2)
4981: hybrid_memory.accessCompleted(0x778910, 1088, 64, read, dram)
4997: hybrid_memory.accessCompleted(0x1099f930, 1024, 64, read, dram)
5013: hybrid_memory.accessCompleted(0x109a2330, 2496, 64, read, dram)
5029: hybrid_memory.accessCompleted(0x109a1e30, 1152, 64, read, dram)
5045: hybrid_memory.accessCompleted(0x778780, 1472, 64, read, dram)
5061: hybrid_memory.accessCompleted(0x109a0d90, 1408, 64, read, dram)
5077: hybrid_memory.accessCompleted(0x109a3900, 2560, 64, read, dram)
5093: hybrid_memory.accessCompleted(0x109a3010, 1216, 64, read, dram)
5259: hybrid_memory.accessCompleted(0x109a2f20, 26112, 64, read, dram)
5307: hybrid_memory.access(0x1099beb0, 7744, 64, read, instr, 0, L2)
5307: hybrid_memory.access(0x1099c170, 31872, 64, read, instr, 0, L2)
5425: hybrid_memory.accessCompleted(0x109a3140, 16320, 64, read, dram)
5591: hybrid_memory.accessCompleted(0x1099beb0, 7744, 64, read, dram)
5627: hybrid_memory.access(0x109a3010, 19648, 64, read, data, 0, L2)
5627: hybrid_memory.access(0x109a2f20, 8576, 64, read, data, 0, L2)
5757: hybrid_memory.accessCompleted(0x1099c170, 31872, 64, read, dram)
5793: hybrid_memory.access(0x1099dff0, 31936, 64, read, instr, 0, L2)
5794: hybrid_memory.access(0x109a2cd0, 640, 64, read, data, 0, L2)
5923: hybrid_memory.accessCompleted(0x109a3010, 19648, 64, read, dram)
6089: hybrid_memory.accessCompleted(0x109a2f20, 8576, 64, read, dram)
6255: hybrid_memory.accessCompleted(0x1099dff0, 31936, 64, read, dram)
6291: hybrid_memory.access(0x109916b0, 7808, 64, read, instr, 0, L2)
6294: hybrid_memory.access(0x778910, 19712, 64, read, data, 0, L2)
6421: hybrid_memory.accessCompleted(0x109a2cd0, 640, 64, read, dram)
6587: hybrid_memory.accessCompleted(0x109916b0, 7808, 64, read, dram)
6621: hybrid_memory.access(0x10992770, 4195264, 64, read, instr, 0, L2)