diff --git a/cmsis-svd-generator b/cmsis-svd-generator index 737e18d..9e41bc3 160000 --- a/cmsis-svd-generator +++ b/cmsis-svd-generator @@ -1 +1 @@ -Subproject commit 737e18da19d317e0a9674a6eb18e0b7bc69e0084 +Subproject commit 9e41bc37be1b6c44c59351b526455bd8908d03f1 diff --git a/jh7110-vf2-12a-pac/jh7110-starfive-visionfive-2-v1.2a.svd b/jh7110-vf2-12a-pac/jh7110-starfive-visionfive-2-v1.2a.svd index 672e423..3faca6a 100644 --- a/jh7110-vf2-12a-pac/jh7110-starfive-visionfive-2-v1.2a.svd +++ b/jh7110-vf2-12a-pac/jh7110-starfive-visionfive-2-v1.2a.svd @@ -180,5555 +180,15467 @@ 0x10000 registers - - - snps_designware_i2c_1 - From snps,designware-i2c, peripheral generator - 0x10040000 - - 0 - 0x10000 - registers - - - - snps_designware_i2c_2 - From snps,designware-i2c, peripheral generator - 0x10050000 - - 0 - 0x10000 - registers - - - - arm_pl022_0 - From arm,pl022, peripheral generator - 0x10060000 - - 0 - 0x10000 - registers - - - - arm_primecell_0 - From arm,primecell, peripheral generator - 0x10060000 - - 0 - 0x10000 - registers - - - - rohm_dh2228fv_0 - From rohm,dh2228fv, peripheral generator - 0x0 - - 0 - 0x0 - registers - - - - arm_pl022_1 - From arm,pl022, peripheral generator - 0x10070000 - - 0 - 0x10000 - registers - - - - arm_primecell_1 - From arm,primecell, peripheral generator - 0x10070000 - - 0 - 0x10000 - registers - - - - arm_pl022_2 - From arm,pl022, peripheral generator - 0x10080000 - - 0 - 0x10000 - registers - - - - arm_primecell_2 - From arm,primecell, peripheral generator - 0x10080000 - - 0 - 0x10000 - registers - - - - starfive_jh7110_tdm_0 - From starfive,jh7110-tdm, peripheral generator - 0x10090000 - - 0 - 0x1000 - registers - - - - starfive_jh7110_usb_phy_0 - From starfive,jh7110-usb-phy, peripheral generator - 0x10200000 - - 0 - 0x10000 - registers - - - - starfive_jh7110_pcie_phy_0 - From starfive,jh7110-pcie-phy, peripheral generator - 0x10210000 - - 0 - 0x10000 - registers - - - - starfive_jh7110_pcie_phy_1 - From starfive,jh7110-pcie-phy, peripheral generator - 0x10220000 - - 0 - 0x10000 - registers - - - - starfive_jh7110_stgcrg_0 - From starfive,jh7110-stgcrg, peripheral generator - 0x10230000 - - 0 - 0x10000 - registers - - clk_hifi4_core - Clock HIFI4 Core + con + DesignWare I2C CON 0x0 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + master + I2C Master Connection - 0: Slave, 1: Master + [0:0] read-write - - - - clk_usb_apb - Clock USB APB - 0x4 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + speed + I2C Speed - 01: Standard, 10: Fast, 11: High + [2:1] + read-write + + + slave_10bitaddr + I2C Slave 10-bit Address - 0: False, 1: True + [3:3] + read-write + + + master_10bitaddr + I2C Master 10-bit Address - 0: False, 1: True + [4:4] + read-write + + + restart_en + I2C Restart Enable - 0: False, 1: True + [5:5] + read-write + + + slave_disable + I2C Slave Disable - 0: False, 1: True + [6:6] + read-write + + + stop_det_ifaddressed + I2C Stop DET If Addressed - 0: False, 1: True + [7:7] + read-write + + + tx_empty_ctrl + I2C TX Empty Control - 0: False, 1: True + [8:8] + read-write + + + rx_fifo_full_hld_ctrl + I2C RX FIFO Full Hold Control - 0: False, 1: True + [9:9] + read-write + + + bus_clear_ctrl + I2C Bus Clear Control - 0: False, 1: True + [11:11] read-write - clk_usb_utmi_apb - Clock USB UTMI APB - 0x8 + tar + DesignWare I2C TAR + 0x4 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + tar + tar + [31:0] read-write - clk_usb_axi - Clock USB AXI - 0xc + sar + DesignWare I2C SAR + 0x8 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + sar + sar + [31:0] read-write - clk_usb_ipm - Clock USB AXI + data_cmd + DesignWare I2C Data Command 0x10 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + dat + Data Command Data Byte + [7:0] read-write - clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 - [23:0] + first_data_byte + Data Command First Data Byte - 0: False, 1: True + [11:11] read-write - clk_usb_stb - Clock USB STB + ss_scl_hcnt + DesignWare I2C SS SCL HCNT 0x14 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write - - - clk_divcfg - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 - [23:0] + ss_scl_hcnt + ss_scl_hcnt + [31:0] read-write - clk_usb_app125 - Clock USB APP 125 + ss_scl_lcnt + DesignWare I2C SS SCL LCNT 0x18 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + ss_scl_lcnt + ss_scl_lcnt + [31:0] read-write - clk_usb_refclk - Clock USB Reference Clock + fs_scl_hcnt + DesignWare I2C FS SCL HCNT 0x1c 32 - clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 - [23:0] + fs_scl_hcnt + fs_scl_hcnt + [31:0] read-write - clk_u0_pcie_axi_mst0 - U0 Clock PCIe AXI MST 0 + fs_scl_lcnt + DesignWare I2C FS SCL LCNT 0x20 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + fs_scl_lcnt + fs_scl_lcnt + [31:0] read-write - clk_u0_pcie_apb - U0 Clock PCIe APB + hs_scl_hcnt + DesignWare I2C HS SCL HCNT 0x24 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + hs_scl_hcnt + hs_scl_hcnt + [31:0] read-write - clk_u0_pcie_tl - U0 Clock PCIe TL + hs_scl_lcnt + DesignWare I2C HS SCL LCNT 0x28 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + hs_scl_lcnt + hs_scl_lcnt + [31:0] read-write - clk_u1_pcie_axi_mst0 - U1 Clock PCIe AXI MST 0 + intr_stat + DesignWare I2C Interrupt Status 0x2c 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + rx_under + RX FIFO Underrun + [0:0] + read-only - - - - clk_u1_pcie_apb - U1 Clock PCIe APB - 0x30 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + rx_over + RX FIFO Overrun + [1:1] + read-only - - - - clk_u1_pcie_tl - U1 Clock PCIe TL - 0x34 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + rx_full + RX FIFO Full + [2:2] + read-only - - - - clk_pcie01_slv_dec_main - Clock PCIe 01 SLV DEC Main - 0x38 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only - clk_sec_hclk - Clock Security HCLK - 0x3c + intr_mask + DesignWare I2C Interrupt Mask + 0x30 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rx_under + RX FIFO Underrun + [0:0] read-write - - - - clk_sec_misc_ahb - Clock Security Miscellaneous AHB - 0x40 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rx_over + RX FIFO Overrun + [1:1] read-write - - - - clk_stg_mtrx_group0_main - Clock STG MTRX Group 0 Main - 0x44 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rx_full + RX FIFO Full + [2:2] read-write - - - - clk_stg_mtrx_group0_bus - Clock STG MTRX Group 0 Bus - 0x48 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + tx_over + TX FIFO Overrun + [3:3] read-write - - - - clk_stg_mtrx_group0_stg - Clock STG MTRX Group 0 STG - 0x4c - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + tx_empty + TX FIFO Empty + [4:4] read-write - - - - clk_stg_mtrx_group1_main - Clock STG MTRX Group 1 Main - 0x50 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rd_req + Read Request + [5:5] read-write - - - - clk_stg_mtrx_group1_bus - Clock STG MTRX Group 1 Bus - 0x54 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + tx_abrt + TX Abort + [6:6] read-write - - - - clk_stg_mtrx_group1_stg - Clock STG MTRX Group 1 STG - 0x58 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rx_done + RX Done + [7:7] read-write - - - - clk_stg_mtrx_group1_hifi - Clock STG MTRX Group 1 HIFI - 0x5c - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + activity + Activity + [8:8] read-write - - - - clk_e2_rtc - Clock E2 RTC - 0x60 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + stop_det + Stop DET + [9:9] read-write - clk_divcfg - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24 - [23:0] + start_det + Start DET + [10:10] read-write - - - - clk_e2_core - Clock E2 Core - 0x64 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + gen_call + General Call + [11:11] read-write - - - - clk_e2_dbg - Clock E2 DBG - 0x68 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + restart_det + Restart DET + [12:12] read-write - - - - clk_dma_axi - Clock DMA AXI - 0x6c - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + mst_on_hold + Master on Hold + [13:13] read-write - clk_dma_ahb - Clock DMA AHB - 0x70 + raw_intr_stat + DesignWare I2C Raw Interrupt Status + 0x34 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write - - - - - soft_rst_addr_sel - Software RESET Address Selector - 0x74 - 32 - - - rstn_u0_stg_syscon_presetn - 1: Assert reset, 0: De-assert reset + rx_under + RX FIFO Underrun [0:0] - read-write + read-only - rst_u0_hifi4_rst_core - 1: Assert reset, 0: De-assert reset + rx_over + RX FIFO Overrun [1:1] - read-write + read-only - rst_u0_hifi4_rst_axi - 1: Assert reset, 0: De-assert reset + rx_full + RX FIFO Full [2:2] - read-write + read-only - rstn_u0_sec_top_hreesetn - 1: Assert reset, 0: De-assert reset + tx_over + TX FIFO Overrun [3:3] - read-write + read-only - rst_u0_e2_sft7110_rst_core - 1: Assert reset, 0: De-assert reset + tx_empty + TX FIFO Empty [4:4] - read-write + read-only - rstn_u0_dma1p_8ch_56hs_rstn_axi - 1: Assert reset, 0: De-assert reset + rd_req + Read Request [5:5] - read-write + read-only - rstn_u0_dma1p_8ch_56hs_rstn_ahb - 1: Assert reset, 0: De-assert reset + tx_abrt + TX Abort [6:6] - read-write + read-only - rstn_u0_cdn_usb_rstn_axi - 1: Assert reset, 0: De-assert reset + rx_done + RX Done [7:7] - read-write + read-only - rstn_u0_cdn_usb_rstn_usb_apb - 1: Assert reset, 0: De-assert reset + activity + Activity [8:8] - read-write + read-only - rstn_u0_cdn_usb_rstn_utmi_apb - 1: Assert reset, 0: De-assert reset + stop_det + Stop DET [9:9] - read-write + read-only - rstn_u0_cdn_usb_rstn_pwrup - 1: Assert reset, 0: De-assert reset + start_det + Start DET [10:10] - read-write + read-only - rstn_u0_plda_pcie_rstn_axi_mst0 - 1: Assert reset, 0: De-assert reset + gen_call + General Call [11:11] - read-write + read-only - rstn_u0_plda_pcie_rstn_axi_slv0 - 1: Assert reset, 0: De-assert reset + restart_det + Restart DET [12:12] - read-write + read-only - rstn_u0_plda_pcie_rstn_axi_slv - 1: Assert reset, 0: De-assert reset + mst_on_hold + Master on Hold [13:13] - read-write - - - rstn_u0_plda_pci_rstn_brg - 1: Assert reset, 0: De-assert reset - [14:14] - read-write - - - rstn_u0_plda_pcie_rstn_pcie - 1: Assert reset, 0: De-assert reset - [15:15] - read-write - - - rstn_u0_plda_pcie_rstn_apb - 1: Assert reset, 0: De-assert reset - [16:16] - read-write - - - rstn_u1_plda_pcie_rstn_axi_mst0 - 1: Assert reset, 0: De-assert reset - [17:17] - read-write - - - rstn_u1_plda_pcie_rstn_axi_slv0 - 1: Assert reset, 0: De-assert reset - [18:18] - read-write - - - rstn_u1_plda_pcie_rstn_axi_slv - 1: Assert reset, 0: De-assert reset - [19:19] - read-write - - - rstn_u1_plda_pcie_rstn_brg - 1: Assert reset, 0: De-assert reset - [20:20] - read-write + read-only + + + + rx_tl + DesignWare I2C RX TL + 0x38 + 32 + - rstn_u1_plda_pcie_rstn_pcie - 1: Assert reset, 0: De-assert reset - [21:21] + rx_tl + rx_tl + [31:0] read-write + + + + tx_tl + DesignWare I2C TX TL + 0x3c + 32 + - rstn_u1_plda_pcie_rstn_apb - 1: Assert reset, 0: De-assert reset - [22:22] + tx_tl + tx_tl + [31:0] read-write - stgcrg_rst_stat - STGCRG RESET Status - 0x78 + clr_intr + DesignWare I2C Clear Interrrupt + 0x40 32 - rstn_u0_stg_syscon_presetn - 1: Assert reset, 0: De-assert reset + rx_under + RX FIFO Underrun [0:0] read-write - rst_u0_hifi4_rst_core - 1: Assert reset, 0: De-assert reset + rx_over + RX FIFO Overrun [1:1] read-write - rst_u0_hifi4_rst_axi - 1: Assert reset, 0: De-assert reset + rx_full + RX FIFO Full [2:2] read-write - rstn_u0_sec_top_hreesetn - 1: Assert reset, 0: De-assert reset + tx_over + TX FIFO Overrun [3:3] read-write - rst_u0_e2_sft7110_rst_core - 1: Assert reset, 0: De-assert reset + tx_empty + TX FIFO Empty [4:4] read-write - rstn_u0_dma1p_8ch_56hs_rstn_axi - 1: Assert reset, 0: De-assert reset + rd_req + Read Request [5:5] read-write - rstn_u0_dma1p_8ch_56hs_rstn_ahb - 1: Assert reset, 0: De-assert reset + tx_abrt + TX Abort [6:6] read-write - rstn_u0_cdn_usb_rstn_axi - 1: Assert reset, 0: De-assert reset + rx_done + RX Done [7:7] read-write - rstn_u0_cdn_usb_rstn_usb_apb - 1: Assert reset, 0: De-assert reset + activity + Activity [8:8] read-write - rstn_u0_cdn_usb_rstn_utmi_apb - 1: Assert reset, 0: De-assert reset + stop_det + Stop DET [9:9] read-write - rstn_u0_cdn_usb_rstn_pwrup - 1: Assert reset, 0: De-assert reset + start_det + Start DET [10:10] read-write - rstn_u0_plda_pcie_rstn_axi_mst0 - 1: Assert reset, 0: De-assert reset + gen_call + General Call [11:11] read-write - rstn_u0_plda_pcie_rstn_axi_slv0 - 1: Assert reset, 0: De-assert reset + restart_det + Restart DET [12:12] read-write - rstn_u0_plda_pcie_rstn_axi_slv - 1: Assert reset, 0: De-assert reset + mst_on_hold + Master on Hold [13:13] read-write + + + + clr_rx_under + DesignWare I2C Clear RX Underrun + 0x44 + 32 + - rstn_u0_plda_pci_rstn_brg - 1: Assert reset, 0: De-assert reset - [14:14] + clr_rx_under + clr_rx_under + [31:0] read-write + + + + clr_rx_over + DesignWare I2C Clear RX Overrun + 0x48 + 32 + - rstn_u0_plda_pcie_rstn_pcie - 1: Assert reset, 0: De-assert reset - [15:15] + clr_rx_over + clr_rx_over + [31:0] read-write + + + + clr_tx_over + DesignWare I2C Clear TX Overrun + 0x4c + 32 + - rstn_u0_plda_pcie_rstn_apb - 1: Assert reset, 0: De-assert reset - [16:16] + clr_tx_over + clr_tx_over + [31:0] read-write + + + + clr_rd_req + DesignWare I2C Clear Read Request + 0x50 + 32 + - rstn_u1_plda_pcie_rstn_axi_mst0 - 1: Assert reset, 0: De-assert reset - [17:17] + clr_rd_req + clr_rd_req + [31:0] read-write + + + + clr_tx_abrt + DesignWare I2C Clear TX Abort + 0x54 + 32 + - rstn_u1_plda_pcie_rstn_axi_slv0 - 1: Assert reset, 0: De-assert reset - [18:18] + clr_tx_abrt + clr_tx_abrt + [31:0] read-write + + + + clr_rx_done + DesignWare I2C Clear RX Done + 0x58 + 32 + - rstn_u1_plda_pcie_rstn_axi_slv - 1: Assert reset, 0: De-assert reset - [19:19] + clr_rx_done + clr_rx_done + [31:0] read-write + + + + clr_activity + DesignWare I2C Clear Activity + 0x5c + 32 + - rstn_u1_plda_pcie_rstn_brg - 1: Assert reset, 0: De-assert reset - [20:20] + clr_activity + clr_activity + [31:0] read-write + + + + clr_stop_det + DesignWare I2C Clear Stop DET + 0x60 + 32 + - rstn_u1_plda_pcie_rstn_pcie - 1: Assert reset, 0: De-assert reset - [21:21] + clr_stop_det + clr_stop_det + [31:0] read-write + + + + clr_start_det + DesignWare I2C Clear Start DET + 0x64 + 32 + - rstn_u1_plda_pcie_rstn_apb - 1: Assert reset, 0: De-assert reset - [22:22] + clr_start_det + clr_start_det + [31:0] read-write - - - - starfive_jh7110_stg_syscon_0 - From starfive,jh7110-stg-syscon, peripheral generator - 0x10240000 - - 0 - 0x1000 - registers - - - stg_sysconsaif_syscfg0 - STG SYSCONSAIF SYSCFG 0 - 0x0 + clr_gen_call + DesignWare I2C Clear General Call + 0x68 32 - scfg_hprot_sd0 - scfg_hprot_sd0 - [3:0] - read-write - - - scfg_hprot_sd1 - scfg_hprot_sd1 - [7:4] + clr_gen_call + clr_gen_call + [31:0] read-write + + + + enable + DesignWare I2C Enable + 0x6c + 32 + - u0_cdn_usb_adp_en - u0_cdn_usb_adp_en - [8:8] - read-only - - - u0_cdn_usb_adp_probe_ana - u0_cdn_usb_adp_probe_ana - [9:9] + abort + abort + [1:1] read-write + + + + status + DesignWare I2C Status + 0x70 + 32 + - u0_cdn_usb_adp_probe_en - u0_cdn_usb_adp_probe_en - [10:10] + activity + activity + [0:0] read-only - u0_cdn_usb_adp_sense_ana - u0_cdn_usb_adp_sense_ana - [11:11] - read-write - - - u0_cdn_usb_adp_sense_en - u0_cdn_usb_adp_sense_en - [12:12] + tfe + tfe + [2:2] read-only - u0_cdn_usb_adp_sink_current_en - u0_cdn_usb_adp_sink_current_en - [13:13] + rfne + rfne + [3:3] read-only - u0_cdn_usb_adp_source_current_en - u0_cdn_usb_adp_source_current_en - [14:14] + master_activity + master_activity + [5:5] read-only - u0_cdn_usb_bc_en - u0_cdn_usb_bc_en - [15:15] + slave_activity + slave_activity + [6:6] read-only + + + + txflr + DesignWare I2C TX Failure + 0x74 + 32 + - u0_cdn_usb_chrg_vbus - u0_cdn_usb_chrg_vbus - [16:16] + txflr + txflr + [31:0] read-write + + + + rxflr + DesignWare I2C RX Failure + 0x78 + 32 + - u0_cdn_usb_dcd_comp_sts - u0_cdn_usb_dcd_comp_sts - [17:17] + rxflr + rxflr + [31:0] read-write + + + + sda_hold + DesignWare I2C SDA Hold + 0x7c + 32 + - u0_cdn_usb_dischrg_vbus - u0_cdn_usb_dischrg_vbus - [18:18] + sda_hold + sda_hold + [31:0] read-write + + + + tx_abrt_source + DesignWare I2C TX Abort Source + 0x80 + 32 + - u0_cdn_usb_dm_vdat_ref_comp_en - u0_cdn_usb_dm_vdat_ref_comp_en - [19:19] + b7_addr_noack + b7_addr_noack + [0:0] read-only - u0_cdn_usb_dm_vdat_ref_comp_sts - u0_cdn_usb_dm_vdat_ref_comp_sts - [20:20] - read-write - - - u0_cdn_usb_dm_vlgc_comp_en - u0_cdn_usb_dm_vlgc_comp_en - [21:21] + b10_addr1_noack + b10_addr1_noack + [1:1] read-only - u0_cdn_usb_dm_vlgc_comp_sts - u0_cdn_usb_dm_vlgc_comp_sts - [22:22] - read-write - - - u0_cdn_usb_dp_vdat_ref_comp_en - u0_cdn_usb_dp_vdat_ref_comp_en - [23:23] + b10_addr2_noack + b10_addr2_noack + [2:2] read-only - u0_cdn_usb_dp_vdat_ref_comp_sts - u0_cdn_usb_dp_vdat_ref_comp_sts - [24:24] - read-write + txdata_noack + txdata_noack + [3:3] + read-only - u0_cdn_usb_host_system_err - u0_cdn_usb_host_system_err - [25:25] - read-write + gcall_noack + gcall_noack + [4:4] + read-only - u0_cdn_usb_hsystem_err_ext - u0_cdn_usb_hsystem_err_ext - [26:26] + gcall_read + gcall_read + [5:5] read-only - u0_cdn_usb_idm_sink_en - u0_cdn_usb_idm_sink_en - [27:27] + sbyte_ackdet + sbyte_ackdet + [7:7] read-only - u0_cdn_usb_idp_sink_en - u0_cdn_usb_idp_sink_en - [28:28] + sbyte_norstrt + sbyte_norstrt + [9:9] read-only - u0_cdn_usb_idp_src_en - u0_cdn_usb_idp_src_en - [29:29] + b10_rd_norstrt + b10_rd_norstrt + [10:10] read-only - - - - stg_sysconsaif_syscfg4 - STG SYSCONSAIF SYSCFG 4 - 0x4 - 32 - - u0_cdn_usb_lowest_belt - LTM interface to software - [11:0] + master_dis + master_dis + [11:11] read-only - u0_cdn_usb_ltm_host_req - LTM interface to software + arb_lost + arb_lost [12:12] read-only - u0_cdn_usb_ltm_host_req_halt - LTM interface to software + slave_flush_txfifo + slave_flush_txfifo [13:13] - read-write + read-only - u0_cdn_usb_mdctrl_clk_sel - u0_cdn_usb_mdctrl_clk_sel + slave_arblost + slave_arblost [14:14] - read-write + read-only - u0_cdn_usb_mdctrl_clk_status - u0_cdn_usb_mdctrl_clk_status + slave_rd_intx + slave_rd_intx [15:15] read-only + + + + enable_status + DesignWare I2C Enable Status + 0x9c + 32 + - u0_cdn_usb_mode_strap - Can onlly be changed when pwrup_rst_n is low - [18:16] + activity + activity + [0:0] read-write - u0_cdn_usb_otg_suspendm - u0_cdn_usb_otg_suspendm - [19:19] + tfe + tfe + [2:2] read-write - u0_cdn_usb_otg_suspendm_byps - u0_cdn_usb_otg_suspendm_byps - [20:20] + rfne + rfne + [3:3] read-write - u0_cdn_usb_phy_bvalid - u0_cdn_usb_phy_bvalid - [21:21] - read-only - - - u0_cdn_usb_pll_en - u0_cdn_usb_pll_en - [22:22] + master_activity + master_activity + [5:5] read-write - u0_cdn_usb_refclk_mode - u0_cdn_usb_refclk_mode - [23:23] + slave_activity + slave_activity + [6:6] read-write + + + + clr_restart_det + DesignWare I2C Clear Restart DET + 0xa8 + 32 + - u0_cdn_usb_rid_a_comp_sts - u0_cdn_usb_rid_a_comp_sts - [24:24] + clr_restart_det + clr_restart_det + [31:0] read-write + + + + comp_param_1 + DesignWare I2C Compatibility Parameter 1 + 0xf4 + 32 + - u0_cdn_usb_rid_b_comp_sts - u0_cdn_usb_rid_b_comp_sts - [25:25] - read-write + speed + Speed mask - 01: Standard, 10: Full, 11: High + [3:2] + read-only + + + + comp_version + DesignWare I2C Compatibility Version + 0xf8 + 32 + - u0_cdn_usb_rid_c_comp_sts - u0_cdn_usb_rid_c_comp_sts - [26:26] - read-write + comp_version + comp_version + [31:0] + read-only + + + + comp_type + DesignWare I2C Compatibility Type + 0xfc + 32 + - u0_cdn_usb_rid_float_comp_en - u0_cdn_usb_rid_float_comp_en - [27:27] + comp_type + comp_type + [31:0] read-only + + + + + + snps_designware_i2c_1 + From snps,designware-i2c, peripheral generator + 0x10040000 + + 0 + 0x10000 + registers + + + + con + DesignWare I2C CON + 0x0 + 32 + - u0_cdn_usb_rid_float_comp_sts - u0_cdn_usb_rid_float_comp_sts - [28:28] + master + I2C Master Connection - 0: Slave, 1: Master + [0:0] read-write - u0_cdn_usb_rid_gnd_comp_sts - u0_cdn_usb_rid_gnd_comp_sts - [29:29] + speed + I2C Speed - 01: Standard, 10: Fast, 11: High + [2:1] read-write - u0_cdn_usb_rid_nonfloat_comp_en - u0_cdn_usb_rid_nonfloat_comp_en - [30:30] - read-only + slave_10bitaddr + I2C Slave 10-bit Address - 0: False, 1: True + [3:3] + read-write - u0_cdn_usb_rx_dm - u0_cdn_usb_rx_dm - [31:31] - read-only + master_10bitaddr + I2C Master 10-bit Address - 0: False, 1: True + [4:4] + read-write + + + restart_en + I2C Restart Enable - 0: False, 1: True + [5:5] + read-write + + + slave_disable + I2C Slave Disable - 0: False, 1: True + [6:6] + read-write + + + stop_det_ifaddressed + I2C Stop DET If Addressed - 0: False, 1: True + [7:7] + read-write + + + tx_empty_ctrl + I2C TX Empty Control - 0: False, 1: True + [8:8] + read-write + + + rx_fifo_full_hld_ctrl + I2C RX FIFO Full Hold Control - 0: False, 1: True + [9:9] + read-write + + + bus_clear_ctrl + I2C Bus Clear Control - 0: False, 1: True + [11:11] + read-write - stg_sysconsaif_syscfg8 - STG SYSCONSAIF SYSCFG 8 + tar + DesignWare I2C TAR + 0x4 + 32 + + + tar + tar + [31:0] + read-write + + + + + sar + DesignWare I2C SAR 0x8 32 - u0_cdn_usb_rx_dp - u0_cdn_usb_rx_dp + sar + sar + [31:0] + read-write + + + + + data_cmd + DesignWare I2C Data Command + 0x10 + 32 + + + dat + Data Command Data Byte + [7:0] + read-write + + + first_data_byte + Data Command First Data Byte - 0: False, 1: True + [11:11] + read-write + + + + + ss_scl_hcnt + DesignWare I2C SS SCL HCNT + 0x14 + 32 + + + ss_scl_hcnt + ss_scl_hcnt + [31:0] + read-write + + + + + ss_scl_lcnt + DesignWare I2C SS SCL LCNT + 0x18 + 32 + + + ss_scl_lcnt + ss_scl_lcnt + [31:0] + read-write + + + + + fs_scl_hcnt + DesignWare I2C FS SCL HCNT + 0x1c + 32 + + + fs_scl_hcnt + fs_scl_hcnt + [31:0] + read-write + + + + + fs_scl_lcnt + DesignWare I2C FS SCL LCNT + 0x20 + 32 + + + fs_scl_lcnt + fs_scl_lcnt + [31:0] + read-write + + + + + hs_scl_hcnt + DesignWare I2C HS SCL HCNT + 0x24 + 32 + + + hs_scl_hcnt + hs_scl_hcnt + [31:0] + read-write + + + + + hs_scl_lcnt + DesignWare I2C HS SCL LCNT + 0x28 + 32 + + + hs_scl_lcnt + hs_scl_lcnt + [31:0] + read-write + + + + + intr_stat + DesignWare I2C Interrupt Status + 0x2c + 32 + + + rx_under + RX FIFO Underrun [0:0] read-only - u0_cdn_usb_rx_rcv - u0_cdn_usb_rx_rcv + rx_over + RX FIFO Overrun [1:1] read-only - u0_cdn_usb_self_test - For software bist_test + rx_full + RX FIFO Full [2:2] - read-write + read-only - u0_cdn_usb_sessend - u0_cdn_usb_sessend + tx_over + TX FIFO Overrun [3:3] read-only - u0_cdn_usb_sessvalid - u0_cdn_usb_sessvalid + tx_empty + TX FIFO Empty [4:4] read-only - u0_cdn_usb_sof - u0_cdn_usb_sof + rd_req + Read Request [5:5] read-only - u0_cdn_usb_test_bist - For software bist_test + tx_abrt + TX Abort [6:6] read-only - u0_cdn_usb_usbdev_main_power_off_ack - u0_cdn_usb_usbdev_main_power_off_ack + rx_done + RX Done [7:7] read-only - u0_cdn_usb_usbdev_main_power_off_ready - u0_cdn_usb_usbdev_main_power_off_ready + activity + Activity [8:8] read-only - u0_cdn_usb_usbdev_main_power_off_req - u0_cdn_usb_usbdev_main_power_off_req + stop_det + Stop DET [9:9] - read-write + read-only - u0_cdn_usb_usbdev_main_power_on_ready - u0_cdn_usb_usbdev_main_power_on_ready + start_det + Start DET [10:10] read-only - u0_cdn_usb_usbdev_main_power_on_req - u0_cdn_usb_usbdev_main_power_on_req + gen_call + General Call [11:11] read-only - u0_cdn_usb_usbdev_main_power_on_valid - u0_cdn_usb_usbdev_main_power_on_valid + restart_det + Restart DET [12:12] - read-write + read-only - u0_cdn_usb_usbdev_power_off_ack - u0_cdn_usb_usbdev_power_off_ack + mst_on_hold + Master on Hold [13:13] read-only + + + + intr_mask + DesignWare I2C Interrupt Mask + 0x30 + 32 + - u0_cdn_usb_usbdev_power_off_ready - u0_cdn_usb_usbdev_power_off_ready - [14:14] - read-only + rx_under + RX FIFO Underrun + [0:0] + read-write - u0_cdn_usb_usbdev_power_off_req - u0_cdn_usb_usbdev_power_off_req - [15:15] + rx_over + RX FIFO Overrun + [1:1] read-write - u0_cdn_usb_usbdev_power_on_ready - u0_cdn_usb_usbdev_power_on_ready - [16:16] - read-only + rx_full + RX FIFO Full + [2:2] + read-write - u0_cdn_usb_usbdev_power_on_req - u0_cdn_usb_usbdev_power_on_req - [17:17] - read-only + tx_over + TX FIFO Overrun + [3:3] + read-write - u0_cdn_usb_usbdev_power_on_valid - u0_cdn_usb_usbdev_power_on_valid - [18:18] + tx_empty + TX FIFO Empty + [4:4] read-write - u0_cdn_usb_utmi_dmpulldown_sit - u0_cdn_usb_utmi_dmpulldown_sit - [19:19] + rd_req + Read Request + [5:5] read-write - u0_cdn_usb_utmi_dppulldown_sit - u0_cdn_usb_utmi_dppulldown_sit - [20:20] + tx_abrt + TX Abort + [6:6] read-write - u0_cdn_usb_utmi_fslsserialmode_sit - u0_cdn_usb_utmi_fslsserialmode_sit - [21:21] + rx_done + RX Done + [7:7] read-write - u0_cdn_usb_utmi_hostdisconnect_sit - u0_cdn_usb_utmi_hostdisconnect_sit - [22:22] - read-only + activity + Activity + [8:8] + read-write - u0_cdn_usb_utmi_iddig_sit - u0_cdn_usb_utmi_iddig_sit - [23:23] - read-only + stop_det + Stop DET + [9:9] + read-write - u0_cdn_usb_utmi_idpullup_sit - u0_cdn_usb_utmi_idpullup_sit - [24:24] + start_det + Start DET + [10:10] read-write - u0_cdn_usb_utmi_linestate_sit - u0_cdn_usb_utmi_linestate_sit - [26:25] - read-only - - - u0_cdn_usb_utmi_opmode_sit - u0_cdn_usb_utmi_opmode_sit - [28:27] + gen_call + General Call + [11:11] read-write - u0_cdn_usb_utmi_rxactive_sit - u0_cdn_usb_utmi_rxactive_sit - [29:29] - read-only - - - u0_cdn_usb_utmi_rxerror_sit - u0_cdn_usb_utmi_rxerror_sit - [30:30] - read-only + restart_det + Restart DET + [12:12] + read-write - u0_cdn_usb_utmi_rxvalid_sit - u0_cdn_usb_utmi_rxvalid_sit - [31:31] - read-only + mst_on_hold + Master on Hold + [13:13] + read-write - stg_sysconsaif_syscfg12 - STG SYSCONSAIF SYSCFG 12 - 0xc + raw_intr_stat + DesignWare I2C Raw Interrupt Status + 0x34 32 - u0_cdn_usb_utmi_rxvalidh_sit - u0_cdn_usb_utmi_rxvalidh_sit + rx_under + RX FIFO Underrun [0:0] read-only - u0_cdn_usb_utmi_sessvld - u0_cdn_usb_utmi_sessvld + rx_over + RX FIFO Overrun [1:1] - read-write + read-only - u0_cdn_usb_utmi_termselect_sit - u0_cdn_usb_utmi_termselect_sit + rx_full + RX FIFO Full [2:2] - read-write + read-only - u0_cdn_usb_utmi_tx_dat_sit - u0_cdn_usb_utmi_tx_dat_sit + tx_over + TX FIFO Overrun [3:3] - read-write + read-only - u0_cdn_usb_utmi_tx_enable_n_sit - u0_cdn_usb_utmi_tx_enable_n_sit + tx_empty + TX FIFO Empty [4:4] - read-write + read-only - u0_cdn_usb_utmi_tx_se0_sit - u0_cdn_usb_utmi_tx_se0_sit + rd_req + Read Request [5:5] - read-write + read-only - u0_cdn_usb_utmi_txbitstuffenable_sit - u0_cdn_usb_utmi_txbitstuffenable_sit + tx_abrt + TX Abort [6:6] - read-write + read-only - u0_cdn_usb_utmi_txready_sit - u0_cdn_usb_utmi_txready_sit + rx_done + RX Done [7:7] read-only - u0_cdn_usb_utmi_txvalid_sit - u0_cdn_usb_utmi_txvalid_sit + activity + Activity [8:8] - read-write + read-only - u0_cdn_usb_utmi_txvalidh_sit - u0_cdn_usb_utmi_txvalidh_sit + stop_det + Stop DET [9:9] - read-write + read-only - u0_cdn_usb_utmi_vbusvalid_sit - u0_cdn_usb_utmi_vbusvalid_sit + start_det + Start DET [10:10] read-only - u0_cdn_usb_utmi_xcvrselect_sit - u0_cdn_usb_utmi_xcvrselect_sit - [12:11] - read-write - - - u0_cdn_usb_utmi_vdm_src_en - u0_cdn_usb_utmi_vdm_src_en - [13:13] + gen_call + General Call + [11:11] read-only - u0_cdn_usb_utmi_vdp_src_en - u0_cdn_usb_utmi_vdp_src_en - [14:14] + restart_det + Restart DET + [12:12] read-only - u0_cdn_usb_wakeup - u0_cdn_usb_wakeup - [15:15] - read-write - - - u0_cdn_usb_xhc_d0_ack - u0_cdn_usb_xhc_d0_ack - [16:16] + mst_on_hold + Master on Hold + [13:13] read-only - - u0_cdn_usb_xhc_d0_req - u0_cdn_usb_xhc_d0_req - [17:17] - read-write - - stg_sysconsaif_syscfg16 - STG SYSCONSAIF SYSCFG 16 - 0x10 + rx_tl + DesignWare I2C RX TL + 0x38 32 - u0_cdn_usb_xhci_debug_bus - u0_cdn_usb_xhci_debug_bus + rx_tl + rx_tl [31:0] - read-only + read-write - stg_sysconsaif_syscfg20 - STG SYSCONSAIF SYSCFG 20 - 0x14 + tx_tl + DesignWare I2C TX TL + 0x3c 32 - u0_cdn_usb_xhci_debug_link_state - u0_cdn_usb_xhci_debug_link_state - [30:0] - read-only + tx_tl + tx_tl + [31:0] + read-write - stg_sysconsaif_syscfg24 - STG SYSCONSAIF SYSCFG 24 - 0x18 + clr_intr + DesignWare I2C Clear Interrrupt + 0x40 32 - u0_cdn_usb_xhci_debug_sel - u0_cdn_usb_xhci_debug_sel - [4:0] + rx_under + RX FIFO Underrun + [0:0] read-write - u0_cdn_usb_xhci_main_power_off_ack - u0_cdn_usb_xhci_main_power_off_ack + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request [5:5] - read-only + read-write - u0_cdn_usb_xhci_main_power_off_req - u0_cdn_usb_xhci_main_power_off_req + tx_abrt + TX Abort [6:6] - read-only + read-write - u0_cdn_usb_xhci_main_power_on_ready - u0_cdn_usb_xhci_main_power_on_ready + rx_done + RX Done [7:7] read-write - u0_cdn_usb_xhci_main_power_on_req - u0_cdn_usb_xhci_main_power_on_req + activity + Activity [8:8] - read-only + read-write - u0_cdn_usb_xhci_main_power_on_valid - u0_cdn_usb_xhci_main_power_on_valid + stop_det + Stop DET [9:9] read-write - u0_cdn_usb_xhci_power_off_ack - u0_cdn_usb_xhci_power_off_ack + start_det + Start DET [10:10] - read-only + read-write - u0_cdn_usb_xhci_power_off_ready - u0_cdn_usb_xhci_power_off_ready + gen_call + General Call [11:11] - read-only + read-write - u0_cdn_usb_xhci_power_off_req - u0_cdn_usb_xhci_power_off_req + restart_det + Restart DET [12:12] read-write - u0_cdn_usb_xhci_power_on_ready - u0_cdn_usb_xhci_power_on_ready + mst_on_hold + Master on Hold [13:13] - read-only - - - u0_cdn_usb_xhci_power_on_req - u0_cdn_usb_xhci_power_on_req - [14:14] - read-only - - - u0_cdn_usb_xhci_power_on_valid - u0_cdn_usb_xhci_power_on_valid - [15:15] read-write + + + + clr_rx_under + DesignWare I2C Clear RX Underrun + 0x44 + 32 + - u0_e2_sft7110_cease_from_tile_0 - u0_e2_sft7110_cease_from_tile_0 - [16:16] - read-only + clr_rx_under + clr_rx_under + [31:0] + read-write + + + + clr_rx_over + DesignWare I2C Clear RX Overrun + 0x48 + 32 + - u0_e2_sft7110_debug_from_tile_0 - u0_e2_sft7110_debug_from_tile_0 - [17:17] - read-only + clr_rx_over + clr_rx_over + [31:0] + read-write + + + + clr_tx_over + DesignWare I2C Clear TX Overrun + 0x4c + 32 + - u0_e2_sft7110_halt_from_tile_0 - u0_e2_sft7110_halt_from_tile_0 - [18:18] - read-only + clr_tx_over + clr_tx_over + [31:0] + read-write - stg_sysconsaif_syscfg28 - STG SYSCONSAIF SYSCFG 28 - 0x1c + clr_rd_req + DesignWare I2C Clear Read Request + 0x50 32 - u0_e2_sft7110_nmi_0_rnmi_exception_vector - u0_e2_sft7110_nmi_0_rnmi_exception_vector + clr_rd_req + clr_rd_req [31:0] read-write - stg_sysconsaif_syscfg32 - STG SYSCONSAIF SYSCFG 32 - 0x20 + clr_tx_abrt + DesignWare I2C Clear TX Abort + 0x54 32 - u0_e2_sft7110_nmi_0_rnmi_interrupt_vector - u0_e2_sft7110_nmi_0_rnmi_interrupt_vector + clr_tx_abrt + clr_tx_abrt [31:0] read-write - stg_sysconsaif_syscfg36 - STG SYSCONSAIF SYSCFG 36 - 0x24 + clr_rx_done + DesignWare I2C Clear RX Done + 0x58 32 - u0_e2_sft7110_reset_vector_0 - u0_e2_sft7110_reset_vector_0 + clr_rx_done + clr_rx_done [31:0] read-write - stg_sysconsaif_syscfg40 - STG SYSCONSAIF SYSCFG 40 - 0x28 + clr_activity + DesignWare I2C Clear Activity + 0x5c 32 - u0_e2_sft7110_wfi_from_tile_0 - u0_e2_sft7110_wfi_from_tile_0 - [0:0] - read-only + clr_activity + clr_activity + [31:0] + read-write - stg_sysconsaif_syscfg44 - STG SYSCONSAIF SYSCFG 44 - 0x2c + clr_stop_det + DesignWare I2C Clear Stop DET + 0x60 32 - u0_hifi4_altresetvec - Reset Vector Address + clr_stop_det + clr_stop_det [31:0] read-write - stg_sysconsaif_syscfg48 - STG SYSCONSAIF SYSCFG 48 - 0x30 + clr_start_det + DesignWare I2C Clear Start DET + 0x64 32 - u0_hifi4_breakin - Debug signal - [0:0] + clr_start_det + clr_start_det + [31:0] read-write + + + + clr_gen_call + DesignWare I2C Clear General Call + 0x68 + 32 + - u0_hifi4_breakinack - Debug signal - [1:1] - read-only - - - u0_hifi4_breakout - Debug signal - [2:2] - read-only - - - u0_hifi4_breakoutack - Debug signal - [3:3] - read-write - - - u0_hifi4_debugmode - Debug signal - [4:4] - read-only - - - u0_hifi4_doubleexceptionerror - Fault Handling Signals - [5:5] - read-only - - - u0_hifi4_iram0loadstore - Indicates that iram0 works - [6:6] - read-only - - - u0_hifi4_iram1loadstore - Indicates that iram1 works - [7:7] - read-only - - - u0_hifi4_ocdhaltonreset - Debug signal - [8:8] + clr_gen_call + clr_gen_call + [31:0] read-write - - u0_hifi4_pfatalerror - Fault Handling Signals - [9:9] - read-only - - stg_sysconsaif_syscfg52 - STG SYSCONSAIF SYSCFG 52 - 0x34 + enable + DesignWare I2C Enable + 0x6c 32 - u0_hifi4_pfaultinfo - Fault Handling Signals - [31:0] - read-only + abort + abort + [1:1] + read-write - stg_sysconsaif_syscfg56 - STG SYSCONSAIF SYSCFG 56 - 0x38 + status + DesignWare I2C Status + 0x70 32 - u0_hifi4_pfaultinfovalid - Fault Handling Signals + activity + activity [0:0] read-only - u0_hifi4_prid - Module ID - [16:1] - read-write + tfe + tfe + [2:2] + read-only - u0_hifi4_pwaitmode - Wait Mode - [17:17] + rfne + rfne + [3:3] read-only - u0_hifi4_runstall - Run Stall - [18:18] - read-write + master_activity + master_activity + [5:5] + read-only + + + slave_activity + slave_activity + [6:6] + read-only - stg_sysconsaif_syscfg60 - STG SYSCONSAIF SYSCFG 60 - 0x3c + txflr + DesignWare I2C TX Failure + 0x74 32 - u0_hifi4_scfg_dsp_mst_offset_master - Indicates that master port remap address - [11:0] + txflr + txflr + [31:0] read-write + + + + rxflr + DesignWare I2C RX Failure + 0x78 + 32 + - u0_hifi4_scfg_dsp_mst_offset_dma - Indicates the DMA port remap address - [27:16] + rxflr + rxflr + [31:0] read-write - stg_sysconsaif_syscfg64 - STG SYSCONSAIF SYSCFG 64 - 0x40 + sda_hold + DesignWare I2C SDA Hold + 0x7c 32 - u0_hifi4_scfg_dsp_slv_offset - The value indicates the slave port remap address + sda_hold + sda_hold [31:0] read-write - stg_sysconsaif_syscfg68 - STG SYSCONSAIF SYSCFG 68 - 0x44 + tx_abrt_source + DesignWare I2C TX Abort Source + 0x80 32 - u0_hifi4_scfg_sram_config_slp - SRAM/ROM configuration. SLP: sleep enable, high active, default is low. + b7_addr_noack + b7_addr_noack [0:0] - read-write + read-only - u0_hifi4_scfg_sram_config_sram_config_sd - SRAM/ROM configuration. SD: shutdown enable, high active, default is low. + b10_addr1_noack + b10_addr1_noack [1:1] - read-write + read-only - u0_hifi4_scfg_sram_config_rtsel - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. - [3:2] - read-write + b10_addr2_noack + b10_addr2_noack + [2:2] + read-only - u0_hifi4_scfg_sram_config_ptsel - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. - [5:4] - read-write + txdata_noack + txdata_noack + [3:3] + read-only - u0_hifi4_scfg_sram_config_trb - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. - [7:6] - read-write + gcall_noack + gcall_noack + [4:4] + read-only - u0_hifi4_scfg_sram_config_wtsel - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. - [9:8] - read-write + gcall_read + gcall_read + [5:5] + read-only - u0_hifi4_scfg_sram_config_vs - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. + sbyte_ackdet + sbyte_ackdet + [7:7] + read-only + + + sbyte_norstrt + sbyte_norstrt + [9:9] + read-only + + + b10_rd_norstrt + b10_rd_norstrt [10:10] - read-write + read-only - u0_hifi4_scfg_sram_config_vg - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. + master_dis + master_dis [11:11] - read-write + read-only - u0_hifi4_statvectorsel - When the value is 1, it indicates that the AltResetVec is valid + arb_lost + arb_lost [12:12] - read-write + read-only - u0_hifi4_trigin_idma - DMA port trigger + slave_flush_txfifo + slave_flush_txfifo [13:13] - read-write + read-only - u0_hifi4_trigout_idma - DMA port trigger + slave_arblost + slave_arblost [14:14] read-only - u0_hifi4_xocdmode - Debug signal + slave_rd_intx + slave_rd_intx [15:15] read-only - - u0_plda_pcie_align_detect - u0_plda_pcie_align_detect - [16:16] - read-only - - stg_sysconsaif_syscfg72 - STG SYSCONSAIF SYSCFG 72 - 0x48 + enable_status + DesignWare I2C Enable Status + 0x9c 32 - u0_plda_pcie_axi4_mst0_aratomop_31_0 - u0_plda_pcie_axi4_mst0_aratomop_31_0 - [31:0] - read-only + activity + activity + [0:0] + read-write - - - - stg_sysconsaif_syscfg76 - STG SYSCONSAIF SYSCFG 76 - 0x4c - 32 - - u0_plda_pcie_axi4_mst0_aratomop_63_32 - u0_plda_pcie_axi4_mst0_aratomop_63_32 - [31:0] - read-only + tfe + tfe + [2:2] + read-write + + + rfne + rfne + [3:3] + read-write + + + master_activity + master_activity + [5:5] + read-write + + + slave_activity + slave_activity + [6:6] + read-write - stg_sysconsaif_syscfg80 - STG SYSCONSAIF SYSCFG 80 - 0x50 + clr_restart_det + DesignWare I2C Clear Restart DET + 0xa8 32 - u0_plda_pcie_axi4_mst0_aratomop_95_64 - u0_plda_pcie_axi4_mst0_aratomop_95_64 + clr_restart_det + clr_restart_det [31:0] - read-only + read-write - stg_sysconsaif_syscfg84 - STG SYSCONSAIF SYSCFG 84 - 0x54 + comp_param_1 + DesignWare I2C Compatibility Parameter 1 + 0xf4 32 - u0_plda_pcie_axi4_mst0_aratomop_127_96 - u0_plda_pcie_axi4_mst0_aratomop_127_96 - [31:0] + speed + Speed mask - 01: Standard, 10: Full, 11: High + [3:2] read-only - stg_sysconsaif_syscfg88 - STG SYSCONSAIF SYSCFG 88 - 0x58 + comp_version + DesignWare I2C Compatibility Version + 0xf8 32 - u0_plda_pcie_axi4_mst0_aratomop_159_128 - u0_plda_pcie_axi4_mst0_aratomop_159_128 + comp_version + comp_version [31:0] read-only - stg_sysconsaif_syscfg92 - STG SYSCONSAIF SYSCFG 92 - 0x5c + comp_type + DesignWare I2C Compatibility Type + 0xfc 32 - u0_plda_pcie_axi4_mst0_aratomop_191_160 - u0_plda_pcie_axi4_mst0_aratomop_191_160 + comp_type + comp_type [31:0] read-only - - stg_sysconsaif_syscfg96 - STG SYSCONSAIF SYSCFG 96 - 0x60 + + + + snps_designware_i2c_2 + From snps,designware-i2c, peripheral generator + 0x10050000 + + 0 + 0x10000 + registers + + + + con + DesignWare I2C CON + 0x0 32 - u0_plda_pcie_axi4_mst0_aratomop_223_192 - u0_plda_pcie_axi4_mst0_aratomop_223_192 - [31:0] - read-only + master + I2C Master Connection - 0: Slave, 1: Master + [0:0] + read-write - - - - stg_sysconsaif_syscfg100 - STG SYSCONSAIF SYSCFG 100 - 0x64 - 32 - - u0_plda_pcie_axi4_mst0_aratomop_255_224 - u0_plda_pcie_axi4_mst0_aratomop_255_224 - [31:0] - read-only + speed + I2C Speed - 01: Standard, 10: Fast, 11: High + [2:1] + read-write - - - - stg_sysconsaif_syscfg104 - STG SYSCONSAIF SYSCFG 104 - 0x68 - 32 - - u0_plda_pcie_axi4_mst0_aratomop_257_256 - u0_plda_pcie_axi4_mst0_aratomop_257_256 - [1:0] - read-only + slave_10bitaddr + I2C Slave 10-bit Address - 0: False, 1: True + [3:3] + read-write - u0_plda_pcie_axi4_mst0_arfunc - u0_plda_pcie_axi4_mst0_arfunc - [16:2] - read-only + master_10bitaddr + I2C Master 10-bit Address - 0: False, 1: True + [4:4] + read-write - u0_plda_pcie_axi4_mst0_arregion - u0_plda_pcie_axi4_mst0_arregion - [20:17] - read-only + restart_en + I2C Restart Enable - 0: False, 1: True + [5:5] + read-write - - - - stg_sysconsaif_syscfg108 - STG SYSCONSAIF SYSCFG 108 - 0x6c - 32 - - u0_plda_pcie_axi4_mst0_aruser_31_0 - u0_plda_pcie_axi4_mst0_aruser_31_0 - [31:0] - read-only + slave_disable + I2C Slave Disable - 0: False, 1: True + [6:6] + read-write - - - - stg_sysconsaif_syscfg112 - STG SYSCONSAIF SYSCFG 112 - 0x70 - 32 - - u0_plda_pcie_axi4_mst0_aruser_63_32 - u0_plda_pcie_axi4_mst0_aruser_63_32 - [31:0] - read-only + stop_det_ifaddressed + I2C Stop DET If Addressed - 0: False, 1: True + [7:7] + read-write - - - - stg_sysconsaif_syscfg116 - STG SYSCONSAIF SYSCFG 116 - 0x74 - 32 - - u0_plda_pcie_axi4_mst0_awfunc - u0_plda_pcie_axi4_mst0_awfunc - [14:0] - read-only + tx_empty_ctrl + I2C TX Empty Control - 0: False, 1: True + [8:8] + read-write - u0_plda_pcie_axi4_mst0_awregion - u0_plda_pcie_axi4_mst0_awregion - [18:15] - read-only + rx_fifo_full_hld_ctrl + I2C RX FIFO Full Hold Control - 0: False, 1: True + [9:9] + read-write - - - - stg_sysconsaif_syscfg120 - STG SYSCONSAIF SYSCFG 120 - 0x78 - 32 - - u0_plda_pcie_axi4_mst0_a2user_31_0 - u0_plda_pcie_axi4_mst0_a2user_31_0 - [31:0] - read-only + bus_clear_ctrl + I2C Bus Clear Control - 0: False, 1: True + [11:11] + read-write - stg_sysconsaif_syscfg124 - STG SYSCONSAIF SYSCFG 124 - 0x7c + tar + DesignWare I2C TAR + 0x4 32 - u0_plda_pcie_axi4_mst0_awuser_42_32 - u0_plda_pcie_axi4_mst0_awuser_42_32 - [10:0] - read-only - - - u0_plda_pcie_axi4_mst0_rderr - u0_plda_pcie_axi4_mst0_rderr - [18:11] + tar + tar + [31:0] read-write - stg_sysconsaif_syscfg128 - STG SYSCONSAIF SYSCFG 128 - 0x80 + sar + DesignWare I2C SAR + 0x8 32 - u0_plda_pcie_axi4_mst0_ruser - u0_plda_pcie_axi4_mst0_ruser + sar + sar [31:0] read-write - stg_sysconsaif_syscfg132 - STG SYSCONSAIF SYSCFG 132 - 0x84 + data_cmd + DesignWare I2C Data Command + 0x10 32 - u0_plda_pcie_axi4_mst0_wderr - u0_plda_pcie_axi4_mst0_wderr + dat + Data Command Data Byte [7:0] - read-only + read-write - - - - stg_sysconsaif_syscfg136 - STG SYSCONSAIF SYSCFG 136 - 0x88 - 32 - - u0_plda_pcie_axi4_slv0_aratomop_31_0 - u0_plda_pcie_axi4_slv0_aratomop_31_0 - [31:0] + first_data_byte + Data Command First Data Byte - 0: False, 1: True + [11:11] read-write - stg_sysconsaif_syscfg140 - STG SYSCONSAIF SYSCFG 140 - 0x8c + ss_scl_hcnt + DesignWare I2C SS SCL HCNT + 0x14 32 - u0_plda_pcie_axi4_slv0_aratomop_63_32 - u0_plda_pcie_axi4_slv0_aratomop_63_32 + ss_scl_hcnt + ss_scl_hcnt [31:0] read-write - stg_sysconsaif_syscfg144 - STG SYSCONSAIF SYSCFG 144 - 0x90 + ss_scl_lcnt + DesignWare I2C SS SCL LCNT + 0x18 32 - u0_plda_pcie_axi4_slv0_aratomop_95_64 - u0_plda_pcie_axi4_slv0_aratomop_95_64 + ss_scl_lcnt + ss_scl_lcnt [31:0] read-write - stg_sysconsaif_syscfg148 - STG SYSCONSAIF SYSCFG 148 - 0x94 + fs_scl_hcnt + DesignWare I2C FS SCL HCNT + 0x1c 32 - u0_plda_pcie_axi4_slv0_aratomop_127_96 - u0_plda_pcie_axi4_slv0_aratomop_127_96 + fs_scl_hcnt + fs_scl_hcnt [31:0] read-write - stg_sysconsaif_syscfg152 - STG SYSCONSAIF SYSCFG 152 - 0x98 + fs_scl_lcnt + DesignWare I2C FS SCL LCNT + 0x20 32 - u0_plda_pcie_axi4_slv0_aratomop_159_128 - u0_plda_pcie_axi4_slv0_aratomop_159_128 + fs_scl_lcnt + fs_scl_lcnt [31:0] read-write - stg_sysconsaif_syscfg156 - STG SYSCONSAIF SYSCFG 156 - 0x9c + hs_scl_hcnt + DesignWare I2C HS SCL HCNT + 0x24 32 - u0_plda_pcie_axi4_slv0_aratomop_191_160 - u0_plda_pcie_axi4_slv0_aratomop_191_160 + hs_scl_hcnt + hs_scl_hcnt [31:0] read-write - stg_sysconsaif_syscfg160 - STG SYSCONSAIF SYSCFG 160 - 0xa0 + hs_scl_lcnt + DesignWare I2C HS SCL LCNT + 0x28 32 - u0_plda_pcie_axi4_slv0_aratomop_223_192 - u0_plda_pcie_axi4_slv0_aratomop_223_192 + hs_scl_lcnt + hs_scl_lcnt [31:0] read-write - stg_sysconsaif_syscfg164 - STG SYSCONSAIF SYSCFG 164 - 0xa4 + intr_stat + DesignWare I2C Interrupt Status + 0x2c 32 - u0_plda_pcie_axi4_slv0_aratomop_255_224 - u0_plda_pcie_axi4_slv0_aratomop_255_224 - [31:0] - read-write + rx_under + RX FIFO Underrun + [0:0] + read-only - - - - stg_sysconsaif_syscfg168 - STG SYSCONSAIF SYSCFG 168 - 0xa8 - 32 - - u0_plda_pcie_axi4_slv0_aratomop_257_256 - u0_plda_pcie_axi4_slv0_aratomop_257_256 - [1:0] - read-write + rx_over + RX FIFO Overrun + [1:1] + read-only - u0_plda_pcie_axi4_slv0_arfunc - u0_plda_pcie_axi4_slv0_arfunc - [16:2] - read-write + rx_full + RX FIFO Full + [2:2] + read-only - u0_plda_pcie_axi4_slv0_arregion - u0_plda_pcie_axi4_slv0_arregion - [20:17] - read-write + tx_over + TX FIFO Overrun + [3:3] + read-only - - - - stg_sysconsaif_syscfg172 - STG SYSCONSAIF SYSCFG 172 - 0xac - 32 - - u0_plda_pcie_axi4_slv0_aruser_31_0 - u0_plda_pcie_axi4_slv0_aruser_31_0 - [31:0] - read-write + tx_empty + TX FIFO Empty + [4:4] + read-only - - - - stg_sysconsaif_syscfg176 - STG SYSCONSAIF SYSCFG 176 - 0xb0 - 32 - - u0_plda_pcie_axi4_slv0_aruser_40_32 - u0_plda_pcie_axi4_slv0_aruser_40_32 - [8:0] - read-write + rd_req + Read Request + [5:5] + read-only - u0_plda_pcie_axi4_slv0_awfunc - u0_plda_pcie_axi4_slv0_awfunc - [23:9] - read-write + tx_abrt + TX Abort + [6:6] + read-only - u0_plda_pcie_axi4_slv0_awregion - u0_plda_pcie_axi4_slv0_awregion - [27:24] - read-write + rx_done + RX Done + [7:7] + read-only - - - - stg_sysconsaif_syscfg180 - STG SYSCONSAIF SYSCFG 180 - 0xb4 - 32 - - u0_plda_pcie_axi4_slv0_awuser_31_0 - u0_plda_pcie_axi4_slv0_awuser_31_0 - [31:0] - read-write + activity + Activity + [8:8] + read-only - - - - stg_sysconsaif_syscfg184 - STG SYSCONSAIF SYSCFG 184 - 0xb8 - 32 - - u0_plda_pcie_axi4_slv0_awuser_40_32 - u0_plda_pcie_axi4_slv0_awuser_40_32 - [8:0] - read-write + stop_det + Stop DET + [9:9] + read-only - u0_plda_pcie_axi4_slv0_rderr - u0_plda_pcie_axi4_slv0_rderr - [16:9] + start_det + Start DET + [10:10] read-only - - - - stg_sysconsaif_syscfg188 - STG SYSCONSAIF SYSCFG 188 - 0xbc - 32 - - u0_plda_pcie_axi4_slv0_ruser - u0_plda_pcie_axi4_slv0_ruser - [31:0] + gen_call + General Call + [11:11] read-only - - - - stg_sysconsaif_syscfg192 - STG SYSCONSAIF SYSCFG 192 - 0xc0 - 32 - - u0_plda_pcie_axi4_slv0_wderr - u0_plda_pcie_axi4_slv0_wderr - [7:0] - read-write + restart_det + Restart DET + [12:12] + read-only - u0_plda_pcie_axi4_slvl_arfunc - u0_plda_pcie_axi4_slvl_arfunc - [22:8] + mst_on_hold + Master on Hold + [13:13] read-only - stg_sysconsaif_syscfg196 - STG SYSCONSAIF SYSCFG 196 - 0xc4 + intr_mask + DesignWare I2C Interrupt Mask + 0x30 32 - u0_plda_pcie_axi4_slvl_awfunc - u0_plda_pcie_axi4_slvl_awfunc - [14:0] + rx_under + RX FIFO Underrun + [0:0] read-write - u0_plda_pcie_bus_width_o - u0_plda_pcie_bus_width_o - [16:15] - read-only + rx_over + RX FIFO Overrun + [1:1] + read-write - u0_plda_pcie_bypass_codec - u0_plda_pcie_bypass_codec - [17:17] + rx_full + RX FIFO Full + [2:2] read-write - u0_plda_pcie_ckref_src - u0_plda_pcie_ckref_src - [19:18] + tx_over + TX FIFO Overrun + [3:3] read-write - u0_plda_pcie_clk_sel - u0_plda_pcie_clk_sel - [21:20] + tx_empty + TX FIFO Empty + [4:4] read-write - u0_plda_pcie_clkreq - u0_plda_pcie_clkreq - [22:22] + rd_req + Read Request + [5:5] read-write - - - - stg_sysconsaif_syscfg200 - STG SYSCONSAIF SYSCFG 200 - 0xc8 - 32 - - u0_plda_pcie_k_phyparam_31_0 - u0_plda_pcie_k_phyparam_31_0 - [31:0] + tx_abrt + TX Abort + [6:6] read-write - - - - stg_sysconsaif_syscfg204 - STG SYSCONSAIF SYSCFG 204 - 0xcc - 32 - - u0_plda_pcie_k_phyparam_63_32 - u0_plda_pcie_k_phyparam_63_32 - [31:0] + rx_done + RX Done + [7:7] read-write - - - - stg_sysconsaif_syscfg208 - STG SYSCONSAIF SYSCFG 208 - 0xd0 - 32 - - u0_plda_pcie_k_phyparam_95_64 - u0_plda_pcie_k_phyparam_95_64 - [31:0] + activity + Activity + [8:8] read-write - - - - stg_sysconsaif_syscfg212 - STG SYSCONSAIF SYSCFG 212 - 0xd4 - 32 - - u0_plda_pcie_k_phyparam_127_96 - u0_plda_pcie_k_phyparam_127_96 - [31:0] + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] read-write - stg_sysconsaif_syscfg216 - STG SYSCONSAIF SYSCFG 216 - 0xd8 + raw_intr_stat + DesignWare I2C Raw Interrupt Status + 0x34 32 - u0_plda_pcie_k_phyparam_159_128 - u0_plda_pcie_k_phyparam_159_128 - [31:0] - read-write + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only - stg_sysconsaif_syscfg220 - STG SYSCONSAIF SYSCFG 220 - 0xdc + rx_tl + DesignWare I2C RX TL + 0x38 32 - u0_plda_pcie_k_phyparam_191_160 - u0_plda_pcie_k_phyparam_191_160 + rx_tl + rx_tl [31:0] read-write - stg_sysconsaif_syscfg224 - STG SYSCONSAIF SYSCFG 224 - 0xe0 + tx_tl + DesignWare I2C TX TL + 0x3c 32 - u0_plda_pcie_k_phyparam_223_192 - u0_plda_pcie_k_phyparam_223_192 + tx_tl + tx_tl [31:0] read-write - stg_sysconsaif_syscfg228 - STG SYSCONSAIF SYSCFG 228 - 0xe4 + clr_intr + DesignWare I2C Clear Interrrupt + 0x40 32 - u0_plda_pcie_k_phyparam_255_224 - u0_plda_pcie_k_phyparam_255_224 - [31:0] + rx_under + RX FIFO Underrun + [0:0] read-write - - - - stg_sysconsaif_syscfg232 - STG SYSCONSAIF SYSCFG 232 - 0xe8 - 32 - - u0_plda_pcie_k_phyparam_287_256 - u0_plda_pcie_k_phyparam_287_256 - [31:0] + rx_over + RX FIFO Overrun + [1:1] read-write - - - - stg_sysconsaif_syscfg236 - STG SYSCONSAIF SYSCFG 236 - 0xec - 32 - - u0_plda_pcie_k_phyparam_319_288 - u0_plda_pcie_k_phyparam_319_288 - [31:0] + rx_full + RX FIFO Full + [2:2] read-write - - - - stg_sysconsaif_syscfg240 - STG SYSCONSAIF SYSCFG 240 - 0xf0 - 32 - - u0_plda_pcie_k_phyparam_351_320 - u0_plda_pcie_k_phyparam_351_320 - [31:0] + tx_over + TX FIFO Overrun + [3:3] read-write - - - - stg_sysconsaif_syscfg244 - STG SYSCONSAIF SYSCFG 244 - 0xf4 - 32 - - u0_plda_pcie_k_phyparam_383_352 - u0_plda_pcie_k_phyparam_383_352 - [31:0] + tx_empty + TX FIFO Empty + [4:4] read-write - - - - stg_sysconsaif_syscfg248 - STG SYSCONSAIF SYSCFG 248 - 0xf8 - 32 - - u0_plda_pcie_k_phyparam_415_384 - u0_plda_pcie_k_phyparam_415_384 - [31:0] + rd_req + Read Request + [5:5] + read-write + + + tx_abrt + TX Abort + [6:6] + read-write + + + rx_done + RX Done + [7:7] + read-write + + + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] read-write - stg_sysconsaif_syscfg252 - STG SYSCONSAIF SYSCFG 252 - 0xfc + clr_rx_under + DesignWare I2C Clear RX Underrun + 0x44 32 - u0_plda_pcie_k_phyparam_447_416 - u0_plda_pcie_k_phyparam_447_416 + clr_rx_under + clr_rx_under [31:0] read-write - stg_sysconsaif_syscfg256 - STG SYSCONSAIF SYSCFG 256 - 0x100 + clr_rx_over + DesignWare I2C Clear RX Overrun + 0x48 32 - u0_plda_pcie_k_phyparam_479_448 - u0_plda_pcie_k_phyparam_479_448 + clr_rx_over + clr_rx_over [31:0] read-write - stg_sysconsaif_syscfg260 - STG SYSCONSAIF SYSCFG 260 - 0x104 + clr_tx_over + DesignWare I2C Clear TX Overrun + 0x4c 32 - u0_plda_pcie_k_phyparam_511_480 - u0_plda_pcie_k_phyparam_511_480 + clr_tx_over + clr_tx_over [31:0] read-write - stg_sysconsaif_syscfg264 - STG SYSCONSAIF SYSCFG 264 - 0x108 + clr_rd_req + DesignWare I2C Clear Read Request + 0x50 32 - u0_plda_pcie_k_phyparam_543_512 - u0_plda_pcie_k_phyparam_543_512 + clr_rd_req + clr_rd_req [31:0] read-write - stg_sysconsaif_syscfg268 - STG SYSCONSAIF SYSCFG 268 - 0x10c + clr_tx_abrt + DesignWare I2C Clear TX Abort + 0x54 32 - u0_plda_pcie_k_phyparam_575_544 - u0_plda_pcie_k_phyparam_575_544 + clr_tx_abrt + clr_tx_abrt [31:0] read-write - stg_sysconsaif_syscfg272 - STG SYSCONSAIF SYSCFG 272 - 0x110 + clr_rx_done + DesignWare I2C Clear RX Done + 0x58 32 - u0_plda_pcie_k_phyparam_607_576 - u0_plda_pcie_k_phyparam_607_576 + clr_rx_done + clr_rx_done [31:0] read-write - stg_sysconsaif_syscfg276 - STG SYSCONSAIF SYSCFG 276 - 0x114 + clr_activity + DesignWare I2C Clear Activity + 0x5c 32 - u0_plda_pcie_k_phyparam_639_608 - u0_plda_pcie_k_phyparam_639_608 + clr_activity + clr_activity [31:0] read-write - stg_sysconsaif_syscfg280 - STG SYSCONSAIF SYSCFG 280 - 0x118 + clr_stop_det + DesignWare I2C Clear Stop DET + 0x60 32 - u0_plda_pcie_k_phyparam_671_640 - u0_plda_pcie_k_phyparam_671_640 + clr_stop_det + clr_stop_det [31:0] read-write - stg_sysconsaif_syscfg284 - STG SYSCONSAIF SYSCFG 284 - 0x11c + clr_start_det + DesignWare I2C Clear Start DET + 0x64 32 - u0_plda_pcie_k_phyparam_703_672 - u0_plda_pcie_k_phyparam_703_672 + clr_start_det + clr_start_det [31:0] read-write - stg_sysconsaif_syscfg288 - STG SYSCONSAIF SYSCFG 288 - 0x120 + clr_gen_call + DesignWare I2C Clear General Call + 0x68 32 - u0_plda_pcie_k_phyparam_735_704 - u0_plda_pcie_k_phyparam_735_704 + clr_gen_call + clr_gen_call [31:0] read-write - stg_sysconsaif_syscfg292 - STG SYSCONSAIF SYSCFG 292 - 0x124 + enable + DesignWare I2C Enable + 0x6c 32 - u0_plda_pcie_k_phyparam_767_736 - u0_plda_pcie_k_phyparam_767_736 - [31:0] + abort + abort + [1:1] read-write - stg_sysconsaif_syscfg296 - STG SYSCONSAIF SYSCFG 296 - 0x128 + status + DesignWare I2C Status + 0x70 32 - u0_plda_pcie_k_phyparam_799_768 - u0_plda_pcie_k_phyparam_799_768 - [31:0] - read-write + activity + activity + [0:0] + read-only + + + tfe + tfe + [2:2] + read-only + + + rfne + rfne + [3:3] + read-only + + + master_activity + master_activity + [5:5] + read-only + + + slave_activity + slave_activity + [6:6] + read-only - stg_sysconsaif_syscfg300 - STG SYSCONSAIF SYSCFG 300 - 0x12c + txflr + DesignWare I2C TX Failure + 0x74 32 - u0_plda_pcie_k_phyparam_831_800 - u0_plda_pcie_k_phyparam_831_800 + txflr + txflr [31:0] read-write - stg_sysconsaif_syscfg304 - STG SYSCONSAIF SYSCFG 304 - 0x130 + rxflr + DesignWare I2C RX Failure + 0x78 32 - u0_plda_pcie_k_phyparam_839_832 - u0_plda_pcie_k_phyparam_839_832 - [7:0] - read-write - - - u0_plda_pcie_k_rp_nep - u0_plda_pcie_k_rp_nep - [8:8] - read-write - - - u0_plda_pcie_l1sub_entack - u0_plda_pcie_l1sub_entack - [9:9] - read-only - - - u0_plda_pcie_l1sub_entreq - u0_plda_pcie_l1sub_entreq - [10:10] + rxflr + rxflr + [31:0] read-write - stg_sysconsaif_syscfg308 - STG SYSCONSAIF SYSCFG 308 - 0x134 + sda_hold + DesignWare I2C SDA Hold + 0x7c 32 - u0_plda_pcie_local_interrupt_in - u0_plda_pcie_local_interrupt_in + sda_hold + sda_hold [31:0] read-write - stg_sysconsaif_syscfg312 - STG SYSCONSAIF SYSCFG 312 - 0x138 + tx_abrt_source + DesignWare I2C TX Abort Source + 0x80 32 - u0_plda_pcie_mperstn - u0_plda_pcie_mperstn + b7_addr_noack + b7_addr_noack [0:0] - read-write + read-only - u0_plda_pcie_pcie_ebuf_mode - u0_plda_pcie_pcie_ebuf_mode + b10_addr1_noack + b10_addr1_noack [1:1] - read-write + read-only - u0_plda_pcie_pcie_phy_test_cfg - u0_plda_pcie_pcie_phy_test_cfg - [24:2] - read-write + b10_addr2_noack + b10_addr2_noack + [2:2] + read-only - u0_plda_pcie_pcie_rx_eq_training - u0_plda_pcie_pcie_rx_eq_training - [25:25] - read-write + txdata_noack + txdata_noack + [3:3] + read-only - u0_plda_pcie_pcie_rxterm_en - u0_plda_pcie_pcie_rxterm_en - [26:26] - read-write + gcall_noack + gcall_noack + [4:4] + read-only - u0_plda_pcie_pcie_tx_onezeros - u0_plda_pcie_pcie_tx_onezeros - [27:27] - read-write + gcall_read + gcall_read + [5:5] + read-only - - - - stg_sysconsaif_syscfg316 - STG SYSCONSAIF SYSCFG 316 - 0x13c - 32 - - u0_plda_pcie_pf0_offset - u0_plda_pcie_pf0_offset - [19:0] - read-write + sbyte_ackdet + sbyte_ackdet + [7:7] + read-only - - - - stg_sysconsaif_syscfg320 - STG SYSCONSAIF SYSCFG 320 - 0x140 - 32 - - u0_plda_pcie_pf1_offset - u0_plda_pcie_pf1_offset - [19:0] - read-write + sbyte_norstrt + sbyte_norstrt + [9:9] + read-only - - - - stg_sysconsaif_syscfg324 - STG SYSCONSAIF SYSCFG 324 - 0x144 - 32 - - u0_plda_pcie_pf2_offset - u0_plda_pcie_pf2_offset - [19:0] - read-write + b10_rd_norstrt + b10_rd_norstrt + [10:10] + read-only + + + master_dis + master_dis + [11:11] + read-only + + + arb_lost + arb_lost + [12:12] + read-only + + + slave_flush_txfifo + slave_flush_txfifo + [13:13] + read-only + + + slave_arblost + slave_arblost + [14:14] + read-only + + + slave_rd_intx + slave_rd_intx + [15:15] + read-only - stg_sysconsaif_syscfg328 - STG SYSCONSAIF SYSCFG 328 - 0x148 + enable_status + DesignWare I2C Enable Status + 0x9c 32 - u0_plda_pcie_pf3_offset - u0_plda_pcie_pf3_offset - [19:0] + activity + activity + [0:0] read-write - u0_plda_pcie_phy_mode - u0_plda_pcie_phy_mode - [21:20] + tfe + tfe + [2:2] read-write - u0_plda_pcie_pl_clkrem_allow - u0_plda_pcie_pl_clkrem_allow - [22:22] + rfne + rfne + [3:3] read-write - u0_plda_pcie_pl_clkreq_oen - u0_plda_pcie_pl_clkreq_oen - [23:23] - read-only - - - u0_plda_pcie_pl_equ_phase - u0_plda_pcie_pl_equ_phase - [25:24] - read-only + master_activity + master_activity + [5:5] + read-write - u0_plda_pcie_pl_ltssm - u0_plda_pcie_pl_ltssm - [30:26] - read-only + slave_activity + slave_activity + [6:6] + read-write - stg_sysconsaif_syscfg332 - STG SYSCONSAIF SYSCFG 332 - 0x14c + clr_restart_det + DesignWare I2C Clear Restart DET + 0xa8 32 - u0_plda_pcie_pl_pclk_rate - u0_plda_pcie_pl_pclk_rate - [4:0] - read-only + clr_restart_det + clr_restart_det + [31:0] + read-write - stg_sysconsaif_syscfg336 - STG SYSCONSAIF SYSCFG 336 - 0x150 + comp_param_1 + DesignWare I2C Compatibility Parameter 1 + 0xf4 32 - u0_plda_pcie_pl_sideband_in_31_0 - u0_plda_pcie_pl_sideband_in_31_0 - [31:0] + speed + Speed mask - 01: Standard, 10: Full, 11: High + [3:2] read-only - stg_sysconsaif_syscfg340 - STG SYSCONSAIF SYSCFG 340 - 0x154 + comp_version + DesignWare I2C Compatibility Version + 0xf8 32 - u0_plda_pcie_pl_sideband_in_63_32 - u0_plda_pcie_pl_sideband_in_63_32 + comp_version + comp_version [31:0] read-only - stg_sysconsaif_syscfg344 - STG SYSCONSAIF SYSCFG 344 - 0x158 + comp_type + DesignWare I2C Compatibility Type + 0xfc 32 - u0_plda_pcie_pl_sideband_out_31_0 - u0_plda_pcie_pl_sideband_out_31_0 + comp_type + comp_type [31:0] read-only + + + + arm_pl022_0 + From arm,pl022, peripheral generator + 0x10060000 + + 0 + 0x10000 + registers + + - stg_sysconsaif_syscfg348 - STG SYSCONSAIF SYSCFG 348 - 0x15c - 32 + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. + 0x0 + 16 - u0_plda_pcie_pl_sideband_out_63_32 - u0_plda_pcie_pl_sideband_out_63_32 - [31:0] - read-only + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] + read-write + + + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] + read-write + + + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] + read-write - stg_sysconsaif_syscfg352 - STG SYSCONSAIF SYSCFG 352 - 0x160 - 32 + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. + 0x4 + 16 - u0_plda_pcie_pl_wake_in - u0_plda_pcie_pl_wake_in + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally [0:0] read-write - u0_plda_pcie_pl_wake_oen - u0_plda_pcie_pl_wake_oen + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled [1:1] - read-only + read-write - u0_plda_pcie_rx_standby_0 - u0_plda_pcie_rx_standby_0 + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave [2:2] - read-only + read-write - - - - stg_sysconsaif_syscfg356 - STG SYSCONSAIF SYSCFG 356 - 0x164 - 32 - - u0_plda_pcie_test_in_31_0 - u0_plda_pcie_test_in_31_0 - [31:0] + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode + [3:3] read-write - stg_sysconsaif_syscfg360 - STG SYSCONSAIF SYSCFG 360 - 0x168 - 32 + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 - u0_plda_pcie_test_in_63_32 - u0_plda_pcie_test_in_63_32 - [31:0] + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] read-write - stg_sysconsaif_syscfg364 - STG SYSCONSAIF SYSCFG 364 - 0x16c - 32 + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 - u0_plda_pcie_test_out_bridge_31_0 - u0_plda_pcie_test_out_bridge_31_0 - [31:0] + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. + [0:0] read-only - - - - stg_sysconsaif_syscfg368 - STG SYSCONSAIF SYSCFG 368 - 0x170 - 32 - - u0_plda_pcie_test_out_bridge_63_32 - u0_plda_pcie_test_out_bridge_63_32 - [31:0] + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. + [1:1] read-only - - - - stg_sysconsaif_syscfg372 - STG SYSCONSAIF SYSCFG 372 - 0x174 - 32 - - u0_plda_pcie_test_out_bridge_95_64 - u0_plda_pcie_test_out_bridge_95_64 - [31:0] + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. + [2:2] + read-only + + + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. + [3:3] + read-only + + + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] read-only - stg_sysconsaif_syscfg376 - STG SYSCONSAIF SYSCFG 376 - 0x178 - 32 + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 - u0_plda_pcie_test_out_bridge_127_96 - u0_plda_pcie_test_out_bridge_127_96 - [31:0] - read-only + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] + read-write - stg_sysconsaif_syscfg380 - STG SYSCONSAIF SYSCFG 380 - 0x17c - 32 + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 - u0_plda_pcie_test_out_bridge_159_128 - u0_plda_pcie_test_out_bridge_159_128 - [31:0] - read-only + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked + [0:0] + read-write - - - - stg_sysconsaif_syscfg384 - STG SYSCONSAIF SYSCFG 384 - 0x180 - 32 - - u0_plda_pcie_test_out_bridge_191_160 - u0_plda_pcie_test_out_bridge_191_160 - [31:0] - read-only + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked + [1:1] + read-write - - - - stg_sysconsaif_syscfg388 - STG SYSCONSAIF SYSCFG 388 - 0x184 - 32 - - u0_plda_pcie_test_out_bridge_223_192 - u0_plda_pcie_test_out_bridge_223_192 - [31:0] - read-only + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked + [2:2] + read-write + + + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] + read-write - stg_sysconsaif_syscfg392 - STG SYSCONSAIF SYSCFG 392 - 0x188 - 32 + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 - u0_plda_pcie_test_out_bridge_255_224 - u0_plda_pcie_test_out_bridge_255_224 - [31:0] + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] read-only - - - - stg_sysconsaif_syscfg396 - STG SYSCONSAIF SYSCFG 396 - 0x18c - 32 - - u0_plda_pcie_test_out_bridge_287_256 - u0_plda_pcie_test_out_bridge_287_256 - [31:0] + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] read-only - - - - stg_sysconsaif_syscfg400 - STG SYSCONSAIF SYSCFG 400 - 0x190 - 32 - - u0_plda_pcie_test_out_bridge_319_288 - u0_plda_pcie_test_out_bridge_319_288 - [31:0] + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] read-only - - - - stg_sysconsaif_syscfg404 - STG SYSCONSAIF SYSCFG 404 - 0x194 - 32 - - u0_plda_pcie_test_out_bridge_351_320 - u0_plda_pcie_test_out_bridge_351_320 - [31:0] + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] read-only - stg_sysconsaif_syscfg408 - STG SYSCONSAIF SYSCFG 408 - 0x198 - 32 + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 - u0_plda_pcie_test_out_bridge_383_352 - u0_plda_pcie_test_out_bridge_383_352 - [31:0] + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] read-only - - - - stg_sysconsaif_syscfg412 - STG SYSCONSAIF SYSCFG 412 - 0x19c - 32 - - u0_plda_pcie_test_out_bridge_415_384 - u0_plda_pcie_test_out_bridge_415_384 - [31:0] + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] read-only - - - - stg_sysconsaif_syscfg416 - STG SYSCONSAIF SYSCFG 416 - 0x1a0 - 32 - - u0_plda_pcie_test_out_bridge_447_416 - u0_plda_pcie_test_out_bridge_447_416 - [31:0] + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] read-only - - - - stg_sysconsaif_syscfg420 - STG SYSCONSAIF SYSCFG 420 - 0x1a4 - 32 - - u0_plda_pcie_test_out_bridge_479_448 - u0_plda_pcie_test_out_bridge_479_448 - [31:0] + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] read-only - stg_sysconsaif_syscfg424 - STG SYSCONSAIF SYSCFG 424 - 0x1a8 - 32 + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 - u0_plda_pcie_test_out_bridge_511_480 - u0_plda_pcie_test_out_bridge_511_480 - [31:0] - read-only + roric + Clears the SSPRORINTR interrupt + [0:0] + read-write + + + rtic + Clears the SSPRTINTR interrupt + [1:1] + read-write - stg_sysconsaif_syscfg428 - STG SYSCONSAIF SYSCFG 428 - 0x1ac - 32 + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 - u0_plda_pcie_test_out_pcie_31_0 - u0_plda_pcie_test_out_pcie_31_0 - [31:0] - read-only + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write - stg_sysconsaif_syscfg432 - STG SYSCONSAIF SYSCFG 432 - 0x1b0 - 32 + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 - u0_plda_pcie_test_out_pcie_63_32 - u0_plda_pcie_test_out_pcie_63_32 - [31:0] + part_number0 + These bits read back as 0x22 + [7:0] read-only - stg_sysconsaif_syscfg436 - STG SYSCONSAIF SYSCFG 436 - 0x1b4 - 32 + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 - u0_plda_pcie_test_out_pcie_95_64 - u0_plda_pcie_test_out_pcie_95_64 - [31:0] + part_number1 + These bits read back as 0x0 + [3:0] read-only - - - - stg_sysconsaif_syscfg440 - STG SYSCONSAIF SYSCFG 440 - 0x1b8 - 32 - - u0_plda_pcie_test_out_pcie_127_96 - u0_plda_pcie_test_out_pcie_127_96 - [31:0] + designer0 + These bits read back as 0x1 + [7:4] read-only - stg_sysconsaif_syscfg444 - STG SYSCONSAIF SYSCFG 444 - 0x1bc - 32 + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 - u0_plda_pcie_test_out_pcie_159_128 - u0_plda_pcie_test_out_pcie_159_128 - [31:0] + designer1 + These bits read back as 0x4 + [3:0] read-only - - - - stg_sysconsaif_syscfg448 - STG SYSCONSAIF SYSCFG 448 - 0x1c0 - 32 - - u0_plda_pcie_test_out_pcie_191_160 - u0_plda_pcie_test_out_pcie_191_160 - [31:0] + revision + These bits return the peripheral revision + [7:4] read-only - stg_sysconsaif_syscfg452 - STG SYSCONSAIF SYSCFG 452 - 0x1c4 - 32 + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 - u0_plda_pcie_test_out_pcie_223_192 - u0_plda_pcie_test_out_pcie_223_192 - [31:0] + configuration + These bits read back as 0x80 + [7:0] read-only - stg_sysconsaif_syscfg456 - STG SYSCONSAIF SYSCFG 456 - 0x1c8 - 32 + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 - u0_plda_pcie_test_out_pcie_255_224 - u0_plda_pcie_test_out_pcie_255_224 - [31:0] + ssp_pcell_id0 + The bits are read as 0xD + [7:0] read-only - stg_sysconsaif_syscfg460 - STG SYSCONSAIF SYSCFG 460 - 0x1cc - 32 + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 - u0_plda_pcie_test_out_pcie_287_256 - u0_plda_pcie_test_out_pcie_287_256 - [31:0] + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] read-only - stg_sysconsaif_syscfg464 - STG SYSCONSAIF SYSCFG 464 - 0x1d0 - 32 + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 - u0_plda_pcie_test_out_pcie_319_288 - u0_plda_pcie_test_out_pcie_319_288 - [31:0] + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] read-only - stg_sysconsaif_syscfg468 - STG SYSCONSAIF SYSCFG 468 - 0x1d4 - 32 + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 - u0_plda_pcie_test_out_pcie_351_320 - u0_plda_pcie_test_out_pcie_351_320 - [31:0] + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] read-only - - stg_sysconsaif_syscfg472 - STG SYSCONSAIF SYSCFG 472 - 0x1d8 - 32 + + + + arm_primecell_0 + From arm,primecell, peripheral generator + 0x10060000 + + 0 + 0x10000 + registers + + + + rohm_dh2228fv_0 + From rohm,dh2228fv, peripheral generator + 0x0 + + 0 + 0x0 + registers + + + + arm_pl022_1 + From arm,pl022, peripheral generator + 0x10070000 + + 0 + 0x10000 + registers + + + + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. + 0x0 + 16 - u0_plda_pcie_test_out_pcie_383_352 - u0_plda_pcie_test_out_pcie_383_352 - [31:0] - read-only + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] + read-write + + + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] + read-write + + + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] + read-write - stg_sysconsaif_syscfg476 - STG SYSCONSAIF SYSCFG 476 - 0x1dc - 32 + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. + 0x4 + 16 - u0_plda_pcie_test_out_pcie_415_384 - u0_plda_pcie_test_out_pcie_415_384 - [31:0] - read-only + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally + [0:0] + read-write + + + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled + [1:1] + read-write + + + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave + [2:2] + read-write + + + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode + [3:3] + read-write - stg_sysconsaif_syscfg480 - STG SYSCONSAIF SYSCFG 480 - 0x1e0 - 32 + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 - u0_plda_pcie_test_out_pcie_447_416 - u0_plda_pcie_test_out_pcie_447_416 - [31:0] - read-only + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] + read-write - stg_sysconsaif_syscfg484 - STG SYSCONSAIF SYSCFG 484 - 0x1e4 - 32 + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 - u0_plda_pcie_test_out_pcie_479_448 - u0_plda_pcie_test_out_pcie_479_448 - [31:0] + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. + [0:0] read-only - - - - stg_sysconsaif_syscfg488 - STG SYSCONSAIF SYSCFG 488 - 0x1e8 - 32 - - u0_plda_pcie_test_out_pcie_511_480 - u0_plda_pcie_test_out_pcie_511_480 - [31:0] + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. + [1:1] + read-only + + + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. + [2:2] + read-only + + + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. + [3:3] + read-only + + + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] read-only - stg_sysconsaif_syscfg492 - STG SYSCONSAIF SYSCFG 492 - 0x1ec - 32 + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 - u0_plda_pcie_test_sel - u0_plda_pcie_test_sel - [3:0] - read-write - - - u0_plda_pcie_tl_clock_freq - u0_plda_pcie_tl_clock_freq - [25:4] + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] read-write - stg_sysconsaif_syscfg500 - STG SYSCONSAIF SYSCFG 500 - 0x1f4 - 32 + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 - u0_plda_pcie_tx_pattern - u0_plda_pcie_tx_pattern - [1:0] + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked + [0:0] read-write - u0_plda_pcie_usb3_bus_width - u0_plda_pcie_usb3_bus_width - [3:2] + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked + [1:1] read-write - u0_plda_pcie_usb3_phy_enable - u0_plda_pcie_usb3_phy_enable - [4:4] + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked + [2:2] read-write - u0_plda_pcie_usb3_rate - u0_plda_pcie_usb3_rate - [6:5] + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] read-write + + + + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 + - u0_plda_pcie_usb3_rx_standby - u0_plda_pcie_usb3_rx_standby - [7:7] - read-write + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only - u0_plda_pcie_xwdecerr - u0_plda_pcie_xwdecerr - [8:8] + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] read-only - u0_plda_pcie_xwerrclr - u0_plda_pcie_xwerrclr - [9:9] - read-write + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only - u0_plda_pcie_xwslverr - u0_plda_pcie_xwslverr - [10:10] + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] read-only + + + + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 + - u0_sec_top_sramcfg_slp - SRAM/ROM configuration. SLP: sleep enable, high active, default is low. - [11:11] - read-write + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only - u0_sec_top_sramcfg_sram_config_sd - SRAM/ROM configuration. SD: shutdown enable, high active, default is low. - [12:12] - read-write + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only - u0_sec_top_sramcfg_rtsel - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. - [14:13] - read-write + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only - u0_sec_top_sramcfg_ptsel - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. - [16:15] - read-write + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 + - u0_sec_top_sramcfg_trb - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. - [18:17] + roric + Clears the SSPRORINTR interrupt + [0:0] read-write - u0_sec_top_sramcfg_wtsel - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. - [20:19] + rtic + Clears the SSPRTINTR interrupt + [1:1] read-write + + + + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 + - u0_sec_top_sramcfg_vs - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. - [21:21] + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] read-write - u0_sec_top_sramcfg_vg - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. - [22:22] + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] read-write - - u0_plda_pcie_align_detect - u0_plda_pcie_align_detect - [23:23] - read-only - - stg_sysconsaif_syscfg504 - STG SYSCONSAIF SYSCFG 504 - 0x1f8 - 32 + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 - u0_plda_pcie_axi4_mst0_aratomop_31_0 - u0_plda_pcie_axi4_mst0_aratomop_31_0 - [31:0] + part_number0 + These bits read back as 0x22 + [7:0] read-only - stg_sysconsaif_syscfg508 - STG SYSCONSAIF SYSCFG 508 - 0x1fc - 32 + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 - u0_plda_pcie_axi4_mst0_aratomop_63_32 - u0_plda_pcie_axi4_mst0_aratomop_63_32 - [31:0] + part_number1 + These bits read back as 0x0 + [3:0] + read-only + + + designer0 + These bits read back as 0x1 + [7:4] read-only - stg_sysconsaif_syscfg512 - STG SYSCONSAIF SYSCFG 512 - 0x200 - 32 + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 - u0_plda_pcie_axi4_mst0_aratomop_95_64 - u0_plda_pcie_axi4_mst0_aratomop_95_64 - [31:0] + designer1 + These bits read back as 0x4 + [3:0] + read-only + + + revision + These bits return the peripheral revision + [7:4] read-only - stg_sysconsaif_syscfg516 - STG SYSCONSAIF SYSCFG 516 - 0x204 - 32 + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 - u0_plda_pcie_axi4_mst0_aratomop_127_96 - u0_plda_pcie_axi4_mst0_aratomop_127_96 - [31:0] + configuration + These bits read back as 0x80 + [7:0] read-only - stg_sysconsaif_syscfg520 - STG SYSCONSAIF SYSCFG 520 - 0x208 - 32 + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 - u0_plda_pcie_axi4_mst0_aratomop_159_128 - u0_plda_pcie_axi4_mst0_aratomop_159_128 - [31:0] + ssp_pcell_id0 + The bits are read as 0xD + [7:0] read-only - stg_sysconsaif_syscfg524 - STG SYSCONSAIF SYSCFG 524 - 0x20c - 32 + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 - u0_plda_pcie_axi4_mst0_aratomop_191_160 - u0_plda_pcie_axi4_mst0_aratomop_191_160 - [31:0] + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] read-only - stg_sysconsaif_syscfg528 - STG SYSCONSAIF SYSCFG 528 - 0x210 - 32 + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 - u0_plda_pcie_axi4_mst0_aratomop_223_192 - u0_plda_pcie_axi4_mst0_aratomop_223_192 - [31:0] + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] read-only - stg_sysconsaif_syscfg532 - STG SYSCONSAIF SYSCFG 532 - 0x214 - 32 + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 - u0_plda_pcie_axi4_mst0_aratomop_255_224 - u0_plda_pcie_axi4_mst0_aratomop_255_224 - [31:0] + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] read-only + + + + arm_primecell_1 + From arm,primecell, peripheral generator + 0x10070000 + + 0 + 0x10000 + registers + + + + arm_pl022_2 + From arm,pl022, peripheral generator + 0x10080000 + + 0 + 0x10000 + registers + + - stg_sysconsaif_syscfg536 - STG SYSCONSAIF SYSCFG 536 - 0x218 - 32 + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. + 0x0 + 16 - u0_plda_pcie_axi4_mst0_aratomop_257_256 - u0_plda_pcie_axi4_mst0_aratomop_257_256 - [1:0] - read-only + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] + read-write - u0_plda_pcie_axi4_mst0_arfunc - u0_plda_pcie_axi4_mst0_arfunc - [16:2] - read-only + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] + read-write - u0_plda_pcie_axi4_mst0_arregion - u0_plda_pcie_axi4_mst0_arregion - [20:17] - read-only + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] + read-write - stg_sysconsaif_syscfg540 - STG SYSCONSAIF SYSCFG 540 - 0x21c - 32 + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. + 0x4 + 16 - u1_plda_pcie_axi4_mst0_aruser_31_0 - u1_plda_pcie_axi4_mst0_aruser_31_0 - [31:0] - read-only + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally + [0:0] + read-write + + + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled + [1:1] + read-write + + + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave + [2:2] + read-write + + + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode + [3:3] + read-write - stg_sysconsaif_syscfg544 - STG SYSCONSAIF SYSCFG 544 - 0x220 - 32 + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 - u1_plda_pcie_axi4_mst0_aruser_52_32 - u1_plda_pcie_axi4_mst0_aruser_52_32 - [20:0] - read-only + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] + read-write - stg_sysconsaif_syscfg548 - STG SYSCONSAIF SYSCFG 548 - 0x224 - 32 + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 - u1_plda_pcie_axi4_mst0_awfunc - u1_plda_pcie_axi4_mst0_awfunc - [14:0] + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. + [0:0] read-only - u1_plda_pcie_axi4_mst0_awregion - u1_plda_pcie_axi4_mst0_awregion - [18:15] + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. + [1:1] read-only - - - - stg_sysconsaif_syscfg552 - STG SYSCONSAIF SYSCFG 552 - 0x228 - 32 - - u1_plda_pcie_axi4_mst0_awuser_31_0 - u1_plda_pcie_axi4_mst0_awuser_31_0 - [31:0] + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. + [2:2] read-only - - - - stg_sysconsaif_syscfg556 - STG SYSCONSAIF SYSCFG 556 - 0x22c - 32 - - u1_plda_pcie_axi4_mst0_awuser_42_32 - u1_plda_pcie_axi4_mst0_awuser_42_32 - [10:0] + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. + [3:3] read-only - u1_plda_pcie_axi4_mst0_rderr - u1_plda_pcie_axi4_mst0_rderr - [18:11] - read-write + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only - stg_sysconsaif_syscfg560 - STG SYSCONSAIF SYSCFG 560 - 0x230 - 32 + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 - u1_plda_pcie_axi4_mst0_ruser - u1_plda_pcie_axi4_mst0_ruser - [31:0] + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] read-write - stg_sysconsaif_syscfg564 - STG SYSCONSAIF SYSCFG 564 - 0x234 - 32 + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 - u1_plda_pcie_axi4_mst0_wderr - u1_plda_pcie_axi4_mst0_wderr - [7:0] - read-only + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked + [0:0] + read-write - - - - stg_sysconsaif_syscfg568 - STG SYSCONSAIF SYSCFG 568 - 0x238 - 32 - - u1_plda_pcie_axi4_slv0_aratomop_31_0 - u1_plda_pcie_axi4_slv0_aratomop_31_0 - [31:0] + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked + [1:1] read-write - - - - stg_sysconsaif_syscfg572 - STG SYSCONSAIF SYSCFG 572 - 0x23c - 32 - - u1_plda_pcie_axi4_slv0_aratomop_63_32 - u1_plda_pcie_axi4_slv0_aratomop_63_32 - [31:0] + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked + [2:2] read-write - - - - stg_sysconsaif_syscfg576 - STG SYSCONSAIF SYSCFG 576 - 0x240 - 32 - - u1_plda_pcie_axi4_slv0_aratomop_95_64 - u1_plda_pcie_axi4_slv0_aratomop_95_64 - [31:0] + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] read-write - stg_sysconsaif_syscfg580 - STG SYSCONSAIF SYSCFG 580 - 0x244 - 32 + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 - u1_plda_pcie_axi4_slv0_aratomop_127_96 - u1_plda_pcie_axi4_slv0_aratomop_127_96 - [31:0] - read-write + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only - - - - stg_sysconsaif_syscfg584 - STG SYSCONSAIF SYSCFG 584 - 0x248 - 32 - - - u1_plda_pcie_axi4_slv0_aratomop_159_128 - u1_plda_pcie_axi4_slv0_aratomop_159_128 - [31:0] - read-write - - - - - stg_sysconsaif_syscfg588 - STG SYSCONSAIF SYSCFG 588 - 0x24c - 32 - - u1_plda_pcie_axi4_slv0_aratomop_191_160 - u1_plda_pcie_axi4_slv0_aratomop_191_160 - [31:0] - read-write + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only - - - - stg_sysconsaif_syscfg592 - STG SYSCONSAIF SYSCFG 592 - 0x250 - 32 - - u1_plda_pcie_axi4_slv0_aratomop_223_192 - u1_plda_pcie_axi4_slv0_aratomop_223_192 - [31:0] - read-write + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only - - - - stg_sysconsaif_syscfg596 - STG SYSCONSAIF SYSCFG 596 - 0x254 - 32 - - u1_plda_pcie_axi4_slv0_aratomop_255_224 - u1_plda_pcie_axi4_slv0_aratomop_255_224 - [31:0] - read-write + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only - stg_sysconsaif_syscfg600 - STG SYSCONSAIF SYSCFG 600 - 0x258 - 32 + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 - u1_plda_pcie_axi4_mst0_aratomop_257_256 - u1_plda_pcie_axi4_mst0_aratomop_257_256 - [1:0] - read-write + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only - u1_plda_pcie_axi4_slv0_arfunc - u1_plda_pcie_axi4_slv0_arfunc - [16:2] - read-write + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only - u1_plda_pcie_axi4_slv0_arregion - u1_plda_pcie_axi4_slv0_arregion - [20:17] - read-write + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only - - - - stg_sysconsaif_syscfg604 - STG SYSCONSAIF SYSCFG 604 - 0x25c - 32 - - u1_plda_pcie_axi4_slv0_aruser_31_0 - u1_plda_pcie_axi4_slv0_aruser_31_0 - [31:0] - read-write + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only - stg_sysconsaif_syscfg608 - STG SYSCONSAIF SYSCFG 608 - 0x260 - 32 + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 - u1_plda_pcie_axi4_slv0_aruser_40_32 - u1_plda_pcie_axi4_slv0_aruser_40_32 - [8:0] - read-write - - - u1_plda_pcie_axi4_slv0_awfunc - u1_plda_pcie_axi4_slv0_awfunc - [23:9] + roric + Clears the SSPRORINTR interrupt + [0:0] read-write - u1_plda_pcie_axi4_slv0_awregion - u1_plda_pcie_axi4_slv0_awregion - [27:24] + rtic + Clears the SSPRTINTR interrupt + [1:1] read-write - stg_sysconsaif_syscfg612 - STG SYSCONSAIF SYSCFG 612 - 0x264 - 32 + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 - u1_plda_pcie_axi4_slv0_awuser_31_0 - u1_plda_pcie_axi4_slv0_awuser_31_0 - [31:0] + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] read-write - - - - stg_sysconsaif_syscfg616 - STG SYSCONSAIF SYSCFG 616 - 0x268 - 32 - - u1_plda_pcie_axi4_slv0_awuser_40_32 - u1_plda_pcie_axi4_slv0_awuser_40_32 - [8:0] + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] read-write - - u1_plda_pcie_axi4_slv0_rderr - u1_plda_pcie_axi4_slv0_rderr - [16:9] - read-only - - stg_sysconsaif_syscfg620 - STG SYSCONSAIF SYSCFG 620 - 0x26c - 32 + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 - u1_plda_pcie_axi4_slv0_ruser - u1_plda_pcie_axi4_slv0_ruser - [31:0] + part_number0 + These bits read back as 0x22 + [7:0] read-only - stg_sysconsaif_syscfg624 - STG SYSCONSAIF SYSCFG 624 - 0x270 - 32 + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 - u1_plda_pcie_axi4_slv0_wderr - u1_plda_pcie_axi4_slv0_wderr - [7:0] - read-write + part_number1 + These bits read back as 0x0 + [3:0] + read-only - u1_plda_pcie_axi4_slvl_arfunc - u1_plda_pcie_axi4_slvl_arfunc - [22:8] - read-write + designer0 + These bits read back as 0x1 + [7:4] + read-only - stg_sysconsaif_syscfg628 - STG SYSCONSAIF SYSCFG 628 - 0x274 - 32 + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 - u1_plda_pcie_axi4_slvl_awfunc - u1_plda_pcie_axi4_slvl_awfunc - [14:0] - read-write - - - u1_plda_pcie_bus_width_o - u1_plda_pcie_bus_width_o - [16:15] + designer1 + These bits read back as 0x4 + [3:0] read-only - u1_plda_pcie_bypass_codec - u1_plda_pcie_bypass_codec - [17:17] - read-write - - - u1_plda_pcie_ckref_src - u1_plda_pcie_ckref_src - [19:18] - read-write - - - u1_plda_pcie_clk_sel - u1_plda_pcie_clk_sel - [21:20] - read-write - - - u1_plda_pcie_clkreq - u1_plda_pcie_clkreq - [22:22] - read-write + revision + These bits return the peripheral revision + [7:4] + read-only - stg_sysconsaif_syscfg632 - STG SYSCONSAIF SYSCFG 632 - 0x278 - 32 + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 - u1_plda_pcie_k_phyparam_31_0 - u1_plda_pcie_k_phyparam_31_0 - [31:0] - read-write + configuration + These bits read back as 0x80 + [7:0] + read-only - stg_sysconsaif_syscfg636 - STG SYSCONSAIF SYSCFG 636 - 0x27c - 32 + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 - u1_plda_pcie_k_phyparam_63_32 - u1_plda_pcie_k_phyparam_63_32 - [31:0] - read-write + ssp_pcell_id0 + The bits are read as 0xD + [7:0] + read-only - stg_sysconsaif_syscfg640 - STG SYSCONSAIF SYSCFG 640 - 0x280 - 32 + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 - u1_plda_pcie_k_phyparam_95_64 - u1_plda_pcie_k_phyparam_95_64 - [31:0] - read-write + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] + read-only - stg_sysconsaif_syscfg644 - STG SYSCONSAIF SYSCFG 644 - 0x284 - 32 + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 - u1_plda_pcie_k_phyparam_127_96 - u1_plda_pcie_k_phyparam_127_96 - [31:0] - read-write + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] + read-only - stg_sysconsaif_syscfg648 - STG SYSCONSAIF SYSCFG 648 - 0x288 - 32 + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 - u1_plda_pcie_k_phyparam_159_128 - u1_plda_pcie_k_phyparam_159_128 - [31:0] - read-write + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] + read-only - - stg_sysconsaif_syscfg652 - STG SYSCONSAIF SYSCFG 652 - 0x28c - 32 + + + + arm_primecell_2 + From arm,primecell, peripheral generator + 0x10080000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_tdm_0 + From starfive,jh7110-tdm, peripheral generator + 0x10090000 + + 0 + 0x1000 + registers + + + + starfive_jh7110_usb_phy_0 + From starfive,jh7110-usb-phy, peripheral generator + 0x10200000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_pcie_phy_0 + From starfive,jh7110-pcie-phy, peripheral generator + 0x10210000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_pcie_phy_1 + From starfive,jh7110-pcie-phy, peripheral generator + 0x10220000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_stgcrg_0 + From starfive,jh7110-stgcrg, peripheral generator + 0x10230000 + + 0 + 0x10000 + registers + + + + clk_hifi4_core + Clock HIFI4 Core + 0x0 + 32 - u1_plda_pcie_k_phyparam_191_160 - u1_plda_pcie_k_phyparam_191_160 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg656 - STG SYSCONSAIF SYSCFG 656 - 0x290 + clk_usb_apb + Clock USB APB + 0x4 32 - u1_plda_pcie_k_phyparam_223_192 - u1_plda_pcie_k_phyparam_223_192 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg660 - STG SYSCONSAIF SYSCFG 660 - 0x294 + clk_usb_utmi_apb + Clock USB UTMI APB + 0x8 32 - u1_plda_pcie_k_phyparam_255_224 - u1_plda_pcie_k_phyparam_255_224 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg664 - STG SYSCONSAIF SYSCFG 664 - 0x298 + clk_usb_axi + Clock USB AXI + 0xc 32 - u1_plda_pcie_k_phyparam_287_256 - u1_plda_pcie_k_phyparam_287_256 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg668 - STG SYSCONSAIF SYSCFG 668 - 0x29c + clk_usb_ipm + Clock USB AXI + 0x10 32 - u1_plda_pcie_k_phyparam_319_288 - u1_plda_pcie_k_phyparam_319_288 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] read-write - stg_sysconsaif_syscfg672 - STG SYSCONSAIF SYSCFG 672 - 0x2a0 + clk_usb_stb + Clock USB STB + 0x14 32 - u1_plda_pcie_k_phyparam_351_320 - u1_plda_pcie_k_phyparam_351_320 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + clk_divcfg + Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 + [23:0] read-write - stg_sysconsaif_syscfg676 - STG SYSCONSAIF SYSCFG 676 - 0x2a4 + clk_usb_app125 + Clock USB APP 125 + 0x18 32 - u1_plda_pcie_k_phyparam_383_352 - u1_plda_pcie_k_phyparam_383_352 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg680 - STG SYSCONSAIF SYSCFG 680 - 0x2a8 + clk_usb_refclk + Clock USB Reference Clock + 0x1c 32 - u1_plda_pcie_k_phyparam_415_384 - u1_plda_pcie_k_phyparam_415_384 - [31:0] + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] read-write - stg_sysconsaif_syscfg684 - STG SYSCONSAIF SYSCFG 684 - 0x2ac + clk_u0_pcie_axi_mst0 + U0 Clock PCIe AXI MST 0 + 0x20 32 - u1_plda_pcie_k_phyparam_447_416 - u1_plda_pcie_k_phyparam_447_416 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg688 - STG SYSCONSAIF SYSCFG 688 - 0x2b0 + clk_u0_pcie_apb + U0 Clock PCIe APB + 0x24 32 - u1_plda_pcie_k_phyparam_479_448 - u1_plda_pcie_k_phyparam_479_448 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg692 - STG SYSCONSAIF SYSCFG 692 - 0x2b4 + clk_u0_pcie_tl + U0 Clock PCIe TL + 0x28 32 - u1_plda_pcie_k_phyparam_511_480 - u1_plda_pcie_k_phyparam_511_480 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg696 - STG SYSCONSAIF SYSCFG 696 - 0x2b8 + clk_u1_pcie_axi_mst0 + U1 Clock PCIe AXI MST 0 + 0x2c 32 - u1_plda_pcie_k_phyparam_543_512 - u1_plda_pcie_k_phyparam_543_512 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg700 - STG SYSCONSAIF SYSCFG 700 - 0x2bc + clk_u1_pcie_apb + U1 Clock PCIe APB + 0x30 32 - u1_plda_pcie_k_phyparam_575_544 - u1_plda_pcie_k_phyparam_575_544 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg704 - STG SYSCONSAIF SYSCFG 704 - 0x2c0 + clk_u1_pcie_tl + U1 Clock PCIe TL + 0x34 32 - u1_plda_pcie_k_phyparam_607_576 - u1_plda_pcie_k_phyparam_607_576 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg708 - STG SYSCONSAIF SYSCFG 708 - 0x2c4 + clk_pcie01_slv_dec_main + Clock PCIe 01 SLV DEC Main + 0x38 32 - u1_plda_pcie_k_phyparam_639_608 - u1_plda_pcie_k_phyparam_639_608 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg712 - STG SYSCONSAIF SYSCFG 712 - 0x2c8 + clk_sec_hclk + Clock Security HCLK + 0x3c 32 - u1_plda_pcie_k_phyparam_671_640 - u1_plda_pcie_k_phyparam_671_640 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg716 - STG SYSCONSAIF SYSCFG 716 - 0x2cc + clk_sec_misc_ahb + Clock Security Miscellaneous AHB + 0x40 32 - u1_plda_pcie_k_phyparam_703_672 - u1_plda_pcie_k_phyparam_703_672 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg720 - STG SYSCONSAIF SYSCFG 720 - 0x2d0 + clk_stg_mtrx_group0_main + Clock STG MTRX Group 0 Main + 0x44 32 - u1_plda_pcie_k_phyparam_735_704 - u1_plda_pcie_k_phyparam_735_704 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg724 - STG SYSCONSAIF SYSCFG 724 - 0x2d4 + clk_stg_mtrx_group0_bus + Clock STG MTRX Group 0 Bus + 0x48 32 - u1_plda_pcie_k_phyparam_767_736 - u1_plda_pcie_k_phyparam_767_736 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg728 - STG SYSCONSAIF SYSCFG 728 - 0x2d8 + clk_stg_mtrx_group0_stg + Clock STG MTRX Group 0 STG + 0x4c 32 - u1_plda_pcie_k_phyparam_799_768 - u1_plda_pcie_k_phyparam_799_768 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg732 - STG SYSCONSAIF SYSCFG 732 - 0x2dc + clk_stg_mtrx_group1_main + Clock STG MTRX Group 1 Main + 0x50 32 - u1_plda_pcie_k_phyparam_831_800 - u1_plda_pcie_k_phyparam_831_800 - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg736 - STG SYSCONSAIF SYSCFG 736 - 0x2e0 + clk_stg_mtrx_group1_bus + Clock STG MTRX Group 1 Bus + 0x54 32 - u1_plda_pcie_k_phyparam_839_832 - u1_plda_pcie_k_phyparam_839_832 - [7:0] - read-write - - - u1_plda_pcie_k_rp_nep - u1_plda_pcie_k_rp_nep - [8:8] - read-write - - - u1_plda_pcie_l1sub_entack - u1_plda_pcie_l1sub_entack - [9:9] - read-only - - - u1_plda_pcie_l1sub_entreq - u1_plda_pcie_l1sub_entreq - [10:10] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg740 - STG SYSCONSAIF SYSCFG 740 - 0x2e4 + clk_stg_mtrx_group1_stg + Clock STG MTRX Group 1 STG + 0x58 32 - u1_plda_pcie_local_interrupt_in - u1_plda_pcie_local_interrupt_in - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg744 - STG SYSCONSAIF SYSCFG 744 - 0x2e8 + clk_stg_mtrx_group1_hifi + Clock STG MTRX Group 1 HIFI + 0x5c 32 - u1_plda_pcie_mperstn - u1_plda_pcie_mperstn - [0:0] - read-write - - - u1_plda_pcie_pcie_ebuf_mode - u1_plda_pcie_pcie_ebuf_mode - [1:1] - read-write - - - u1_plda_pcie_pcie_phy_test_cfg - u1_plda_pcie_pcie_phy_test_cfg - [24:2] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_e2_rtc + Clock E2 RTC + 0x60 + 32 + - u1_plda_pcie_pcie_rx_eq_training - u1_plda_pcie_pcie_rx_eq_training - [25:25] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - u1_plda_pcie_pcie_rxterm_en - u1_plda_pcie_pcie_rxterm_en - [26:26] + clk_divcfg + Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24 + [23:0] read-write + + + + clk_e2_core + Clock E2 Core + 0x64 + 32 + - u1_plda_pcie_pcie_tx_oneszeros - u1_plda_pcie_pcie_tx_oneszeros - [27:27] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg748 - STG SYSCONSAIF SYSCFG 748 - 0x2ec + clk_e2_dbg + Clock E2 DBG + 0x68 32 - u1_plda_pcie_pf0_offset - u1_plda_pcie_pf0_offset - [19:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg752 - STG SYSCONSAIF SYSCFG 752 - 0x2f0 + clk_dma_axi + Clock DMA AXI + 0x6c 32 - u1_plda_pcie_pf1_offset - u1_plda_pcie_pf1_offset - [19:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg756 - STG SYSCONSAIF SYSCFG 756 - 0x2f4 + clk_dma_ahb + Clock DMA AHB + 0x70 32 - u1_plda_pcie_pf2_offset - u1_plda_pcie_pf2_offset - [19:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - stg_sysconsaif_syscfg760 - STG SYSCONSAIF SYSCFG 760 - 0x2f8 + soft_rst_addr_sel + Software RESET Address Selector + 0x74 32 - u1_plda_pcie_pf3_offset - u1_plda_pcie_pf3_offset - [19:0] + rstn_u0_stg_syscon_presetn + 1: Assert reset, 0: De-assert reset + [0:0] read-write - u1_plda_pcie_phy_mode - u1_plda_pcie_phy_mode - [21:20] + rst_u0_hifi4_rst_core + 1: Assert reset, 0: De-assert reset + [1:1] read-write - u1_plda_pcie_pl_clkrem_allow - u1_plda_pcie_pl_clkrem_allow - [22:22] + rst_u0_hifi4_rst_axi + 1: Assert reset, 0: De-assert reset + [2:2] read-write - u1_plda_pcie_pl_clkreq_oen - u1_plda_pcie_pl_clkreq_oen - [23:23] - read-only + rstn_u0_sec_top_hreesetn + 1: Assert reset, 0: De-assert reset + [3:3] + read-write - u1_plda_pcie_pl_equ_phase - u1_plda_pcie_pl_equ_phase - [25:24] - read-only + rst_u0_e2_sft7110_rst_core + 1: Assert reset, 0: De-assert reset + [4:4] + read-write - u1_plda_pcie_pl_ltssm - u1_plda_pcie_pl_ltssm - [30:26] - read-only + rstn_u0_dma1p_8ch_56hs_rstn_axi + 1: Assert reset, 0: De-assert reset + [5:5] + read-write - - - - stg_sysconsaif_syscfg764 - STG SYSCONSAIF SYSCFG 764 - 0x2fc - 32 - - u1_plda_pcie_pl_pclk_rate - u1_plda_pcie_pl_pclk_rate - [4:0] - read-only + rstn_u0_dma1p_8ch_56hs_rstn_ahb + 1: Assert reset, 0: De-assert reset + [6:6] + read-write - - - - stg_sysconsaif_syscfg768 - STG SYSCONSAIF SYSCFG 768 - 0x300 - 32 - - u1_plda_pcie_pl_sideband_in_31_0 - u1_plda_pcie_pl_sideband_in_31_0 - [31:0] + rstn_u0_cdn_usb_rstn_axi + 1: Assert reset, 0: De-assert reset + [7:7] read-write - - - - stg_sysconsaif_syscfg772 - STG SYSCONSAIF SYSCFG 772 - 0x304 - 32 - - u1_plda_pcie_pl_sideband_in_63_32 - u1_plda_pcie_pl_sideband_in_63_32 - [31:0] + rstn_u0_cdn_usb_rstn_usb_apb + 1: Assert reset, 0: De-assert reset + [8:8] read-write - - - - stg_sysconsaif_syscfg776 - STG SYSCONSAIF SYSCFG 776 - 0x308 - 32 - - u1_plda_pcie_pl_sideband_out_31_0 - u1_plda_pcie_pl_sideband_out_31_0 - [31:0] + rstn_u0_cdn_usb_rstn_utmi_apb + 1: Assert reset, 0: De-assert reset + [9:9] read-write - - - - stg_sysconsaif_syscfg780 - STG SYSCONSAIF SYSCFG 780 - 0x30c - 32 - - u1_plda_pcie_pl_sideband_out_63_32 - u1_plda_pcie_pl_sideband_out_63_32 - [31:0] + rstn_u0_cdn_usb_rstn_pwrup + 1: Assert reset, 0: De-assert reset + [10:10] read-write - - - - stg_sysconsaif_syscfg784 - STG SYSCONSAIF SYSCFG 784 - 0x310 - 32 - - u1_plda_pcie_pl_wake_in - u1_plda_pcie_pl_wake_in - [0:0] + rstn_u0_plda_pcie_rstn_axi_mst0 + 1: Assert reset, 0: De-assert reset + [11:11] read-write - u1_plda_pcie_pl_wake_oen - u1_plda_pcie_pl_wake_oen - [1:1] - read-only + rstn_u0_plda_pcie_rstn_axi_slv0 + 1: Assert reset, 0: De-assert reset + [12:12] + read-write - u1_plda_pcie_rx_standby_o - u1_plda_pcie_rx_standby_o - [2:2] - read-only + rstn_u0_plda_pcie_rstn_axi_slv + 1: Assert reset, 0: De-assert reset + [13:13] + read-write - - - - stg_sysconsaif_syscfg788 - STG SYSCONSAIF SYSCFG 788 - 0x314 - 32 - - u1_plda_pcie_test_in_31_0 - u1_plda_pcie_test_in_31_0 - [31:0] + rstn_u0_plda_pci_rstn_brg + 1: Assert reset, 0: De-assert reset + [14:14] read-write - - - - stg_sysconsaif_syscfg792 - STG SYSCONSAIF SYSCFG 792 - 0x318 - 32 - - u1_plda_pcie_test_in_63_32 - u1_plda_pcie_test_in_63_32 - [31:0] + rstn_u0_plda_pcie_rstn_pcie + 1: Assert reset, 0: De-assert reset + [15:15] read-write - - - - stg_sysconsaif_syscfg796 - STG SYSCONSAIF SYSCFG 796 - 0x31c - 32 - - u1_plda_pcie_test_out_bridge_31_0 - u1_plda_pcie_test_out_bridge_31_0 - [31:0] + rstn_u0_plda_pcie_rstn_apb + 1: Assert reset, 0: De-assert reset + [16:16] read-write - - - - stg_sysconsaif_syscfg800 - STG SYSCONSAIF SYSCFG 800 - 0x320 - 32 - - u1_plda_pcie_test_out_bridge_63_32 - u1_plda_pcie_test_out_bridge_63_32 - [31:0] + rstn_u1_plda_pcie_rstn_axi_mst0 + 1: Assert reset, 0: De-assert reset + [17:17] read-write - - - - stg_sysconsaif_syscfg804 - STG SYSCONSAIF SYSCFG 804 - 0x324 - 32 - - u1_plda_pcie_test_out_bridge_95_64 - u1_plda_pcie_test_out_bridge_95_64 - [31:0] + rstn_u1_plda_pcie_rstn_axi_slv0 + 1: Assert reset, 0: De-assert reset + [18:18] read-write - - - - stg_sysconsaif_syscfg808 - STG SYSCONSAIF SYSCFG 808 - 0x328 - 32 - - u1_plda_pcie_test_out_bridge_127_96 - u1_plda_pcie_test_out_bridge_127_96 - [31:0] + rstn_u1_plda_pcie_rstn_axi_slv + 1: Assert reset, 0: De-assert reset + [19:19] read-write - - - - stg_sysconsaif_syscfg812 - STG SYSCONSAIF SYSCFG 812 - 0x32c - 32 - - u1_plda_pcie_test_out_bridge_159_128 - u1_plda_pcie_test_out_bridge_159_128 - [31:0] + rstn_u1_plda_pcie_rstn_brg + 1: Assert reset, 0: De-assert reset + [20:20] read-write - - - - stg_sysconsaif_syscfg816 - STG SYSCONSAIF SYSCFG 816 - 0x330 - 32 - - u1_plda_pcie_test_out_bridge_191_160 - u1_plda_pcie_test_out_bridge_191_160 - [31:0] + rstn_u1_plda_pcie_rstn_pcie + 1: Assert reset, 0: De-assert reset + [21:21] read-write - - - - stg_sysconsaif_syscfg820 - STG SYSCONSAIF SYSCFG 820 - 0x334 - 32 - - u1_plda_pcie_test_out_bridge_223_192 - u1_plda_pcie_test_out_bridge_223_192 - [31:0] + rstn_u1_plda_pcie_rstn_apb + 1: Assert reset, 0: De-assert reset + [22:22] read-write - stg_sysconsaif_syscfg824 - STG SYSCONSAIF SYSCFG 824 - 0x338 + stgcrg_rst_stat + STGCRG RESET Status + 0x78 32 - u1_plda_pcie_test_out_bridge_255_224 - u1_plda_pcie_test_out_bridge_255_224 - [31:0] + rstn_u0_stg_syscon_presetn + 1: Assert reset, 0: De-assert reset + [0:0] read-write - - - - stg_sysconsaif_syscfg828 - STG SYSCONSAIF SYSCFG 828 - 0x33c - 32 - - u1_plda_pcie_test_out_bridge_287_256 - u1_plda_pcie_test_out_bridge_287_256 - [31:0] + rst_u0_hifi4_rst_core + 1: Assert reset, 0: De-assert reset + [1:1] read-write - - - - stg_sysconsaif_syscfg832 - STG SYSCONSAIF SYSCFG 832 - 0x340 + + rst_u0_hifi4_rst_axi + 1: Assert reset, 0: De-assert reset + [2:2] + read-write + + + rstn_u0_sec_top_hreesetn + 1: Assert reset, 0: De-assert reset + [3:3] + read-write + + + rst_u0_e2_sft7110_rst_core + 1: Assert reset, 0: De-assert reset + [4:4] + read-write + + + rstn_u0_dma1p_8ch_56hs_rstn_axi + 1: Assert reset, 0: De-assert reset + [5:5] + read-write + + + rstn_u0_dma1p_8ch_56hs_rstn_ahb + 1: Assert reset, 0: De-assert reset + [6:6] + read-write + + + rstn_u0_cdn_usb_rstn_axi + 1: Assert reset, 0: De-assert reset + [7:7] + read-write + + + rstn_u0_cdn_usb_rstn_usb_apb + 1: Assert reset, 0: De-assert reset + [8:8] + read-write + + + rstn_u0_cdn_usb_rstn_utmi_apb + 1: Assert reset, 0: De-assert reset + [9:9] + read-write + + + rstn_u0_cdn_usb_rstn_pwrup + 1: Assert reset, 0: De-assert reset + [10:10] + read-write + + + rstn_u0_plda_pcie_rstn_axi_mst0 + 1: Assert reset, 0: De-assert reset + [11:11] + read-write + + + rstn_u0_plda_pcie_rstn_axi_slv0 + 1: Assert reset, 0: De-assert reset + [12:12] + read-write + + + rstn_u0_plda_pcie_rstn_axi_slv + 1: Assert reset, 0: De-assert reset + [13:13] + read-write + + + rstn_u0_plda_pci_rstn_brg + 1: Assert reset, 0: De-assert reset + [14:14] + read-write + + + rstn_u0_plda_pcie_rstn_pcie + 1: Assert reset, 0: De-assert reset + [15:15] + read-write + + + rstn_u0_plda_pcie_rstn_apb + 1: Assert reset, 0: De-assert reset + [16:16] + read-write + + + rstn_u1_plda_pcie_rstn_axi_mst0 + 1: Assert reset, 0: De-assert reset + [17:17] + read-write + + + rstn_u1_plda_pcie_rstn_axi_slv0 + 1: Assert reset, 0: De-assert reset + [18:18] + read-write + + + rstn_u1_plda_pcie_rstn_axi_slv + 1: Assert reset, 0: De-assert reset + [19:19] + read-write + + + rstn_u1_plda_pcie_rstn_brg + 1: Assert reset, 0: De-assert reset + [20:20] + read-write + + + rstn_u1_plda_pcie_rstn_pcie + 1: Assert reset, 0: De-assert reset + [21:21] + read-write + + + rstn_u1_plda_pcie_rstn_apb + 1: Assert reset, 0: De-assert reset + [22:22] + read-write + + + + + + + starfive_jh7110_stg_syscon_0 + From starfive,jh7110-stg-syscon, peripheral generator + 0x10240000 + + 0 + 0x1000 + registers + + + + stg_sysconsaif_syscfg0 + STG SYSCONSAIF SYSCFG 0 + 0x0 32 - u1_plda_pcie_test_out_bridge_319_288 - u1_plda_pcie_test_out_bridge_319_288 - [31:0] + scfg_hprot_sd0 + scfg_hprot_sd0 + [3:0] + read-write + + + scfg_hprot_sd1 + scfg_hprot_sd1 + [7:4] + read-write + + + u0_cdn_usb_adp_en + u0_cdn_usb_adp_en + [8:8] + read-only + + + u0_cdn_usb_adp_probe_ana + u0_cdn_usb_adp_probe_ana + [9:9] + read-write + + + u0_cdn_usb_adp_probe_en + u0_cdn_usb_adp_probe_en + [10:10] + read-only + + + u0_cdn_usb_adp_sense_ana + u0_cdn_usb_adp_sense_ana + [11:11] + read-write + + + u0_cdn_usb_adp_sense_en + u0_cdn_usb_adp_sense_en + [12:12] + read-only + + + u0_cdn_usb_adp_sink_current_en + u0_cdn_usb_adp_sink_current_en + [13:13] + read-only + + + u0_cdn_usb_adp_source_current_en + u0_cdn_usb_adp_source_current_en + [14:14] + read-only + + + u0_cdn_usb_bc_en + u0_cdn_usb_bc_en + [15:15] + read-only + + + u0_cdn_usb_chrg_vbus + u0_cdn_usb_chrg_vbus + [16:16] + read-write + + + u0_cdn_usb_dcd_comp_sts + u0_cdn_usb_dcd_comp_sts + [17:17] + read-write + + + u0_cdn_usb_dischrg_vbus + u0_cdn_usb_dischrg_vbus + [18:18] + read-write + + + u0_cdn_usb_dm_vdat_ref_comp_en + u0_cdn_usb_dm_vdat_ref_comp_en + [19:19] + read-only + + + u0_cdn_usb_dm_vdat_ref_comp_sts + u0_cdn_usb_dm_vdat_ref_comp_sts + [20:20] + read-write + + + u0_cdn_usb_dm_vlgc_comp_en + u0_cdn_usb_dm_vlgc_comp_en + [21:21] + read-only + + + u0_cdn_usb_dm_vlgc_comp_sts + u0_cdn_usb_dm_vlgc_comp_sts + [22:22] + read-write + + + u0_cdn_usb_dp_vdat_ref_comp_en + u0_cdn_usb_dp_vdat_ref_comp_en + [23:23] + read-only + + + u0_cdn_usb_dp_vdat_ref_comp_sts + u0_cdn_usb_dp_vdat_ref_comp_sts + [24:24] + read-write + + + u0_cdn_usb_host_system_err + u0_cdn_usb_host_system_err + [25:25] + read-write + + + u0_cdn_usb_hsystem_err_ext + u0_cdn_usb_hsystem_err_ext + [26:26] + read-only + + + u0_cdn_usb_idm_sink_en + u0_cdn_usb_idm_sink_en + [27:27] + read-only + + + u0_cdn_usb_idp_sink_en + u0_cdn_usb_idp_sink_en + [28:28] + read-only + + + u0_cdn_usb_idp_src_en + u0_cdn_usb_idp_src_en + [29:29] + read-only + + + + + stg_sysconsaif_syscfg4 + STG SYSCONSAIF SYSCFG 4 + 0x4 + 32 + + + u0_cdn_usb_lowest_belt + LTM interface to software + [11:0] + read-only + + + u0_cdn_usb_ltm_host_req + LTM interface to software + [12:12] + read-only + + + u0_cdn_usb_ltm_host_req_halt + LTM interface to software + [13:13] + read-write + + + u0_cdn_usb_mdctrl_clk_sel + u0_cdn_usb_mdctrl_clk_sel + [14:14] + read-write + + + u0_cdn_usb_mdctrl_clk_status + u0_cdn_usb_mdctrl_clk_status + [15:15] + read-only + + + u0_cdn_usb_mode_strap + Can onlly be changed when pwrup_rst_n is low + [18:16] + read-write + + + u0_cdn_usb_otg_suspendm + u0_cdn_usb_otg_suspendm + [19:19] + read-write + + + u0_cdn_usb_otg_suspendm_byps + u0_cdn_usb_otg_suspendm_byps + [20:20] + read-write + + + u0_cdn_usb_phy_bvalid + u0_cdn_usb_phy_bvalid + [21:21] + read-only + + + u0_cdn_usb_pll_en + u0_cdn_usb_pll_en + [22:22] + read-write + + + u0_cdn_usb_refclk_mode + u0_cdn_usb_refclk_mode + [23:23] + read-write + + + u0_cdn_usb_rid_a_comp_sts + u0_cdn_usb_rid_a_comp_sts + [24:24] + read-write + + + u0_cdn_usb_rid_b_comp_sts + u0_cdn_usb_rid_b_comp_sts + [25:25] + read-write + + + u0_cdn_usb_rid_c_comp_sts + u0_cdn_usb_rid_c_comp_sts + [26:26] + read-write + + + u0_cdn_usb_rid_float_comp_en + u0_cdn_usb_rid_float_comp_en + [27:27] + read-only + + + u0_cdn_usb_rid_float_comp_sts + u0_cdn_usb_rid_float_comp_sts + [28:28] + read-write + + + u0_cdn_usb_rid_gnd_comp_sts + u0_cdn_usb_rid_gnd_comp_sts + [29:29] + read-write + + + u0_cdn_usb_rid_nonfloat_comp_en + u0_cdn_usb_rid_nonfloat_comp_en + [30:30] + read-only + + + u0_cdn_usb_rx_dm + u0_cdn_usb_rx_dm + [31:31] + read-only + + + + + stg_sysconsaif_syscfg8 + STG SYSCONSAIF SYSCFG 8 + 0x8 + 32 + + + u0_cdn_usb_rx_dp + u0_cdn_usb_rx_dp + [0:0] + read-only + + + u0_cdn_usb_rx_rcv + u0_cdn_usb_rx_rcv + [1:1] + read-only + + + u0_cdn_usb_self_test + For software bist_test + [2:2] + read-write + + + u0_cdn_usb_sessend + u0_cdn_usb_sessend + [3:3] + read-only + + + u0_cdn_usb_sessvalid + u0_cdn_usb_sessvalid + [4:4] + read-only + + + u0_cdn_usb_sof + u0_cdn_usb_sof + [5:5] + read-only + + + u0_cdn_usb_test_bist + For software bist_test + [6:6] + read-only + + + u0_cdn_usb_usbdev_main_power_off_ack + u0_cdn_usb_usbdev_main_power_off_ack + [7:7] + read-only + + + u0_cdn_usb_usbdev_main_power_off_ready + u0_cdn_usb_usbdev_main_power_off_ready + [8:8] + read-only + + + u0_cdn_usb_usbdev_main_power_off_req + u0_cdn_usb_usbdev_main_power_off_req + [9:9] + read-write + + + u0_cdn_usb_usbdev_main_power_on_ready + u0_cdn_usb_usbdev_main_power_on_ready + [10:10] + read-only + + + u0_cdn_usb_usbdev_main_power_on_req + u0_cdn_usb_usbdev_main_power_on_req + [11:11] + read-only + + + u0_cdn_usb_usbdev_main_power_on_valid + u0_cdn_usb_usbdev_main_power_on_valid + [12:12] + read-write + + + u0_cdn_usb_usbdev_power_off_ack + u0_cdn_usb_usbdev_power_off_ack + [13:13] + read-only + + + u0_cdn_usb_usbdev_power_off_ready + u0_cdn_usb_usbdev_power_off_ready + [14:14] + read-only + + + u0_cdn_usb_usbdev_power_off_req + u0_cdn_usb_usbdev_power_off_req + [15:15] + read-write + + + u0_cdn_usb_usbdev_power_on_ready + u0_cdn_usb_usbdev_power_on_ready + [16:16] + read-only + + + u0_cdn_usb_usbdev_power_on_req + u0_cdn_usb_usbdev_power_on_req + [17:17] + read-only + + + u0_cdn_usb_usbdev_power_on_valid + u0_cdn_usb_usbdev_power_on_valid + [18:18] + read-write + + + u0_cdn_usb_utmi_dmpulldown_sit + u0_cdn_usb_utmi_dmpulldown_sit + [19:19] + read-write + + + u0_cdn_usb_utmi_dppulldown_sit + u0_cdn_usb_utmi_dppulldown_sit + [20:20] + read-write + + + u0_cdn_usb_utmi_fslsserialmode_sit + u0_cdn_usb_utmi_fslsserialmode_sit + [21:21] + read-write + + + u0_cdn_usb_utmi_hostdisconnect_sit + u0_cdn_usb_utmi_hostdisconnect_sit + [22:22] + read-only + + + u0_cdn_usb_utmi_iddig_sit + u0_cdn_usb_utmi_iddig_sit + [23:23] + read-only + + + u0_cdn_usb_utmi_idpullup_sit + u0_cdn_usb_utmi_idpullup_sit + [24:24] + read-write + + + u0_cdn_usb_utmi_linestate_sit + u0_cdn_usb_utmi_linestate_sit + [26:25] + read-only + + + u0_cdn_usb_utmi_opmode_sit + u0_cdn_usb_utmi_opmode_sit + [28:27] + read-write + + + u0_cdn_usb_utmi_rxactive_sit + u0_cdn_usb_utmi_rxactive_sit + [29:29] + read-only + + + u0_cdn_usb_utmi_rxerror_sit + u0_cdn_usb_utmi_rxerror_sit + [30:30] + read-only + + + u0_cdn_usb_utmi_rxvalid_sit + u0_cdn_usb_utmi_rxvalid_sit + [31:31] + read-only + + + + + stg_sysconsaif_syscfg12 + STG SYSCONSAIF SYSCFG 12 + 0xc + 32 + + + u0_cdn_usb_utmi_rxvalidh_sit + u0_cdn_usb_utmi_rxvalidh_sit + [0:0] + read-only + + + u0_cdn_usb_utmi_sessvld + u0_cdn_usb_utmi_sessvld + [1:1] + read-write + + + u0_cdn_usb_utmi_termselect_sit + u0_cdn_usb_utmi_termselect_sit + [2:2] + read-write + + + u0_cdn_usb_utmi_tx_dat_sit + u0_cdn_usb_utmi_tx_dat_sit + [3:3] + read-write + + + u0_cdn_usb_utmi_tx_enable_n_sit + u0_cdn_usb_utmi_tx_enable_n_sit + [4:4] + read-write + + + u0_cdn_usb_utmi_tx_se0_sit + u0_cdn_usb_utmi_tx_se0_sit + [5:5] + read-write + + + u0_cdn_usb_utmi_txbitstuffenable_sit + u0_cdn_usb_utmi_txbitstuffenable_sit + [6:6] + read-write + + + u0_cdn_usb_utmi_txready_sit + u0_cdn_usb_utmi_txready_sit + [7:7] + read-only + + + u0_cdn_usb_utmi_txvalid_sit + u0_cdn_usb_utmi_txvalid_sit + [8:8] + read-write + + + u0_cdn_usb_utmi_txvalidh_sit + u0_cdn_usb_utmi_txvalidh_sit + [9:9] + read-write + + + u0_cdn_usb_utmi_vbusvalid_sit + u0_cdn_usb_utmi_vbusvalid_sit + [10:10] + read-only + + + u0_cdn_usb_utmi_xcvrselect_sit + u0_cdn_usb_utmi_xcvrselect_sit + [12:11] + read-write + + + u0_cdn_usb_utmi_vdm_src_en + u0_cdn_usb_utmi_vdm_src_en + [13:13] + read-only + + + u0_cdn_usb_utmi_vdp_src_en + u0_cdn_usb_utmi_vdp_src_en + [14:14] + read-only + + + u0_cdn_usb_wakeup + u0_cdn_usb_wakeup + [15:15] + read-write + + + u0_cdn_usb_xhc_d0_ack + u0_cdn_usb_xhc_d0_ack + [16:16] + read-only + + + u0_cdn_usb_xhc_d0_req + u0_cdn_usb_xhc_d0_req + [17:17] + read-write + + + + + stg_sysconsaif_syscfg16 + STG SYSCONSAIF SYSCFG 16 + 0x10 + 32 + + + u0_cdn_usb_xhci_debug_bus + u0_cdn_usb_xhci_debug_bus + [31:0] + read-only + + + + + stg_sysconsaif_syscfg20 + STG SYSCONSAIF SYSCFG 20 + 0x14 + 32 + + + u0_cdn_usb_xhci_debug_link_state + u0_cdn_usb_xhci_debug_link_state + [30:0] + read-only + + + + + stg_sysconsaif_syscfg24 + STG SYSCONSAIF SYSCFG 24 + 0x18 + 32 + + + u0_cdn_usb_xhci_debug_sel + u0_cdn_usb_xhci_debug_sel + [4:0] + read-write + + + u0_cdn_usb_xhci_main_power_off_ack + u0_cdn_usb_xhci_main_power_off_ack + [5:5] + read-only + + + u0_cdn_usb_xhci_main_power_off_req + u0_cdn_usb_xhci_main_power_off_req + [6:6] + read-only + + + u0_cdn_usb_xhci_main_power_on_ready + u0_cdn_usb_xhci_main_power_on_ready + [7:7] + read-write + + + u0_cdn_usb_xhci_main_power_on_req + u0_cdn_usb_xhci_main_power_on_req + [8:8] + read-only + + + u0_cdn_usb_xhci_main_power_on_valid + u0_cdn_usb_xhci_main_power_on_valid + [9:9] + read-write + + + u0_cdn_usb_xhci_power_off_ack + u0_cdn_usb_xhci_power_off_ack + [10:10] + read-only + + + u0_cdn_usb_xhci_power_off_ready + u0_cdn_usb_xhci_power_off_ready + [11:11] + read-only + + + u0_cdn_usb_xhci_power_off_req + u0_cdn_usb_xhci_power_off_req + [12:12] + read-write + + + u0_cdn_usb_xhci_power_on_ready + u0_cdn_usb_xhci_power_on_ready + [13:13] + read-only + + + u0_cdn_usb_xhci_power_on_req + u0_cdn_usb_xhci_power_on_req + [14:14] + read-only + + + u0_cdn_usb_xhci_power_on_valid + u0_cdn_usb_xhci_power_on_valid + [15:15] + read-write + + + u0_e2_sft7110_cease_from_tile_0 + u0_e2_sft7110_cease_from_tile_0 + [16:16] + read-only + + + u0_e2_sft7110_debug_from_tile_0 + u0_e2_sft7110_debug_from_tile_0 + [17:17] + read-only + + + u0_e2_sft7110_halt_from_tile_0 + u0_e2_sft7110_halt_from_tile_0 + [18:18] + read-only + + + + + stg_sysconsaif_syscfg28 + STG SYSCONSAIF SYSCFG 28 + 0x1c + 32 + + + u0_e2_sft7110_nmi_0_rnmi_exception_vector + u0_e2_sft7110_nmi_0_rnmi_exception_vector + [31:0] + read-write + + + + + stg_sysconsaif_syscfg32 + STG SYSCONSAIF SYSCFG 32 + 0x20 + 32 + + + u0_e2_sft7110_nmi_0_rnmi_interrupt_vector + u0_e2_sft7110_nmi_0_rnmi_interrupt_vector + [31:0] + read-write + + + + + stg_sysconsaif_syscfg36 + STG SYSCONSAIF SYSCFG 36 + 0x24 + 32 + + + u0_e2_sft7110_reset_vector_0 + u0_e2_sft7110_reset_vector_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg40 + STG SYSCONSAIF SYSCFG 40 + 0x28 + 32 + + + u0_e2_sft7110_wfi_from_tile_0 + u0_e2_sft7110_wfi_from_tile_0 + [0:0] + read-only + + + + + stg_sysconsaif_syscfg44 + STG SYSCONSAIF SYSCFG 44 + 0x2c + 32 + + + u0_hifi4_altresetvec + Reset Vector Address + [31:0] + read-write + + + + + stg_sysconsaif_syscfg48 + STG SYSCONSAIF SYSCFG 48 + 0x30 + 32 + + + u0_hifi4_breakin + Debug signal + [0:0] + read-write + + + u0_hifi4_breakinack + Debug signal + [1:1] + read-only + + + u0_hifi4_breakout + Debug signal + [2:2] + read-only + + + u0_hifi4_breakoutack + Debug signal + [3:3] + read-write + + + u0_hifi4_debugmode + Debug signal + [4:4] + read-only + + + u0_hifi4_doubleexceptionerror + Fault Handling Signals + [5:5] + read-only + + + u0_hifi4_iram0loadstore + Indicates that iram0 works + [6:6] + read-only + + + u0_hifi4_iram1loadstore + Indicates that iram1 works + [7:7] + read-only + + + u0_hifi4_ocdhaltonreset + Debug signal + [8:8] + read-write + + + u0_hifi4_pfatalerror + Fault Handling Signals + [9:9] + read-only + + + + + stg_sysconsaif_syscfg52 + STG SYSCONSAIF SYSCFG 52 + 0x34 + 32 + + + u0_hifi4_pfaultinfo + Fault Handling Signals + [31:0] + read-only + + + + + stg_sysconsaif_syscfg56 + STG SYSCONSAIF SYSCFG 56 + 0x38 + 32 + + + u0_hifi4_pfaultinfovalid + Fault Handling Signals + [0:0] + read-only + + + u0_hifi4_prid + Module ID + [16:1] + read-write + + + u0_hifi4_pwaitmode + Wait Mode + [17:17] + read-only + + + u0_hifi4_runstall + Run Stall + [18:18] + read-write + + + + + stg_sysconsaif_syscfg60 + STG SYSCONSAIF SYSCFG 60 + 0x3c + 32 + + + u0_hifi4_scfg_dsp_mst_offset_master + Indicates that master port remap address + [11:0] + read-write + + + u0_hifi4_scfg_dsp_mst_offset_dma + Indicates the DMA port remap address + [27:16] + read-write + + + + + stg_sysconsaif_syscfg64 + STG SYSCONSAIF SYSCFG 64 + 0x40 + 32 + + + u0_hifi4_scfg_dsp_slv_offset + The value indicates the slave port remap address + [31:0] + read-write + + + + + stg_sysconsaif_syscfg68 + STG SYSCONSAIF SYSCFG 68 + 0x44 + 32 + + + u0_hifi4_scfg_sram_config_slp + SRAM/ROM configuration. SLP: sleep enable, high active, default is low. + [0:0] + read-write + + + u0_hifi4_scfg_sram_config_sram_config_sd + SRAM/ROM configuration. SD: shutdown enable, high active, default is low. + [1:1] + read-write + + + u0_hifi4_scfg_sram_config_rtsel + SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. + [3:2] + read-write + + + u0_hifi4_scfg_sram_config_ptsel + SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. + [5:4] + read-write + + + u0_hifi4_scfg_sram_config_trb + SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. + [7:6] + read-write + + + u0_hifi4_scfg_sram_config_wtsel + SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. + [9:8] + read-write + + + u0_hifi4_scfg_sram_config_vs + SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. + [10:10] + read-write + + + u0_hifi4_scfg_sram_config_vg + SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. + [11:11] + read-write + + + u0_hifi4_statvectorsel + When the value is 1, it indicates that the AltResetVec is valid + [12:12] + read-write + + + u0_hifi4_trigin_idma + DMA port trigger + [13:13] + read-write + + + u0_hifi4_trigout_idma + DMA port trigger + [14:14] + read-only + + + u0_hifi4_xocdmode + Debug signal + [15:15] + read-only + + + u0_plda_pcie_align_detect + u0_plda_pcie_align_detect + [16:16] + read-only + + + + + stg_sysconsaif_syscfg72 + STG SYSCONSAIF SYSCFG 72 + 0x48 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_31_0 + u0_plda_pcie_axi4_mst0_aratomop_31_0 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg76 + STG SYSCONSAIF SYSCFG 76 + 0x4c + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_63_32 + u0_plda_pcie_axi4_mst0_aratomop_63_32 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg80 + STG SYSCONSAIF SYSCFG 80 + 0x50 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_95_64 + u0_plda_pcie_axi4_mst0_aratomop_95_64 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg84 + STG SYSCONSAIF SYSCFG 84 + 0x54 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_127_96 + u0_plda_pcie_axi4_mst0_aratomop_127_96 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg88 + STG SYSCONSAIF SYSCFG 88 + 0x58 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_159_128 + u0_plda_pcie_axi4_mst0_aratomop_159_128 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg92 + STG SYSCONSAIF SYSCFG 92 + 0x5c + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_191_160 + u0_plda_pcie_axi4_mst0_aratomop_191_160 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg96 + STG SYSCONSAIF SYSCFG 96 + 0x60 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_223_192 + u0_plda_pcie_axi4_mst0_aratomop_223_192 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg100 + STG SYSCONSAIF SYSCFG 100 + 0x64 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_255_224 + u0_plda_pcie_axi4_mst0_aratomop_255_224 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg104 + STG SYSCONSAIF SYSCFG 104 + 0x68 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_257_256 + u0_plda_pcie_axi4_mst0_aratomop_257_256 + [1:0] + read-only + + + u0_plda_pcie_axi4_mst0_arfunc + u0_plda_pcie_axi4_mst0_arfunc + [16:2] + read-only + + + u0_plda_pcie_axi4_mst0_arregion + u0_plda_pcie_axi4_mst0_arregion + [20:17] + read-only + + + + + stg_sysconsaif_syscfg108 + STG SYSCONSAIF SYSCFG 108 + 0x6c + 32 + + + u0_plda_pcie_axi4_mst0_aruser_31_0 + u0_plda_pcie_axi4_mst0_aruser_31_0 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg112 + STG SYSCONSAIF SYSCFG 112 + 0x70 + 32 + + + u0_plda_pcie_axi4_mst0_aruser_63_32 + u0_plda_pcie_axi4_mst0_aruser_63_32 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg116 + STG SYSCONSAIF SYSCFG 116 + 0x74 + 32 + + + u0_plda_pcie_axi4_mst0_awfunc + u0_plda_pcie_axi4_mst0_awfunc + [14:0] + read-only + + + u0_plda_pcie_axi4_mst0_awregion + u0_plda_pcie_axi4_mst0_awregion + [18:15] + read-only + + + + + stg_sysconsaif_syscfg120 + STG SYSCONSAIF SYSCFG 120 + 0x78 + 32 + + + u0_plda_pcie_axi4_mst0_a2user_31_0 + u0_plda_pcie_axi4_mst0_a2user_31_0 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg124 + STG SYSCONSAIF SYSCFG 124 + 0x7c + 32 + + + u0_plda_pcie_axi4_mst0_awuser_42_32 + u0_plda_pcie_axi4_mst0_awuser_42_32 + [10:0] + read-only + + + u0_plda_pcie_axi4_mst0_rderr + u0_plda_pcie_axi4_mst0_rderr + [18:11] + read-write + + + + + stg_sysconsaif_syscfg128 + STG SYSCONSAIF SYSCFG 128 + 0x80 + 32 + + + u0_plda_pcie_axi4_mst0_ruser + u0_plda_pcie_axi4_mst0_ruser + [31:0] + read-write + + + + + stg_sysconsaif_syscfg132 + STG SYSCONSAIF SYSCFG 132 + 0x84 + 32 + + + u0_plda_pcie_axi4_mst0_wderr + u0_plda_pcie_axi4_mst0_wderr + [7:0] + read-only + + + + + stg_sysconsaif_syscfg136 + STG SYSCONSAIF SYSCFG 136 + 0x88 + 32 + + + u0_plda_pcie_axi4_slv0_aratomop_31_0 + u0_plda_pcie_axi4_slv0_aratomop_31_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg140 + STG SYSCONSAIF SYSCFG 140 + 0x8c + 32 + + + u0_plda_pcie_axi4_slv0_aratomop_63_32 + u0_plda_pcie_axi4_slv0_aratomop_63_32 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg144 + STG SYSCONSAIF SYSCFG 144 + 0x90 + 32 + + + u0_plda_pcie_axi4_slv0_aratomop_95_64 + u0_plda_pcie_axi4_slv0_aratomop_95_64 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg148 + STG SYSCONSAIF SYSCFG 148 + 0x94 + 32 + + + u0_plda_pcie_axi4_slv0_aratomop_127_96 + u0_plda_pcie_axi4_slv0_aratomop_127_96 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg152 + STG SYSCONSAIF SYSCFG 152 + 0x98 + 32 + + + u0_plda_pcie_axi4_slv0_aratomop_159_128 + u0_plda_pcie_axi4_slv0_aratomop_159_128 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg156 + STG SYSCONSAIF SYSCFG 156 + 0x9c + 32 + + + u0_plda_pcie_axi4_slv0_aratomop_191_160 + u0_plda_pcie_axi4_slv0_aratomop_191_160 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg160 + STG SYSCONSAIF SYSCFG 160 + 0xa0 + 32 + + + u0_plda_pcie_axi4_slv0_aratomop_223_192 + u0_plda_pcie_axi4_slv0_aratomop_223_192 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg164 + STG SYSCONSAIF SYSCFG 164 + 0xa4 + 32 + + + u0_plda_pcie_axi4_slv0_aratomop_255_224 + u0_plda_pcie_axi4_slv0_aratomop_255_224 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg168 + STG SYSCONSAIF SYSCFG 168 + 0xa8 + 32 + + + u0_plda_pcie_axi4_slv0_aratomop_257_256 + u0_plda_pcie_axi4_slv0_aratomop_257_256 + [1:0] + read-write + + + u0_plda_pcie_axi4_slv0_arfunc + u0_plda_pcie_axi4_slv0_arfunc + [16:2] + read-write + + + u0_plda_pcie_axi4_slv0_arregion + u0_plda_pcie_axi4_slv0_arregion + [20:17] + read-write + + + + + stg_sysconsaif_syscfg172 + STG SYSCONSAIF SYSCFG 172 + 0xac + 32 + + + u0_plda_pcie_axi4_slv0_aruser_31_0 + u0_plda_pcie_axi4_slv0_aruser_31_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg176 + STG SYSCONSAIF SYSCFG 176 + 0xb0 + 32 + + + u0_plda_pcie_axi4_slv0_aruser_40_32 + u0_plda_pcie_axi4_slv0_aruser_40_32 + [8:0] + read-write + + + u0_plda_pcie_axi4_slv0_awfunc + u0_plda_pcie_axi4_slv0_awfunc + [23:9] + read-write + + + u0_plda_pcie_axi4_slv0_awregion + u0_plda_pcie_axi4_slv0_awregion + [27:24] + read-write + + + + + stg_sysconsaif_syscfg180 + STG SYSCONSAIF SYSCFG 180 + 0xb4 + 32 + + + u0_plda_pcie_axi4_slv0_awuser_31_0 + u0_plda_pcie_axi4_slv0_awuser_31_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg184 + STG SYSCONSAIF SYSCFG 184 + 0xb8 + 32 + + + u0_plda_pcie_axi4_slv0_awuser_40_32 + u0_plda_pcie_axi4_slv0_awuser_40_32 + [8:0] + read-write + + + u0_plda_pcie_axi4_slv0_rderr + u0_plda_pcie_axi4_slv0_rderr + [16:9] + read-only + + + + + stg_sysconsaif_syscfg188 + STG SYSCONSAIF SYSCFG 188 + 0xbc + 32 + + + u0_plda_pcie_axi4_slv0_ruser + u0_plda_pcie_axi4_slv0_ruser + [31:0] + read-only + + + + + stg_sysconsaif_syscfg192 + STG SYSCONSAIF SYSCFG 192 + 0xc0 + 32 + + + u0_plda_pcie_axi4_slv0_wderr + u0_plda_pcie_axi4_slv0_wderr + [7:0] + read-write + + + u0_plda_pcie_axi4_slvl_arfunc + u0_plda_pcie_axi4_slvl_arfunc + [22:8] + read-only + + + + + stg_sysconsaif_syscfg196 + STG SYSCONSAIF SYSCFG 196 + 0xc4 + 32 + + + u0_plda_pcie_axi4_slvl_awfunc + u0_plda_pcie_axi4_slvl_awfunc + [14:0] + read-write + + + u0_plda_pcie_bus_width_o + u0_plda_pcie_bus_width_o + [16:15] + read-only + + + u0_plda_pcie_bypass_codec + u0_plda_pcie_bypass_codec + [17:17] + read-write + + + u0_plda_pcie_ckref_src + u0_plda_pcie_ckref_src + [19:18] + read-write + + + u0_plda_pcie_clk_sel + u0_plda_pcie_clk_sel + [21:20] + read-write + + + u0_plda_pcie_clkreq + u0_plda_pcie_clkreq + [22:22] + read-write + + + + + stg_sysconsaif_syscfg200 + STG SYSCONSAIF SYSCFG 200 + 0xc8 + 32 + + + u0_plda_pcie_k_phyparam_31_0 + u0_plda_pcie_k_phyparam_31_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg204 + STG SYSCONSAIF SYSCFG 204 + 0xcc + 32 + + + u0_plda_pcie_k_phyparam_63_32 + u0_plda_pcie_k_phyparam_63_32 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg208 + STG SYSCONSAIF SYSCFG 208 + 0xd0 + 32 + + + u0_plda_pcie_k_phyparam_95_64 + u0_plda_pcie_k_phyparam_95_64 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg212 + STG SYSCONSAIF SYSCFG 212 + 0xd4 + 32 + + + u0_plda_pcie_k_phyparam_127_96 + u0_plda_pcie_k_phyparam_127_96 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg216 + STG SYSCONSAIF SYSCFG 216 + 0xd8 + 32 + + + u0_plda_pcie_k_phyparam_159_128 + u0_plda_pcie_k_phyparam_159_128 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg220 + STG SYSCONSAIF SYSCFG 220 + 0xdc + 32 + + + u0_plda_pcie_k_phyparam_191_160 + u0_plda_pcie_k_phyparam_191_160 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg224 + STG SYSCONSAIF SYSCFG 224 + 0xe0 + 32 + + + u0_plda_pcie_k_phyparam_223_192 + u0_plda_pcie_k_phyparam_223_192 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg228 + STG SYSCONSAIF SYSCFG 228 + 0xe4 + 32 + + + u0_plda_pcie_k_phyparam_255_224 + u0_plda_pcie_k_phyparam_255_224 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg232 + STG SYSCONSAIF SYSCFG 232 + 0xe8 + 32 + + + u0_plda_pcie_k_phyparam_287_256 + u0_plda_pcie_k_phyparam_287_256 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg236 + STG SYSCONSAIF SYSCFG 236 + 0xec + 32 + + + u0_plda_pcie_k_phyparam_319_288 + u0_plda_pcie_k_phyparam_319_288 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg240 + STG SYSCONSAIF SYSCFG 240 + 0xf0 + 32 + + + u0_plda_pcie_k_phyparam_351_320 + u0_plda_pcie_k_phyparam_351_320 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg244 + STG SYSCONSAIF SYSCFG 244 + 0xf4 + 32 + + + u0_plda_pcie_k_phyparam_383_352 + u0_plda_pcie_k_phyparam_383_352 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg248 + STG SYSCONSAIF SYSCFG 248 + 0xf8 + 32 + + + u0_plda_pcie_k_phyparam_415_384 + u0_plda_pcie_k_phyparam_415_384 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg252 + STG SYSCONSAIF SYSCFG 252 + 0xfc + 32 + + + u0_plda_pcie_k_phyparam_447_416 + u0_plda_pcie_k_phyparam_447_416 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg256 + STG SYSCONSAIF SYSCFG 256 + 0x100 + 32 + + + u0_plda_pcie_k_phyparam_479_448 + u0_plda_pcie_k_phyparam_479_448 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg260 + STG SYSCONSAIF SYSCFG 260 + 0x104 + 32 + + + u0_plda_pcie_k_phyparam_511_480 + u0_plda_pcie_k_phyparam_511_480 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg264 + STG SYSCONSAIF SYSCFG 264 + 0x108 + 32 + + + u0_plda_pcie_k_phyparam_543_512 + u0_plda_pcie_k_phyparam_543_512 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg268 + STG SYSCONSAIF SYSCFG 268 + 0x10c + 32 + + + u0_plda_pcie_k_phyparam_575_544 + u0_plda_pcie_k_phyparam_575_544 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg272 + STG SYSCONSAIF SYSCFG 272 + 0x110 + 32 + + + u0_plda_pcie_k_phyparam_607_576 + u0_plda_pcie_k_phyparam_607_576 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg276 + STG SYSCONSAIF SYSCFG 276 + 0x114 + 32 + + + u0_plda_pcie_k_phyparam_639_608 + u0_plda_pcie_k_phyparam_639_608 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg280 + STG SYSCONSAIF SYSCFG 280 + 0x118 + 32 + + + u0_plda_pcie_k_phyparam_671_640 + u0_plda_pcie_k_phyparam_671_640 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg284 + STG SYSCONSAIF SYSCFG 284 + 0x11c + 32 + + + u0_plda_pcie_k_phyparam_703_672 + u0_plda_pcie_k_phyparam_703_672 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg288 + STG SYSCONSAIF SYSCFG 288 + 0x120 + 32 + + + u0_plda_pcie_k_phyparam_735_704 + u0_plda_pcie_k_phyparam_735_704 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg292 + STG SYSCONSAIF SYSCFG 292 + 0x124 + 32 + + + u0_plda_pcie_k_phyparam_767_736 + u0_plda_pcie_k_phyparam_767_736 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg296 + STG SYSCONSAIF SYSCFG 296 + 0x128 + 32 + + + u0_plda_pcie_k_phyparam_799_768 + u0_plda_pcie_k_phyparam_799_768 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg300 + STG SYSCONSAIF SYSCFG 300 + 0x12c + 32 + + + u0_plda_pcie_k_phyparam_831_800 + u0_plda_pcie_k_phyparam_831_800 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg304 + STG SYSCONSAIF SYSCFG 304 + 0x130 + 32 + + + u0_plda_pcie_k_phyparam_839_832 + u0_plda_pcie_k_phyparam_839_832 + [7:0] + read-write + + + u0_plda_pcie_k_rp_nep + u0_plda_pcie_k_rp_nep + [8:8] + read-write + + + u0_plda_pcie_l1sub_entack + u0_plda_pcie_l1sub_entack + [9:9] + read-only + + + u0_plda_pcie_l1sub_entreq + u0_plda_pcie_l1sub_entreq + [10:10] + read-write + + + + + stg_sysconsaif_syscfg308 + STG SYSCONSAIF SYSCFG 308 + 0x134 + 32 + + + u0_plda_pcie_local_interrupt_in + u0_plda_pcie_local_interrupt_in + [31:0] + read-write + + + + + stg_sysconsaif_syscfg312 + STG SYSCONSAIF SYSCFG 312 + 0x138 + 32 + + + u0_plda_pcie_mperstn + u0_plda_pcie_mperstn + [0:0] + read-write + + + u0_plda_pcie_pcie_ebuf_mode + u0_plda_pcie_pcie_ebuf_mode + [1:1] + read-write + + + u0_plda_pcie_pcie_phy_test_cfg + u0_plda_pcie_pcie_phy_test_cfg + [24:2] + read-write + + + u0_plda_pcie_pcie_rx_eq_training + u0_plda_pcie_pcie_rx_eq_training + [25:25] + read-write + + + u0_plda_pcie_pcie_rxterm_en + u0_plda_pcie_pcie_rxterm_en + [26:26] + read-write + + + u0_plda_pcie_pcie_tx_onezeros + u0_plda_pcie_pcie_tx_onezeros + [27:27] + read-write + + + + + stg_sysconsaif_syscfg316 + STG SYSCONSAIF SYSCFG 316 + 0x13c + 32 + + + u0_plda_pcie_pf0_offset + u0_plda_pcie_pf0_offset + [19:0] + read-write + + + + + stg_sysconsaif_syscfg320 + STG SYSCONSAIF SYSCFG 320 + 0x140 + 32 + + + u0_plda_pcie_pf1_offset + u0_plda_pcie_pf1_offset + [19:0] + read-write + + + + + stg_sysconsaif_syscfg324 + STG SYSCONSAIF SYSCFG 324 + 0x144 + 32 + + + u0_plda_pcie_pf2_offset + u0_plda_pcie_pf2_offset + [19:0] + read-write + + + + + stg_sysconsaif_syscfg328 + STG SYSCONSAIF SYSCFG 328 + 0x148 + 32 + + + u0_plda_pcie_pf3_offset + u0_plda_pcie_pf3_offset + [19:0] + read-write + + + u0_plda_pcie_phy_mode + u0_plda_pcie_phy_mode + [21:20] + read-write + + + u0_plda_pcie_pl_clkrem_allow + u0_plda_pcie_pl_clkrem_allow + [22:22] + read-write + + + u0_plda_pcie_pl_clkreq_oen + u0_plda_pcie_pl_clkreq_oen + [23:23] + read-only + + + u0_plda_pcie_pl_equ_phase + u0_plda_pcie_pl_equ_phase + [25:24] + read-only + + + u0_plda_pcie_pl_ltssm + u0_plda_pcie_pl_ltssm + [30:26] + read-only + + + + + stg_sysconsaif_syscfg332 + STG SYSCONSAIF SYSCFG 332 + 0x14c + 32 + + + u0_plda_pcie_pl_pclk_rate + u0_plda_pcie_pl_pclk_rate + [4:0] + read-only + + + + + stg_sysconsaif_syscfg336 + STG SYSCONSAIF SYSCFG 336 + 0x150 + 32 + + + u0_plda_pcie_pl_sideband_in_31_0 + u0_plda_pcie_pl_sideband_in_31_0 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg340 + STG SYSCONSAIF SYSCFG 340 + 0x154 + 32 + + + u0_plda_pcie_pl_sideband_in_63_32 + u0_plda_pcie_pl_sideband_in_63_32 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg344 + STG SYSCONSAIF SYSCFG 344 + 0x158 + 32 + + + u0_plda_pcie_pl_sideband_out_31_0 + u0_plda_pcie_pl_sideband_out_31_0 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg348 + STG SYSCONSAIF SYSCFG 348 + 0x15c + 32 + + + u0_plda_pcie_pl_sideband_out_63_32 + u0_plda_pcie_pl_sideband_out_63_32 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg352 + STG SYSCONSAIF SYSCFG 352 + 0x160 + 32 + + + u0_plda_pcie_pl_wake_in + u0_plda_pcie_pl_wake_in + [0:0] + read-write + + + u0_plda_pcie_pl_wake_oen + u0_plda_pcie_pl_wake_oen + [1:1] + read-only + + + u0_plda_pcie_rx_standby_0 + u0_plda_pcie_rx_standby_0 + [2:2] + read-only + + + + + stg_sysconsaif_syscfg356 + STG SYSCONSAIF SYSCFG 356 + 0x164 + 32 + + + u0_plda_pcie_test_in_31_0 + u0_plda_pcie_test_in_31_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg360 + STG SYSCONSAIF SYSCFG 360 + 0x168 + 32 + + + u0_plda_pcie_test_in_63_32 + u0_plda_pcie_test_in_63_32 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg364 + STG SYSCONSAIF SYSCFG 364 + 0x16c + 32 + + + u0_plda_pcie_test_out_bridge_31_0 + u0_plda_pcie_test_out_bridge_31_0 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg368 + STG SYSCONSAIF SYSCFG 368 + 0x170 + 32 + + + u0_plda_pcie_test_out_bridge_63_32 + u0_plda_pcie_test_out_bridge_63_32 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg372 + STG SYSCONSAIF SYSCFG 372 + 0x174 + 32 + + + u0_plda_pcie_test_out_bridge_95_64 + u0_plda_pcie_test_out_bridge_95_64 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg376 + STG SYSCONSAIF SYSCFG 376 + 0x178 + 32 + + + u0_plda_pcie_test_out_bridge_127_96 + u0_plda_pcie_test_out_bridge_127_96 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg380 + STG SYSCONSAIF SYSCFG 380 + 0x17c + 32 + + + u0_plda_pcie_test_out_bridge_159_128 + u0_plda_pcie_test_out_bridge_159_128 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg384 + STG SYSCONSAIF SYSCFG 384 + 0x180 + 32 + + + u0_plda_pcie_test_out_bridge_191_160 + u0_plda_pcie_test_out_bridge_191_160 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg388 + STG SYSCONSAIF SYSCFG 388 + 0x184 + 32 + + + u0_plda_pcie_test_out_bridge_223_192 + u0_plda_pcie_test_out_bridge_223_192 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg392 + STG SYSCONSAIF SYSCFG 392 + 0x188 + 32 + + + u0_plda_pcie_test_out_bridge_255_224 + u0_plda_pcie_test_out_bridge_255_224 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg396 + STG SYSCONSAIF SYSCFG 396 + 0x18c + 32 + + + u0_plda_pcie_test_out_bridge_287_256 + u0_plda_pcie_test_out_bridge_287_256 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg400 + STG SYSCONSAIF SYSCFG 400 + 0x190 + 32 + + + u0_plda_pcie_test_out_bridge_319_288 + u0_plda_pcie_test_out_bridge_319_288 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg404 + STG SYSCONSAIF SYSCFG 404 + 0x194 + 32 + + + u0_plda_pcie_test_out_bridge_351_320 + u0_plda_pcie_test_out_bridge_351_320 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg408 + STG SYSCONSAIF SYSCFG 408 + 0x198 + 32 + + + u0_plda_pcie_test_out_bridge_383_352 + u0_plda_pcie_test_out_bridge_383_352 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg412 + STG SYSCONSAIF SYSCFG 412 + 0x19c + 32 + + + u0_plda_pcie_test_out_bridge_415_384 + u0_plda_pcie_test_out_bridge_415_384 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg416 + STG SYSCONSAIF SYSCFG 416 + 0x1a0 + 32 + + + u0_plda_pcie_test_out_bridge_447_416 + u0_plda_pcie_test_out_bridge_447_416 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg420 + STG SYSCONSAIF SYSCFG 420 + 0x1a4 + 32 + + + u0_plda_pcie_test_out_bridge_479_448 + u0_plda_pcie_test_out_bridge_479_448 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg424 + STG SYSCONSAIF SYSCFG 424 + 0x1a8 + 32 + + + u0_plda_pcie_test_out_bridge_511_480 + u0_plda_pcie_test_out_bridge_511_480 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg428 + STG SYSCONSAIF SYSCFG 428 + 0x1ac + 32 + + + u0_plda_pcie_test_out_pcie_31_0 + u0_plda_pcie_test_out_pcie_31_0 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg432 + STG SYSCONSAIF SYSCFG 432 + 0x1b0 + 32 + + + u0_plda_pcie_test_out_pcie_63_32 + u0_plda_pcie_test_out_pcie_63_32 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg436 + STG SYSCONSAIF SYSCFG 436 + 0x1b4 + 32 + + + u0_plda_pcie_test_out_pcie_95_64 + u0_plda_pcie_test_out_pcie_95_64 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg440 + STG SYSCONSAIF SYSCFG 440 + 0x1b8 + 32 + + + u0_plda_pcie_test_out_pcie_127_96 + u0_plda_pcie_test_out_pcie_127_96 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg444 + STG SYSCONSAIF SYSCFG 444 + 0x1bc + 32 + + + u0_plda_pcie_test_out_pcie_159_128 + u0_plda_pcie_test_out_pcie_159_128 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg448 + STG SYSCONSAIF SYSCFG 448 + 0x1c0 + 32 + + + u0_plda_pcie_test_out_pcie_191_160 + u0_plda_pcie_test_out_pcie_191_160 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg452 + STG SYSCONSAIF SYSCFG 452 + 0x1c4 + 32 + + + u0_plda_pcie_test_out_pcie_223_192 + u0_plda_pcie_test_out_pcie_223_192 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg456 + STG SYSCONSAIF SYSCFG 456 + 0x1c8 + 32 + + + u0_plda_pcie_test_out_pcie_255_224 + u0_plda_pcie_test_out_pcie_255_224 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg460 + STG SYSCONSAIF SYSCFG 460 + 0x1cc + 32 + + + u0_plda_pcie_test_out_pcie_287_256 + u0_plda_pcie_test_out_pcie_287_256 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg464 + STG SYSCONSAIF SYSCFG 464 + 0x1d0 + 32 + + + u0_plda_pcie_test_out_pcie_319_288 + u0_plda_pcie_test_out_pcie_319_288 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg468 + STG SYSCONSAIF SYSCFG 468 + 0x1d4 + 32 + + + u0_plda_pcie_test_out_pcie_351_320 + u0_plda_pcie_test_out_pcie_351_320 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg472 + STG SYSCONSAIF SYSCFG 472 + 0x1d8 + 32 + + + u0_plda_pcie_test_out_pcie_383_352 + u0_plda_pcie_test_out_pcie_383_352 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg476 + STG SYSCONSAIF SYSCFG 476 + 0x1dc + 32 + + + u0_plda_pcie_test_out_pcie_415_384 + u0_plda_pcie_test_out_pcie_415_384 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg480 + STG SYSCONSAIF SYSCFG 480 + 0x1e0 + 32 + + + u0_plda_pcie_test_out_pcie_447_416 + u0_plda_pcie_test_out_pcie_447_416 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg484 + STG SYSCONSAIF SYSCFG 484 + 0x1e4 + 32 + + + u0_plda_pcie_test_out_pcie_479_448 + u0_plda_pcie_test_out_pcie_479_448 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg488 + STG SYSCONSAIF SYSCFG 488 + 0x1e8 + 32 + + + u0_plda_pcie_test_out_pcie_511_480 + u0_plda_pcie_test_out_pcie_511_480 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg492 + STG SYSCONSAIF SYSCFG 492 + 0x1ec + 32 + + + u0_plda_pcie_test_sel + u0_plda_pcie_test_sel + [3:0] + read-write + + + u0_plda_pcie_tl_clock_freq + u0_plda_pcie_tl_clock_freq + [25:4] + read-write + + + + + stg_sysconsaif_syscfg500 + STG SYSCONSAIF SYSCFG 500 + 0x1f4 + 32 + + + u0_plda_pcie_tx_pattern + u0_plda_pcie_tx_pattern + [1:0] + read-write + + + u0_plda_pcie_usb3_bus_width + u0_plda_pcie_usb3_bus_width + [3:2] + read-write + + + u0_plda_pcie_usb3_phy_enable + u0_plda_pcie_usb3_phy_enable + [4:4] + read-write + + + u0_plda_pcie_usb3_rate + u0_plda_pcie_usb3_rate + [6:5] + read-write + + + u0_plda_pcie_usb3_rx_standby + u0_plda_pcie_usb3_rx_standby + [7:7] + read-write + + + u0_plda_pcie_xwdecerr + u0_plda_pcie_xwdecerr + [8:8] + read-only + + + u0_plda_pcie_xwerrclr + u0_plda_pcie_xwerrclr + [9:9] + read-write + + + u0_plda_pcie_xwslverr + u0_plda_pcie_xwslverr + [10:10] + read-only + + + u0_sec_top_sramcfg_slp + SRAM/ROM configuration. SLP: sleep enable, high active, default is low. + [11:11] + read-write + + + u0_sec_top_sramcfg_sram_config_sd + SRAM/ROM configuration. SD: shutdown enable, high active, default is low. + [12:12] + read-write + + + u0_sec_top_sramcfg_rtsel + SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. + [14:13] + read-write + + + u0_sec_top_sramcfg_ptsel + SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. + [16:15] + read-write + + + u0_sec_top_sramcfg_trb + SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. + [18:17] + read-write + + + u0_sec_top_sramcfg_wtsel + SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. + [20:19] + read-write + + + u0_sec_top_sramcfg_vs + SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. + [21:21] + read-write + + + u0_sec_top_sramcfg_vg + SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. + [22:22] + read-write + + + u0_plda_pcie_align_detect + u0_plda_pcie_align_detect + [23:23] + read-only + + + + + stg_sysconsaif_syscfg504 + STG SYSCONSAIF SYSCFG 504 + 0x1f8 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_31_0 + u0_plda_pcie_axi4_mst0_aratomop_31_0 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg508 + STG SYSCONSAIF SYSCFG 508 + 0x1fc + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_63_32 + u0_plda_pcie_axi4_mst0_aratomop_63_32 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg512 + STG SYSCONSAIF SYSCFG 512 + 0x200 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_95_64 + u0_plda_pcie_axi4_mst0_aratomop_95_64 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg516 + STG SYSCONSAIF SYSCFG 516 + 0x204 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_127_96 + u0_plda_pcie_axi4_mst0_aratomop_127_96 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg520 + STG SYSCONSAIF SYSCFG 520 + 0x208 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_159_128 + u0_plda_pcie_axi4_mst0_aratomop_159_128 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg524 + STG SYSCONSAIF SYSCFG 524 + 0x20c + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_191_160 + u0_plda_pcie_axi4_mst0_aratomop_191_160 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg528 + STG SYSCONSAIF SYSCFG 528 + 0x210 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_223_192 + u0_plda_pcie_axi4_mst0_aratomop_223_192 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg532 + STG SYSCONSAIF SYSCFG 532 + 0x214 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_255_224 + u0_plda_pcie_axi4_mst0_aratomop_255_224 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg536 + STG SYSCONSAIF SYSCFG 536 + 0x218 + 32 + + + u0_plda_pcie_axi4_mst0_aratomop_257_256 + u0_plda_pcie_axi4_mst0_aratomop_257_256 + [1:0] + read-only + + + u0_plda_pcie_axi4_mst0_arfunc + u0_plda_pcie_axi4_mst0_arfunc + [16:2] + read-only + + + u0_plda_pcie_axi4_mst0_arregion + u0_plda_pcie_axi4_mst0_arregion + [20:17] + read-only + + + + + stg_sysconsaif_syscfg540 + STG SYSCONSAIF SYSCFG 540 + 0x21c + 32 + + + u1_plda_pcie_axi4_mst0_aruser_31_0 + u1_plda_pcie_axi4_mst0_aruser_31_0 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg544 + STG SYSCONSAIF SYSCFG 544 + 0x220 + 32 + + + u1_plda_pcie_axi4_mst0_aruser_52_32 + u1_plda_pcie_axi4_mst0_aruser_52_32 + [20:0] + read-only + + + + + stg_sysconsaif_syscfg548 + STG SYSCONSAIF SYSCFG 548 + 0x224 + 32 + + + u1_plda_pcie_axi4_mst0_awfunc + u1_plda_pcie_axi4_mst0_awfunc + [14:0] + read-only + + + u1_plda_pcie_axi4_mst0_awregion + u1_plda_pcie_axi4_mst0_awregion + [18:15] + read-only + + + + + stg_sysconsaif_syscfg552 + STG SYSCONSAIF SYSCFG 552 + 0x228 + 32 + + + u1_plda_pcie_axi4_mst0_awuser_31_0 + u1_plda_pcie_axi4_mst0_awuser_31_0 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg556 + STG SYSCONSAIF SYSCFG 556 + 0x22c + 32 + + + u1_plda_pcie_axi4_mst0_awuser_42_32 + u1_plda_pcie_axi4_mst0_awuser_42_32 + [10:0] + read-only + + + u1_plda_pcie_axi4_mst0_rderr + u1_plda_pcie_axi4_mst0_rderr + [18:11] + read-write + + + + + stg_sysconsaif_syscfg560 + STG SYSCONSAIF SYSCFG 560 + 0x230 + 32 + + + u1_plda_pcie_axi4_mst0_ruser + u1_plda_pcie_axi4_mst0_ruser + [31:0] + read-write + + + + + stg_sysconsaif_syscfg564 + STG SYSCONSAIF SYSCFG 564 + 0x234 + 32 + + + u1_plda_pcie_axi4_mst0_wderr + u1_plda_pcie_axi4_mst0_wderr + [7:0] + read-only + + + + + stg_sysconsaif_syscfg568 + STG SYSCONSAIF SYSCFG 568 + 0x238 + 32 + + + u1_plda_pcie_axi4_slv0_aratomop_31_0 + u1_plda_pcie_axi4_slv0_aratomop_31_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg572 + STG SYSCONSAIF SYSCFG 572 + 0x23c + 32 + + + u1_plda_pcie_axi4_slv0_aratomop_63_32 + u1_plda_pcie_axi4_slv0_aratomop_63_32 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg576 + STG SYSCONSAIF SYSCFG 576 + 0x240 + 32 + + + u1_plda_pcie_axi4_slv0_aratomop_95_64 + u1_plda_pcie_axi4_slv0_aratomop_95_64 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg580 + STG SYSCONSAIF SYSCFG 580 + 0x244 + 32 + + + u1_plda_pcie_axi4_slv0_aratomop_127_96 + u1_plda_pcie_axi4_slv0_aratomop_127_96 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg584 + STG SYSCONSAIF SYSCFG 584 + 0x248 + 32 + + + u1_plda_pcie_axi4_slv0_aratomop_159_128 + u1_plda_pcie_axi4_slv0_aratomop_159_128 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg588 + STG SYSCONSAIF SYSCFG 588 + 0x24c + 32 + + + u1_plda_pcie_axi4_slv0_aratomop_191_160 + u1_plda_pcie_axi4_slv0_aratomop_191_160 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg592 + STG SYSCONSAIF SYSCFG 592 + 0x250 + 32 + + + u1_plda_pcie_axi4_slv0_aratomop_223_192 + u1_plda_pcie_axi4_slv0_aratomop_223_192 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg596 + STG SYSCONSAIF SYSCFG 596 + 0x254 + 32 + + + u1_plda_pcie_axi4_slv0_aratomop_255_224 + u1_plda_pcie_axi4_slv0_aratomop_255_224 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg600 + STG SYSCONSAIF SYSCFG 600 + 0x258 + 32 + + + u1_plda_pcie_axi4_mst0_aratomop_257_256 + u1_plda_pcie_axi4_mst0_aratomop_257_256 + [1:0] + read-write + + + u1_plda_pcie_axi4_slv0_arfunc + u1_plda_pcie_axi4_slv0_arfunc + [16:2] + read-write + + + u1_plda_pcie_axi4_slv0_arregion + u1_plda_pcie_axi4_slv0_arregion + [20:17] + read-write + + + + + stg_sysconsaif_syscfg604 + STG SYSCONSAIF SYSCFG 604 + 0x25c + 32 + + + u1_plda_pcie_axi4_slv0_aruser_31_0 + u1_plda_pcie_axi4_slv0_aruser_31_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg608 + STG SYSCONSAIF SYSCFG 608 + 0x260 + 32 + + + u1_plda_pcie_axi4_slv0_aruser_40_32 + u1_plda_pcie_axi4_slv0_aruser_40_32 + [8:0] + read-write + + + u1_plda_pcie_axi4_slv0_awfunc + u1_plda_pcie_axi4_slv0_awfunc + [23:9] + read-write + + + u1_plda_pcie_axi4_slv0_awregion + u1_plda_pcie_axi4_slv0_awregion + [27:24] + read-write + + + + + stg_sysconsaif_syscfg612 + STG SYSCONSAIF SYSCFG 612 + 0x264 + 32 + + + u1_plda_pcie_axi4_slv0_awuser_31_0 + u1_plda_pcie_axi4_slv0_awuser_31_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg616 + STG SYSCONSAIF SYSCFG 616 + 0x268 + 32 + + + u1_plda_pcie_axi4_slv0_awuser_40_32 + u1_plda_pcie_axi4_slv0_awuser_40_32 + [8:0] + read-write + + + u1_plda_pcie_axi4_slv0_rderr + u1_plda_pcie_axi4_slv0_rderr + [16:9] + read-only + + + + + stg_sysconsaif_syscfg620 + STG SYSCONSAIF SYSCFG 620 + 0x26c + 32 + + + u1_plda_pcie_axi4_slv0_ruser + u1_plda_pcie_axi4_slv0_ruser + [31:0] + read-only + + + + + stg_sysconsaif_syscfg624 + STG SYSCONSAIF SYSCFG 624 + 0x270 + 32 + + + u1_plda_pcie_axi4_slv0_wderr + u1_plda_pcie_axi4_slv0_wderr + [7:0] + read-write + + + u1_plda_pcie_axi4_slvl_arfunc + u1_plda_pcie_axi4_slvl_arfunc + [22:8] + read-write + + + + + stg_sysconsaif_syscfg628 + STG SYSCONSAIF SYSCFG 628 + 0x274 + 32 + + + u1_plda_pcie_axi4_slvl_awfunc + u1_plda_pcie_axi4_slvl_awfunc + [14:0] + read-write + + + u1_plda_pcie_bus_width_o + u1_plda_pcie_bus_width_o + [16:15] + read-only + + + u1_plda_pcie_bypass_codec + u1_plda_pcie_bypass_codec + [17:17] + read-write + + + u1_plda_pcie_ckref_src + u1_plda_pcie_ckref_src + [19:18] + read-write + + + u1_plda_pcie_clk_sel + u1_plda_pcie_clk_sel + [21:20] + read-write + + + u1_plda_pcie_clkreq + u1_plda_pcie_clkreq + [22:22] + read-write + + + + + stg_sysconsaif_syscfg632 + STG SYSCONSAIF SYSCFG 632 + 0x278 + 32 + + + u1_plda_pcie_k_phyparam_31_0 + u1_plda_pcie_k_phyparam_31_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg636 + STG SYSCONSAIF SYSCFG 636 + 0x27c + 32 + + + u1_plda_pcie_k_phyparam_63_32 + u1_plda_pcie_k_phyparam_63_32 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg640 + STG SYSCONSAIF SYSCFG 640 + 0x280 + 32 + + + u1_plda_pcie_k_phyparam_95_64 + u1_plda_pcie_k_phyparam_95_64 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg644 + STG SYSCONSAIF SYSCFG 644 + 0x284 + 32 + + + u1_plda_pcie_k_phyparam_127_96 + u1_plda_pcie_k_phyparam_127_96 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg648 + STG SYSCONSAIF SYSCFG 648 + 0x288 + 32 + + + u1_plda_pcie_k_phyparam_159_128 + u1_plda_pcie_k_phyparam_159_128 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg652 + STG SYSCONSAIF SYSCFG 652 + 0x28c + 32 + + + u1_plda_pcie_k_phyparam_191_160 + u1_plda_pcie_k_phyparam_191_160 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg656 + STG SYSCONSAIF SYSCFG 656 + 0x290 + 32 + + + u1_plda_pcie_k_phyparam_223_192 + u1_plda_pcie_k_phyparam_223_192 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg660 + STG SYSCONSAIF SYSCFG 660 + 0x294 + 32 + + + u1_plda_pcie_k_phyparam_255_224 + u1_plda_pcie_k_phyparam_255_224 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg664 + STG SYSCONSAIF SYSCFG 664 + 0x298 + 32 + + + u1_plda_pcie_k_phyparam_287_256 + u1_plda_pcie_k_phyparam_287_256 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg668 + STG SYSCONSAIF SYSCFG 668 + 0x29c + 32 + + + u1_plda_pcie_k_phyparam_319_288 + u1_plda_pcie_k_phyparam_319_288 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg672 + STG SYSCONSAIF SYSCFG 672 + 0x2a0 + 32 + + + u1_plda_pcie_k_phyparam_351_320 + u1_plda_pcie_k_phyparam_351_320 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg676 + STG SYSCONSAIF SYSCFG 676 + 0x2a4 + 32 + + + u1_plda_pcie_k_phyparam_383_352 + u1_plda_pcie_k_phyparam_383_352 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg680 + STG SYSCONSAIF SYSCFG 680 + 0x2a8 + 32 + + + u1_plda_pcie_k_phyparam_415_384 + u1_plda_pcie_k_phyparam_415_384 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg684 + STG SYSCONSAIF SYSCFG 684 + 0x2ac + 32 + + + u1_plda_pcie_k_phyparam_447_416 + u1_plda_pcie_k_phyparam_447_416 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg688 + STG SYSCONSAIF SYSCFG 688 + 0x2b0 + 32 + + + u1_plda_pcie_k_phyparam_479_448 + u1_plda_pcie_k_phyparam_479_448 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg692 + STG SYSCONSAIF SYSCFG 692 + 0x2b4 + 32 + + + u1_plda_pcie_k_phyparam_511_480 + u1_plda_pcie_k_phyparam_511_480 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg696 + STG SYSCONSAIF SYSCFG 696 + 0x2b8 + 32 + + + u1_plda_pcie_k_phyparam_543_512 + u1_plda_pcie_k_phyparam_543_512 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg700 + STG SYSCONSAIF SYSCFG 700 + 0x2bc + 32 + + + u1_plda_pcie_k_phyparam_575_544 + u1_plda_pcie_k_phyparam_575_544 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg704 + STG SYSCONSAIF SYSCFG 704 + 0x2c0 + 32 + + + u1_plda_pcie_k_phyparam_607_576 + u1_plda_pcie_k_phyparam_607_576 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg708 + STG SYSCONSAIF SYSCFG 708 + 0x2c4 + 32 + + + u1_plda_pcie_k_phyparam_639_608 + u1_plda_pcie_k_phyparam_639_608 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg712 + STG SYSCONSAIF SYSCFG 712 + 0x2c8 + 32 + + + u1_plda_pcie_k_phyparam_671_640 + u1_plda_pcie_k_phyparam_671_640 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg716 + STG SYSCONSAIF SYSCFG 716 + 0x2cc + 32 + + + u1_plda_pcie_k_phyparam_703_672 + u1_plda_pcie_k_phyparam_703_672 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg720 + STG SYSCONSAIF SYSCFG 720 + 0x2d0 + 32 + + + u1_plda_pcie_k_phyparam_735_704 + u1_plda_pcie_k_phyparam_735_704 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg724 + STG SYSCONSAIF SYSCFG 724 + 0x2d4 + 32 + + + u1_plda_pcie_k_phyparam_767_736 + u1_plda_pcie_k_phyparam_767_736 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg728 + STG SYSCONSAIF SYSCFG 728 + 0x2d8 + 32 + + + u1_plda_pcie_k_phyparam_799_768 + u1_plda_pcie_k_phyparam_799_768 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg732 + STG SYSCONSAIF SYSCFG 732 + 0x2dc + 32 + + + u1_plda_pcie_k_phyparam_831_800 + u1_plda_pcie_k_phyparam_831_800 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg736 + STG SYSCONSAIF SYSCFG 736 + 0x2e0 + 32 + + + u1_plda_pcie_k_phyparam_839_832 + u1_plda_pcie_k_phyparam_839_832 + [7:0] + read-write + + + u1_plda_pcie_k_rp_nep + u1_plda_pcie_k_rp_nep + [8:8] + read-write + + + u1_plda_pcie_l1sub_entack + u1_plda_pcie_l1sub_entack + [9:9] + read-only + + + u1_plda_pcie_l1sub_entreq + u1_plda_pcie_l1sub_entreq + [10:10] + read-write + + + + + stg_sysconsaif_syscfg740 + STG SYSCONSAIF SYSCFG 740 + 0x2e4 + 32 + + + u1_plda_pcie_local_interrupt_in + u1_plda_pcie_local_interrupt_in + [31:0] + read-write + + + + + stg_sysconsaif_syscfg744 + STG SYSCONSAIF SYSCFG 744 + 0x2e8 + 32 + + + u1_plda_pcie_mperstn + u1_plda_pcie_mperstn + [0:0] + read-write + + + u1_plda_pcie_pcie_ebuf_mode + u1_plda_pcie_pcie_ebuf_mode + [1:1] + read-write + + + u1_plda_pcie_pcie_phy_test_cfg + u1_plda_pcie_pcie_phy_test_cfg + [24:2] + read-write + + + u1_plda_pcie_pcie_rx_eq_training + u1_plda_pcie_pcie_rx_eq_training + [25:25] + read-write + + + u1_plda_pcie_pcie_rxterm_en + u1_plda_pcie_pcie_rxterm_en + [26:26] + read-write + + + u1_plda_pcie_pcie_tx_oneszeros + u1_plda_pcie_pcie_tx_oneszeros + [27:27] + read-write + + + + + stg_sysconsaif_syscfg748 + STG SYSCONSAIF SYSCFG 748 + 0x2ec + 32 + + + u1_plda_pcie_pf0_offset + u1_plda_pcie_pf0_offset + [19:0] + read-write + + + + + stg_sysconsaif_syscfg752 + STG SYSCONSAIF SYSCFG 752 + 0x2f0 + 32 + + + u1_plda_pcie_pf1_offset + u1_plda_pcie_pf1_offset + [19:0] + read-write + + + + + stg_sysconsaif_syscfg756 + STG SYSCONSAIF SYSCFG 756 + 0x2f4 + 32 + + + u1_plda_pcie_pf2_offset + u1_plda_pcie_pf2_offset + [19:0] + read-write + + + + + stg_sysconsaif_syscfg760 + STG SYSCONSAIF SYSCFG 760 + 0x2f8 + 32 + + + u1_plda_pcie_pf3_offset + u1_plda_pcie_pf3_offset + [19:0] + read-write + + + u1_plda_pcie_phy_mode + u1_plda_pcie_phy_mode + [21:20] + read-write + + + u1_plda_pcie_pl_clkrem_allow + u1_plda_pcie_pl_clkrem_allow + [22:22] + read-write + + + u1_plda_pcie_pl_clkreq_oen + u1_plda_pcie_pl_clkreq_oen + [23:23] + read-only + + + u1_plda_pcie_pl_equ_phase + u1_plda_pcie_pl_equ_phase + [25:24] + read-only + + + u1_plda_pcie_pl_ltssm + u1_plda_pcie_pl_ltssm + [30:26] + read-only + + + + + stg_sysconsaif_syscfg764 + STG SYSCONSAIF SYSCFG 764 + 0x2fc + 32 + + + u1_plda_pcie_pl_pclk_rate + u1_plda_pcie_pl_pclk_rate + [4:0] + read-only + + + + + stg_sysconsaif_syscfg768 + STG SYSCONSAIF SYSCFG 768 + 0x300 + 32 + + + u1_plda_pcie_pl_sideband_in_31_0 + u1_plda_pcie_pl_sideband_in_31_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg772 + STG SYSCONSAIF SYSCFG 772 + 0x304 + 32 + + + u1_plda_pcie_pl_sideband_in_63_32 + u1_plda_pcie_pl_sideband_in_63_32 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg776 + STG SYSCONSAIF SYSCFG 776 + 0x308 + 32 + + + u1_plda_pcie_pl_sideband_out_31_0 + u1_plda_pcie_pl_sideband_out_31_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg780 + STG SYSCONSAIF SYSCFG 780 + 0x30c + 32 + + + u1_plda_pcie_pl_sideband_out_63_32 + u1_plda_pcie_pl_sideband_out_63_32 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg784 + STG SYSCONSAIF SYSCFG 784 + 0x310 + 32 + + + u1_plda_pcie_pl_wake_in + u1_plda_pcie_pl_wake_in + [0:0] + read-write + + + u1_plda_pcie_pl_wake_oen + u1_plda_pcie_pl_wake_oen + [1:1] + read-only + + + u1_plda_pcie_rx_standby_o + u1_plda_pcie_rx_standby_o + [2:2] + read-only + + + + + stg_sysconsaif_syscfg788 + STG SYSCONSAIF SYSCFG 788 + 0x314 + 32 + + + u1_plda_pcie_test_in_31_0 + u1_plda_pcie_test_in_31_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg792 + STG SYSCONSAIF SYSCFG 792 + 0x318 + 32 + + + u1_plda_pcie_test_in_63_32 + u1_plda_pcie_test_in_63_32 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg796 + STG SYSCONSAIF SYSCFG 796 + 0x31c + 32 + + + u1_plda_pcie_test_out_bridge_31_0 + u1_plda_pcie_test_out_bridge_31_0 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg800 + STG SYSCONSAIF SYSCFG 800 + 0x320 + 32 + + + u1_plda_pcie_test_out_bridge_63_32 + u1_plda_pcie_test_out_bridge_63_32 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg804 + STG SYSCONSAIF SYSCFG 804 + 0x324 + 32 + + + u1_plda_pcie_test_out_bridge_95_64 + u1_plda_pcie_test_out_bridge_95_64 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg808 + STG SYSCONSAIF SYSCFG 808 + 0x328 + 32 + + + u1_plda_pcie_test_out_bridge_127_96 + u1_plda_pcie_test_out_bridge_127_96 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg812 + STG SYSCONSAIF SYSCFG 812 + 0x32c + 32 + + + u1_plda_pcie_test_out_bridge_159_128 + u1_plda_pcie_test_out_bridge_159_128 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg816 + STG SYSCONSAIF SYSCFG 816 + 0x330 + 32 + + + u1_plda_pcie_test_out_bridge_191_160 + u1_plda_pcie_test_out_bridge_191_160 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg820 + STG SYSCONSAIF SYSCFG 820 + 0x334 + 32 + + + u1_plda_pcie_test_out_bridge_223_192 + u1_plda_pcie_test_out_bridge_223_192 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg824 + STG SYSCONSAIF SYSCFG 824 + 0x338 + 32 + + + u1_plda_pcie_test_out_bridge_255_224 + u1_plda_pcie_test_out_bridge_255_224 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg828 + STG SYSCONSAIF SYSCFG 828 + 0x33c + 32 + + + u1_plda_pcie_test_out_bridge_287_256 + u1_plda_pcie_test_out_bridge_287_256 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg832 + STG SYSCONSAIF SYSCFG 832 + 0x340 + 32 + + + u1_plda_pcie_test_out_bridge_319_288 + u1_plda_pcie_test_out_bridge_319_288 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg836 + STG SYSCONSAIF SYSCFG 836 + 0x344 + 32 + + + u1_plda_pcie_test_out_bridge_351_320 + u1_plda_pcie_test_out_bridge_351_320 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg840 + STG SYSCONSAIF SYSCFG 840 + 0x348 + 32 + + + u1_plda_pcie_test_out_bridge_383_352 + u1_plda_pcie_test_out_bridge_383_352 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg844 + STG SYSCONSAIF SYSCFG 844 + 0x34c + 32 + + + u1_plda_pcie_test_out_bridge_415_384 + u1_plda_pcie_test_out_bridge_415_384 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg848 + STG SYSCONSAIF SYSCFG 848 + 0x350 + 32 + + + u1_plda_pcie_test_out_bridge_447_416 + u1_plda_pcie_test_out_bridge_447_416 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg852 + STG SYSCONSAIF SYSCFG 852 + 0x354 + 32 + + + u1_plda_pcie_test_out_bridge_479_448 + u1_plda_pcie_test_out_bridge_479_448 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg856 + STG SYSCONSAIF SYSCFG 856 + 0x358 + 32 + + + u1_plda_pcie_test_out_bridge_511_480 + u1_plda_pcie_test_out_bridge_511_480 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg860 + STG SYSCONSAIF SYSCFG 860 + 0x35c + 32 + + + u1_plda_pcie_test_out_pcie_31_0 + u1_plda_pcie_test_out_pcie_31_0 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg864 + STG SYSCONSAIF SYSCFG 864 + 0x360 + 32 + + + u1_plda_pcie_test_out_pcie_63_32 + u1_plda_pcie_test_out_pcie_63_32 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg868 + STG SYSCONSAIF SYSCFG 868 + 0x364 + 32 + + + u1_plda_pcie_test_out_pcie_95_64 + u1_plda_pcie_test_out_pcie_95_64 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg872 + STG SYSCONSAIF SYSCFG 872 + 0x368 + 32 + + + u1_plda_pcie_test_out_pcie_127_96 + u1_plda_pcie_test_out_pcie_127_96 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg876 + STG SYSCONSAIF SYSCFG 876 + 0x36c + 32 + + + u1_plda_pcie_test_out_pcie_159_128 + u1_plda_pcie_test_out_pcie_159_128 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg880 + STG SYSCONSAIF SYSCFG 880 + 0x370 + 32 + + + u1_plda_pcie_test_out_pcie_191_160 + u1_plda_pcie_test_out_pcie_191_160 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg884 + STG SYSCONSAIF SYSCFG 884 + 0x374 + 32 + + + u1_plda_pcie_test_out_pcie_223_192 + u1_plda_pcie_test_out_pcie_223_192 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg888 + STG SYSCONSAIF SYSCFG 888 + 0x378 + 32 + + + u1_plda_pcie_test_out_pcie_255_224 + u1_plda_pcie_test_out_pcie_255_224 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg892 + STG SYSCONSAIF SYSCFG 892 + 0x37c + 32 + + + u1_plda_pcie_test_out_pcie_287_256 + u1_plda_pcie_test_out_pcie_287_256 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg896 + STG SYSCONSAIF SYSCFG 896 + 0x380 + 32 + + + u1_plda_pcie_test_out_pcie_319_288 + u1_plda_pcie_test_out_pcie_319_288 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg900 + STG SYSCONSAIF SYSCFG 900 + 0x384 + 32 + + + u1_plda_pcie_test_out_pcie_351_320 + u1_plda_pcie_test_out_pcie_351_320 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg904 + STG SYSCONSAIF SYSCFG 904 + 0x388 + 32 + + + u1_plda_pcie_test_out_pcie_383_352 + u1_plda_pcie_test_out_pcie_383_352 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg908 + STG SYSCONSAIF SYSCFG 908 + 0x38c + 32 + + + u1_plda_pcie_test_out_pcie_415_384 + u1_plda_pcie_test_out_pcie_415_384 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg912 + STG SYSCONSAIF SYSCFG 912 + 0x390 + 32 + + + u1_plda_pcie_test_out_pcie_447_416 + u1_plda_pcie_test_out_pcie_447_416 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg916 + STG SYSCONSAIF SYSCFG 916 + 0x394 + 32 + + + u1_plda_pcie_test_out_pcie_479_448 + u1_plda_pcie_test_out_pcie_479_448 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg920 + STG SYSCONSAIF SYSCFG 920 + 0x398 + 32 + + + u1_plda_pcie_test_out_pcie_511_480 + u1_plda_pcie_test_out_pcie_511_480 + [31:0] + read-only + + + + + stg_sysconsaif_syscfg924 + STG SYSCONSAIF SYSCFG 924 + 0x39c + 32 + + + u1_plda_pcie_test_sel + u1_plda_pcie_test_sel + [3:0] + read-write + + + u1_plda_pcie_tl_clock_freq + u1_plda_pcie_tl_clock_freq + [25:4] + read-write + + + + + stg_sysconsaif_syscfg928 + STG SYSCONSAIF SYSCFG 928 + 0x3a0 + 32 + + + u1_plda_pcie_tl_ctrl_hotplug + u1_plda_pcie_tl_ctrl_hotplug + [15:0] + read-only + + + u1_plda_pcie_tl_report_hotplug + u1_plda_pcie_tl_report_hotplug + [31:16] + read-write + + + + + stg_sysconsaif_syscfg932 + STG SYSCONSAIF SYSCFG 932 + 0x3a4 + 32 + + + u1_plda_pcie_tx_pattern + u1_plda_pcie_tx_pattern + [1:0] + read-write + + + u1_plda_pcie_usb3_bus_width + u1_plda_pcie_usb3_bus_width + [3:2] + read-write + + + u1_plda_pcie_usb3_phy_enable + u1_plda_pcie_usb3_phy_enable + [4:4] + read-write + + + u1_plda_pcie_usb3_rate + u1_plda_pcie_usb3_rate + [6:5] + read-write + + + u1_plda_pcie_usb3_rx_standby + u1_plda_pcie_usb3_rx_standby + [7:7] + read-write + + + u1_plda_pcie_xwdecerr + u1_plda_pcie_xwdecerr + [8:8] + read-only + + + u1_plda_pcie_xwerrclr + u1_plda_pcie_xwerrclr + [9:9] + read-write + + + u1_plda_pcie_xwslverr + u1_plda_pcie_xwslverr + [10:10] + read-only + + + + + + + syscon_0 + From syscon, peripheral generator + 0x10240000 + + 0 + 0x1000 + registers + + + + snps_dw_apb_uart_3 + From snps,dw-apb-uart, peripheral generator + 0x12000000 + + 0 + 0x10000 + registers + + + + snps_dw_apb_uart_4 + From snps,dw-apb-uart, peripheral generator + 0x12010000 + + 0 + 0x10000 + registers + + + + snps_dw_apb_uart_5 + From snps,dw-apb-uart, peripheral generator + 0x12020000 + + 0 + 0x10000 + registers + + + + snps_designware_i2c_3 + From snps,designware-i2c, peripheral generator + 0x12030000 + + 0 + 0x10000 + registers + + + + con + DesignWare I2C CON + 0x0 + 32 + + + master + I2C Master Connection - 0: Slave, 1: Master + [0:0] + read-write + + + speed + I2C Speed - 01: Standard, 10: Fast, 11: High + [2:1] + read-write + + + slave_10bitaddr + I2C Slave 10-bit Address - 0: False, 1: True + [3:3] + read-write + + + master_10bitaddr + I2C Master 10-bit Address - 0: False, 1: True + [4:4] + read-write + + + restart_en + I2C Restart Enable - 0: False, 1: True + [5:5] + read-write + + + slave_disable + I2C Slave Disable - 0: False, 1: True + [6:6] + read-write + + + stop_det_ifaddressed + I2C Stop DET If Addressed - 0: False, 1: True + [7:7] + read-write + + + tx_empty_ctrl + I2C TX Empty Control - 0: False, 1: True + [8:8] + read-write + + + rx_fifo_full_hld_ctrl + I2C RX FIFO Full Hold Control - 0: False, 1: True + [9:9] + read-write + + + bus_clear_ctrl + I2C Bus Clear Control - 0: False, 1: True + [11:11] + read-write + + + + + tar + DesignWare I2C TAR + 0x4 + 32 + + + tar + tar + [31:0] + read-write + + + + + sar + DesignWare I2C SAR + 0x8 + 32 + + + sar + sar + [31:0] + read-write + + + + + data_cmd + DesignWare I2C Data Command + 0x10 + 32 + + + dat + Data Command Data Byte + [7:0] + read-write + + + first_data_byte + Data Command First Data Byte - 0: False, 1: True + [11:11] + read-write + + + + + ss_scl_hcnt + DesignWare I2C SS SCL HCNT + 0x14 + 32 + + + ss_scl_hcnt + ss_scl_hcnt + [31:0] + read-write + + + + + ss_scl_lcnt + DesignWare I2C SS SCL LCNT + 0x18 + 32 + + + ss_scl_lcnt + ss_scl_lcnt + [31:0] + read-write + + + + + fs_scl_hcnt + DesignWare I2C FS SCL HCNT + 0x1c + 32 + + + fs_scl_hcnt + fs_scl_hcnt + [31:0] + read-write + + + + + fs_scl_lcnt + DesignWare I2C FS SCL LCNT + 0x20 + 32 + + + fs_scl_lcnt + fs_scl_lcnt + [31:0] + read-write + + + + + hs_scl_hcnt + DesignWare I2C HS SCL HCNT + 0x24 + 32 + + + hs_scl_hcnt + hs_scl_hcnt + [31:0] + read-write + + + + + hs_scl_lcnt + DesignWare I2C HS SCL LCNT + 0x28 + 32 + + + hs_scl_lcnt + hs_scl_lcnt + [31:0] + read-write + + + + + intr_stat + DesignWare I2C Interrupt Status + 0x2c + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + + + + intr_mask + DesignWare I2C Interrupt Mask + 0x30 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] + read-write + + + tx_abrt + TX Abort + [6:6] + read-write + + + rx_done + RX Done + [7:7] + read-write + + + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + + + + raw_intr_stat + DesignWare I2C Raw Interrupt Status + 0x34 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + + + + rx_tl + DesignWare I2C RX TL + 0x38 + 32 + + + rx_tl + rx_tl + [31:0] + read-write + + + + + tx_tl + DesignWare I2C TX TL + 0x3c + 32 + + + tx_tl + tx_tl + [31:0] + read-write + + + + + clr_intr + DesignWare I2C Clear Interrrupt + 0x40 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] + read-write + + + tx_abrt + TX Abort + [6:6] + read-write + + + rx_done + RX Done + [7:7] + read-write + + + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + + + + clr_rx_under + DesignWare I2C Clear RX Underrun + 0x44 + 32 + + + clr_rx_under + clr_rx_under + [31:0] + read-write + + + + + clr_rx_over + DesignWare I2C Clear RX Overrun + 0x48 + 32 + + + clr_rx_over + clr_rx_over + [31:0] + read-write + + + + + clr_tx_over + DesignWare I2C Clear TX Overrun + 0x4c + 32 + + + clr_tx_over + clr_tx_over + [31:0] + read-write + + + + + clr_rd_req + DesignWare I2C Clear Read Request + 0x50 + 32 + + + clr_rd_req + clr_rd_req + [31:0] + read-write + + + + + clr_tx_abrt + DesignWare I2C Clear TX Abort + 0x54 + 32 + + + clr_tx_abrt + clr_tx_abrt + [31:0] + read-write + + + + + clr_rx_done + DesignWare I2C Clear RX Done + 0x58 + 32 + + + clr_rx_done + clr_rx_done + [31:0] + read-write + + + + + clr_activity + DesignWare I2C Clear Activity + 0x5c + 32 + + + clr_activity + clr_activity + [31:0] + read-write + + + + + clr_stop_det + DesignWare I2C Clear Stop DET + 0x60 + 32 + + + clr_stop_det + clr_stop_det + [31:0] + read-write + + + + + clr_start_det + DesignWare I2C Clear Start DET + 0x64 + 32 + + + clr_start_det + clr_start_det + [31:0] + read-write + + + + + clr_gen_call + DesignWare I2C Clear General Call + 0x68 + 32 + + + clr_gen_call + clr_gen_call + [31:0] + read-write + + + + + enable + DesignWare I2C Enable + 0x6c + 32 + + + abort + abort + [1:1] + read-write + + + + + status + DesignWare I2C Status + 0x70 + 32 + + + activity + activity + [0:0] + read-only + + + tfe + tfe + [2:2] + read-only + + + rfne + rfne + [3:3] + read-only + + + master_activity + master_activity + [5:5] + read-only + + + slave_activity + slave_activity + [6:6] + read-only + + + + + txflr + DesignWare I2C TX Failure + 0x74 + 32 + + + txflr + txflr + [31:0] + read-write + + + + + rxflr + DesignWare I2C RX Failure + 0x78 + 32 + + + rxflr + rxflr + [31:0] + read-write + + + + + sda_hold + DesignWare I2C SDA Hold + 0x7c + 32 + + + sda_hold + sda_hold + [31:0] + read-write + + + + + tx_abrt_source + DesignWare I2C TX Abort Source + 0x80 + 32 + + + b7_addr_noack + b7_addr_noack + [0:0] + read-only + + + b10_addr1_noack + b10_addr1_noack + [1:1] + read-only + + + b10_addr2_noack + b10_addr2_noack + [2:2] + read-only + + + txdata_noack + txdata_noack + [3:3] + read-only + + + gcall_noack + gcall_noack + [4:4] + read-only + + + gcall_read + gcall_read + [5:5] + read-only + + + sbyte_ackdet + sbyte_ackdet + [7:7] + read-only + + + sbyte_norstrt + sbyte_norstrt + [9:9] + read-only + + + b10_rd_norstrt + b10_rd_norstrt + [10:10] + read-only + + + master_dis + master_dis + [11:11] + read-only + + + arb_lost + arb_lost + [12:12] + read-only + + + slave_flush_txfifo + slave_flush_txfifo + [13:13] + read-only + + + slave_arblost + slave_arblost + [14:14] + read-only + + + slave_rd_intx + slave_rd_intx + [15:15] + read-only + + + + + enable_status + DesignWare I2C Enable Status + 0x9c + 32 + + + activity + activity + [0:0] + read-write + + + tfe + tfe + [2:2] + read-write + + + rfne + rfne + [3:3] + read-write + + + master_activity + master_activity + [5:5] + read-write + + + slave_activity + slave_activity + [6:6] + read-write + + + + + clr_restart_det + DesignWare I2C Clear Restart DET + 0xa8 + 32 + + + clr_restart_det + clr_restart_det + [31:0] + read-write + + + + + comp_param_1 + DesignWare I2C Compatibility Parameter 1 + 0xf4 + 32 + + + speed + Speed mask - 01: Standard, 10: Full, 11: High + [3:2] + read-only + + + + + comp_version + DesignWare I2C Compatibility Version + 0xf8 + 32 + + + comp_version + comp_version + [31:0] + read-only + + + + + comp_type + DesignWare I2C Compatibility Type + 0xfc + 32 + + + comp_type + comp_type + [31:0] + read-only + + + + + + + snps_designware_i2c_4 + From snps,designware-i2c, peripheral generator + 0x12040000 + + 0 + 0x10000 + registers + + + + con + DesignWare I2C CON + 0x0 + 32 + + + master + I2C Master Connection - 0: Slave, 1: Master + [0:0] + read-write + + + speed + I2C Speed - 01: Standard, 10: Fast, 11: High + [2:1] + read-write + + + slave_10bitaddr + I2C Slave 10-bit Address - 0: False, 1: True + [3:3] + read-write + + + master_10bitaddr + I2C Master 10-bit Address - 0: False, 1: True + [4:4] + read-write + + + restart_en + I2C Restart Enable - 0: False, 1: True + [5:5] + read-write + + + slave_disable + I2C Slave Disable - 0: False, 1: True + [6:6] + read-write + + + stop_det_ifaddressed + I2C Stop DET If Addressed - 0: False, 1: True + [7:7] + read-write + + + tx_empty_ctrl + I2C TX Empty Control - 0: False, 1: True + [8:8] + read-write + + + rx_fifo_full_hld_ctrl + I2C RX FIFO Full Hold Control - 0: False, 1: True + [9:9] + read-write + + + bus_clear_ctrl + I2C Bus Clear Control - 0: False, 1: True + [11:11] + read-write + + + + + tar + DesignWare I2C TAR + 0x4 + 32 + + + tar + tar + [31:0] + read-write + + + + + sar + DesignWare I2C SAR + 0x8 + 32 + + + sar + sar + [31:0] + read-write + + + + + data_cmd + DesignWare I2C Data Command + 0x10 + 32 + + + dat + Data Command Data Byte + [7:0] + read-write + + + first_data_byte + Data Command First Data Byte - 0: False, 1: True + [11:11] + read-write + + + + + ss_scl_hcnt + DesignWare I2C SS SCL HCNT + 0x14 + 32 + + + ss_scl_hcnt + ss_scl_hcnt + [31:0] + read-write + + + + + ss_scl_lcnt + DesignWare I2C SS SCL LCNT + 0x18 + 32 + + + ss_scl_lcnt + ss_scl_lcnt + [31:0] + read-write + + + + + fs_scl_hcnt + DesignWare I2C FS SCL HCNT + 0x1c + 32 + + + fs_scl_hcnt + fs_scl_hcnt + [31:0] + read-write + + + + + fs_scl_lcnt + DesignWare I2C FS SCL LCNT + 0x20 + 32 + + + fs_scl_lcnt + fs_scl_lcnt + [31:0] + read-write + + + + + hs_scl_hcnt + DesignWare I2C HS SCL HCNT + 0x24 + 32 + + + hs_scl_hcnt + hs_scl_hcnt + [31:0] + read-write + + + + + hs_scl_lcnt + DesignWare I2C HS SCL LCNT + 0x28 + 32 + + + hs_scl_lcnt + hs_scl_lcnt + [31:0] + read-write + + + + + intr_stat + DesignWare I2C Interrupt Status + 0x2c + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + + + + intr_mask + DesignWare I2C Interrupt Mask + 0x30 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] + read-write + + + tx_abrt + TX Abort + [6:6] + read-write + + + rx_done + RX Done + [7:7] + read-write + + + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + + + + raw_intr_stat + DesignWare I2C Raw Interrupt Status + 0x34 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + + + + rx_tl + DesignWare I2C RX TL + 0x38 + 32 + + + rx_tl + rx_tl + [31:0] + read-write + + + + + tx_tl + DesignWare I2C TX TL + 0x3c + 32 + + + tx_tl + tx_tl + [31:0] + read-write + + + + + clr_intr + DesignWare I2C Clear Interrrupt + 0x40 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] + read-write + + + tx_abrt + TX Abort + [6:6] + read-write + + + rx_done + RX Done + [7:7] + read-write + + + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + + + + clr_rx_under + DesignWare I2C Clear RX Underrun + 0x44 + 32 + + + clr_rx_under + clr_rx_under + [31:0] + read-write + + + + + clr_rx_over + DesignWare I2C Clear RX Overrun + 0x48 + 32 + + + clr_rx_over + clr_rx_over + [31:0] + read-write + + + + + clr_tx_over + DesignWare I2C Clear TX Overrun + 0x4c + 32 + + + clr_tx_over + clr_tx_over + [31:0] + read-write + + + + + clr_rd_req + DesignWare I2C Clear Read Request + 0x50 + 32 + + + clr_rd_req + clr_rd_req + [31:0] + read-write + + + + + clr_tx_abrt + DesignWare I2C Clear TX Abort + 0x54 + 32 + + + clr_tx_abrt + clr_tx_abrt + [31:0] + read-write + + + + + clr_rx_done + DesignWare I2C Clear RX Done + 0x58 + 32 + + + clr_rx_done + clr_rx_done + [31:0] + read-write + + + + + clr_activity + DesignWare I2C Clear Activity + 0x5c + 32 + + + clr_activity + clr_activity + [31:0] + read-write + + + + + clr_stop_det + DesignWare I2C Clear Stop DET + 0x60 + 32 + + + clr_stop_det + clr_stop_det + [31:0] + read-write + + + + + clr_start_det + DesignWare I2C Clear Start DET + 0x64 + 32 + + + clr_start_det + clr_start_det + [31:0] + read-write + + + + + clr_gen_call + DesignWare I2C Clear General Call + 0x68 + 32 + + + clr_gen_call + clr_gen_call + [31:0] + read-write + + + + + enable + DesignWare I2C Enable + 0x6c + 32 + + + abort + abort + [1:1] + read-write + + + + + status + DesignWare I2C Status + 0x70 + 32 + + + activity + activity + [0:0] + read-only + + + tfe + tfe + [2:2] + read-only + + + rfne + rfne + [3:3] + read-only + + + master_activity + master_activity + [5:5] + read-only + + + slave_activity + slave_activity + [6:6] + read-only + + + + + txflr + DesignWare I2C TX Failure + 0x74 + 32 + + + txflr + txflr + [31:0] + read-write + + + + + rxflr + DesignWare I2C RX Failure + 0x78 + 32 + + + rxflr + rxflr + [31:0] + read-write + + + + + sda_hold + DesignWare I2C SDA Hold + 0x7c + 32 + + + sda_hold + sda_hold + [31:0] + read-write + + + + + tx_abrt_source + DesignWare I2C TX Abort Source + 0x80 + 32 + + + b7_addr_noack + b7_addr_noack + [0:0] + read-only + + + b10_addr1_noack + b10_addr1_noack + [1:1] + read-only + + + b10_addr2_noack + b10_addr2_noack + [2:2] + read-only + + + txdata_noack + txdata_noack + [3:3] + read-only + + + gcall_noack + gcall_noack + [4:4] + read-only + + + gcall_read + gcall_read + [5:5] + read-only + + + sbyte_ackdet + sbyte_ackdet + [7:7] + read-only + + + sbyte_norstrt + sbyte_norstrt + [9:9] + read-only + + + b10_rd_norstrt + b10_rd_norstrt + [10:10] + read-only + + + master_dis + master_dis + [11:11] + read-only + + + arb_lost + arb_lost + [12:12] + read-only + + + slave_flush_txfifo + slave_flush_txfifo + [13:13] + read-only + + + slave_arblost + slave_arblost + [14:14] + read-only + + + slave_rd_intx + slave_rd_intx + [15:15] + read-only + + + + + enable_status + DesignWare I2C Enable Status + 0x9c + 32 + + + activity + activity + [0:0] + read-write + + + tfe + tfe + [2:2] + read-write + + + rfne + rfne + [3:3] + read-write + + + master_activity + master_activity + [5:5] + read-write + + + slave_activity + slave_activity + [6:6] + read-write + + + + + clr_restart_det + DesignWare I2C Clear Restart DET + 0xa8 + 32 + + + clr_restart_det + clr_restart_det + [31:0] + read-write + + + + + comp_param_1 + DesignWare I2C Compatibility Parameter 1 + 0xf4 + 32 + + + speed + Speed mask - 01: Standard, 10: Full, 11: High + [3:2] + read-only + + + + + comp_version + DesignWare I2C Compatibility Version + 0xf8 + 32 + + + comp_version + comp_version + [31:0] + read-only + + + + + comp_type + DesignWare I2C Compatibility Type + 0xfc + 32 + + + comp_type + comp_type + [31:0] + read-only + + + + + + + snps_designware_i2c_5 + From snps,designware-i2c, peripheral generator + 0x12050000 + + 0 + 0x10000 + registers + + + + con + DesignWare I2C CON + 0x0 + 32 + + + master + I2C Master Connection - 0: Slave, 1: Master + [0:0] + read-write + + + speed + I2C Speed - 01: Standard, 10: Fast, 11: High + [2:1] + read-write + + + slave_10bitaddr + I2C Slave 10-bit Address - 0: False, 1: True + [3:3] + read-write + + + master_10bitaddr + I2C Master 10-bit Address - 0: False, 1: True + [4:4] + read-write + + + restart_en + I2C Restart Enable - 0: False, 1: True + [5:5] + read-write + + + slave_disable + I2C Slave Disable - 0: False, 1: True + [6:6] + read-write + + + stop_det_ifaddressed + I2C Stop DET If Addressed - 0: False, 1: True + [7:7] + read-write + + + tx_empty_ctrl + I2C TX Empty Control - 0: False, 1: True + [8:8] + read-write + + + rx_fifo_full_hld_ctrl + I2C RX FIFO Full Hold Control - 0: False, 1: True + [9:9] + read-write + + + bus_clear_ctrl + I2C Bus Clear Control - 0: False, 1: True + [11:11] + read-write + + + + + tar + DesignWare I2C TAR + 0x4 + 32 + + + tar + tar + [31:0] + read-write + + + + + sar + DesignWare I2C SAR + 0x8 + 32 + + + sar + sar + [31:0] + read-write + + + + + data_cmd + DesignWare I2C Data Command + 0x10 + 32 + + + dat + Data Command Data Byte + [7:0] + read-write + + + first_data_byte + Data Command First Data Byte - 0: False, 1: True + [11:11] + read-write + + + + + ss_scl_hcnt + DesignWare I2C SS SCL HCNT + 0x14 + 32 + + + ss_scl_hcnt + ss_scl_hcnt + [31:0] + read-write + + + + + ss_scl_lcnt + DesignWare I2C SS SCL LCNT + 0x18 + 32 + + + ss_scl_lcnt + ss_scl_lcnt + [31:0] + read-write + + + + + fs_scl_hcnt + DesignWare I2C FS SCL HCNT + 0x1c + 32 + + + fs_scl_hcnt + fs_scl_hcnt + [31:0] + read-write + + + + + fs_scl_lcnt + DesignWare I2C FS SCL LCNT + 0x20 + 32 + + + fs_scl_lcnt + fs_scl_lcnt + [31:0] + read-write + + + + + hs_scl_hcnt + DesignWare I2C HS SCL HCNT + 0x24 + 32 + + + hs_scl_hcnt + hs_scl_hcnt + [31:0] + read-write + + + + + hs_scl_lcnt + DesignWare I2C HS SCL LCNT + 0x28 + 32 + + + hs_scl_lcnt + hs_scl_lcnt + [31:0] + read-write + + + + + intr_stat + DesignWare I2C Interrupt Status + 0x2c + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + + + + intr_mask + DesignWare I2C Interrupt Mask + 0x30 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] + read-write + + + tx_abrt + TX Abort + [6:6] + read-write + + + rx_done + RX Done + [7:7] + read-write + + + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + + + + raw_intr_stat + DesignWare I2C Raw Interrupt Status + 0x34 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + + + + rx_tl + DesignWare I2C RX TL + 0x38 + 32 + + + rx_tl + rx_tl + [31:0] + read-write + + + + + tx_tl + DesignWare I2C TX TL + 0x3c + 32 + + + tx_tl + tx_tl + [31:0] + read-write + + + + + clr_intr + DesignWare I2C Clear Interrrupt + 0x40 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] + read-write + + + tx_abrt + TX Abort + [6:6] + read-write + + + rx_done + RX Done + [7:7] + read-write + + + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + + + + clr_rx_under + DesignWare I2C Clear RX Underrun + 0x44 + 32 + + + clr_rx_under + clr_rx_under + [31:0] + read-write + + + + + clr_rx_over + DesignWare I2C Clear RX Overrun + 0x48 + 32 + + + clr_rx_over + clr_rx_over + [31:0] + read-write + + + + + clr_tx_over + DesignWare I2C Clear TX Overrun + 0x4c + 32 + + + clr_tx_over + clr_tx_over + [31:0] + read-write + + + + + clr_rd_req + DesignWare I2C Clear Read Request + 0x50 + 32 + + + clr_rd_req + clr_rd_req + [31:0] + read-write + + + + + clr_tx_abrt + DesignWare I2C Clear TX Abort + 0x54 + 32 + + + clr_tx_abrt + clr_tx_abrt + [31:0] + read-write + + + + + clr_rx_done + DesignWare I2C Clear RX Done + 0x58 + 32 + + + clr_rx_done + clr_rx_done + [31:0] + read-write + + + + + clr_activity + DesignWare I2C Clear Activity + 0x5c + 32 + + + clr_activity + clr_activity + [31:0] + read-write + + + + + clr_stop_det + DesignWare I2C Clear Stop DET + 0x60 + 32 + + + clr_stop_det + clr_stop_det + [31:0] + read-write + + + + + clr_start_det + DesignWare I2C Clear Start DET + 0x64 + 32 + + + clr_start_det + clr_start_det + [31:0] + read-write + + + + + clr_gen_call + DesignWare I2C Clear General Call + 0x68 + 32 + + + clr_gen_call + clr_gen_call + [31:0] + read-write + + + + + enable + DesignWare I2C Enable + 0x6c + 32 + + + abort + abort + [1:1] + read-write + + + + + status + DesignWare I2C Status + 0x70 + 32 + + + activity + activity + [0:0] + read-only + + + tfe + tfe + [2:2] + read-only + + + rfne + rfne + [3:3] + read-only + + + master_activity + master_activity + [5:5] + read-only + + + slave_activity + slave_activity + [6:6] + read-only + + + + + txflr + DesignWare I2C TX Failure + 0x74 + 32 + + + txflr + txflr + [31:0] + read-write + + + + + rxflr + DesignWare I2C RX Failure + 0x78 + 32 + + + rxflr + rxflr + [31:0] + read-write + + + + + sda_hold + DesignWare I2C SDA Hold + 0x7c + 32 + + + sda_hold + sda_hold + [31:0] + read-write + + + + + tx_abrt_source + DesignWare I2C TX Abort Source + 0x80 + 32 + + + b7_addr_noack + b7_addr_noack + [0:0] + read-only + + + b10_addr1_noack + b10_addr1_noack + [1:1] + read-only + + + b10_addr2_noack + b10_addr2_noack + [2:2] + read-only + + + txdata_noack + txdata_noack + [3:3] + read-only + + + gcall_noack + gcall_noack + [4:4] + read-only + + + gcall_read + gcall_read + [5:5] + read-only + + + sbyte_ackdet + sbyte_ackdet + [7:7] + read-only + + + sbyte_norstrt + sbyte_norstrt + [9:9] + read-only + + + b10_rd_norstrt + b10_rd_norstrt + [10:10] + read-only + + + master_dis + master_dis + [11:11] + read-only + + + arb_lost + arb_lost + [12:12] + read-only + + + slave_flush_txfifo + slave_flush_txfifo + [13:13] + read-only + + + slave_arblost + slave_arblost + [14:14] + read-only + + + slave_rd_intx + slave_rd_intx + [15:15] + read-only + + + + + enable_status + DesignWare I2C Enable Status + 0x9c + 32 + + + activity + activity + [0:0] + read-write + + + tfe + tfe + [2:2] + read-write + + + rfne + rfne + [3:3] + read-write + + + master_activity + master_activity + [5:5] + read-write + + + slave_activity + slave_activity + [6:6] + read-write + + + + + clr_restart_det + DesignWare I2C Clear Restart DET + 0xa8 + 32 + + + clr_restart_det + clr_restart_det + [31:0] + read-write + + + + + comp_param_1 + DesignWare I2C Compatibility Parameter 1 + 0xf4 + 32 + + + speed + Speed mask - 01: Standard, 10: Full, 11: High + [3:2] + read-only + + + + + comp_version + DesignWare I2C Compatibility Version + 0xf8 + 32 + + + comp_version + comp_version + [31:0] + read-only + + + + + comp_type + DesignWare I2C Compatibility Type + 0xfc + 32 + + + comp_type + comp_type + [31:0] + read-only + + + + + + + snps_designware_i2c_6 + From snps,designware-i2c, peripheral generator + 0x12060000 + + 0 + 0x10000 + registers + + + + con + DesignWare I2C CON + 0x0 + 32 + + + master + I2C Master Connection - 0: Slave, 1: Master + [0:0] + read-write + + + speed + I2C Speed - 01: Standard, 10: Fast, 11: High + [2:1] + read-write + + + slave_10bitaddr + I2C Slave 10-bit Address - 0: False, 1: True + [3:3] + read-write + + + master_10bitaddr + I2C Master 10-bit Address - 0: False, 1: True + [4:4] + read-write + + + restart_en + I2C Restart Enable - 0: False, 1: True + [5:5] + read-write + + + slave_disable + I2C Slave Disable - 0: False, 1: True + [6:6] + read-write + + + stop_det_ifaddressed + I2C Stop DET If Addressed - 0: False, 1: True + [7:7] + read-write + + + tx_empty_ctrl + I2C TX Empty Control - 0: False, 1: True + [8:8] + read-write + + + rx_fifo_full_hld_ctrl + I2C RX FIFO Full Hold Control - 0: False, 1: True + [9:9] + read-write + + + bus_clear_ctrl + I2C Bus Clear Control - 0: False, 1: True + [11:11] + read-write + + + + + tar + DesignWare I2C TAR + 0x4 + 32 + + + tar + tar + [31:0] + read-write + + + + + sar + DesignWare I2C SAR + 0x8 + 32 + + + sar + sar + [31:0] + read-write + + + + + data_cmd + DesignWare I2C Data Command + 0x10 + 32 + + + dat + Data Command Data Byte + [7:0] + read-write + + + first_data_byte + Data Command First Data Byte - 0: False, 1: True + [11:11] + read-write + + + + + ss_scl_hcnt + DesignWare I2C SS SCL HCNT + 0x14 + 32 + + + ss_scl_hcnt + ss_scl_hcnt + [31:0] + read-write + + + + + ss_scl_lcnt + DesignWare I2C SS SCL LCNT + 0x18 + 32 + + + ss_scl_lcnt + ss_scl_lcnt + [31:0] + read-write + + + + + fs_scl_hcnt + DesignWare I2C FS SCL HCNT + 0x1c + 32 + + + fs_scl_hcnt + fs_scl_hcnt + [31:0] + read-write + + + + + fs_scl_lcnt + DesignWare I2C FS SCL LCNT + 0x20 + 32 + + + fs_scl_lcnt + fs_scl_lcnt + [31:0] + read-write + + + + + hs_scl_hcnt + DesignWare I2C HS SCL HCNT + 0x24 + 32 + + + hs_scl_hcnt + hs_scl_hcnt + [31:0] + read-write + + + + + hs_scl_lcnt + DesignWare I2C HS SCL LCNT + 0x28 + 32 + + + hs_scl_lcnt + hs_scl_lcnt + [31:0] + read-write + + + + + intr_stat + DesignWare I2C Interrupt Status + 0x2c + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + + + + intr_mask + DesignWare I2C Interrupt Mask + 0x30 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] + read-write + + + tx_abrt + TX Abort + [6:6] + read-write + + + rx_done + RX Done + [7:7] + read-write + + + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + + + + raw_intr_stat + DesignWare I2C Raw Interrupt Status + 0x34 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + + + + rx_tl + DesignWare I2C RX TL + 0x38 + 32 + + + rx_tl + rx_tl + [31:0] + read-write + + + + + tx_tl + DesignWare I2C TX TL + 0x3c + 32 + + + tx_tl + tx_tl + [31:0] + read-write + + + + + clr_intr + DesignWare I2C Clear Interrrupt + 0x40 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] + read-write + + + tx_abrt + TX Abort + [6:6] + read-write + + + rx_done + RX Done + [7:7] + read-write + + + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + + + + clr_rx_under + DesignWare I2C Clear RX Underrun + 0x44 + 32 + + + clr_rx_under + clr_rx_under + [31:0] + read-write + + + + + clr_rx_over + DesignWare I2C Clear RX Overrun + 0x48 + 32 + + + clr_rx_over + clr_rx_over + [31:0] + read-write + + + + + clr_tx_over + DesignWare I2C Clear TX Overrun + 0x4c + 32 + + + clr_tx_over + clr_tx_over + [31:0] + read-write + + + + + clr_rd_req + DesignWare I2C Clear Read Request + 0x50 + 32 + + + clr_rd_req + clr_rd_req + [31:0] + read-write + + + + + clr_tx_abrt + DesignWare I2C Clear TX Abort + 0x54 + 32 + + + clr_tx_abrt + clr_tx_abrt + [31:0] + read-write + + + + + clr_rx_done + DesignWare I2C Clear RX Done + 0x58 + 32 + + + clr_rx_done + clr_rx_done + [31:0] + read-write + + + + + clr_activity + DesignWare I2C Clear Activity + 0x5c + 32 + + + clr_activity + clr_activity + [31:0] + read-write + + + + + clr_stop_det + DesignWare I2C Clear Stop DET + 0x60 + 32 + + + clr_stop_det + clr_stop_det + [31:0] + read-write + + + + + clr_start_det + DesignWare I2C Clear Start DET + 0x64 + 32 + + + clr_start_det + clr_start_det + [31:0] + read-write + + + + + clr_gen_call + DesignWare I2C Clear General Call + 0x68 + 32 + + + clr_gen_call + clr_gen_call + [31:0] + read-write + + + + + enable + DesignWare I2C Enable + 0x6c + 32 + + + abort + abort + [1:1] + read-write + + + + + status + DesignWare I2C Status + 0x70 + 32 + + + activity + activity + [0:0] + read-only + + + tfe + tfe + [2:2] + read-only + + + rfne + rfne + [3:3] + read-only + + + master_activity + master_activity + [5:5] + read-only + + + slave_activity + slave_activity + [6:6] + read-only + + + + + txflr + DesignWare I2C TX Failure + 0x74 + 32 + + + txflr + txflr + [31:0] + read-write + + + + + rxflr + DesignWare I2C RX Failure + 0x78 + 32 + + + rxflr + rxflr + [31:0] + read-write + + + + + sda_hold + DesignWare I2C SDA Hold + 0x7c + 32 + + + sda_hold + sda_hold + [31:0] + read-write + + + + + tx_abrt_source + DesignWare I2C TX Abort Source + 0x80 + 32 + + + b7_addr_noack + b7_addr_noack + [0:0] + read-only + + + b10_addr1_noack + b10_addr1_noack + [1:1] + read-only + + + b10_addr2_noack + b10_addr2_noack + [2:2] + read-only + + + txdata_noack + txdata_noack + [3:3] + read-only + + + gcall_noack + gcall_noack + [4:4] + read-only + + + gcall_read + gcall_read + [5:5] + read-only + + + sbyte_ackdet + sbyte_ackdet + [7:7] + read-only + + + sbyte_norstrt + sbyte_norstrt + [9:9] + read-only + + + b10_rd_norstrt + b10_rd_norstrt + [10:10] + read-only + + + master_dis + master_dis + [11:11] + read-only + + + arb_lost + arb_lost + [12:12] + read-only + + + slave_flush_txfifo + slave_flush_txfifo + [13:13] + read-only + + + slave_arblost + slave_arblost + [14:14] + read-only + + + slave_rd_intx + slave_rd_intx + [15:15] + read-only + + + + + enable_status + DesignWare I2C Enable Status + 0x9c + 32 + + + activity + activity + [0:0] + read-write + + + tfe + tfe + [2:2] + read-write + + + rfne + rfne + [3:3] + read-write + + + master_activity + master_activity + [5:5] + read-write + + + slave_activity + slave_activity + [6:6] + read-write + + + + + clr_restart_det + DesignWare I2C Clear Restart DET + 0xa8 + 32 + + + clr_restart_det + clr_restart_det + [31:0] + read-write + + + + + comp_param_1 + DesignWare I2C Compatibility Parameter 1 + 0xf4 + 32 + + + speed + Speed mask - 01: Standard, 10: Full, 11: High + [3:2] + read-only + + + + + comp_version + DesignWare I2C Compatibility Version + 0xf8 + 32 + + + comp_version + comp_version + [31:0] + read-only + + + + + comp_type + DesignWare I2C Compatibility Type + 0xfc + 32 + + + comp_type + comp_type + [31:0] + read-only + + + + + + + arm_pl022_3 + From arm,pl022, peripheral generator + 0x12070000 + + 0 + 0x10000 + registers + + + + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. + 0x0 + 16 + + + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] + read-write + + + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] + read-write + + + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] + read-write + + + + + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. + 0x4 + 16 + + + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally + [0:0] + read-write + + + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled + [1:1] + read-write + + + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave + [2:2] + read-write + + + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode + [3:3] + read-write + + + + + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 + + + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] + read-write + + + + + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 + + + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. + [0:0] + read-only + + + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. + [1:1] + read-only + + + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. + [2:2] + read-only + + + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. + [3:3] + read-only + + + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only + + + + + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 + + + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] + read-write + + + + + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 + + + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked + [0:0] + read-write + + + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked + [1:1] + read-write + + + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked + [2:2] + read-write + + + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] + read-write + + + + + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 + + + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + + + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 + + + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + + + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 + + + roric + Clears the SSPRORINTR interrupt + [0:0] + read-write + + + rtic + Clears the SSPRTINTR interrupt + [1:1] + read-write + + + + + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 + + + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + + + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 + + + part_number0 + These bits read back as 0x22 + [7:0] + read-only + + + + + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 + + + part_number1 + These bits read back as 0x0 + [3:0] + read-only + + + designer0 + These bits read back as 0x1 + [7:4] + read-only + + + + + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 + + + designer1 + These bits read back as 0x4 + [3:0] + read-only + + + revision + These bits return the peripheral revision + [7:4] + read-only + + + + + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 + + + configuration + These bits read back as 0x80 + [7:0] + read-only + + + + + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 + + + ssp_pcell_id0 + The bits are read as 0xD + [7:0] + read-only + + + + + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 + + + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] + read-only + + + + + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 + + + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] + read-only + + + + + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 + + + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] + read-only + + + + + + + arm_primecell_3 + From arm,primecell, peripheral generator + 0x12070000 + + 0 + 0x10000 + registers + + + + arm_pl022_4 + From arm,pl022, peripheral generator + 0x12080000 + + 0 + 0x10000 + registers + + + + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. + 0x0 + 16 + + + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] + read-write + + + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] + read-write + + + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] + read-write + + + + + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. + 0x4 + 16 + + + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally + [0:0] + read-write + + + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled + [1:1] + read-write + + + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave + [2:2] + read-write + + + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode + [3:3] + read-write + + + + + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 + + + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] + read-write + + + + + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 + + + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. + [0:0] + read-only + + + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. + [1:1] + read-only + + + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. + [2:2] + read-only + + + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. + [3:3] + read-only + + + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only + + + + + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 + + + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] + read-write + + + + + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 + + + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked + [0:0] + read-write + + + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked + [1:1] + read-write + + + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked + [2:2] + read-write + + + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] + read-write + + + + + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 + + + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + + + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 + + + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + + + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 + + + roric + Clears the SSPRORINTR interrupt + [0:0] + read-write + + + rtic + Clears the SSPRTINTR interrupt + [1:1] + read-write + + + + + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 + + + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + + + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 + + + part_number0 + These bits read back as 0x22 + [7:0] + read-only + + + + + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 + + + part_number1 + These bits read back as 0x0 + [3:0] + read-only + + + designer0 + These bits read back as 0x1 + [7:4] + read-only + + + + + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 + + + designer1 + These bits read back as 0x4 + [3:0] + read-only + + + revision + These bits return the peripheral revision + [7:4] + read-only + + + + + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 + + + configuration + These bits read back as 0x80 + [7:0] + read-only + + + + + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 + + + ssp_pcell_id0 + The bits are read as 0xD + [7:0] + read-only + + + + + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 + + + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] + read-only + + + + + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 + + + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] + read-only + + + + + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 + + + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] + read-only + + + + + + + arm_primecell_4 + From arm,primecell, peripheral generator + 0x12080000 + + 0 + 0x10000 + registers + + + + arm_pl022_5 + From arm,pl022, peripheral generator + 0x12090000 + + 0 + 0x10000 + registers + + + + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. + 0x0 + 16 + + + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] + read-write + + + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] + read-write + + + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] read-write - stg_sysconsaif_syscfg836 - STG SYSCONSAIF SYSCFG 836 - 0x344 - 32 + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. + 0x4 + 16 - u1_plda_pcie_test_out_bridge_351_320 - u1_plda_pcie_test_out_bridge_351_320 - [31:0] + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally + [0:0] + read-write + + + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled + [1:1] + read-write + + + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave + [2:2] + read-write + + + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode + [3:3] read-write - stg_sysconsaif_syscfg840 - STG SYSCONSAIF SYSCFG 840 - 0x348 - 32 + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 - u1_plda_pcie_test_out_bridge_383_352 - u1_plda_pcie_test_out_bridge_383_352 - [31:0] + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] read-write - stg_sysconsaif_syscfg844 - STG SYSCONSAIF SYSCFG 844 - 0x34c - 32 + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 - u1_plda_pcie_test_out_bridge_415_384 - u1_plda_pcie_test_out_bridge_415_384 - [31:0] + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. + [0:0] + read-only + + + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. + [1:1] + read-only + + + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. + [2:2] + read-only + + + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. + [3:3] + read-only + + + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only + + + + + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 + + + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] read-write - stg_sysconsaif_syscfg848 - STG SYSCONSAIF SYSCFG 848 - 0x350 - 32 + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 - u1_plda_pcie_test_out_bridge_447_416 - u1_plda_pcie_test_out_bridge_447_416 - [31:0] + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked + [0:0] + read-write + + + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked + [1:1] + read-write + + + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked + [2:2] + read-write + + + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] read-write - stg_sysconsaif_syscfg852 - STG SYSCONSAIF SYSCFG 852 - 0x354 - 32 + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 - u1_plda_pcie_test_out_bridge_479_448 - u1_plda_pcie_test_out_bridge_479_448 - [31:0] + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + + + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 + + + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + + + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 + + + roric + Clears the SSPRORINTR interrupt + [0:0] + read-write + + + rtic + Clears the SSPRTINTR interrupt + [1:1] read-write - stg_sysconsaif_syscfg856 - STG SYSCONSAIF SYSCFG 856 - 0x358 - 32 + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 + + + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + + + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 + + + part_number0 + These bits read back as 0x22 + [7:0] + read-only + + + + + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 + + + part_number1 + These bits read back as 0x0 + [3:0] + read-only + + + designer0 + These bits read back as 0x1 + [7:4] + read-only + + + + + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 - u1_plda_pcie_test_out_bridge_511_480 - u1_plda_pcie_test_out_bridge_511_480 - [31:0] - read-write + designer1 + These bits read back as 0x4 + [3:0] + read-only + + + revision + These bits return the peripheral revision + [7:4] + read-only - stg_sysconsaif_syscfg860 - STG SYSCONSAIF SYSCFG 860 - 0x35c - 32 + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 - u1_plda_pcie_test_out_pcie_31_0 - u1_plda_pcie_test_out_pcie_31_0 - [31:0] + configuration + These bits read back as 0x80 + [7:0] read-only - stg_sysconsaif_syscfg864 - STG SYSCONSAIF SYSCFG 864 - 0x360 - 32 + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 - u1_plda_pcie_test_out_pcie_63_32 - u1_plda_pcie_test_out_pcie_63_32 - [31:0] + ssp_pcell_id0 + The bits are read as 0xD + [7:0] read-only - stg_sysconsaif_syscfg868 - STG SYSCONSAIF SYSCFG 868 - 0x364 - 32 + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 - u1_plda_pcie_test_out_pcie_95_64 - u1_plda_pcie_test_out_pcie_95_64 - [31:0] + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] read-only - stg_sysconsaif_syscfg872 - STG SYSCONSAIF SYSCFG 872 - 0x368 - 32 + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 - u1_plda_pcie_test_out_pcie_127_96 - u1_plda_pcie_test_out_pcie_127_96 - [31:0] + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] read-only - stg_sysconsaif_syscfg876 - STG SYSCONSAIF SYSCFG 876 - 0x36c - 32 + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 - u1_plda_pcie_test_out_pcie_159_128 - u1_plda_pcie_test_out_pcie_159_128 - [31:0] + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] read-only + + + + arm_primecell_5 + From arm,primecell, peripheral generator + 0x12090000 + + 0 + 0x10000 + registers + + + + arm_pl022_6 + From arm,pl022, peripheral generator + 0x120A0000 + + 0 + 0x10000 + registers + + - stg_sysconsaif_syscfg880 - STG SYSCONSAIF SYSCFG 880 - 0x370 - 32 + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. + 0x0 + 16 - u1_plda_pcie_test_out_pcie_191_160 - u1_plda_pcie_test_out_pcie_191_160 - [31:0] - read-only + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] + read-write + + + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] + read-write + + + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] + read-write - stg_sysconsaif_syscfg884 - STG SYSCONSAIF SYSCFG 884 - 0x374 - 32 + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. + 0x4 + 16 - u1_plda_pcie_test_out_pcie_223_192 - u1_plda_pcie_test_out_pcie_223_192 - [31:0] - read-only + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally + [0:0] + read-write + + + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled + [1:1] + read-write + + + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave + [2:2] + read-write + + + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode + [3:3] + read-write - stg_sysconsaif_syscfg888 - STG SYSCONSAIF SYSCFG 888 - 0x378 - 32 + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 - u1_plda_pcie_test_out_pcie_255_224 - u1_plda_pcie_test_out_pcie_255_224 - [31:0] - read-only + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] + read-write - stg_sysconsaif_syscfg892 - STG SYSCONSAIF SYSCFG 892 - 0x37c - 32 + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 - u1_plda_pcie_test_out_pcie_287_256 - u1_plda_pcie_test_out_pcie_287_256 - [31:0] + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. + [0:0] + read-only + + + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. + [1:1] + read-only + + + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. + [2:2] + read-only + + + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. + [3:3] + read-only + + + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] read-only - stg_sysconsaif_syscfg896 - STG SYSCONSAIF SYSCFG 896 - 0x380 - 32 + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 - u1_plda_pcie_test_out_pcie_319_288 - u1_plda_pcie_test_out_pcie_319_288 - [31:0] - read-only + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] + read-write - stg_sysconsaif_syscfg900 - STG SYSCONSAIF SYSCFG 900 - 0x384 - 32 + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 - u1_plda_pcie_test_out_pcie_351_320 - u1_plda_pcie_test_out_pcie_351_320 - [31:0] - read-only + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked + [0:0] + read-write + + + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked + [1:1] + read-write + + + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked + [2:2] + read-write + + + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] + read-write - stg_sysconsaif_syscfg904 - STG SYSCONSAIF SYSCFG 904 - 0x388 - 32 + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 - u1_plda_pcie_test_out_pcie_383_352 - u1_plda_pcie_test_out_pcie_383_352 - [31:0] + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] read-only - stg_sysconsaif_syscfg908 - STG SYSCONSAIF SYSCFG 908 - 0x38c - 32 + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 - u1_plda_pcie_test_out_pcie_415_384 - u1_plda_pcie_test_out_pcie_415_384 - [31:0] + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] read-only - stg_sysconsaif_syscfg912 - STG SYSCONSAIF SYSCFG 912 - 0x390 - 32 + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 - u1_plda_pcie_test_out_pcie_447_416 - u1_plda_pcie_test_out_pcie_447_416 - [31:0] - read-only + roric + Clears the SSPRORINTR interrupt + [0:0] + read-write + + + rtic + Clears the SSPRTINTR interrupt + [1:1] + read-write - stg_sysconsaif_syscfg916 - STG SYSCONSAIF SYSCFG 916 - 0x394 - 32 + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 - u1_plda_pcie_test_out_pcie_479_448 - u1_plda_pcie_test_out_pcie_479_448 - [31:0] - read-only + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write - stg_sysconsaif_syscfg920 - STG SYSCONSAIF SYSCFG 920 - 0x398 - 32 + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 - u1_plda_pcie_test_out_pcie_511_480 - u1_plda_pcie_test_out_pcie_511_480 - [31:0] + part_number0 + These bits read back as 0x22 + [7:0] read-only - stg_sysconsaif_syscfg924 - STG SYSCONSAIF SYSCFG 924 - 0x39c - 32 + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 - u1_plda_pcie_test_sel - u1_plda_pcie_test_sel + part_number1 + These bits read back as 0x0 [3:0] - read-write + read-only - u1_plda_pcie_tl_clock_freq - u1_plda_pcie_tl_clock_freq - [25:4] - read-write + designer0 + These bits read back as 0x1 + [7:4] + read-only - stg_sysconsaif_syscfg928 - STG SYSCONSAIF SYSCFG 928 - 0x3a0 - 32 + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 - u1_plda_pcie_tl_ctrl_hotplug - u1_plda_pcie_tl_ctrl_hotplug - [15:0] + designer1 + These bits read back as 0x4 + [3:0] read-only - u1_plda_pcie_tl_report_hotplug - u1_plda_pcie_tl_report_hotplug - [31:16] - read-write + revision + These bits return the peripheral revision + [7:4] + read-only - stg_sysconsaif_syscfg932 - STG SYSCONSAIF SYSCFG 932 - 0x3a4 - 32 + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 - u1_plda_pcie_tx_pattern - u1_plda_pcie_tx_pattern - [1:0] - read-write - - - u1_plda_pcie_usb3_bus_width - u1_plda_pcie_usb3_bus_width - [3:2] - read-write - - - u1_plda_pcie_usb3_phy_enable - u1_plda_pcie_usb3_phy_enable - [4:4] - read-write - - - u1_plda_pcie_usb3_rate - u1_plda_pcie_usb3_rate - [6:5] - read-write + configuration + These bits read back as 0x80 + [7:0] + read-only + + + + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 + - u1_plda_pcie_usb3_rx_standby - u1_plda_pcie_usb3_rx_standby - [7:7] - read-write + ssp_pcell_id0 + The bits are read as 0xD + [7:0] + read-only + + + + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 + - u1_plda_pcie_xwdecerr - u1_plda_pcie_xwdecerr - [8:8] + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] read-only + + + + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 + - u1_plda_pcie_xwerrclr - u1_plda_pcie_xwerrclr - [9:9] - read-write + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] + read-only + + + + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 + - u1_plda_pcie_xwslverr - u1_plda_pcie_xwslverr - [10:10] + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] read-only - - syscon_0 - From syscon, peripheral generator - 0x10240000 - - 0 - 0x1000 - registers - - - - snps_dw_apb_uart_3 - From snps,dw-apb-uart, peripheral generator - 0x12000000 - - 0 - 0x10000 - registers - - - - snps_dw_apb_uart_4 - From snps,dw-apb-uart, peripheral generator - 0x12010000 - - 0 - 0x10000 - registers - - - - snps_dw_apb_uart_5 - From snps,dw-apb-uart, peripheral generator - 0x12020000 - - 0 - 0x10000 - registers - - - - snps_designware_i2c_3 - From snps,designware-i2c, peripheral generator - 0x12030000 - - 0 - 0x10000 - registers - - - - snps_designware_i2c_4 - From snps,designware-i2c, peripheral generator - 0x12040000 - - 0 - 0x10000 - registers - - - - snps_designware_i2c_5 - From snps,designware-i2c, peripheral generator - 0x12050000 - - 0 - 0x10000 - registers - - - - snps_designware_i2c_6 - From snps,designware-i2c, peripheral generator - 0x12060000 - - 0 - 0x10000 - registers - - - - arm_pl022_3 - From arm,pl022, peripheral generator - 0x12070000 - - 0 - 0x10000 - registers - - - - arm_primecell_3 - From arm,primecell, peripheral generator - 0x12070000 - - 0 - 0x10000 - registers - - - - arm_pl022_4 - From arm,pl022, peripheral generator - 0x12080000 - - 0 - 0x10000 - registers - - - - arm_primecell_4 - From arm,primecell, peripheral generator - 0x12080000 - - 0 - 0x10000 - registers - - - - arm_pl022_5 - From arm,pl022, peripheral generator - 0x12090000 - - 0 - 0x10000 - registers - - - - arm_primecell_5 - From arm,primecell, peripheral generator - 0x12090000 - - 0 - 0x10000 - registers - - - - arm_pl022_6 - From arm,pl022, peripheral generator - 0x120A0000 - - 0 - 0x10000 - registers - - arm_primecell_6 From arm,primecell, peripheral generator diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_dr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_icr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_mis.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_ris.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_sr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_0/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_dr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_icr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_mis.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_ris.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_sr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_1/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_dr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_icr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_mis.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_ris.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_sr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_2/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_dr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_icr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_mis.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_ris.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_sr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_3/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_dr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_icr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_mis.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_ris.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_sr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_4/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_dr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_icr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_mis.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_ris.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_sr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_5/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_dr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_icr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_mis.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_ris.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_sr.rs b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/arm_pl022_6/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/lib.rs b/jh7110-vf2-12a-pac/src/lib.rs index 8a22552..7879194 100644 --- a/jh7110-vf2-12a-pac/src/lib.rs +++ b/jh7110-vf2-12a-pac/src/lib.rs @@ -80,6 +80,282 @@ impl core::fmt::Debug for SIFIVE_CLINT0_0 { } #[doc = "From sifive,clint0, peripheral generator"] pub mod sifive_clint0_0; +#[doc = "From snps,designware-i2c, peripheral generator"] +pub struct SNPS_DESIGNWARE_I2C_0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SNPS_DESIGNWARE_I2C_0 {} +impl SNPS_DESIGNWARE_I2C_0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const snps_designware_i2c_0::RegisterBlock = 0x1003_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const snps_designware_i2c_0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SNPS_DESIGNWARE_I2C_0 { + type Target = snps_designware_i2c_0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SNPS_DESIGNWARE_I2C_0").finish() + } +} +#[doc = "From snps,designware-i2c, peripheral generator"] +pub mod snps_designware_i2c_0; +#[doc = "From snps,designware-i2c, peripheral generator"] +pub struct SNPS_DESIGNWARE_I2C_1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SNPS_DESIGNWARE_I2C_1 {} +impl SNPS_DESIGNWARE_I2C_1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const snps_designware_i2c_1::RegisterBlock = 0x1004_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const snps_designware_i2c_1::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SNPS_DESIGNWARE_I2C_1 { + type Target = snps_designware_i2c_1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SNPS_DESIGNWARE_I2C_1").finish() + } +} +#[doc = "From snps,designware-i2c, peripheral generator"] +pub mod snps_designware_i2c_1; +#[doc = "From snps,designware-i2c, peripheral generator"] +pub struct SNPS_DESIGNWARE_I2C_2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SNPS_DESIGNWARE_I2C_2 {} +impl SNPS_DESIGNWARE_I2C_2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const snps_designware_i2c_2::RegisterBlock = 0x1005_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const snps_designware_i2c_2::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SNPS_DESIGNWARE_I2C_2 { + type Target = snps_designware_i2c_2::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SNPS_DESIGNWARE_I2C_2").finish() + } +} +#[doc = "From snps,designware-i2c, peripheral generator"] +pub mod snps_designware_i2c_2; +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ARM_PL022_0 {} +impl ARM_PL022_0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const arm_pl022_0::RegisterBlock = 0x1006_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const arm_pl022_0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ARM_PL022_0 { + type Target = arm_pl022_0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ARM_PL022_0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARM_PL022_0").finish() + } +} +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_0; +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ARM_PL022_1 {} +impl ARM_PL022_1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const arm_pl022_1::RegisterBlock = 0x1007_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const arm_pl022_1::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ARM_PL022_1 { + type Target = arm_pl022_1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ARM_PL022_1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARM_PL022_1").finish() + } +} +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_1; +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ARM_PL022_2 {} +impl ARM_PL022_2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const arm_pl022_2::RegisterBlock = 0x1008_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const arm_pl022_2::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ARM_PL022_2 { + type Target = arm_pl022_2::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ARM_PL022_2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARM_PL022_2").finish() + } +} +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_2; #[doc = "From starfive,jh7110-stgcrg, peripheral generator"] pub struct STARFIVE_JH7110_STGCRG_0 { _marker: PhantomData<*const ()>, @@ -172,6 +448,374 @@ impl core::fmt::Debug for STARFIVE_JH7110_STG_SYSCON_0 { } #[doc = "From starfive,jh7110-stg-syscon, peripheral generator"] pub mod starfive_jh7110_stg_syscon_0; +#[doc = "From snps,designware-i2c, peripheral generator"] +pub struct SNPS_DESIGNWARE_I2C_3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SNPS_DESIGNWARE_I2C_3 {} +impl SNPS_DESIGNWARE_I2C_3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const snps_designware_i2c_3::RegisterBlock = 0x1203_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const snps_designware_i2c_3::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SNPS_DESIGNWARE_I2C_3 { + type Target = snps_designware_i2c_3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SNPS_DESIGNWARE_I2C_3").finish() + } +} +#[doc = "From snps,designware-i2c, peripheral generator"] +pub mod snps_designware_i2c_3; +#[doc = "From snps,designware-i2c, peripheral generator"] +pub struct SNPS_DESIGNWARE_I2C_4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SNPS_DESIGNWARE_I2C_4 {} +impl SNPS_DESIGNWARE_I2C_4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const snps_designware_i2c_4::RegisterBlock = 0x1204_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const snps_designware_i2c_4::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SNPS_DESIGNWARE_I2C_4 { + type Target = snps_designware_i2c_4::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SNPS_DESIGNWARE_I2C_4").finish() + } +} +#[doc = "From snps,designware-i2c, peripheral generator"] +pub mod snps_designware_i2c_4; +#[doc = "From snps,designware-i2c, peripheral generator"] +pub struct SNPS_DESIGNWARE_I2C_5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SNPS_DESIGNWARE_I2C_5 {} +impl SNPS_DESIGNWARE_I2C_5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const snps_designware_i2c_5::RegisterBlock = 0x1205_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const snps_designware_i2c_5::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SNPS_DESIGNWARE_I2C_5 { + type Target = snps_designware_i2c_5::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SNPS_DESIGNWARE_I2C_5").finish() + } +} +#[doc = "From snps,designware-i2c, peripheral generator"] +pub mod snps_designware_i2c_5; +#[doc = "From snps,designware-i2c, peripheral generator"] +pub struct SNPS_DESIGNWARE_I2C_6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SNPS_DESIGNWARE_I2C_6 {} +impl SNPS_DESIGNWARE_I2C_6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const snps_designware_i2c_6::RegisterBlock = 0x1206_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const snps_designware_i2c_6::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SNPS_DESIGNWARE_I2C_6 { + type Target = snps_designware_i2c_6::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SNPS_DESIGNWARE_I2C_6").finish() + } +} +#[doc = "From snps,designware-i2c, peripheral generator"] +pub mod snps_designware_i2c_6; +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ARM_PL022_3 {} +impl ARM_PL022_3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const arm_pl022_3::RegisterBlock = 0x1207_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const arm_pl022_3::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ARM_PL022_3 { + type Target = arm_pl022_3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ARM_PL022_3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARM_PL022_3").finish() + } +} +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_3; +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ARM_PL022_4 {} +impl ARM_PL022_4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const arm_pl022_4::RegisterBlock = 0x1208_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const arm_pl022_4::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ARM_PL022_4 { + type Target = arm_pl022_4::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ARM_PL022_4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARM_PL022_4").finish() + } +} +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_4; +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ARM_PL022_5 {} +impl ARM_PL022_5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const arm_pl022_5::RegisterBlock = 0x1209_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const arm_pl022_5::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ARM_PL022_5 { + type Target = arm_pl022_5::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ARM_PL022_5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARM_PL022_5").finish() + } +} +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_5; +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ARM_PL022_6 {} +impl ARM_PL022_6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const arm_pl022_6::RegisterBlock = 0x120a_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const arm_pl022_6::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ARM_PL022_6 { + type Target = arm_pl022_6::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ARM_PL022_6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARM_PL022_6").finish() + } +} +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_6; #[doc = "From starfive,jh7110-pwm, peripheral generator"] pub struct STARFIVE_JH7110_PWM_0 { _marker: PhantomData<*const ()>, @@ -593,10 +1237,38 @@ static mut DEVICE_PERIPHERALS: bool = false; pub struct Peripherals { #[doc = "SIFIVE_CLINT0_0"] pub SIFIVE_CLINT0_0: SIFIVE_CLINT0_0, + #[doc = "SNPS_DESIGNWARE_I2C_0"] + pub SNPS_DESIGNWARE_I2C_0: SNPS_DESIGNWARE_I2C_0, + #[doc = "SNPS_DESIGNWARE_I2C_1"] + pub SNPS_DESIGNWARE_I2C_1: SNPS_DESIGNWARE_I2C_1, + #[doc = "SNPS_DESIGNWARE_I2C_2"] + pub SNPS_DESIGNWARE_I2C_2: SNPS_DESIGNWARE_I2C_2, + #[doc = "ARM_PL022_0"] + pub ARM_PL022_0: ARM_PL022_0, + #[doc = "ARM_PL022_1"] + pub ARM_PL022_1: ARM_PL022_1, + #[doc = "ARM_PL022_2"] + pub ARM_PL022_2: ARM_PL022_2, #[doc = "STARFIVE_JH7110_STGCRG_0"] pub STARFIVE_JH7110_STGCRG_0: STARFIVE_JH7110_STGCRG_0, #[doc = "STARFIVE_JH7110_STG_SYSCON_0"] pub STARFIVE_JH7110_STG_SYSCON_0: STARFIVE_JH7110_STG_SYSCON_0, + #[doc = "SNPS_DESIGNWARE_I2C_3"] + pub SNPS_DESIGNWARE_I2C_3: SNPS_DESIGNWARE_I2C_3, + #[doc = "SNPS_DESIGNWARE_I2C_4"] + pub SNPS_DESIGNWARE_I2C_4: SNPS_DESIGNWARE_I2C_4, + #[doc = "SNPS_DESIGNWARE_I2C_5"] + pub SNPS_DESIGNWARE_I2C_5: SNPS_DESIGNWARE_I2C_5, + #[doc = "SNPS_DESIGNWARE_I2C_6"] + pub SNPS_DESIGNWARE_I2C_6: SNPS_DESIGNWARE_I2C_6, + #[doc = "ARM_PL022_3"] + pub ARM_PL022_3: ARM_PL022_3, + #[doc = "ARM_PL022_4"] + pub ARM_PL022_4: ARM_PL022_4, + #[doc = "ARM_PL022_5"] + pub ARM_PL022_5: ARM_PL022_5, + #[doc = "ARM_PL022_6"] + pub ARM_PL022_6: ARM_PL022_6, #[doc = "STARFIVE_JH7110_PWM_0"] pub STARFIVE_JH7110_PWM_0: STARFIVE_JH7110_PWM_0, #[doc = "STARFIVE_JH7110_SYSCRG_0"] @@ -640,12 +1312,54 @@ impl Peripherals { SIFIVE_CLINT0_0: SIFIVE_CLINT0_0 { _marker: PhantomData, }, + SNPS_DESIGNWARE_I2C_0: SNPS_DESIGNWARE_I2C_0 { + _marker: PhantomData, + }, + SNPS_DESIGNWARE_I2C_1: SNPS_DESIGNWARE_I2C_1 { + _marker: PhantomData, + }, + SNPS_DESIGNWARE_I2C_2: SNPS_DESIGNWARE_I2C_2 { + _marker: PhantomData, + }, + ARM_PL022_0: ARM_PL022_0 { + _marker: PhantomData, + }, + ARM_PL022_1: ARM_PL022_1 { + _marker: PhantomData, + }, + ARM_PL022_2: ARM_PL022_2 { + _marker: PhantomData, + }, STARFIVE_JH7110_STGCRG_0: STARFIVE_JH7110_STGCRG_0 { _marker: PhantomData, }, STARFIVE_JH7110_STG_SYSCON_0: STARFIVE_JH7110_STG_SYSCON_0 { _marker: PhantomData, }, + SNPS_DESIGNWARE_I2C_3: SNPS_DESIGNWARE_I2C_3 { + _marker: PhantomData, + }, + SNPS_DESIGNWARE_I2C_4: SNPS_DESIGNWARE_I2C_4 { + _marker: PhantomData, + }, + SNPS_DESIGNWARE_I2C_5: SNPS_DESIGNWARE_I2C_5 { + _marker: PhantomData, + }, + SNPS_DESIGNWARE_I2C_6: SNPS_DESIGNWARE_I2C_6 { + _marker: PhantomData, + }, + ARM_PL022_3: ARM_PL022_3 { + _marker: PhantomData, + }, + ARM_PL022_4: ARM_PL022_4 { + _marker: PhantomData, + }, + ARM_PL022_5: ARM_PL022_5 { + _marker: PhantomData, + }, + ARM_PL022_6: ARM_PL022_6 { + _marker: PhantomData, + }, STARFIVE_JH7110_PWM_0: STARFIVE_JH7110_PWM_0 { _marker: PhantomData, }, diff --git a/jh7110-vf2-13b-pac/jh7110-starfive-visionfive-2-v1.3b.dts b/jh7110-vf2-13b-pac/jh7110-starfive-visionfive-2-v1.3b.dts index ca3bf63..7f575bb 100644 --- a/jh7110-vf2-13b-pac/jh7110-starfive-visionfive-2-v1.3b.dts +++ b/jh7110-vf2-13b-pac/jh7110-starfive-visionfive-2-v1.3b.dts @@ -1,10 +1,10 @@ /dts-v1/; / { - model = "StarFive VisionFive 2 v1.3b"; compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; #address-cells = <0x02>; #size-cells = <0x02>; + model = "StarFive VisionFive 2 v1.3B"; cpus { #address-cells = <0x01>; @@ -21,13 +21,13 @@ next-level-cache = <&ccache>; riscv,isa = "rv64imac_zba_zbb"; status = "disabled"; - phandle = <0x02>; + phandle = <0x05>; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; #interrupt-cells = <0x01>; - phandle = <0x07>; + phandle = <0x0d>; }; }; @@ -49,13 +49,18 @@ next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; - phandle = <0x03>; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg 0x01>; + clock-names = "cpu"; + #cooling-cells = <0x02>; + cpu-supply = <&vdd_cpu>; + phandle = <0x06>; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; #interrupt-cells = <0x01>; - phandle = <0x08>; + phandle = <0x0e>; }; }; @@ -77,13 +82,18 @@ next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; - phandle = <0x04>; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg 0x01>; + clock-names = "cpu"; + #cooling-cells = <0x02>; + cpu-supply = <&vdd_cpu>; + phandle = <0x07>; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; #interrupt-cells = <0x01>; - phandle = <0x09>; + phandle = <0x0f>; }; }; @@ -105,13 +115,18 @@ next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; - phandle = <0x05>; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg 0x01>; + clock-names = "cpu"; + #cooling-cells = <0x02>; + cpu-supply = <&vdd_cpu>; + phandle = <0x08>; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; #interrupt-cells = <0x01>; - phandle = <0x0a>; + phandle = <0x10>; }; }; @@ -133,62 +148,36 @@ next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; - phandle = <0x06>; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg 0x01>; + clock-names = "cpu"; + #cooling-cells = <0x02>; + cpu-supply = <&vdd_cpu>; + phandle = <0x09>; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; #interrupt-cells = <0x01>; - phandle = <0x0b>; - }; - }; - - cpu-map { - - cluster0 { - - core0 { - cpu = <&S7_0>; - }; - - core1 { - cpu = <&U74_1>; - }; - - core2 { - cpu = <&U74_2>; - }; - - core3 { - cpu = <&U74_3>; - }; - - core4 { - cpu = <&U74_4>; - }; + phandle = <0x11>; }; }; }; - timer { - compatible = "riscv,timer"; - interrupts-extended = <&cpu0_intc 0x05>, <&cpu1_intc 0x05>, <&cpu2_intc 0x05>, <&cpu3_intc 0x05>, <&cpu4_intc 0x05>; - }; - - osc: oscillator { + dvp_clk: dvp-clock { compatible = "fixed-clock"; - clock-output-names = "osc"; + clock-output-names = "dvp_clk"; #clock-cells = <0x00>; - clock-frequency = <0x16e3600>; - phandle = <0x13>; + clock-frequency = <0x46cf710>; + phandle = <0x35>; }; - rtc_osc: rtc-oscillator { + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { compatible = "fixed-clock"; - clock-output-names = "rtc_osc"; + clock-output-names = "gmac0_rgmii_rxin"; #clock-cells = <0x00>; - clock-frequency = <0x8000>; - phandle = <0x25>; + clock-frequency = <0x7735940>; + phandle = <0x33>; }; gmac0_rmii_refin: gmac0-rmii-refin-clock { @@ -196,15 +185,15 @@ clock-output-names = "gmac0_rmii_refin"; #clock-cells = <0x00>; clock-frequency = <0x2faf080>; - phandle = <0x26>; + phandle = <0x32>; }; - gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { + gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { compatible = "fixed-clock"; - clock-output-names = "gmac0_rgmii_rxin"; + clock-output-names = "gmac1_rgmii_rxin"; #clock-cells = <0x00>; clock-frequency = <0x7735940>; - phandle = <0x27>; + phandle = <0x20>; }; gmac1_rmii_refin: gmac1-rmii-refin-clock { @@ -212,71 +201,87 @@ clock-output-names = "gmac1_rmii_refin"; #clock-cells = <0x00>; clock-frequency = <0x2faf080>; - phandle = <0x14>; + phandle = <0x1f>; }; - gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { + hdmitx0_pixelclk: hdmitx0-pixel-clock { compatible = "fixed-clock"; - clock-output-names = "gmac1_rgmii_rxin"; + clock-output-names = "hdmitx0_pixelclk"; #clock-cells = <0x00>; - clock-frequency = <0x7735940>; - phandle = <0x15>; + clock-frequency = <0x11b3dc40>; + phandle = <0x37>; }; - i2stx_bclk_ext: i2stx-bclk-ext-clock { + i2srx_bclk_ext: i2srx-bclk-ext-clock { compatible = "fixed-clock"; - clock-output-names = "i2stx_bclk_ext"; + clock-output-names = "i2srx_bclk_ext"; #clock-cells = <0x00>; clock-frequency = <0xbb8000>; - phandle = <0x16>; + phandle = <0x23>; }; - i2stx_lrck_ext: i2stx-lrck-ext-clock { + i2srx_lrck_ext: i2srx-lrck-ext-clock { compatible = "fixed-clock"; - clock-output-names = "i2stx_lrck_ext"; + clock-output-names = "i2srx_lrck_ext"; #clock-cells = <0x00>; clock-frequency = <0x2ee00>; - phandle = <0x17>; + phandle = <0x24>; }; - i2srx_bclk_ext: i2srx-bclk-ext-clock { + i2stx_bclk_ext: i2stx-bclk-ext-clock { compatible = "fixed-clock"; - clock-output-names = "i2srx_bclk_ext"; + clock-output-names = "i2stx_bclk_ext"; #clock-cells = <0x00>; clock-frequency = <0xbb8000>; - phandle = <0x18>; + phandle = <0x21>; }; - i2srx_lrck_ext: i2srx-lrck-ext-clock { + i2stx_lrck_ext: i2stx-lrck-ext-clock { compatible = "fixed-clock"; - clock-output-names = "i2srx_lrck_ext"; + clock-output-names = "i2stx_lrck_ext"; #clock-cells = <0x00>; clock-frequency = <0x2ee00>; - phandle = <0x19>; + phandle = <0x22>; }; - tdm_ext: tdm-ext-clock { + mclk_ext: mclk-ext-clock { compatible = "fixed-clock"; - clock-output-names = "tdm_ext"; + clock-output-names = "mclk_ext"; #clock-cells = <0x00>; - clock-frequency = <0x2ee0000>; - phandle = <0x1a>; + clock-frequency = <0xbb8000>; + phandle = <0x25>; }; - mclk_ext: mclk-ext-clock { + osc: oscillator { compatible = "fixed-clock"; - clock-output-names = "mclk_ext"; + clock-output-names = "osc"; #clock-cells = <0x00>; - clock-frequency = <0xbb8000>; - phandle = <0x1b>; + clock-frequency = <0x16e3600>; + phandle = <0x1c>; + }; + + rtc_osc: rtc-oscillator { + compatible = "fixed-clock"; + clock-output-names = "rtc_osc"; + #clock-cells = <0x00>; + clock-frequency = <0x8000>; + phandle = <0x34>; }; stmmac_axi_setup: stmmac-axi-config { snps,lpi_en; - snps,wr_osr_lmt = <0x04>; - snps,rd_osr_lmt = <0x04>; + snps,wr_osr_lmt = <0x0f>; + snps,rd_osr_lmt = <0x0f>; snps,blen = <0x100 0x80 0x40 0x20 0x00 0x00 0x00>; - phandle = <0x21>; + phandle = <0x2e>; + }; + + tdm_ext: tdm-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "tdm_ext"; + #clock-cells = <0x00>; + clock-frequency = <0x2ee0000>; + phandle = <0x16>; }; soc { @@ -292,17 +297,6 @@ interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, <&cpu4_intc 0x03>, <&cpu4_intc 0x07>; }; - plic: interrupt-controller@c000000 { - compatible = "starfive,jh7110-plic", "sifive,plic0"; - reg = <0x00 0xc000000 0x00 0x4000000>; - interrupts-extended = <&cpu0_intc 0x0b>, <&cpu1_intc 0x0b>, <&cpu1_intc 0x09>, <&cpu2_intc 0x0b>, <&cpu2_intc 0x09>, <&cpu3_intc 0x0b>, <&cpu3_intc 0x09>, <&cpu4_intc 0x0b>, <&cpu4_intc 0x09>; - interrupt-controller; - #interrupt-cells = <0x01>; - #address-cells = <0x00>; - riscv,ndev = <0x88>; - phandle = <0x0c>; - }; - ccache: cache-controller@2010000 { compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; reg = <0x00 0x2010000 0x00 0x4000>; @@ -315,19 +309,27 @@ phandle = <0x01>; }; + plic: interrupt-controller@c000000 { + compatible = "starfive,jh7110-plic", "sifive,plic"; + reg = <0x00 0xc000000 0x00 0x4000000>; + interrupts-extended = <&cpu0_intc 0x0b>, <&cpu1_intc 0x0b>, <&cpu1_intc 0x09>, <&cpu2_intc 0x0b>, <&cpu2_intc 0x09>, <&cpu3_intc 0x0b>, <&cpu3_intc 0x09>, <&cpu4_intc 0x0b>, <&cpu4_intc 0x09>; + interrupt-controller; + #interrupt-cells = <0x01>; + #address-cells = <0x00>; + riscv,ndev = <0x88>; + phandle = <0x0c>; + }; + uart0: serial@10000000 { compatible = "snps,dw-apb-uart"; reg = <0x00 0x10000000 0x00 0x10000>; clocks = <&syscrg 0x92>, <&syscrg 0x91>; clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg 0x53>, <&syscrg 0x54>; + resets = <&syscrg 0x53>; interrupts = <0x20>; reg-io-width = <0x04>; reg-shift = <0x02>; status = "okay"; - reg-offset = <0x00>; - current-speed = <0x1c200>; - clock-frequency = <0x16e3600>; pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; }; @@ -337,7 +339,7 @@ reg = <0x00 0x10010000 0x00 0x10000>; clocks = <&syscrg 0x94>, <&syscrg 0x93>; clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg 0x55>, <&syscrg 0x56>; + resets = <&syscrg 0x55>; interrupts = <0x21>; reg-io-width = <0x04>; reg-shift = <0x02>; @@ -349,7 +351,7 @@ reg = <0x00 0x10020000 0x00 0x10000>; clocks = <&syscrg 0x96>, <&syscrg 0x95>; clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg 0x57>, <&syscrg 0x58>; + resets = <&syscrg 0x57>; interrupts = <0x22>; reg-io-width = <0x04>; reg-shift = <0x02>; @@ -404,18 +406,129 @@ pinctrl-0 = <&i2c2_pins>; }; + spi0: spi@10060000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00 0x10060000 0x00 0x10000>; + clocks = <&syscrg 0x83>, <&syscrg 0x83>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg 0x45>; + interrupts = <0x26>; + arm,primecell-periphid = <0x41022>; + num-cs = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + + spi_dev0: spi@0 { + compatible = "rohm,dh2228fv"; + reg = <0x00>; + spi-max-frequency = <0x989680>; + }; + }; + + spi1: spi@10070000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00 0x10070000 0x00 0x10000>; + clocks = <&syscrg 0x84>, <&syscrg 0x84>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg 0x46>; + interrupts = <0x27>; + arm,primecell-periphid = <0x41022>; + num-cs = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + spi2: spi@10080000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00 0x10080000 0x00 0x10000>; + clocks = <&syscrg 0x85>, <&syscrg 0x85>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg 0x47>; + interrupts = <0x28>; + arm,primecell-periphid = <0x41022>; + num-cs = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + tdm: tdm@10090000 { + compatible = "starfive,jh7110-tdm"; + reg = <0x00 0x10090000 0x00 0x1000>; + clocks = <&syscrg 0xb8>, <&syscrg 0xb9>, <&syscrg 0xba>, <&syscrg 0xbb>, <&syscrg 0x11>, <&tdm_ext>; + clock-names = "tdm_ahb", "tdm_apb", "tdm_internal", "tdm", "mclk_inner", "tdm_ext"; + resets = <&syscrg 0x69>, <&syscrg 0x6b>, <&syscrg 0x6a>; + dmas = <&dma 0x14>, <&dma 0x15>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0x00>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&tdm_pins>; + }; + + usb0: usb@10100000 { + compatible = "starfive,jh7110-usb"; + ranges = <0x00 0x00 0x10100000 0x100000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + starfive,stg-syscon = <&stg_syscon 0x04>; + clocks = <&stgcrg 0x04>, <&stgcrg 0x05>, <&stgcrg 0x01>, <&stgcrg 0x03>, <&stgcrg 0x02>; + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; + resets = <&stgcrg 0x0a>, <&stgcrg 0x08>, <&stgcrg 0x07>, <&stgcrg 0x09>; + reset-names = "pwrup", "apb", "axi", "utmi_apb"; + status = "disabled"; + dr_mode = "peripheral"; + + usb_cdns3: usb@0 { + compatible = "cdns,usb3"; + reg = <0x00 0x10000>, <0x10000 0x10000>, <0x20000 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <0x64>, <0x6c>, <0x6e>; + interrupt-names = "host", "peripheral", "otg"; + phys = <&usbphy0>; + phy-names = "cdns3,usb2-phy"; + }; + }; + + usbphy0: phy@10200000 { + compatible = "starfive,jh7110-usb-phy"; + reg = <0x00 0x10200000 0x00 0x10000>; + clocks = <&syscrg 0x5f>, <&stgcrg 0x06>; + clock-names = "125m", "app_125m"; + #phy-cells = <0x00>; + phandle = <0x1b>; + }; + + pciephy0: phy@10210000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x00 0x10210000 0x00 0x10000>; + #phy-cells = <0x00>; + }; + + pciephy1: phy@10220000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x00 0x10220000 0x00 0x10000>; + #phy-cells = <0x00>; + }; + stgcrg: clock-controller@10230000 { compatible = "starfive,jh7110-stgcrg"; reg = <0x00 0x10230000 0x00 0x10000>; + clocks = <&osc>, <&syscrg 0x36>, <&syscrg 0x08>, <&syscrg 0x5f>, <&syscrg 0x02>, <&syscrg 0x37>, <&syscrg 0x06>, <&syscrg 0x0b>; + clock-names = "osc", "hifi4_core", "stg_axiahb", "usb_125m", "cpu_bus", "hifi4_axi", "nocstg_bus", "apb_bus"; #clock-cells = <0x01>; #reset-cells = <0x01>; - phandle = <0x29>; + phandle = <0x1a>; }; - stg_syscon: stg_syscon@10240000 { + stg_syscon: syscon@10240000 { compatible = "starfive,jh7110-stg-syscon", "syscon"; reg = <0x00 0x10240000 0x00 0x1000>; - phandle = <0x28>; + phandle = <0x19>; }; uart3: serial@12000000 { @@ -423,7 +536,7 @@ reg = <0x00 0x12000000 0x00 0x10000>; clocks = <&syscrg 0x98>, <&syscrg 0x97>; clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg 0x59>, <&syscrg 0x5a>; + resets = <&syscrg 0x59>; interrupts = <0x2d>; reg-io-width = <0x04>; reg-shift = <0x02>; @@ -435,7 +548,7 @@ reg = <0x00 0x12010000 0x00 0x10000>; clocks = <&syscrg 0x9a>, <&syscrg 0x99>; clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg 0x5b>, <&syscrg 0x5c>; + resets = <&syscrg 0x5b>; interrupts = <0x2e>; reg-io-width = <0x04>; reg-shift = <0x02>; @@ -447,7 +560,7 @@ reg = <0x00 0x12020000 0x00 0x10000>; clocks = <&syscrg 0x9c>, <&syscrg 0x9b>; clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg 0x5d>, <&syscrg 0x5e>; + resets = <&syscrg 0x5d>; interrupts = <0x2f>; reg-io-width = <0x04>; reg-shift = <0x02>; @@ -495,10 +608,41 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c5_pins>; - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <0x10>; + axp15060: pmic@36 { + compatible = "x-powers,axp15060"; + reg = <0x36>; + interrupts = <0x00>; + interrupt-controller; + #interrupt-cells = <0x01>; + + regulators { + + vcc_3v3: dcdc1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vcc_3v3"; + phandle = <0x2a>; + }; + + vdd_cpu: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <0x7a120>; + regulator-max-microvolt = <0x177fa0>; + regulator-name = "vdd-cpu"; + phandle = <0x04>; + }; + + emmc_vdd: aldo4 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "emmc_vdd"; + phandle = <0x2b>; + }; + }; }; }; @@ -520,24 +664,93 @@ pinctrl-0 = <&i2c6_pins>; }; + spi3: spi@12070000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00 0x12070000 0x00 0x10000>; + clocks = <&syscrg 0x86>, <&syscrg 0x86>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg 0x48>; + interrupts = <0x34>; + arm,primecell-periphid = <0x41022>; + num-cs = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + spi4: spi@12080000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00 0x12080000 0x00 0x10000>; + clocks = <&syscrg 0x87>, <&syscrg 0x87>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg 0x49>; + interrupts = <0x35>; + arm,primecell-periphid = <0x41022>; + num-cs = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + spi5: spi@12090000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00 0x12090000 0x00 0x10000>; + clocks = <&syscrg 0x88>, <&syscrg 0x88>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg 0x4a>; + interrupts = <0x36>; + arm,primecell-periphid = <0x41022>; + num-cs = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + spi6: spi@120a0000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00 0x120a0000 0x00 0x10000>; + clocks = <&syscrg 0x89>, <&syscrg 0x89>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg 0x4b>; + interrupts = <0x37>; + arm,primecell-periphid = <0x41022>; + num-cs = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + sfctemp: temperature-sensor@120e0000 { + compatible = "starfive,jh7110-temp"; + reg = <0x00 0x120e0000 0x00 0x10000>; + clocks = <&syscrg 0x82>, <&syscrg 0x81>; + clock-names = "sense", "bus"; + resets = <&syscrg 0x7c>, <&syscrg 0x7b>; + reset-names = "sense", "bus"; + #thermal-sensor-cells = <0x00>; + phandle = <0x0a>; + }; + qspi: spi@13010000 { - compatible = "cdns,qspi-nor"; - reg = <0x00 0x13010000 0x00 0x10000 0x00 0x21000000 0x00 0x400000>; - clocks = <&syscrg 0x5a>; - clock-names = "clk_ref"; + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; + reg = <0x00 0x13010000 0x00 0x10000>, <0x00 0x21000000 0x00 0x400000>; + interrupts = <0x19>; + clocks = <&syscrg 0x5a>, <&syscrg 0x57>, <&syscrg 0x58>; + clock-names = "ref", "ahb", "apb"; resets = <&syscrg 0x3e>, <&syscrg 0x3d>, <&syscrg 0x3f>; - reset-names = "rst_apb", "rst_ahb", "rst_ref"; + reset-names = "qspi", "qspi-ocp", "rstc_ref"; cdns,fifo-depth = <0x100>; cdns,fifo-width = <0x04>; + cdns,trigger-address = <0x00>; + status = "okay"; #address-cells = <0x01>; #size-cells = <0x00>; - spi-max-frequency = <0xee6b280>; - status = "okay"; - nor-flash@0 { + nor_flash: flash@0 { compatible = "jedec,spi-nor"; reg = <0x00>; - spi-max-frequency = <0x5f5e100>; + cdns,read-delay = <0x05>; + spi-max-frequency = <0xb71b00>; cdns,tshsl-ns = <0x01>; cdns,tsd2d-ns = <0x01>; cdns,tchsh-ns = <0x01>; @@ -545,15 +758,6 @@ }; }; - ptc: pwm@120d0000 { - compatible = "starfive,jh7110-pwm"; - reg = <0x0 0x120d0000 0x0 0x10000>; - clocks = <&syscrg 121>; - resets = <&syscrg 108>; - #pwm-cells = <3>; - status = "disabled"; - }; - syscrg: clock-controller@13020000 { compatible = "starfive,jh7110-syscrg"; reg = <0x00 0x13020000 0x00 0x10000>; @@ -561,22 +765,19 @@ clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", "tdm_ext", "mclk_ext", "pll0_out", "pll1_out", "pll2_out"; #clock-cells = <0x01>; #reset-cells = <0x01>; - assigned-clocks = <&syscrg 0x00>, <&syscrg 0x05>, <&syscrg 0x04>, <&syscrg 0x5a>; - assigned-clock-parents = <&pllclk 0x00>, <&pllclk 0x02>, <&pllclk 0x02>, <&syscrg 0x59>; - assigned-clock-rates = <0x00>, <0x00>, <0x00>, <0x00>; - phandle = <0x0d>; + phandle = <0x03>; }; - sys_syscon: sys_syscon@13030000 { + sys_syscon: syscon@13030000 { compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; reg = <0x00 0x13030000 0x00 0x1000>; - phandle = <0x1d>; + phandle = <0x28>; pllclk: clock-controller { compatible = "starfive,jh7110-pll"; clocks = <&osc>; #clock-cells = <0x01>; - phandle = <0x1c>; + phandle = <0x26>; }; }; @@ -590,33 +791,10 @@ #interrupt-cells = <0x02>; gpio-controller; #gpio-cells = <0x02>; - status = "okay"; - phandle = <0x2a>; - - uart0_pins: uart0-0 { - phandle = <0x0e>; - - tx-pins { - pinmux = <0xff140005>; - bias-disable; - drive-strength = <0x0c>; - input-disable; - input-schmitt-disable; - slew-rate = <0x00>; - }; - - rx-pins { - pinmux = <0xe000406>; - bias-disable; - drive-strength = <0x02>; - input-enable; - input-schmitt-enable; - slew-rate = <0x00>; - }; - }; + phandle = <0x38>; i2c0_pins: i2c0-0 { - phandle = <0x0f>; + phandle = <0x13>; i2c-pins { pinmux = <0x9001439>, <0xa00183a>; @@ -627,7 +805,7 @@ }; i2c2_pins: i2c2-0 { - phandle = <0x10>; + phandle = <0x14>; i2c-pins { pinmux = <0x3b007803>, <0x3c007c02>; @@ -638,7 +816,7 @@ }; i2c5_pins: i2c5-0 { - phandle = <0x11>; + phandle = <0x1d>; i2c-pins { pinmux = <0x4f00a813>, <0x5000ac14>; @@ -649,7 +827,7 @@ }; i2c6_pins: i2c6-0 { - phandle = <0x12>; + phandle = <0x1e>; i2c-pins { pinmux = <0x5600b810>, <0x5700bc11>; @@ -659,10 +837,10 @@ }; }; - mmc0_pins: mmc0-pins { - phandle = <0x1e>; + mmc0_pins: mmc0-0 { + phandle = <0x29>; - mmc0-pins-rest { + rst-pins { pinmux = <0xff13003e>; bias-pull-up; drive-strength = <0x0c>; @@ -670,12 +848,19 @@ input-schmitt-disable; slew-rate = <0x00>; }; + + mmc-pins { + pinmux = <0x440>, <0x441>, <0x442>, <0x443>, <0x444>, <0x445>, <0x446>, <0x447>, <0x448>, <0x449>; + bias-pull-up; + drive-strength = <0x0c>; + input-enable; + }; }; - mmc1_pins: mmc1-pins { - phandle = <0x1f>; + mmc1_pins: mmc1-0 { + phandle = <0x2c>; - mmc1-pins0 { + clk-pins { pinmux = <0xff37000a>; bias-pull-up; drive-strength = <0x0c>; @@ -684,7 +869,7 @@ slew-rate = <0x00>; }; - mmc1-pins1 { + mmc-pins { pinmux = <0x2c394c09>, <0x2d3a500b>, <0x2e3b540c>, <0x2f3c5807>, <0x303d5c08>; bias-pull-up; drive-strength = <0x0c>; @@ -693,10 +878,136 @@ slew-rate = <0x00>; }; }; + + spi0_pins: spi0-0 { + phandle = <0x15>; + + mosi-pins { + pinmux = <0xff200034>; + bias-disable; + input-disable; + input-schmitt-disable; + }; + + miso-pins { + pinmux = <0x1c000435>; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + + sck-pins { + pinmux = <0x1a1e0030>; + bias-disable; + input-disable; + input-schmitt-disable; + }; + + ss-pins { + pinmux = <0x1b1f0030>; + bias-disable; + input-disable; + input-schmitt-disable; + }; + }; + + uart0_pins: uart0-0 { + phandle = <0x12>; + + tx-pins { + pinmux = <0xff140005>; + bias-disable; + drive-strength = <0x0c>; + input-disable; + input-schmitt-disable; + slew-rate = <0x00>; + }; + + rx-pins { + pinmux = <0xe000406>; + bias-disable; + drive-strength = <0x02>; + input-enable; + input-schmitt-enable; + slew-rate = <0x00>; + }; + }; + + tdm_pins: tdm-0 { + phandle = <0x18>; + + tx-pins { + pinmux = <0xff29002c>; + bias-pull-up; + drive-strength = <0x02>; + input-disable; + input-schmitt-disable; + slew-rate = <0x00>; + }; + + rx-pins { + pinmux = <0x2401043d>; + input-enable; + }; + + sync-pins { + pinmux = <0x2501043f>; + input-enable; + }; + + pcmclk-pins { + pinmux = <0x23010426>; + input-enable; + }; + }; + }; + + watchdog@13070000 { + compatible = "starfive,jh7110-wdt"; + reg = <0x00 0x13070000 0x00 0x10000>; + clocks = <&syscrg 0x7a>, <&syscrg 0x7b>; + clock-names = "apb", "core"; + resets = <&syscrg 0x6d>, <&syscrg 0x6e>; + }; + + crypto: crypto@16000000 { + compatible = "starfive,jh7110-crypto"; + reg = <0x00 0x16000000 0x00 0x4000>; + clocks = <&stgcrg 0x0f>, <&stgcrg 0x10>; + clock-names = "hclk", "ahb"; + interrupts = <0x1c>; + resets = <&stgcrg 0x03>; + dmas = <&sdma 0x01 0x02>, <&sdma 0x00 0x02>; + dma-names = "tx", "rx"; + }; + + sdma: dma-controller@16008000 { + compatible = "arm,pl080", "arm,primecell"; + arm,primecell-periphid = <0x41080>; + reg = <0x00 0x16008000 0x00 0x4000>; + interrupts = <0x1d>; + clocks = <&stgcrg 0x0f>; + clock-names = "apb_pclk"; + resets = <&stgcrg 0x03>; + lli-bus-interface-ahb1; + mem-bus-interface-ahb1; + memcpy-burst-size = <0x100>; + memcpy-bus-width = <0x20>; + #dma-cells = <0x02>; + phandle = <0x27>; + }; + + rng: rng@1600c000 { + compatible = "starfive,jh7110-trng"; + reg = <0x00 0x1600c000 0x00 0x4000>; + clocks = <&stgcrg 0x0f>, <&stgcrg 0x10>; + clock-names = "hclk", "ahb"; + resets = <&stgcrg 0x03>; + interrupts = <0x1e>; }; mmc0: mmc@16010000 { - compatible = "snps,dw-mshc"; + compatible = "starfive,jh7110-mmc"; reg = <0x00 0x16010000 0x00 0x10000>; clocks = <&syscrg 0x5b>, <&syscrg 0x5d>; clock-names = "biu", "ciu"; @@ -710,18 +1021,20 @@ status = "okay"; max-frequency = <0x5f5e100>; bus-width = <0x08>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; cap-mmc-highspeed; mmc-ddr-1_8v; mmc-hs200-1_8v; non-removable; cap-mmc-hw-reset; post-power-on-delay-ms = <0xc8>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&emmc_vdd>; }; mmc1: mmc@16020000 { - compatible = "snps,dw-mshc"; + compatible = "starfive,jh7110-mmc"; reg = <0x00 0x16020000 0x00 0x10000>; clocks = <&syscrg 0x5c>, <&syscrg 0x5e>; clock-names = "biu", "ciu"; @@ -735,17 +1048,17 @@ status = "okay"; max-frequency = <0x5f5e100>; bus-width = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; no-sdio; no-mmc; broken-cd; cap-sd-highspeed; post-power-on-delay-ms = <0xc8>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; }; gmac0: ethernet@16030000 { - compatible = "starfive,jh7110-dwmac", "snps,dwmac-5_20"; + compatible = "starfive,jh7110-dwmac", "snps,dwmac"; reg = <0x00 0x16030000 0x00 0x10000>; clocks = <&aoncrg 0x03>, <&aoncrg 0x02>, <&syscrg 0x6d>, <&aoncrg 0x06>, <&syscrg 0x6f>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx"; @@ -753,10 +1066,10 @@ reset-names = "stmmaceth", "ahb"; interrupts = <0x07>, <0x06>, <0x05>; interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - snps,multicast-filter-bins = <0x40>; - snps,perfect-filter-entries = <0x08>; rx-fifo-depth = <0x800>; tx-fifo-depth = <0x800>; + snps,multicast-filter-bins = <0x40>; + snps,perfect-filter-entries = <0x100>; snps,fixed-burst; snps,no-pbl-x8; snps,force_thresh_dma_mode; @@ -769,6 +1082,9 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + starfive,tx-use-rgmii-clk; + assigned-clocks = <&aoncrg 0x05>; + assigned-clock-parents = <&aoncrg 0x04>; mdio { #address-cells = <0x01>; @@ -777,13 +1093,20 @@ phy0: ethernet-phy@0 { reg = <0x00>; - phandle = <0x23>; + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-100-inverted; + motorcomm,tx-clk-1000-inverted; + motorcomm,rx-clk-drv-microamp = <0xf82>; + motorcomm,rx-data-drv-microamp = <0xb5e>; + rx-internal-delay-ps = <0x5dc>; + tx-internal-delay-ps = <0x5dc>; + phandle = <0x30>; }; }; }; gmac1: ethernet@16040000 { - compatible = "starfive,jh7110-dwmac", "snps,dwmac-5_20"; + compatible = "starfive,jh7110-dwmac", "snps,dwmac"; reg = <0x00 0x16040000 0x00 0x10000>; clocks = <&syscrg 0x62>, <&syscrg 0x61>, <&syscrg 0x66>, <&syscrg 0x6a>, <&syscrg 0x6b>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx"; @@ -791,10 +1114,10 @@ reset-names = "stmmaceth", "ahb"; interrupts = <0x4e>, <0x4d>, <0x4c>; interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - snps,multicast-filter-bins = <0x40>; - snps,perfect-filter-entries = <0x08>; rx-fifo-depth = <0x800>; tx-fifo-depth = <0x800>; + snps,multicast-filter-bins = <0x40>; + snps,perfect-filter-entries = <0x100>; snps,fixed-burst; snps,no-pbl-x8; snps,force_thresh_dma_mode; @@ -807,6 +1130,9 @@ status = "okay"; phy-handle = <&phy1>; phy-mode = "rgmii-id"; + starfive,tx-use-rgmii-clk; + assigned-clocks = <&syscrg 0x69>; + assigned-clock-parents = <&syscrg 0x65>; mdio { #address-cells = <0x01>; @@ -815,28 +1141,49 @@ phy1: ethernet-phy@1 { reg = <0x00>; - phandle = <0x24>; + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-100-inverted; + motorcomm,rx-clk-drv-microamp = <0xf82>; + motorcomm,rx-data-drv-microamp = <0xb5e>; + rx-internal-delay-ps = <0x12c>; + tx-internal-delay-ps = <0x00>; + phandle = <0x31>; }; }; }; + dma: dma-controller@16050000 { + compatible = "starfive,jh7110-axi-dma"; + reg = <0x00 0x16050000 0x00 0x10000>; + clocks = <&stgcrg 0x1b>, <&stgcrg 0x1c>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&stgcrg 0x05>, <&stgcrg 0x06>; + interrupts = <0x49>; + #dma-cells = <0x01>; + dma-channels = <0x04>; + snps,dma-masters = <0x01>; + snps,data-width = <0x03>; + snps,block-size = <0x10000 0x10000 0x10000 0x10000>; + snps,priority = <0x00 0x01 0x02 0x03>; + snps,axi-max-burst-len = <0x10>; + phandle = <0x17>; + }; + aoncrg: clock-controller@17000000 { compatible = "starfive,jh7110-aoncrg"; reg = <0x00 0x17000000 0x00 0x10000>; - clocks = <&osc>, <&rtc_osc>, <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, <&syscrg 0x08>, <&syscrg 0x0b>, <&syscrg 0x6c>; - clock-names = "osc", "rtc_osc", "gmac0_rmii_refin", "gmac0_rgmii_rxin", "stg_axiahb", "apb_bus", "gmac0_gtxclk"; + clocks = <&osc>, <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, <&syscrg 0x08>, <&syscrg 0x0b>, <&syscrg 0x6c>, <&rtc_osc>; + clock-names = "osc", "gmac0_rmii_refin", "gmac0_rgmii_rxin", "stg_axiahb", "apb_bus", "gmac0_gtxclk", "rtc_osc"; #clock-cells = <0x01>; #reset-cells = <0x01>; - assigned-clocks = <&aoncrg 0x01>; - assigned-clock-parents = <&osc>; - assigned-clock-rates = <0x00>; - phandle = <0x20>; + phandle = <0x2d>; }; - aon_syscon: aon_syscon@17010000 { + aon_syscon: syscon@17010000 { compatible = "starfive,jh7110-aon-syscon", "syscon"; reg = <0x00 0x17010000 0x00 0x1000>; - phandle = <0x22>; + #power-domain-cells = <0x01>; + phandle = <0x2f>; }; aongpio: pinctrl@17020000 { @@ -850,66 +1197,47 @@ #gpio-cells = <0x02>; }; - pcie0: pcie@2b000000 { - compatible = "starfive,jh7110-pcie"; - reg = <0x00 0x2b000000 0x00 0x1000000 0x09 0x40000000 0x00 0x10000000>; - reg-names = "reg", "config"; - #address-cells = <0x03>; - #size-cells = <0x02>; - #interrupt-cells = <0x01>; - ranges = <0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x8000000>, <0xc3000000 0x09 0x00 0x09 0x00 0x00 0x40000000>; - interrupts = <0x38>; - interrupt-parent = <&plic>; - interrupt-map-mask = <0x00 0x00 0x00 0x07>; - interrupt-map = <0x00 0x00 0x00 0x01&plic 0x01>, <0x00 0x00 0x00 0x02&plic 0x02>, <0x00 0x00 0x00 0x03&plic 0x03>, <0x00 0x00 0x00 0x04&plic 0x04>; - msi-parent = <&plic>; - device_type = "pci"; - starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; - bus-range = <0x00 0xff>; - clocks = <&syscrg 0x60>, <&stgcrg 0x0a>, <&stgcrg 0x08>, <&stgcrg 0x09>; - clock-names = "noc", "tl", "axi", "apb"; - resets = <&stgcrg 0x0b>, <&stgcrg 0x0c>, <&stgcrg 0x0d>, <&stgcrg 0x0e>, <&stgcrg 0x0f>, <&stgcrg 0x10>; - reset-names = "mst0", "slv0", "slv", "brg", "core", "apb"; - status = "okay"; - reset-gpios = <&sysgpio 0x1a 0x01>; + pwrc: power-controller@17030000 { + compatible = "starfive,jh7110-pmu"; + reg = <0x00 0x17030000 0x00 0x10000>; + interrupts = <0x6f>; + #power-domain-cells = <0x01>; + phandle = <0x36>; }; - pcie1: pcie@2c000000 { - compatible = "starfive,jh7110-pcie"; - reg = <0x00 0x2c000000 0x00 0x1000000 0x09 0xc0000000 0x00 0x10000000>; - reg-names = "reg", "config"; - #address-cells = <0x03>; - #size-cells = <0x02>; - #interrupt-cells = <0x01>; - ranges = <0x82000000 0x00 0x38000000 0x00 0x38000000 0x00 0x8000000>, <0xc3000000 0x09 0x80000000 0x09 0x80000000 0x00 0x40000000>; - interrupts = <0x39>; - interrupt-parent = <&plic>; - interrupt-map-mask = <0x00 0x00 0x00 0x07>; - interrupt-map = <0x00 0x00 0x00 0x01&plic 0x01>, <0x00 0x00 0x00 0x02&plic 0x02>, <0x00 0x00 0x00 0x03&plic 0x03>, <0x00 0x00 0x00 0x04&plic 0x04>; - msi-parent = <&plic>; - device_type = "pci"; - starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>; - bus-range = <0x00 0xff>; - clocks = <&syscrg 0x60>, <&stgcrg 0x0d>, <&stgcrg 0x0b>, <&stgcrg 0x0c>; - clock-names = "noc", "tl", "axi", "apb"; - resets = <&stgcrg 0x11>, <&stgcrg 0x12>, <&stgcrg 0x13>, <&stgcrg 0x14>, <&stgcrg 0x15>, <&stgcrg 0x16>; - reset-names = "mst0", "slv0", "slv", "brg", "core", "apb"; - status = "okay"; - reset-gpios = <&sysgpio 0x1c 0x01>; + ispcrg: clock-controller@19810000 { + compatible = "starfive,jh7110-ispcrg"; + reg = <0x00 0x19810000 0x00 0x10000>; + clocks = <&syscrg 0x33>, <&syscrg 0x34>, <&syscrg 0x35>, <&dvp_clk>; + clock-names = "isp_top_core", "isp_top_axi", "noc_bus_isp_axi", "dvp_clk"; + resets = <&syscrg 0x29>, <&syscrg 0x2a>, <&syscrg 0x1c>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + power-domains = <&pwrc 0x05>; + }; + + voutcrg: clock-controller@295c0000 { + compatible = "starfive,jh7110-voutcrg"; + reg = <0x00 0x295c0000 0x00 0x10000>; + clocks = <&syscrg 0x3a>, <&syscrg 0x3d>, <&syscrg 0x3e>, <&syscrg 0x3f>, <&syscrg 0xa5>, <&hdmitx0_pixelclk>; + clock-names = "vout_src", "vout_top_ahb", "vout_top_axi", "vout_top_hdmitx0_mclk", "i2stx0_bclk", "hdmitx0_pixelclk"; + resets = <&syscrg 0x2b>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + power-domains = <&pwrc 0x04>; }; }; aliases { - serial0 = "/soc/serial@10000000"; - spi0 = "/soc/spi@13010000"; - mmc0 = "/soc/mmc@16010000"; - mmc1 = "/soc/mmc@16020000"; + ethernet0 = "/soc/ethernet@16030000"; + ethernet1 = "/soc/ethernet@16040000"; i2c0 = "/soc/i2c@10030000"; i2c2 = "/soc/i2c@10050000"; i2c5 = "/soc/i2c@12050000"; i2c6 = "/soc/i2c@12060000"; - ethernet0 = "/soc/ethernet@16030000"; - ethernet1 = "/soc/ethernet@16040000"; + mmc0 = "/soc/mmc@16010000"; + mmc1 = "/soc/mmc@16020000"; + serial0 = "/soc/serial@10000000"; }; chosen { @@ -918,6 +1246,12 @@ memory@40000000 { device_type = "memory"; - reg = <0x00 0x40000000 0x02 0x00>; + reg = <0x00 0x40000000 0x01 0x00>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&sysgpio 0x23 0x00>; + priority = <0xe0>; }; }; diff --git a/jh7110-vf2-13b-pac/jh7110-starfive-visionfive-2-v1.3b.svd b/jh7110-vf2-13b-pac/jh7110-starfive-visionfive-2-v1.3b.svd index 5f86d0d..8402a76 100644 --- a/jh7110-vf2-13b-pac/jh7110-starfive-visionfive-2-v1.3b.svd +++ b/jh7110-vf2-13b-pac/jh7110-starfive-visionfive-2-v1.3b.svd @@ -1,8 +1,8 @@ - StarFive VisionFive 2 v1.3b + StarFive VisionFive 2 v1.3B 0.1 - From StarFive VisionFive 2 v1.3b,model device generator + From StarFive VisionFive 2 v1.3B,model device generator 8 32 32 @@ -91,6 +91,36 @@ + + starfive_jh7110_ccache_0 + From starfive,jh7110-ccache, peripheral generator + 0x2010000 + + 0 + 0x4000 + registers + + + + sifive_ccache0_0 + From sifive,ccache0, peripheral generator + 0x2010000 + + 0 + 0x4000 + registers + + + + cache_0 + From cache, peripheral generator + 0x2010000 + + 0 + 0x4000 + registers + + starfive_jh7110_plic_0 From starfive,jh7110-plic, peripheral generator @@ -102,961 +132,2105 @@ - sifive_plic0_0 - From sifive,plic0, peripheral generator + sifive_plic_0 + From sifive,plic, peripheral generator 0xC000000 0 0x4000000 registers + + + snps_dw_apb_uart_0 + From snps,dw-apb-uart, peripheral generator + 0x10000000 + + 0 + 0x10000 + registers + + + + snps_dw_apb_uart_1 + From snps,dw-apb-uart, peripheral generator + 0x10010000 + + 0 + 0x10000 + registers + + + + snps_dw_apb_uart_2 + From snps,dw-apb-uart, peripheral generator + 0x10020000 + + 0 + 0x10000 + registers + + + + snps_designware_i2c_0 + From snps,designware-i2c, peripheral generator + 0x10030000 + + 0 + 0x10000 + registers + - priority_1 - PRIORITY Register for interrupt id 1 - 0x4 + con + DesignWare I2C CON + 0x0 + 32 + + + master + I2C Master Connection - 0: Slave, 1: Master + [0:0] + read-write + + + speed + I2C Speed - 01: Standard, 10: Fast, 11: High + [2:1] + read-write + + + slave_10bitaddr + I2C Slave 10-bit Address - 0: False, 1: True + [3:3] + read-write + + + master_10bitaddr + I2C Master 10-bit Address - 0: False, 1: True + [4:4] + read-write + + + restart_en + I2C Restart Enable - 0: False, 1: True + [5:5] + read-write + + + slave_disable + I2C Slave Disable - 0: False, 1: True + [6:6] + read-write + + + stop_det_ifaddressed + I2C Stop DET If Addressed - 0: False, 1: True + [7:7] + read-write + + + tx_empty_ctrl + I2C TX Empty Control - 0: False, 1: True + [8:8] + read-write + + + rx_fifo_full_hld_ctrl + I2C RX FIFO Full Hold Control - 0: False, 1: True + [9:9] + read-write + + + bus_clear_ctrl + I2C Bus Clear Control - 0: False, 1: True + [11:11] + read-write + + - priority_2 - PRIORITY Register for interrupt id 2 - 0x8 + tar + DesignWare I2C TAR + 0x4 + 32 + + + tar + tar + [31:0] + read-write + + - priority_3 - PRIORITY Register for interrupt id 3 - 0xC + sar + DesignWare I2C SAR + 0x8 + 32 + + + sar + sar + [31:0] + read-write + + - priority_4 - PRIORITY Register for interrupt id 4 + data_cmd + DesignWare I2C Data Command 0x10 + 32 + + + dat + Data Command Data Byte + [7:0] + read-write + + + first_data_byte + Data Command First Data Byte - 0: False, 1: True + [11:11] + read-write + + - priority_5 - PRIORITY Register for interrupt id 5 + ss_scl_hcnt + DesignWare I2C SS SCL HCNT 0x14 + 32 + + + ss_scl_hcnt + ss_scl_hcnt + [31:0] + read-write + + - priority_6 - PRIORITY Register for interrupt id 6 + ss_scl_lcnt + DesignWare I2C SS SCL LCNT 0x18 + 32 + + + ss_scl_lcnt + ss_scl_lcnt + [31:0] + read-write + + - priority_7 - PRIORITY Register for interrupt id 7 - 0x1C + fs_scl_hcnt + DesignWare I2C FS SCL HCNT + 0x1c + 32 + + + fs_scl_hcnt + fs_scl_hcnt + [31:0] + read-write + + - priority_8 - PRIORITY Register for interrupt id 8 + fs_scl_lcnt + DesignWare I2C FS SCL LCNT 0x20 + 32 + + + fs_scl_lcnt + fs_scl_lcnt + [31:0] + read-write + + - priority_9 - PRIORITY Register for interrupt id 9 + hs_scl_hcnt + DesignWare I2C HS SCL HCNT 0x24 + 32 + + + hs_scl_hcnt + hs_scl_hcnt + [31:0] + read-write + + - priority_10 - PRIORITY Register for interrupt id 10 + hs_scl_lcnt + DesignWare I2C HS SCL LCNT 0x28 + 32 + + + hs_scl_lcnt + hs_scl_lcnt + [31:0] + read-write + + - priority_11 - PRIORITY Register for interrupt id 11 - 0x2C - - - priority_12 - PRIORITY Register for interrupt id 12 - 0x30 - - - priority_13 - PRIORITY Register for interrupt id 13 - 0x34 - - - priority_14 - PRIORITY Register for interrupt id 14 - 0x38 - - - priority_15 - PRIORITY Register for interrupt id 15 - 0x3C - - - priority_16 - PRIORITY Register for interrupt id 16 - 0x40 - - - priority_17 - PRIORITY Register for interrupt id 17 - 0x44 - - - priority_18 - PRIORITY Register for interrupt id 18 - 0x48 - - - priority_19 - PRIORITY Register for interrupt id 19 - 0x4C - - - priority_20 - PRIORITY Register for interrupt id 20 - 0x50 - - - priority_21 - PRIORITY Register for interrupt id 21 - 0x54 - - - priority_22 - PRIORITY Register for interrupt id 22 - 0x58 - - - priority_23 - PRIORITY Register for interrupt id 23 - 0x5C - - - priority_24 - PRIORITY Register for interrupt id 24 - 0x60 - - - priority_25 - PRIORITY Register for interrupt id 25 - 0x64 - - - priority_26 - PRIORITY Register for interrupt id 26 - 0x68 - - - priority_27 - PRIORITY Register for interrupt id 27 - 0x6C - - - priority_28 - PRIORITY Register for interrupt id 28 - 0x70 - - - priority_29 - PRIORITY Register for interrupt id 29 - 0x74 - - - priority_30 - PRIORITY Register for interrupt id 30 - 0x78 - - - priority_31 - PRIORITY Register for interrupt id 31 - 0x7C - - - priority_32 - PRIORITY Register for interrupt id 32 - 0x80 - - - priority_33 - PRIORITY Register for interrupt id 33 - 0x84 - - - priority_34 - PRIORITY Register for interrupt id 34 - 0x88 - - - priority_35 - PRIORITY Register for interrupt id 35 - 0x8C - - - priority_36 - PRIORITY Register for interrupt id 36 - 0x90 - - - priority_37 - PRIORITY Register for interrupt id 37 - 0x94 - - - priority_38 - PRIORITY Register for interrupt id 38 - 0x98 - - - priority_39 - PRIORITY Register for interrupt id 39 - 0x9C - - - priority_40 - PRIORITY Register for interrupt id 40 - 0xA0 - - - priority_41 - PRIORITY Register for interrupt id 41 - 0xA4 - - - priority_42 - PRIORITY Register for interrupt id 42 - 0xA8 - - - priority_43 - PRIORITY Register for interrupt id 43 - 0xAC - - - priority_44 - PRIORITY Register for interrupt id 44 - 0xB0 - - - priority_45 - PRIORITY Register for interrupt id 45 - 0xB4 - - - priority_46 - PRIORITY Register for interrupt id 46 - 0xB8 - - - priority_47 - PRIORITY Register for interrupt id 47 - 0xBC - - - priority_48 - PRIORITY Register for interrupt id 48 - 0xC0 - - - priority_49 - PRIORITY Register for interrupt id 49 - 0xC4 - - - priority_50 - PRIORITY Register for interrupt id 50 - 0xC8 - - - priority_51 - PRIORITY Register for interrupt id 51 - 0xCC - - - priority_52 - PRIORITY Register for interrupt id 52 - 0xD0 - - - priority_53 - PRIORITY Register for interrupt id 53 - 0xD4 - - - priority_54 - PRIORITY Register for interrupt id 54 - 0xD8 - - - priority_55 - PRIORITY Register for interrupt id 55 - 0xDC - - - priority_56 - PRIORITY Register for interrupt id 56 - 0xE0 - - - priority_57 - PRIORITY Register for interrupt id 57 - 0xE4 - - - priority_58 - PRIORITY Register for interrupt id 58 - 0xE8 - - - priority_59 - PRIORITY Register for interrupt id 59 - 0xEC - - - priority_60 - PRIORITY Register for interrupt id 60 - 0xF0 - - - priority_61 - PRIORITY Register for interrupt id 61 - 0xF4 - - - priority_62 - PRIORITY Register for interrupt id 62 - 0xF8 - - - priority_63 - PRIORITY Register for interrupt id 63 - 0xFC - - - priority_64 - PRIORITY Register for interrupt id 64 - 0x100 - - - priority_65 - PRIORITY Register for interrupt id 65 - 0x104 - - - priority_66 - PRIORITY Register for interrupt id 66 - 0x108 - - - priority_67 - PRIORITY Register for interrupt id 67 - 0x10C - - - priority_68 - PRIORITY Register for interrupt id 68 - 0x110 - - - priority_69 - PRIORITY Register for interrupt id 69 - 0x114 - - - priority_70 - PRIORITY Register for interrupt id 70 - 0x118 - - - priority_71 - PRIORITY Register for interrupt id 71 - 0x11C - - - priority_72 - PRIORITY Register for interrupt id 72 - 0x120 - - - priority_73 - PRIORITY Register for interrupt id 73 - 0x124 - - - priority_74 - PRIORITY Register for interrupt id 74 - 0x128 - - - priority_75 - PRIORITY Register for interrupt id 75 - 0x12C - - - priority_76 - PRIORITY Register for interrupt id 76 - 0x130 - - - priority_77 - PRIORITY Register for interrupt id 77 - 0x134 - - - priority_78 - PRIORITY Register for interrupt id 78 - 0x138 - - - priority_79 - PRIORITY Register for interrupt id 79 - 0x13C - - - priority_80 - PRIORITY Register for interrupt id 80 - 0x140 - - - priority_81 - PRIORITY Register for interrupt id 81 - 0x144 - - - priority_82 - PRIORITY Register for interrupt id 82 - 0x148 - - - priority_83 - PRIORITY Register for interrupt id 83 - 0x14C - - - priority_84 - PRIORITY Register for interrupt id 84 - 0x150 - - - priority_85 - PRIORITY Register for interrupt id 85 - 0x154 - - - priority_86 - PRIORITY Register for interrupt id 86 - 0x158 - - - priority_87 - PRIORITY Register for interrupt id 87 - 0x15C - - - priority_88 - PRIORITY Register for interrupt id 88 - 0x160 - - - priority_89 - PRIORITY Register for interrupt id 89 - 0x164 - - - priority_90 - PRIORITY Register for interrupt id 90 - 0x168 - - - priority_91 - PRIORITY Register for interrupt id 91 - 0x16C - - - priority_92 - PRIORITY Register for interrupt id 92 - 0x170 - - - priority_93 - PRIORITY Register for interrupt id 93 - 0x174 - - - priority_94 - PRIORITY Register for interrupt id 94 - 0x178 - - - priority_95 - PRIORITY Register for interrupt id 95 - 0x17C - - - priority_96 - PRIORITY Register for interrupt id 96 - 0x180 - - - priority_97 - PRIORITY Register for interrupt id 97 - 0x184 - - - priority_98 - PRIORITY Register for interrupt id 98 - 0x188 - - - priority_99 - PRIORITY Register for interrupt id 99 - 0x18C - - - priority_100 - PRIORITY Register for interrupt id 100 - 0x190 - - - priority_101 - PRIORITY Register for interrupt id 101 - 0x194 - - - priority_102 - PRIORITY Register for interrupt id 102 - 0x198 - - - priority_103 - PRIORITY Register for interrupt id 103 - 0x19C - - - priority_104 - PRIORITY Register for interrupt id 104 - 0x1A0 - - - priority_105 - PRIORITY Register for interrupt id 105 - 0x1A4 - - - priority_106 - PRIORITY Register for interrupt id 106 - 0x1A8 - - - priority_107 - PRIORITY Register for interrupt id 107 - 0x1AC - - - priority_108 - PRIORITY Register for interrupt id 108 - 0x1B0 - - - priority_109 - PRIORITY Register for interrupt id 109 - 0x1B4 - - - priority_110 - PRIORITY Register for interrupt id 110 - 0x1B8 - - - priority_111 - PRIORITY Register for interrupt id 111 - 0x1BC - - - priority_112 - PRIORITY Register for interrupt id 112 - 0x1C0 - - - priority_113 - PRIORITY Register for interrupt id 113 - 0x1C4 - - - priority_114 - PRIORITY Register for interrupt id 114 - 0x1C8 + intr_stat + DesignWare I2C Interrupt Status + 0x2c + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + - priority_115 - PRIORITY Register for interrupt id 115 - 0x1CC + intr_mask + DesignWare I2C Interrupt Mask + 0x30 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] + read-write + + + tx_abrt + TX Abort + [6:6] + read-write + + + rx_done + RX Done + [7:7] + read-write + + + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + - priority_116 - PRIORITY Register for interrupt id 116 - 0x1D0 + raw_intr_stat + DesignWare I2C Raw Interrupt Status + 0x34 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + - priority_117 - PRIORITY Register for interrupt id 117 - 0x1D4 + rx_tl + DesignWare I2C RX TL + 0x38 + 32 + + + rx_tl + rx_tl + [31:0] + read-write + + - priority_118 - PRIORITY Register for interrupt id 118 - 0x1D8 + tx_tl + DesignWare I2C TX TL + 0x3c + 32 + + + tx_tl + tx_tl + [31:0] + read-write + + - priority_119 - PRIORITY Register for interrupt id 119 - 0x1DC + clr_intr + DesignWare I2C Clear Interrrupt + 0x40 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] + read-write + + + tx_abrt + TX Abort + [6:6] + read-write + + + rx_done + RX Done + [7:7] + read-write + + + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + - priority_120 - PRIORITY Register for interrupt id 120 - 0x1E0 + clr_rx_under + DesignWare I2C Clear RX Underrun + 0x44 + 32 + + + clr_rx_under + clr_rx_under + [31:0] + read-write + + - priority_121 - PRIORITY Register for interrupt id 121 - 0x1E4 + clr_rx_over + DesignWare I2C Clear RX Overrun + 0x48 + 32 + + + clr_rx_over + clr_rx_over + [31:0] + read-write + + - priority_122 - PRIORITY Register for interrupt id 122 - 0x1E8 + clr_tx_over + DesignWare I2C Clear TX Overrun + 0x4c + 32 + + + clr_tx_over + clr_tx_over + [31:0] + read-write + + - priority_123 - PRIORITY Register for interrupt id 123 - 0x1EC + clr_rd_req + DesignWare I2C Clear Read Request + 0x50 + 32 + + + clr_rd_req + clr_rd_req + [31:0] + read-write + + - priority_124 - PRIORITY Register for interrupt id 124 - 0x1F0 + clr_tx_abrt + DesignWare I2C Clear TX Abort + 0x54 + 32 + + + clr_tx_abrt + clr_tx_abrt + [31:0] + read-write + + - priority_125 - PRIORITY Register for interrupt id 125 - 0x1F4 + clr_rx_done + DesignWare I2C Clear RX Done + 0x58 + 32 + + + clr_rx_done + clr_rx_done + [31:0] + read-write + + - priority_126 - PRIORITY Register for interrupt id 126 - 0x1F8 + clr_activity + DesignWare I2C Clear Activity + 0x5c + 32 + + + clr_activity + clr_activity + [31:0] + read-write + + - priority_127 - PRIORITY Register for interrupt id 127 - 0x1FC + clr_stop_det + DesignWare I2C Clear Stop DET + 0x60 + 32 + + + clr_stop_det + clr_stop_det + [31:0] + read-write + + - priority_128 - PRIORITY Register for interrupt id 128 - 0x200 + clr_start_det + DesignWare I2C Clear Start DET + 0x64 + 32 + + + clr_start_det + clr_start_det + [31:0] + read-write + + - priority_129 - PRIORITY Register for interrupt id 129 - 0x204 + clr_gen_call + DesignWare I2C Clear General Call + 0x68 + 32 + + + clr_gen_call + clr_gen_call + [31:0] + read-write + + - priority_130 - PRIORITY Register for interrupt id 130 - 0x208 + enable + DesignWare I2C Enable + 0x6c + 32 + + + abort + abort + [1:1] + read-write + + - priority_131 - PRIORITY Register for interrupt id 131 - 0x20C + status + DesignWare I2C Status + 0x70 + 32 + + + activity + activity + [0:0] + read-only + + + tfe + tfe + [2:2] + read-only + + + rfne + rfne + [3:3] + read-only + + + master_activity + master_activity + [5:5] + read-only + + + slave_activity + slave_activity + [6:6] + read-only + + - priority_132 - PRIORITY Register for interrupt id 132 - 0x210 + txflr + DesignWare I2C TX Failure + 0x74 + 32 + + + txflr + txflr + [31:0] + read-write + + - priority_133 - PRIORITY Register for interrupt id 133 - 0x214 + rxflr + DesignWare I2C RX Failure + 0x78 + 32 + + + rxflr + rxflr + [31:0] + read-write + + - priority_134 - PRIORITY Register for interrupt id 134 - 0x218 + sda_hold + DesignWare I2C SDA Hold + 0x7c + 32 + + + sda_hold + sda_hold + [31:0] + read-write + + - priority_135 - PRIORITY Register for interrupt id 135 - 0x21C + tx_abrt_source + DesignWare I2C TX Abort Source + 0x80 + 32 + + + b7_addr_noack + b7_addr_noack + [0:0] + read-only + + + b10_addr1_noack + b10_addr1_noack + [1:1] + read-only + + + b10_addr2_noack + b10_addr2_noack + [2:2] + read-only + + + txdata_noack + txdata_noack + [3:3] + read-only + + + gcall_noack + gcall_noack + [4:4] + read-only + + + gcall_read + gcall_read + [5:5] + read-only + + + sbyte_ackdet + sbyte_ackdet + [7:7] + read-only + + + sbyte_norstrt + sbyte_norstrt + [9:9] + read-only + + + b10_rd_norstrt + b10_rd_norstrt + [10:10] + read-only + + + master_dis + master_dis + [11:11] + read-only + + + arb_lost + arb_lost + [12:12] + read-only + + + slave_flush_txfifo + slave_flush_txfifo + [13:13] + read-only + + + slave_arblost + slave_arblost + [14:14] + read-only + + + slave_rd_intx + slave_rd_intx + [15:15] + read-only + + - priority_136 - PRIORITY Register for interrupt id 136 - 0x220 + enable_status + DesignWare I2C Enable Status + 0x9c + 32 + + + activity + activity + [0:0] + read-write + + + tfe + tfe + [2:2] + read-write + + + rfne + rfne + [3:3] + read-write + + + master_activity + master_activity + [5:5] + read-write + + + slave_activity + slave_activity + [6:6] + read-write + + - pending_0 - PENDING Register for interrupt ids 31 to 0 - 0x1000 + clr_restart_det + DesignWare I2C Clear Restart DET + 0xa8 + 32 + + + clr_restart_det + clr_restart_det + [31:0] + read-write + + - pending_1 - PENDING Register for interrupt ids 63 to 32 - 0x1004 + comp_param_1 + DesignWare I2C Compatibility Parameter 1 + 0xf4 + 32 + + + speed + Speed mask - 01: Standard, 10: Full, 11: High + [3:2] + read-only + + - pending_2 - PENDING Register for interrupt ids 95 to 64 - 0x1008 + comp_version + DesignWare I2C Compatibility Version + 0xf8 + 32 + + + comp_version + comp_version + [31:0] + read-only + + - pending_3 - PENDING Register for interrupt ids 127 to 96 - 0x100C + comp_type + DesignWare I2C Compatibility Type + 0xfc + 32 + + + comp_type + comp_type + [31:0] + read-only + + + + + + snps_designware_i2c_1 + From snps,designware-i2c, peripheral generator + 0x10040000 + + 0 + 0x10000 + registers + + - pending_4 - PENDING Register for interrupt ids 136 to 128 - 0x1010 + con + DesignWare I2C CON + 0x0 + 32 + + + master + I2C Master Connection - 0: Slave, 1: Master + [0:0] + read-write + + + speed + I2C Speed - 01: Standard, 10: Fast, 11: High + [2:1] + read-write + + + slave_10bitaddr + I2C Slave 10-bit Address - 0: False, 1: True + [3:3] + read-write + + + master_10bitaddr + I2C Master 10-bit Address - 0: False, 1: True + [4:4] + read-write + + + restart_en + I2C Restart Enable - 0: False, 1: True + [5:5] + read-write + + + slave_disable + I2C Slave Disable - 0: False, 1: True + [6:6] + read-write + + + stop_det_ifaddressed + I2C Stop DET If Addressed - 0: False, 1: True + [7:7] + read-write + + + tx_empty_ctrl + I2C TX Empty Control - 0: False, 1: True + [8:8] + read-write + + + rx_fifo_full_hld_ctrl + I2C RX FIFO Full Hold Control - 0: False, 1: True + [9:9] + read-write + + + bus_clear_ctrl + I2C Bus Clear Control - 0: False, 1: True + [11:11] + read-write + + - enable_0_0 - ENABLE Register for interrupt ids 31 to 0 for hart 0 - 0x2000 + tar + DesignWare I2C TAR + 0x4 + 32 + + + tar + tar + [31:0] + read-write + + - enable_1_0 - ENABLE Register for interrupt ids 63 to 32 for hart 0 - 0x2004 + sar + DesignWare I2C SAR + 0x8 + 32 + + + sar + sar + [31:0] + read-write + + - enable_2_0 - ENABLE Register for interrupt ids 95 to 64 for hart 0 - 0x2008 + data_cmd + DesignWare I2C Data Command + 0x10 + 32 + + + dat + Data Command Data Byte + [7:0] + read-write + + + first_data_byte + Data Command First Data Byte - 0: False, 1: True + [11:11] + read-write + + - enable_3_0 - ENABLE Register for interrupt ids 127 to 96 for hart 0 - 0x200C + ss_scl_hcnt + DesignWare I2C SS SCL HCNT + 0x14 + 32 + + + ss_scl_hcnt + ss_scl_hcnt + [31:0] + read-write + + - enable_4_0 - ENABLE Register for interrupt ids 136 to 128 for hart 0 - 0x2010 + ss_scl_lcnt + DesignWare I2C SS SCL LCNT + 0x18 + 32 + + + ss_scl_lcnt + ss_scl_lcnt + [31:0] + read-write + + - enable_0_1 - ENABLE Register for interrupt ids 31 to 0 for hart 1 - 0x2080 + fs_scl_hcnt + DesignWare I2C FS SCL HCNT + 0x1c + 32 + + + fs_scl_hcnt + fs_scl_hcnt + [31:0] + read-write + + - enable_1_1 - ENABLE Register for interrupt ids 63 to 32 for hart 1 - 0x2084 + fs_scl_lcnt + DesignWare I2C FS SCL LCNT + 0x20 + 32 + + + fs_scl_lcnt + fs_scl_lcnt + [31:0] + read-write + + - enable_2_1 - ENABLE Register for interrupt ids 95 to 64 for hart 1 - 0x2088 + hs_scl_hcnt + DesignWare I2C HS SCL HCNT + 0x24 + 32 + + + hs_scl_hcnt + hs_scl_hcnt + [31:0] + read-write + + - enable_3_1 - ENABLE Register for interrupt ids 127 to 96 for hart 1 - 0x208C + hs_scl_lcnt + DesignWare I2C HS SCL LCNT + 0x28 + 32 + + + hs_scl_lcnt + hs_scl_lcnt + [31:0] + read-write + + - enable_4_1 - ENABLE Register for interrupt ids 136 to 128 for hart 1 - 0x2090 + intr_stat + DesignWare I2C Interrupt Status + 0x2c + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + - enable_0_2 - ENABLE Register for interrupt ids 31 to 0 for hart 2 - 0x2100 + intr_mask + DesignWare I2C Interrupt Mask + 0x30 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] + read-write + + + tx_abrt + TX Abort + [6:6] + read-write + + + rx_done + RX Done + [7:7] + read-write + + + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + - enable_1_2 - ENABLE Register for interrupt ids 63 to 32 for hart 2 - 0x2104 + raw_intr_stat + DesignWare I2C Raw Interrupt Status + 0x34 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + - enable_2_2 - ENABLE Register for interrupt ids 95 to 64 for hart 2 - 0x2108 + rx_tl + DesignWare I2C RX TL + 0x38 + 32 + + + rx_tl + rx_tl + [31:0] + read-write + + - enable_3_2 - ENABLE Register for interrupt ids 127 to 96 for hart 2 - 0x210C + tx_tl + DesignWare I2C TX TL + 0x3c + 32 + + + tx_tl + tx_tl + [31:0] + read-write + + - enable_4_2 - ENABLE Register for interrupt ids 136 to 128 for hart 2 - 0x2110 + clr_intr + DesignWare I2C Clear Interrrupt + 0x40 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] + read-write + + + tx_abrt + TX Abort + [6:6] + read-write + + + rx_done + RX Done + [7:7] + read-write + + + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + - enable_0_3 - ENABLE Register for interrupt ids 31 to 0 for hart 3 - 0x2180 + clr_rx_under + DesignWare I2C Clear RX Underrun + 0x44 + 32 + + + clr_rx_under + clr_rx_under + [31:0] + read-write + + - enable_1_3 - ENABLE Register for interrupt ids 63 to 32 for hart 3 - 0x2184 + clr_rx_over + DesignWare I2C Clear RX Overrun + 0x48 + 32 + + + clr_rx_over + clr_rx_over + [31:0] + read-write + + - enable_2_3 - ENABLE Register for interrupt ids 95 to 64 for hart 3 - 0x2188 + clr_tx_over + DesignWare I2C Clear TX Overrun + 0x4c + 32 + + + clr_tx_over + clr_tx_over + [31:0] + read-write + + - enable_3_3 - ENABLE Register for interrupt ids 127 to 96 for hart 3 - 0x218C + clr_rd_req + DesignWare I2C Clear Read Request + 0x50 + 32 + + + clr_rd_req + clr_rd_req + [31:0] + read-write + + - enable_4_3 - ENABLE Register for interrupt ids 136 to 128 for hart 3 - 0x2190 + clr_tx_abrt + DesignWare I2C Clear TX Abort + 0x54 + 32 + + + clr_tx_abrt + clr_tx_abrt + [31:0] + read-write + + - enable_0_4 - ENABLE Register for interrupt ids 31 to 0 for hart 4 - 0x2200 + clr_rx_done + DesignWare I2C Clear RX Done + 0x58 + 32 + + + clr_rx_done + clr_rx_done + [31:0] + read-write + + - enable_1_4 - ENABLE Register for interrupt ids 63 to 32 for hart 4 - 0x2204 + clr_activity + DesignWare I2C Clear Activity + 0x5c + 32 + + + clr_activity + clr_activity + [31:0] + read-write + + - enable_2_4 - ENABLE Register for interrupt ids 95 to 64 for hart 4 - 0x2208 + clr_stop_det + DesignWare I2C Clear Stop DET + 0x60 + 32 + + + clr_stop_det + clr_stop_det + [31:0] + read-write + + - enable_3_4 - ENABLE Register for interrupt ids 127 to 96 for hart 4 - 0x220C + clr_start_det + DesignWare I2C Clear Start DET + 0x64 + 32 + + + clr_start_det + clr_start_det + [31:0] + read-write + + - enable_4_4 - ENABLE Register for interrupt ids 136 to 128 for hart 4 - 0x2210 + clr_gen_call + DesignWare I2C Clear General Call + 0x68 + 32 + + + clr_gen_call + clr_gen_call + [31:0] + read-write + + - threshold_0 - PRIORITY THRESHOLD Register for hart 0 - 0x200000 + enable + DesignWare I2C Enable + 0x6c + 32 + + + abort + abort + [1:1] + read-write + + - claimplete_0 - CLAIM and COMPLETE Register for hart 0 - 0x200004 + status + DesignWare I2C Status + 0x70 + 32 + + + activity + activity + [0:0] + read-only + + + tfe + tfe + [2:2] + read-only + + + rfne + rfne + [3:3] + read-only + + + master_activity + master_activity + [5:5] + read-only + + + slave_activity + slave_activity + [6:6] + read-only + + - threshold_1 - PRIORITY THRESHOLD Register for hart 1 - 0x201000 + txflr + DesignWare I2C TX Failure + 0x74 + 32 + + + txflr + txflr + [31:0] + read-write + + - claimplete_1 - CLAIM and COMPLETE Register for hart 1 - 0x201004 + rxflr + DesignWare I2C RX Failure + 0x78 + 32 + + + rxflr + rxflr + [31:0] + read-write + + - threshold_2 - PRIORITY THRESHOLD Register for hart 2 - 0x202000 + sda_hold + DesignWare I2C SDA Hold + 0x7c + 32 + + + sda_hold + sda_hold + [31:0] + read-write + + - claimplete_2 - CLAIM and COMPLETE Register for hart 2 - 0x202004 + tx_abrt_source + DesignWare I2C TX Abort Source + 0x80 + 32 + + + b7_addr_noack + b7_addr_noack + [0:0] + read-only + + + b10_addr1_noack + b10_addr1_noack + [1:1] + read-only + + + b10_addr2_noack + b10_addr2_noack + [2:2] + read-only + + + txdata_noack + txdata_noack + [3:3] + read-only + + + gcall_noack + gcall_noack + [4:4] + read-only + + + gcall_read + gcall_read + [5:5] + read-only + + + sbyte_ackdet + sbyte_ackdet + [7:7] + read-only + + + sbyte_norstrt + sbyte_norstrt + [9:9] + read-only + + + b10_rd_norstrt + b10_rd_norstrt + [10:10] + read-only + + + master_dis + master_dis + [11:11] + read-only + + + arb_lost + arb_lost + [12:12] + read-only + + + slave_flush_txfifo + slave_flush_txfifo + [13:13] + read-only + + + slave_arblost + slave_arblost + [14:14] + read-only + + + slave_rd_intx + slave_rd_intx + [15:15] + read-only + + - threshold_3 - PRIORITY THRESHOLD Register for hart 3 - 0x203000 + enable_status + DesignWare I2C Enable Status + 0x9c + 32 + + + activity + activity + [0:0] + read-write + + + tfe + tfe + [2:2] + read-write + + + rfne + rfne + [3:3] + read-write + + + master_activity + master_activity + [5:5] + read-write + + + slave_activity + slave_activity + [6:6] + read-write + + - claimplete_3 - CLAIM and COMPLETE Register for hart 3 - 0x203004 + clr_restart_det + DesignWare I2C Clear Restart DET + 0xa8 + 32 + + + clr_restart_det + clr_restart_det + [31:0] + read-write + + - threshold_4 - PRIORITY THRESHOLD Register for hart 4 - 0x204000 + comp_param_1 + DesignWare I2C Compatibility Parameter 1 + 0xf4 + 32 + + + speed + Speed mask - 01: Standard, 10: Full, 11: High + [3:2] + read-only + + - claimplete_4 - CLAIM and COMPLETE Register for hart 4 - 0x204004 - - - - - starfive_jh7110_ccache_0 - From starfive,jh7110-ccache, peripheral generator - 0x2010000 - - 0 - 0x4000 - registers - - - - sifive_ccache0_0 - From sifive,ccache0, peripheral generator - 0x2010000 - - 0 - 0x4000 - registers - - - - cache_0 - From cache, peripheral generator - 0x2010000 - - 0 - 0x4000 - registers - - - - snps_dw_apb_uart_0 - From snps,dw-apb-uart, peripheral generator - 0x10000000 - - 0 - 0x10000 - registers - - - - snps_dw_apb_uart_1 - From snps,dw-apb-uart, peripheral generator - 0x10010000 - - 0 - 0x10000 - registers - - - - snps_dw_apb_uart_2 - From snps,dw-apb-uart, peripheral generator - 0x10020000 - - 0 - 0x10000 - registers - + comp_version + DesignWare I2C Compatibility Version + 0xf8 + 32 + + + comp_version + comp_version + [31:0] + read-only + + + + + comp_type + DesignWare I2C Compatibility Type + 0xfc + 32 + + + comp_type + comp_type + [31:0] + read-only + + + + - snps_designware_i2c_0 + snps_designware_i2c_2 From snps,designware-i2c, peripheral generator - 0x10030000 + 0x10050000 0 0x10000 @@ -1166,107 +2340,291 @@ 32 - dat - Data Command Data Byte - [7:0] + dat + Data Command Data Byte + [7:0] + read-write + + + first_data_byte + Data Command First Data Byte - 0: False, 1: True + [11:11] + read-write + + + + + ss_scl_hcnt + DesignWare I2C SS SCL HCNT + 0x14 + 32 + + + ss_scl_hcnt + ss_scl_hcnt + [31:0] + read-write + + + + + ss_scl_lcnt + DesignWare I2C SS SCL LCNT + 0x18 + 32 + + + ss_scl_lcnt + ss_scl_lcnt + [31:0] + read-write + + + + + fs_scl_hcnt + DesignWare I2C FS SCL HCNT + 0x1c + 32 + + + fs_scl_hcnt + fs_scl_hcnt + [31:0] + read-write + + + + + fs_scl_lcnt + DesignWare I2C FS SCL LCNT + 0x20 + 32 + + + fs_scl_lcnt + fs_scl_lcnt + [31:0] + read-write + + + + + hs_scl_hcnt + DesignWare I2C HS SCL HCNT + 0x24 + 32 + + + hs_scl_hcnt + hs_scl_hcnt + [31:0] + read-write + + + + + hs_scl_lcnt + DesignWare I2C HS SCL LCNT + 0x28 + 32 + + + hs_scl_lcnt + hs_scl_lcnt + [31:0] + read-write + + + + + intr_stat + DesignWare I2C Interrupt Status + 0x2c + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + + + + intr_mask + DesignWare I2C Interrupt Mask + 0x30 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] read-write - first_data_byte - Data Command First Data Byte - 0: False, 1: True - [11:11] + tx_abrt + TX Abort + [6:6] read-write - - - - ss_scl_hcnt - DesignWare I2C SS SCL HCNT - 0x14 - 32 - - ss_scl_hcnt - ss_scl_hcnt - [31:0] + rx_done + RX Done + [7:7] read-write - - - - ss_scl_lcnt - DesignWare I2C SS SCL LCNT - 0x18 - 32 - - ss_scl_lcnt - ss_scl_lcnt - [31:0] + activity + Activity + [8:8] read-write - - - - fs_scl_hcnt - DesignWare I2C FS SCL HCNT - 0x1c - 32 - - fs_scl_hcnt - fs_scl_hcnt - [31:0] + stop_det + Stop DET + [9:9] read-write - - - - fs_scl_lcnt - DesignWare I2C FS SCL LCNT - 0x20 - 32 - - fs_scl_lcnt - fs_scl_lcnt - [31:0] + start_det + Start DET + [10:10] read-write - - - - hs_scl_hcnt - DesignWare I2C HS SCL HCNT - 0x24 - 32 - - hs_scl_hcnt - hs_scl_hcnt - [31:0] + gen_call + General Call + [11:11] read-write - - - - hs_scl_lcnt - DesignWare I2C HS SCL LCNT - 0x28 - 32 - - hs_scl_lcnt - hs_scl_lcnt - [31:0] + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] read-write - intr_stat - DesignWare I2C Interrupt Status - 0x2c + raw_intr_stat + DesignWare I2C Raw Interrupt Status + 0x34 32 @@ -1356,9 +2714,37 @@ - intr_mask - DesignWare I2C Interrupt Mask - 0x30 + rx_tl + DesignWare I2C RX TL + 0x38 + 32 + + + rx_tl + rx_tl + [31:0] + read-write + + + + + tx_tl + DesignWare I2C TX TL + 0x3c + 32 + + + tx_tl + tx_tl + [31:0] + read-write + + + + + clr_intr + DesignWare I2C Clear Interrrupt + 0x40 32 @@ -1416,8039 +2802,9131 @@ read-write - stop_det - Stop DET - [9:9] + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + + + + clr_rx_under + DesignWare I2C Clear RX Underrun + 0x44 + 32 + + + clr_rx_under + clr_rx_under + [31:0] + read-write + + + + + clr_rx_over + DesignWare I2C Clear RX Overrun + 0x48 + 32 + + + clr_rx_over + clr_rx_over + [31:0] + read-write + + + + + clr_tx_over + DesignWare I2C Clear TX Overrun + 0x4c + 32 + + + clr_tx_over + clr_tx_over + [31:0] + read-write + + + + + clr_rd_req + DesignWare I2C Clear Read Request + 0x50 + 32 + + + clr_rd_req + clr_rd_req + [31:0] + read-write + + + + + clr_tx_abrt + DesignWare I2C Clear TX Abort + 0x54 + 32 + + + clr_tx_abrt + clr_tx_abrt + [31:0] + read-write + + + + + clr_rx_done + DesignWare I2C Clear RX Done + 0x58 + 32 + + + clr_rx_done + clr_rx_done + [31:0] + read-write + + + + + clr_activity + DesignWare I2C Clear Activity + 0x5c + 32 + + + clr_activity + clr_activity + [31:0] read-write + + + + clr_stop_det + DesignWare I2C Clear Stop DET + 0x60 + 32 + - start_det - Start DET - [10:10] + clr_stop_det + clr_stop_det + [31:0] read-write + + + + clr_start_det + DesignWare I2C Clear Start DET + 0x64 + 32 + - gen_call - General Call - [11:11] + clr_start_det + clr_start_det + [31:0] read-write + + + + clr_gen_call + DesignWare I2C Clear General Call + 0x68 + 32 + - restart_det - Restart DET - [12:12] + clr_gen_call + clr_gen_call + [31:0] read-write + + + + enable + DesignWare I2C Enable + 0x6c + 32 + - mst_on_hold - Master on Hold - [13:13] + abort + abort + [1:1] read-write - raw_intr_stat - DesignWare I2C Raw Interrupt Status - 0x34 + status + DesignWare I2C Status + 0x70 32 - rx_under - RX FIFO Underrun + activity + activity [0:0] read-only - rx_over - RX FIFO Overrun - [1:1] - read-only - - - rx_full - RX FIFO Full + tfe + tfe [2:2] read-only - tx_over - TX FIFO Overrun + rfne + rfne [3:3] read-only - tx_empty - TX FIFO Empty - [4:4] - read-only - - - rd_req - Read Request + master_activity + master_activity [5:5] read-only - tx_abrt - TX Abort + slave_activity + slave_activity [6:6] read-only + + + + txflr + DesignWare I2C TX Failure + 0x74 + 32 + - rx_done - RX Done - [7:7] - read-only - - - activity - Activity - [8:8] - read-only - - - stop_det - Stop DET - [9:9] - read-only - - - start_det - Start DET - [10:10] - read-only - - - gen_call - General Call - [11:11] - read-only - - - restart_det - Restart DET - [12:12] - read-only - - - mst_on_hold - Master on Hold - [13:13] - read-only + txflr + txflr + [31:0] + read-write - rx_tl - DesignWare I2C RX TL - 0x38 + rxflr + DesignWare I2C RX Failure + 0x78 32 - rx_tl - rx_tl + rxflr + rxflr [31:0] read-write - tx_tl - DesignWare I2C TX TL - 0x3c + sda_hold + DesignWare I2C SDA Hold + 0x7c 32 - tx_tl - tx_tl + sda_hold + sda_hold [31:0] read-write - clr_intr - DesignWare I2C Clear Interrrupt - 0x40 + tx_abrt_source + DesignWare I2C TX Abort Source + 0x80 32 - rx_under - RX FIFO Underrun + b7_addr_noack + b7_addr_noack [0:0] - read-write + read-only - rx_over - RX FIFO Overrun + b10_addr1_noack + b10_addr1_noack [1:1] - read-write + read-only - rx_full - RX FIFO Full + b10_addr2_noack + b10_addr2_noack [2:2] - read-write + read-only - tx_over - TX FIFO Overrun + txdata_noack + txdata_noack [3:3] - read-write + read-only - tx_empty - TX FIFO Empty + gcall_noack + gcall_noack [4:4] - read-write + read-only - rd_req - Read Request + gcall_read + gcall_read [5:5] - read-write + read-only + + + sbyte_ackdet + sbyte_ackdet + [7:7] + read-only + + + sbyte_norstrt + sbyte_norstrt + [9:9] + read-only + + + b10_rd_norstrt + b10_rd_norstrt + [10:10] + read-only + + + master_dis + master_dis + [11:11] + read-only + + + arb_lost + arb_lost + [12:12] + read-only + + + slave_flush_txfifo + slave_flush_txfifo + [13:13] + read-only - tx_abrt - TX Abort - [6:6] - read-write + slave_arblost + slave_arblost + [14:14] + read-only - rx_done - RX Done - [7:7] - read-write + slave_rd_intx + slave_rd_intx + [15:15] + read-only + + + + enable_status + DesignWare I2C Enable Status + 0x9c + 32 + activity - Activity - [8:8] - read-write - - - stop_det - Stop DET - [9:9] + activity + [0:0] read-write - start_det - Start DET - [10:10] + tfe + tfe + [2:2] read-write - gen_call - General Call - [11:11] + rfne + rfne + [3:3] read-write - restart_det - Restart DET - [12:12] + master_activity + master_activity + [5:5] read-write - mst_on_hold - Master on Hold - [13:13] + slave_activity + slave_activity + [6:6] read-write - clr_rx_under - DesignWare I2C Clear RX Underrun - 0x44 + clr_restart_det + DesignWare I2C Clear Restart DET + 0xa8 32 - clr_rx_under - clr_rx_under + clr_restart_det + clr_restart_det [31:0] read-write - clr_rx_over - DesignWare I2C Clear RX Overrun - 0x48 + comp_param_1 + DesignWare I2C Compatibility Parameter 1 + 0xf4 32 - clr_rx_over - clr_rx_over - [31:0] - read-write + speed + Speed mask - 01: Standard, 10: Full, 11: High + [3:2] + read-only - clr_tx_over - DesignWare I2C Clear TX Overrun - 0x4c + comp_version + DesignWare I2C Compatibility Version + 0xf8 32 - clr_tx_over - clr_tx_over + comp_version + comp_version [31:0] - read-write + read-only - clr_rd_req - DesignWare I2C Clear Read Request - 0x50 + comp_type + DesignWare I2C Compatibility Type + 0xfc 32 - clr_rd_req - clr_rd_req + comp_type + comp_type [31:0] - read-write + read-only + + + + arm_pl022_0 + From arm,pl022, peripheral generator + 0x10060000 + + 0 + 0x10000 + registers + + - clr_tx_abrt - DesignWare I2C Clear TX Abort - 0x54 - 32 + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. + 0x0 + 16 - clr_tx_abrt - clr_tx_abrt - [31:0] + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] + read-write + + + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] + read-write + + + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] read-write - clr_rx_done - DesignWare I2C Clear RX Done - 0x58 - 32 + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. + 0x4 + 16 - clr_rx_done - clr_rx_done - [31:0] + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally + [0:0] + read-write + + + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled + [1:1] + read-write + + + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave + [2:2] + read-write + + + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode + [3:3] read-write - clr_activity - DesignWare I2C Clear Activity - 0x5c - 32 + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 - clr_activity - clr_activity - [31:0] + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] read-write - clr_stop_det - DesignWare I2C Clear Stop DET - 0x60 - 32 + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 - clr_stop_det - clr_stop_det - [31:0] - read-write + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. + [0:0] + read-only + + + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. + [1:1] + read-only + + + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. + [2:2] + read-only + + + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. + [3:3] + read-only + + + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only - clr_start_det - DesignWare I2C Clear Start DET - 0x64 - 32 + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 - clr_start_det - clr_start_det - [31:0] + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] read-write - clr_gen_call - DesignWare I2C Clear General Call - 0x68 - 32 + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 - clr_gen_call - clr_gen_call - [31:0] + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked + [0:0] + read-write + + + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked + [1:1] + read-write + + + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked + [2:2] + read-write + + + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] read-write - enable - DesignWare I2C Enable - 0x6c - 32 + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 - abort - abort + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] - read-write + read-only + + + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only - status - DesignWare I2C Status - 0x70 - 32 + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 - activity - activity + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only - tfe - tfe - [2:2] - read-only - - - rfne - rfne - [3:3] + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] read-only - master_activity - master_activity - [5:5] + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] read-only - slave_activity - slave_activity - [6:6] + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] read-only - txflr - DesignWare I2C TX Failure - 0x74 - 32 + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 - txflr - txflr - [31:0] + roric + Clears the SSPRORINTR interrupt + [0:0] + read-write + + + rtic + Clears the SSPRTINTR interrupt + [1:1] read-write - rxflr - DesignWare I2C RX Failure - 0x78 - 32 + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 - rxflr - rxflr - [31:0] + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] read-write - sda_hold - DesignWare I2C SDA Hold - 0x7c - 32 + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 - sda_hold - sda_hold - [31:0] - read-write + part_number0 + These bits read back as 0x22 + [7:0] + read-only - tx_abrt_source - DesignWare I2C TX Abort Source - 0x80 - 32 + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 - b7_addr_noack - b7_addr_noack - [0:0] + part_number1 + These bits read back as 0x0 + [3:0] read-only - b10_addr1_noack - b10_addr1_noack - [1:1] + designer0 + These bits read back as 0x1 + [7:4] read-only + + + + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 + - b10_addr2_noack - b10_addr2_noack - [2:2] + designer1 + These bits read back as 0x4 + [3:0] read-only - txdata_noack - txdata_noack - [3:3] + revision + These bits return the peripheral revision + [7:4] read-only + + + + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 + - gcall_noack - gcall_noack - [4:4] + configuration + These bits read back as 0x80 + [7:0] read-only + + + + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 + - gcall_read - gcall_read - [5:5] + ssp_pcell_id0 + The bits are read as 0xD + [7:0] read-only + + + + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 + - sbyte_ackdet - sbyte_ackdet - [7:7] + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] read-only + + + + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 + - sbyte_norstrt - sbyte_norstrt - [9:9] + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] read-only + + + + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 + - b10_rd_norstrt - b10_rd_norstrt - [10:10] + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] read-only + + + + + + arm_primecell_0 + From arm,primecell, peripheral generator + 0x10060000 + + 0 + 0x10000 + registers + + + + rohm_dh2228fv_0 + From rohm,dh2228fv, peripheral generator + 0x0 + + 0 + 0x0 + registers + + + + arm_pl022_1 + From arm,pl022, peripheral generator + 0x10070000 + + 0 + 0x10000 + registers + + + + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. + 0x0 + 16 + - master_dis - master_dis - [11:11] - read-only + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] + read-write - arb_lost - arb_lost - [12:12] - read-only + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] + read-write - slave_flush_txfifo - slave_flush_txfifo - [13:13] - read-only + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. + [6:6] + read-write - slave_arblost - slave_arblost - [14:14] - read-only + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] + read-write - slave_rd_intx - slave_rd_intx - [15:15] - read-only + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] + read-write - enable_status - DesignWare I2C Enable Status - 0x9c - 32 + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. + 0x4 + 16 - activity - activity + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally [0:0] read-write - tfe - tfe + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled + [1:1] + read-write + + + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave [2:2] read-write - rfne - rfne + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write + + + + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 + - master_activity - master_activity - [5:5] + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] read-write + + + + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 + - slave_activity - slave_activity - [6:6] - read-write + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. + [0:0] + read-only + + + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. + [1:1] + read-only + + + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. + [2:2] + read-only + + + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. + [3:3] + read-only + + + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only - clr_restart_det - DesignWare I2C Clear Restart DET - 0xa8 - 32 + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 - clr_restart_det - clr_restart_det - [31:0] + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] read-write - comp_param_1 - DesignWare I2C Compatibility Parameter 1 - 0xf4 - 32 + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 - speed - Speed mask - 01: Standard, 10: Full, 11: High - [3:2] - read-only + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked + [0:0] + read-write + + + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked + [1:1] + read-write + + + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked + [2:2] + read-write + + + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] + read-write - comp_version - DesignWare I2C Compatibility Version - 0xf8 - 32 + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 - comp_version - comp_version - [31:0] + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] read-only - - - - comp_type - DesignWare I2C Compatibility Type - 0xfc - 32 - - comp_type - comp_type - [31:0] + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] read-only - - - - snps_designware_i2c_1 - From snps,designware-i2c, peripheral generator - 0x10040000 - - 0 - 0x10000 - registers - - - con - DesignWare I2C CON - 0x0 - 32 + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 - master - I2C Master Connection - 0: Slave, 1: Master + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] - read-write + read-only - speed - I2C Speed - 01: Standard, 10: Fast, 11: High - [2:1] - read-write + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only - slave_10bitaddr - I2C Slave 10-bit Address - 0: False, 1: True + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] - read-write + read-only + + + + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 + - master_10bitaddr - I2C Master 10-bit Address - 0: False, 1: True - [4:4] + roric + Clears the SSPRORINTR interrupt + [0:0] read-write - restart_en - I2C Restart Enable - 0: False, 1: True - [5:5] + rtic + Clears the SSPRTINTR interrupt + [1:1] read-write + + + + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 + - slave_disable - I2C Slave Disable - 0: False, 1: True - [6:6] + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] read-write - stop_det_ifaddressed - I2C Stop DET If Addressed - 0: False, 1: True - [7:7] + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] read-write + + + + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 + - tx_empty_ctrl - I2C TX Empty Control - 0: False, 1: True - [8:8] - read-write + part_number0 + These bits read back as 0x22 + [7:0] + read-only + + + + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 + - rx_fifo_full_hld_ctrl - I2C RX FIFO Full Hold Control - 0: False, 1: True - [9:9] - read-write + part_number1 + These bits read back as 0x0 + [3:0] + read-only - bus_clear_ctrl - I2C Bus Clear Control - 0: False, 1: True - [11:11] - read-write + designer0 + These bits read back as 0x1 + [7:4] + read-only - tar - DesignWare I2C TAR - 0x4 - 32 + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 - tar - tar - [31:0] - read-write + designer1 + These bits read back as 0x4 + [3:0] + read-only + + + revision + These bits return the peripheral revision + [7:4] + read-only - sar - DesignWare I2C SAR - 0x8 - 32 + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 - sar - sar - [31:0] - read-write + configuration + These bits read back as 0x80 + [7:0] + read-only - data_cmd - DesignWare I2C Data Command - 0x10 - 32 + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 - dat - Data Command Data Byte + ssp_pcell_id0 + The bits are read as 0xD [7:0] - read-write - - - first_data_byte - Data Command First Data Byte - 0: False, 1: True - [11:11] - read-write + read-only - ss_scl_hcnt - DesignWare I2C SS SCL HCNT - 0x14 - 32 + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 - ss_scl_hcnt - ss_scl_hcnt - [31:0] - read-write + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] + read-only - ss_scl_lcnt - DesignWare I2C SS SCL LCNT - 0x18 - 32 + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 - ss_scl_lcnt - ss_scl_lcnt - [31:0] - read-write + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] + read-only - fs_scl_hcnt - DesignWare I2C FS SCL HCNT - 0x1c - 32 + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 - fs_scl_hcnt - fs_scl_hcnt - [31:0] - read-write + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] + read-only + + + + arm_primecell_1 + From arm,primecell, peripheral generator + 0x10070000 + + 0 + 0x10000 + registers + + + + arm_pl022_2 + From arm,pl022, peripheral generator + 0x10080000 + + 0 + 0x10000 + registers + + - fs_scl_lcnt - DesignWare I2C FS SCL LCNT - 0x20 - 32 + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. + 0x0 + 16 - fs_scl_lcnt - fs_scl_lcnt - [31:0] + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] + read-write + + + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] + read-write + + + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] + read-write + + + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] read-write - hs_scl_hcnt - DesignWare I2C HS SCL HCNT - 0x24 - 32 + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. + 0x4 + 16 - hs_scl_hcnt - hs_scl_hcnt - [31:0] + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally + [0:0] + read-write + + + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled + [1:1] + read-write + + + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave + [2:2] + read-write + + + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode + [3:3] read-write - hs_scl_lcnt - DesignWare I2C HS SCL LCNT - 0x28 - 32 + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 - hs_scl_lcnt - hs_scl_lcnt - [31:0] + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] read-write - intr_stat - DesignWare I2C Interrupt Status - 0x2c - 32 + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 - rx_under - RX FIFO Underrun + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. [0:0] read-only - rx_over - RX FIFO Overrun + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. [1:1] read-only - rx_full - RX FIFO Full + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. [2:2] read-only - tx_over - TX FIFO Overrun + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. [3:3] read-only - tx_empty - TX FIFO Empty + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [4:4] read-only + + + + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 + - rd_req - Read Request - [5:5] - read-only + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] + read-write + + + + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 + - tx_abrt - TX Abort - [6:6] - read-only + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked + [0:0] + read-write - rx_done - RX Done - [7:7] - read-only + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked + [1:1] + read-write - activity - Activity - [8:8] - read-only + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked + [2:2] + read-write - stop_det - Stop DET - [9:9] - read-only + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] + read-write + + + + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 + - start_det - Start DET - [10:10] + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] read-only - gen_call - General Call - [11:11] + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] read-only - restart_det - Restart DET - [12:12] + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] read-only - mst_on_hold - Master on Hold - [13:13] + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] read-only - intr_mask - DesignWare I2C Interrupt Mask - 0x30 - 32 + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 - rx_under - RX FIFO Underrun + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] - read-write + read-only - rx_over - RX FIFO Overrun + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] - read-write + read-only - rx_full - RX FIFO Full + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] - read-write + read-only - tx_over - TX FIFO Overrun + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] - read-write - - - tx_empty - TX FIFO Empty - [4:4] - read-write - - - rd_req - Read Request - [5:5] - read-write - - - tx_abrt - TX Abort - [6:6] - read-write - - - rx_done - RX Done - [7:7] - read-write - - - activity - Activity - [8:8] - read-write - - - stop_det - Stop DET - [9:9] - read-write - - - start_det - Start DET - [10:10] - read-write - - - gen_call - General Call - [11:11] - read-write + read-only + + + + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 + - restart_det - Restart DET - [12:12] + roric + Clears the SSPRORINTR interrupt + [0:0] read-write - mst_on_hold - Master on Hold - [13:13] + rtic + Clears the SSPRTINTR interrupt + [1:1] read-write - raw_intr_stat - DesignWare I2C Raw Interrupt Status - 0x34 - 32 + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 - rx_under - RX FIFO Underrun + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] - read-only + read-write - rx_over - RX FIFO Overrun + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] - read-only + read-write + + + + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 + - rx_full - RX FIFO Full - [2:2] + part_number0 + These bits read back as 0x22 + [7:0] read-only + + + + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 + - tx_over - TX FIFO Overrun - [3:3] + part_number1 + These bits read back as 0x0 + [3:0] read-only - tx_empty - TX FIFO Empty - [4:4] + designer0 + These bits read back as 0x1 + [7:4] read-only + + + + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 + - rd_req - Read Request - [5:5] + designer1 + These bits read back as 0x4 + [3:0] read-only - tx_abrt - TX Abort - [6:6] + revision + These bits return the peripheral revision + [7:4] read-only + + + + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 + - rx_done - RX Done - [7:7] + configuration + These bits read back as 0x80 + [7:0] read-only + + + + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 + - activity - Activity - [8:8] + ssp_pcell_id0 + The bits are read as 0xD + [7:0] read-only + + + + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 + - stop_det - Stop DET - [9:9] + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] read-only + + + + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 + - start_det - Start DET - [10:10] + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] read-only + + + + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 + - gen_call - General Call - [11:11] + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] read-only + + + + + + arm_primecell_2 + From arm,primecell, peripheral generator + 0x10080000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_tdm_0 + From starfive,jh7110-tdm, peripheral generator + 0x10090000 + + 0 + 0x1000 + registers + + + + starfive_jh7110_usb_phy_0 + From starfive,jh7110-usb-phy, peripheral generator + 0x10200000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_pcie_phy_0 + From starfive,jh7110-pcie-phy, peripheral generator + 0x10210000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_pcie_phy_1 + From starfive,jh7110-pcie-phy, peripheral generator + 0x10220000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_stgcrg_0 + From starfive,jh7110-stgcrg, peripheral generator + 0x10230000 + + 0 + 0x10000 + registers + + + + clk_hifi4_core + Clock HIFI4 Core + 0x0 + 32 + - restart_det - Restart DET - [12:12] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + + clk_usb_apb + Clock USB APB + 0x4 + 32 + - mst_on_hold - Master on Hold - [13:13] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write - rx_tl - DesignWare I2C RX TL - 0x38 + clk_usb_utmi_apb + Clock USB UTMI APB + 0x8 32 - rx_tl - rx_tl - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - tx_tl - DesignWare I2C TX TL - 0x3c + clk_usb_axi + Clock USB AXI + 0xc 32 - tx_tl - tx_tl - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_intr - DesignWare I2C Clear Interrrupt - 0x40 + clk_usb_ipm + Clock USB AXI + 0x10 32 - rx_under - RX FIFO Underrun - [0:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - rx_over - RX FIFO Overrun - [1:1] + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] read-write + + + + clk_usb_stb + Clock USB STB + 0x14 + 32 + - rx_full - RX FIFO Full - [2:2] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - tx_over - TX FIFO Overrun - [3:3] + clk_divcfg + Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 + [23:0] read-write + + + + clk_usb_app125 + Clock USB APP 125 + 0x18 + 32 + - tx_empty - TX FIFO Empty - [4:4] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_usb_refclk + Clock USB Reference Clock + 0x1c + 32 + - rd_req - Read Request - [5:5] + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] read-write + + + + clk_u0_pcie_axi_mst0 + U0 Clock PCIe AXI MST 0 + 0x20 + 32 + - tx_abrt - TX Abort - [6:6] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u0_pcie_apb + U0 Clock PCIe APB + 0x24 + 32 + - rx_done - RX Done - [7:7] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + + + clk_u0_pcie_tl + U0 Clock PCIe TL + 0x28 + 32 + + + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u1_pcie_axi_mst0 + U1 Clock PCIe AXI MST 0 + 0x2c + 32 + - activity - Activity - [8:8] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u1_pcie_apb + U1 Clock PCIe APB + 0x30 + 32 + - stop_det - Stop DET - [9:9] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u1_pcie_tl + U1 Clock PCIe TL + 0x34 + 32 + - start_det - Start DET - [10:10] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_pcie01_slv_dec_main + Clock PCIe 01 SLV DEC Main + 0x38 + 32 + - gen_call - General Call - [11:11] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_sec_hclk + Clock Security HCLK + 0x3c + 32 + - restart_det - Restart DET - [12:12] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_sec_misc_ahb + Clock Security Miscellaneous AHB + 0x40 + 32 + - mst_on_hold - Master on Hold - [13:13] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_rx_under - DesignWare I2C Clear RX Underrun + clk_stg_mtrx_group0_main + Clock STG MTRX Group 0 Main 0x44 32 - clr_rx_under - clr_rx_under - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_rx_over - DesignWare I2C Clear RX Overrun + clk_stg_mtrx_group0_bus + Clock STG MTRX Group 0 Bus 0x48 32 - clr_rx_over - clr_rx_over - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_tx_over - DesignWare I2C Clear TX Overrun + clk_stg_mtrx_group0_stg + Clock STG MTRX Group 0 STG 0x4c 32 - clr_tx_over - clr_tx_over - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_rd_req - DesignWare I2C Clear Read Request + clk_stg_mtrx_group1_main + Clock STG MTRX Group 1 Main 0x50 32 - clr_rd_req - clr_rd_req - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_tx_abrt - DesignWare I2C Clear TX Abort + clk_stg_mtrx_group1_bus + Clock STG MTRX Group 1 Bus 0x54 32 - clr_tx_abrt - clr_tx_abrt - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_rx_done - DesignWare I2C Clear RX Done + clk_stg_mtrx_group1_stg + Clock STG MTRX Group 1 STG 0x58 32 - clr_rx_done - clr_rx_done - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_activity - DesignWare I2C Clear Activity + clk_stg_mtrx_group1_hifi + Clock STG MTRX Group 1 HIFI 0x5c 32 - clr_activity - clr_activity - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_stop_det - DesignWare I2C Clear Stop DET + clk_e2_rtc + Clock E2 RTC 0x60 32 - clr_stop_det - clr_stop_det - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + clk_divcfg + Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24 + [23:0] read-write - clr_start_det - DesignWare I2C Clear Start DET + clk_e2_core + Clock E2 Core 0x64 32 - clr_start_det - clr_start_det - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_gen_call - DesignWare I2C Clear General Call + clk_e2_dbg + Clock E2 DBG 0x68 32 - clr_gen_call - clr_gen_call - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - enable - DesignWare I2C Enable + clk_dma_axi + Clock DMA AXI 0x6c 32 - abort - abort + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + + + clk_dma_ahb + Clock DMA AHB + 0x70 + 32 + + + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + + + soft_rst_addr_sel + Software RESET Address Selector + 0x74 + 32 + + + rstn_u0_stg_syscon_presetn + 1: Assert reset, 0: De-assert reset + [0:0] + read-write + + + rst_u0_hifi4_rst_core + 1: Assert reset, 0: De-assert reset [1:1] read-write - - - - status - DesignWare I2C Status - 0x70 - 32 - - activity - activity - [0:0] - read-only + rst_u0_hifi4_rst_axi + 1: Assert reset, 0: De-assert reset + [2:2] + read-write + + + rstn_u0_sec_top_hreesetn + 1: Assert reset, 0: De-assert reset + [3:3] + read-write + + + rst_u0_e2_sft7110_rst_core + 1: Assert reset, 0: De-assert reset + [4:4] + read-write + + + rstn_u0_dma1p_8ch_56hs_rstn_axi + 1: Assert reset, 0: De-assert reset + [5:5] + read-write + + + rstn_u0_dma1p_8ch_56hs_rstn_ahb + 1: Assert reset, 0: De-assert reset + [6:6] + read-write + + + rstn_u0_cdn_usb_rstn_axi + 1: Assert reset, 0: De-assert reset + [7:7] + read-write + + + rstn_u0_cdn_usb_rstn_usb_apb + 1: Assert reset, 0: De-assert reset + [8:8] + read-write + + + rstn_u0_cdn_usb_rstn_utmi_apb + 1: Assert reset, 0: De-assert reset + [9:9] + read-write + + + rstn_u0_cdn_usb_rstn_pwrup + 1: Assert reset, 0: De-assert reset + [10:10] + read-write + + + rstn_u0_plda_pcie_rstn_axi_mst0 + 1: Assert reset, 0: De-assert reset + [11:11] + read-write + + + rstn_u0_plda_pcie_rstn_axi_slv0 + 1: Assert reset, 0: De-assert reset + [12:12] + read-write + + + rstn_u0_plda_pcie_rstn_axi_slv + 1: Assert reset, 0: De-assert reset + [13:13] + read-write + + + rstn_u0_plda_pci_rstn_brg + 1: Assert reset, 0: De-assert reset + [14:14] + read-write + + + rstn_u0_plda_pcie_rstn_pcie + 1: Assert reset, 0: De-assert reset + [15:15] + read-write - tfe - tfe - [2:2] - read-only + rstn_u0_plda_pcie_rstn_apb + 1: Assert reset, 0: De-assert reset + [16:16] + read-write - rfne - rfne - [3:3] - read-only + rstn_u1_plda_pcie_rstn_axi_mst0 + 1: Assert reset, 0: De-assert reset + [17:17] + read-write - master_activity - master_activity - [5:5] - read-only + rstn_u1_plda_pcie_rstn_axi_slv0 + 1: Assert reset, 0: De-assert reset + [18:18] + read-write - slave_activity - slave_activity - [6:6] - read-only + rstn_u1_plda_pcie_rstn_axi_slv + 1: Assert reset, 0: De-assert reset + [19:19] + read-write - - - - txflr - DesignWare I2C TX Failure - 0x74 - 32 - - txflr - txflr - [31:0] + rstn_u1_plda_pcie_rstn_brg + 1: Assert reset, 0: De-assert reset + [20:20] read-write - - - - rxflr - DesignWare I2C RX Failure - 0x78 - 32 - - rxflr - rxflr - [31:0] + rstn_u1_plda_pcie_rstn_pcie + 1: Assert reset, 0: De-assert reset + [21:21] read-write - - - - sda_hold - DesignWare I2C SDA Hold - 0x7c - 32 - - sda_hold - sda_hold - [31:0] + rstn_u1_plda_pcie_rstn_apb + 1: Assert reset, 0: De-assert reset + [22:22] read-write - tx_abrt_source - DesignWare I2C TX Abort Source - 0x80 + stgcrg_rst_stat + STGCRG RESET Status + 0x78 32 - b7_addr_noack - b7_addr_noack + rstn_u0_stg_syscon_presetn + 1: Assert reset, 0: De-assert reset [0:0] - read-only + read-write - b10_addr1_noack - b10_addr1_noack + rst_u0_hifi4_rst_core + 1: Assert reset, 0: De-assert reset [1:1] - read-only + read-write - b10_addr2_noack - b10_addr2_noack + rst_u0_hifi4_rst_axi + 1: Assert reset, 0: De-assert reset [2:2] - read-only + read-write - txdata_noack - txdata_noack + rstn_u0_sec_top_hreesetn + 1: Assert reset, 0: De-assert reset [3:3] - read-only + read-write - gcall_noack - gcall_noack + rst_u0_e2_sft7110_rst_core + 1: Assert reset, 0: De-assert reset [4:4] - read-only + read-write - gcall_read - gcall_read + rstn_u0_dma1p_8ch_56hs_rstn_axi + 1: Assert reset, 0: De-assert reset [5:5] - read-only + read-write - sbyte_ackdet - sbyte_ackdet + rstn_u0_dma1p_8ch_56hs_rstn_ahb + 1: Assert reset, 0: De-assert reset + [6:6] + read-write + + + rstn_u0_cdn_usb_rstn_axi + 1: Assert reset, 0: De-assert reset [7:7] - read-only + read-write - sbyte_norstrt - sbyte_norstrt + rstn_u0_cdn_usb_rstn_usb_apb + 1: Assert reset, 0: De-assert reset + [8:8] + read-write + + + rstn_u0_cdn_usb_rstn_utmi_apb + 1: Assert reset, 0: De-assert reset [9:9] - read-only + read-write - b10_rd_norstrt - b10_rd_norstrt + rstn_u0_cdn_usb_rstn_pwrup + 1: Assert reset, 0: De-assert reset [10:10] - read-only + read-write - master_dis - master_dis + rstn_u0_plda_pcie_rstn_axi_mst0 + 1: Assert reset, 0: De-assert reset [11:11] - read-only + read-write - arb_lost - arb_lost + rstn_u0_plda_pcie_rstn_axi_slv0 + 1: Assert reset, 0: De-assert reset [12:12] - read-only + read-write - slave_flush_txfifo - slave_flush_txfifo + rstn_u0_plda_pcie_rstn_axi_slv + 1: Assert reset, 0: De-assert reset [13:13] - read-only + read-write - slave_arblost - slave_arblost + rstn_u0_plda_pci_rstn_brg + 1: Assert reset, 0: De-assert reset [14:14] - read-only - - - slave_rd_intx - slave_rd_intx - [15:15] - read-only - - - - - enable_status - DesignWare I2C Enable Status - 0x9c - 32 - - - activity - activity - [0:0] read-write - tfe - tfe - [2:2] + rstn_u0_plda_pcie_rstn_pcie + 1: Assert reset, 0: De-assert reset + [15:15] read-write - rfne - rfne - [3:3] + rstn_u0_plda_pcie_rstn_apb + 1: Assert reset, 0: De-assert reset + [16:16] read-write - master_activity - master_activity - [5:5] + rstn_u1_plda_pcie_rstn_axi_mst0 + 1: Assert reset, 0: De-assert reset + [17:17] read-write - slave_activity - slave_activity - [6:6] + rstn_u1_plda_pcie_rstn_axi_slv0 + 1: Assert reset, 0: De-assert reset + [18:18] read-write - - - - clr_restart_det - DesignWare I2C Clear Restart DET - 0xa8 - 32 - - clr_restart_det - clr_restart_det - [31:0] + rstn_u1_plda_pcie_rstn_axi_slv + 1: Assert reset, 0: De-assert reset + [19:19] read-write - - - - comp_param_1 - DesignWare I2C Compatibility Parameter 1 - 0xf4 - 32 - - speed - Speed mask - 01: Standard, 10: Full, 11: High - [3:2] - read-only + rstn_u1_plda_pcie_rstn_brg + 1: Assert reset, 0: De-assert reset + [20:20] + read-write - - - - comp_version - DesignWare I2C Compatibility Version - 0xf8 - 32 - - comp_version - comp_version - [31:0] - read-only + rstn_u1_plda_pcie_rstn_pcie + 1: Assert reset, 0: De-assert reset + [21:21] + read-write - - - - comp_type - DesignWare I2C Compatibility Type - 0xfc - 32 - - comp_type - comp_type - [31:0] - read-only + rstn_u1_plda_pcie_rstn_apb + 1: Assert reset, 0: De-assert reset + [22:22] + read-write - snps_designware_i2c_2 - From snps,designware-i2c, peripheral generator - 0x10050000 + starfive_jh7110_stg_syscon_0 + From starfive,jh7110-stg-syscon, peripheral generator + 0x10240000 0 - 0x10000 + 0x1000 registers - con - DesignWare I2C CON + stg_sysconsaif_syscfg0 + STG SYSCONSAIF SYSCFG 0 0x0 32 - master - I2C Master Connection - 0: Slave, 1: Master - [0:0] + scfg_hprot_sd0 + scfg_hprot_sd0 + [3:0] read-write - speed - I2C Speed - 01: Standard, 10: Fast, 11: High - [2:1] + scfg_hprot_sd1 + scfg_hprot_sd1 + [7:4] read-write - slave_10bitaddr - I2C Slave 10-bit Address - 0: False, 1: True - [3:3] - read-write + u0_cdn_usb_adp_en + u0_cdn_usb_adp_en + [8:8] + read-only - master_10bitaddr - I2C Master 10-bit Address - 0: False, 1: True - [4:4] + u0_cdn_usb_adp_probe_ana + u0_cdn_usb_adp_probe_ana + [9:9] read-write - restart_en - I2C Restart Enable - 0: False, 1: True - [5:5] - read-write + u0_cdn_usb_adp_probe_en + u0_cdn_usb_adp_probe_en + [10:10] + read-only - slave_disable - I2C Slave Disable - 0: False, 1: True - [6:6] + u0_cdn_usb_adp_sense_ana + u0_cdn_usb_adp_sense_ana + [11:11] read-write - stop_det_ifaddressed - I2C Stop DET If Addressed - 0: False, 1: True - [7:7] - read-write + u0_cdn_usb_adp_sense_en + u0_cdn_usb_adp_sense_en + [12:12] + read-only - tx_empty_ctrl - I2C TX Empty Control - 0: False, 1: True - [8:8] - read-write + u0_cdn_usb_adp_sink_current_en + u0_cdn_usb_adp_sink_current_en + [13:13] + read-only - rx_fifo_full_hld_ctrl - I2C RX FIFO Full Hold Control - 0: False, 1: True - [9:9] - read-write + u0_cdn_usb_adp_source_current_en + u0_cdn_usb_adp_source_current_en + [14:14] + read-only - bus_clear_ctrl - I2C Bus Clear Control - 0: False, 1: True - [11:11] - read-write + u0_cdn_usb_bc_en + u0_cdn_usb_bc_en + [15:15] + read-only - - - - tar - DesignWare I2C TAR - 0x4 - 32 - - tar - tar - [31:0] + u0_cdn_usb_chrg_vbus + u0_cdn_usb_chrg_vbus + [16:16] read-write - - - - sar - DesignWare I2C SAR - 0x8 - 32 - - sar - sar - [31:0] + u0_cdn_usb_dcd_comp_sts + u0_cdn_usb_dcd_comp_sts + [17:17] read-write - - - - data_cmd - DesignWare I2C Data Command - 0x10 - 32 - - dat - Data Command Data Byte - [7:0] + u0_cdn_usb_dischrg_vbus + u0_cdn_usb_dischrg_vbus + [18:18] read-write - first_data_byte - Data Command First Data Byte - 0: False, 1: True - [11:11] - read-write + u0_cdn_usb_dm_vdat_ref_comp_en + u0_cdn_usb_dm_vdat_ref_comp_en + [19:19] + read-only - - - - ss_scl_hcnt - DesignWare I2C SS SCL HCNT - 0x14 - 32 - - ss_scl_hcnt - ss_scl_hcnt - [31:0] + u0_cdn_usb_dm_vdat_ref_comp_sts + u0_cdn_usb_dm_vdat_ref_comp_sts + [20:20] read-write - - - - ss_scl_lcnt - DesignWare I2C SS SCL LCNT - 0x18 - 32 - - ss_scl_lcnt - ss_scl_lcnt - [31:0] + u0_cdn_usb_dm_vlgc_comp_en + u0_cdn_usb_dm_vlgc_comp_en + [21:21] + read-only + + + u0_cdn_usb_dm_vlgc_comp_sts + u0_cdn_usb_dm_vlgc_comp_sts + [22:22] read-write - - - - fs_scl_hcnt - DesignWare I2C FS SCL HCNT - 0x1c - 32 - - fs_scl_hcnt - fs_scl_hcnt - [31:0] + u0_cdn_usb_dp_vdat_ref_comp_en + u0_cdn_usb_dp_vdat_ref_comp_en + [23:23] + read-only + + + u0_cdn_usb_dp_vdat_ref_comp_sts + u0_cdn_usb_dp_vdat_ref_comp_sts + [24:24] read-write - - - - fs_scl_lcnt - DesignWare I2C FS SCL LCNT - 0x20 - 32 - - fs_scl_lcnt - fs_scl_lcnt - [31:0] + u0_cdn_usb_host_system_err + u0_cdn_usb_host_system_err + [25:25] read-write + + u0_cdn_usb_hsystem_err_ext + u0_cdn_usb_hsystem_err_ext + [26:26] + read-only + + + u0_cdn_usb_idm_sink_en + u0_cdn_usb_idm_sink_en + [27:27] + read-only + + + u0_cdn_usb_idp_sink_en + u0_cdn_usb_idp_sink_en + [28:28] + read-only + + + u0_cdn_usb_idp_src_en + u0_cdn_usb_idp_src_en + [29:29] + read-only + - hs_scl_hcnt - DesignWare I2C HS SCL HCNT - 0x24 + stg_sysconsaif_syscfg4 + STG SYSCONSAIF SYSCFG 4 + 0x4 32 - hs_scl_hcnt - hs_scl_hcnt - [31:0] + u0_cdn_usb_lowest_belt + LTM interface to software + [11:0] + read-only + + + u0_cdn_usb_ltm_host_req + LTM interface to software + [12:12] + read-only + + + u0_cdn_usb_ltm_host_req_halt + LTM interface to software + [13:13] read-write - - - - hs_scl_lcnt - DesignWare I2C HS SCL LCNT - 0x28 - 32 - - hs_scl_lcnt - hs_scl_lcnt - [31:0] + u0_cdn_usb_mdctrl_clk_sel + u0_cdn_usb_mdctrl_clk_sel + [14:14] read-write - - - - intr_stat - DesignWare I2C Interrupt Status - 0x2c - 32 - - rx_under - RX FIFO Underrun - [0:0] + u0_cdn_usb_mdctrl_clk_status + u0_cdn_usb_mdctrl_clk_status + [15:15] read-only - rx_over - RX FIFO Overrun - [1:1] - read-only + u0_cdn_usb_mode_strap + Can onlly be changed when pwrup_rst_n is low + [18:16] + read-write - rx_full - RX FIFO Full - [2:2] - read-only + u0_cdn_usb_otg_suspendm + u0_cdn_usb_otg_suspendm + [19:19] + read-write - tx_over - TX FIFO Overrun - [3:3] - read-only + u0_cdn_usb_otg_suspendm_byps + u0_cdn_usb_otg_suspendm_byps + [20:20] + read-write - tx_empty - TX FIFO Empty - [4:4] + u0_cdn_usb_phy_bvalid + u0_cdn_usb_phy_bvalid + [21:21] read-only - rd_req - Read Request - [5:5] - read-only + u0_cdn_usb_pll_en + u0_cdn_usb_pll_en + [22:22] + read-write - tx_abrt - TX Abort - [6:6] - read-only + u0_cdn_usb_refclk_mode + u0_cdn_usb_refclk_mode + [23:23] + read-write - rx_done - RX Done - [7:7] - read-only + u0_cdn_usb_rid_a_comp_sts + u0_cdn_usb_rid_a_comp_sts + [24:24] + read-write - activity - Activity - [8:8] - read-only + u0_cdn_usb_rid_b_comp_sts + u0_cdn_usb_rid_b_comp_sts + [25:25] + read-write - stop_det - Stop DET - [9:9] - read-only + u0_cdn_usb_rid_c_comp_sts + u0_cdn_usb_rid_c_comp_sts + [26:26] + read-write - start_det - Start DET - [10:10] + u0_cdn_usb_rid_float_comp_en + u0_cdn_usb_rid_float_comp_en + [27:27] read-only - gen_call - General Call - [11:11] - read-only + u0_cdn_usb_rid_float_comp_sts + u0_cdn_usb_rid_float_comp_sts + [28:28] + read-write - restart_det - Restart DET - [12:12] + u0_cdn_usb_rid_gnd_comp_sts + u0_cdn_usb_rid_gnd_comp_sts + [29:29] + read-write + + + u0_cdn_usb_rid_nonfloat_comp_en + u0_cdn_usb_rid_nonfloat_comp_en + [30:30] read-only - mst_on_hold - Master on Hold - [13:13] + u0_cdn_usb_rx_dm + u0_cdn_usb_rx_dm + [31:31] read-only - intr_mask - DesignWare I2C Interrupt Mask - 0x30 + stg_sysconsaif_syscfg8 + STG SYSCONSAIF SYSCFG 8 + 0x8 32 - rx_under - RX FIFO Underrun + u0_cdn_usb_rx_dp + u0_cdn_usb_rx_dp [0:0] - read-write + read-only - rx_over - RX FIFO Overrun + u0_cdn_usb_rx_rcv + u0_cdn_usb_rx_rcv [1:1] - read-write + read-only - rx_full - RX FIFO Full + u0_cdn_usb_self_test + For software bist_test [2:2] read-write - tx_over - TX FIFO Overrun + u0_cdn_usb_sessend + u0_cdn_usb_sessend [3:3] - read-write + read-only - tx_empty - TX FIFO Empty + u0_cdn_usb_sessvalid + u0_cdn_usb_sessvalid [4:4] - read-write + read-only - rd_req - Read Request + u0_cdn_usb_sof + u0_cdn_usb_sof [5:5] - read-write + read-only - tx_abrt - TX Abort + u0_cdn_usb_test_bist + For software bist_test [6:6] - read-write + read-only - rx_done - RX Done + u0_cdn_usb_usbdev_main_power_off_ack + u0_cdn_usb_usbdev_main_power_off_ack [7:7] - read-write + read-only - activity - Activity + u0_cdn_usb_usbdev_main_power_off_ready + u0_cdn_usb_usbdev_main_power_off_ready [8:8] - read-write + read-only - stop_det - Stop DET + u0_cdn_usb_usbdev_main_power_off_req + u0_cdn_usb_usbdev_main_power_off_req [9:9] read-write - start_det - Start DET + u0_cdn_usb_usbdev_main_power_on_ready + u0_cdn_usb_usbdev_main_power_on_ready [10:10] - read-write + read-only - gen_call - General Call + u0_cdn_usb_usbdev_main_power_on_req + u0_cdn_usb_usbdev_main_power_on_req [11:11] - read-write + read-only - restart_det - Restart DET + u0_cdn_usb_usbdev_main_power_on_valid + u0_cdn_usb_usbdev_main_power_on_valid [12:12] read-write - mst_on_hold - Master on Hold - [13:13] - read-write - - - - - raw_intr_stat - DesignWare I2C Raw Interrupt Status - 0x34 - 32 - - - rx_under - RX FIFO Underrun - [0:0] + u0_cdn_usb_usbdev_power_off_ack + u0_cdn_usb_usbdev_power_off_ack + [13:13] read-only - rx_over - RX FIFO Overrun - [1:1] + u0_cdn_usb_usbdev_power_off_ready + u0_cdn_usb_usbdev_power_off_ready + [14:14] read-only - rx_full - RX FIFO Full - [2:2] - read-only + u0_cdn_usb_usbdev_power_off_req + u0_cdn_usb_usbdev_power_off_req + [15:15] + read-write - tx_over - TX FIFO Overrun - [3:3] + u0_cdn_usb_usbdev_power_on_ready + u0_cdn_usb_usbdev_power_on_ready + [16:16] read-only - tx_empty - TX FIFO Empty - [4:4] + u0_cdn_usb_usbdev_power_on_req + u0_cdn_usb_usbdev_power_on_req + [17:17] read-only - rd_req - Read Request - [5:5] - read-only + u0_cdn_usb_usbdev_power_on_valid + u0_cdn_usb_usbdev_power_on_valid + [18:18] + read-write - tx_abrt - TX Abort - [6:6] - read-only + u0_cdn_usb_utmi_dmpulldown_sit + u0_cdn_usb_utmi_dmpulldown_sit + [19:19] + read-write - rx_done - RX Done - [7:7] - read-only + u0_cdn_usb_utmi_dppulldown_sit + u0_cdn_usb_utmi_dppulldown_sit + [20:20] + read-write - activity - Activity - [8:8] - read-only + u0_cdn_usb_utmi_fslsserialmode_sit + u0_cdn_usb_utmi_fslsserialmode_sit + [21:21] + read-write - stop_det - Stop DET - [9:9] + u0_cdn_usb_utmi_hostdisconnect_sit + u0_cdn_usb_utmi_hostdisconnect_sit + [22:22] read-only - start_det - Start DET - [10:10] + u0_cdn_usb_utmi_iddig_sit + u0_cdn_usb_utmi_iddig_sit + [23:23] read-only - gen_call - General Call - [11:11] - read-only + u0_cdn_usb_utmi_idpullup_sit + u0_cdn_usb_utmi_idpullup_sit + [24:24] + read-write - restart_det - Restart DET - [12:12] + u0_cdn_usb_utmi_linestate_sit + u0_cdn_usb_utmi_linestate_sit + [26:25] read-only - mst_on_hold - Master on Hold - [13:13] + u0_cdn_usb_utmi_opmode_sit + u0_cdn_usb_utmi_opmode_sit + [28:27] + read-write + + + u0_cdn_usb_utmi_rxactive_sit + u0_cdn_usb_utmi_rxactive_sit + [29:29] read-only - - - - rx_tl - DesignWare I2C RX TL - 0x38 - 32 - - rx_tl - rx_tl - [31:0] - read-write + u0_cdn_usb_utmi_rxerror_sit + u0_cdn_usb_utmi_rxerror_sit + [30:30] + read-only - - - - tx_tl - DesignWare I2C TX TL - 0x3c - 32 - - tx_tl - tx_tl - [31:0] - read-write + u0_cdn_usb_utmi_rxvalid_sit + u0_cdn_usb_utmi_rxvalid_sit + [31:31] + read-only - clr_intr - DesignWare I2C Clear Interrrupt - 0x40 + stg_sysconsaif_syscfg12 + STG SYSCONSAIF SYSCFG 12 + 0xc 32 - rx_under - RX FIFO Underrun + u0_cdn_usb_utmi_rxvalidh_sit + u0_cdn_usb_utmi_rxvalidh_sit [0:0] - read-write + read-only - rx_over - RX FIFO Overrun + u0_cdn_usb_utmi_sessvld + u0_cdn_usb_utmi_sessvld [1:1] read-write - rx_full - RX FIFO Full + u0_cdn_usb_utmi_termselect_sit + u0_cdn_usb_utmi_termselect_sit [2:2] read-write - tx_over - TX FIFO Overrun + u0_cdn_usb_utmi_tx_dat_sit + u0_cdn_usb_utmi_tx_dat_sit [3:3] read-write - tx_empty - TX FIFO Empty + u0_cdn_usb_utmi_tx_enable_n_sit + u0_cdn_usb_utmi_tx_enable_n_sit [4:4] read-write - rd_req - Read Request + u0_cdn_usb_utmi_tx_se0_sit + u0_cdn_usb_utmi_tx_se0_sit [5:5] read-write - tx_abrt - TX Abort + u0_cdn_usb_utmi_txbitstuffenable_sit + u0_cdn_usb_utmi_txbitstuffenable_sit [6:6] read-write - rx_done - RX Done + u0_cdn_usb_utmi_txready_sit + u0_cdn_usb_utmi_txready_sit [7:7] - read-write + read-only - activity - Activity + u0_cdn_usb_utmi_txvalid_sit + u0_cdn_usb_utmi_txvalid_sit [8:8] read-write - stop_det - Stop DET + u0_cdn_usb_utmi_txvalidh_sit + u0_cdn_usb_utmi_txvalidh_sit [9:9] read-write - start_det - Start DET + u0_cdn_usb_utmi_vbusvalid_sit + u0_cdn_usb_utmi_vbusvalid_sit [10:10] - read-write - - - gen_call - General Call - [11:11] - read-write + read-only - restart_det - Restart DET - [12:12] + u0_cdn_usb_utmi_xcvrselect_sit + u0_cdn_usb_utmi_xcvrselect_sit + [12:11] read-write - mst_on_hold - Master on Hold + u0_cdn_usb_utmi_vdm_src_en + u0_cdn_usb_utmi_vdm_src_en [13:13] - read-write + read-only - - - - clr_rx_under - DesignWare I2C Clear RX Underrun - 0x44 - 32 - - clr_rx_under - clr_rx_under - [31:0] - read-write + u0_cdn_usb_utmi_vdp_src_en + u0_cdn_usb_utmi_vdp_src_en + [14:14] + read-only - - - - clr_rx_over - DesignWare I2C Clear RX Overrun - 0x48 - 32 - - clr_rx_over - clr_rx_over - [31:0] + u0_cdn_usb_wakeup + u0_cdn_usb_wakeup + [15:15] read-write - - - - clr_tx_over - DesignWare I2C Clear TX Overrun - 0x4c - 32 - - clr_tx_over - clr_tx_over - [31:0] - read-write - - - - - clr_rd_req - DesignWare I2C Clear Read Request - 0x50 - 32 - + u0_cdn_usb_xhc_d0_ack + u0_cdn_usb_xhc_d0_ack + [16:16] + read-only + - clr_rd_req - clr_rd_req - [31:0] + u0_cdn_usb_xhc_d0_req + u0_cdn_usb_xhc_d0_req + [17:17] read-write - clr_tx_abrt - DesignWare I2C Clear TX Abort - 0x54 + stg_sysconsaif_syscfg16 + STG SYSCONSAIF SYSCFG 16 + 0x10 32 - clr_tx_abrt - clr_tx_abrt + u0_cdn_usb_xhci_debug_bus + u0_cdn_usb_xhci_debug_bus [31:0] - read-write + read-only - clr_rx_done - DesignWare I2C Clear RX Done - 0x58 + stg_sysconsaif_syscfg20 + STG SYSCONSAIF SYSCFG 20 + 0x14 32 - clr_rx_done - clr_rx_done - [31:0] - read-write + u0_cdn_usb_xhci_debug_link_state + u0_cdn_usb_xhci_debug_link_state + [30:0] + read-only - clr_activity - DesignWare I2C Clear Activity - 0x5c + stg_sysconsaif_syscfg24 + STG SYSCONSAIF SYSCFG 24 + 0x18 32 - clr_activity - clr_activity - [31:0] + u0_cdn_usb_xhci_debug_sel + u0_cdn_usb_xhci_debug_sel + [4:0] read-write - - - - clr_stop_det - DesignWare I2C Clear Stop DET - 0x60 - 32 - - clr_stop_det - clr_stop_det - [31:0] - read-write + u0_cdn_usb_xhci_main_power_off_ack + u0_cdn_usb_xhci_main_power_off_ack + [5:5] + read-only - - - - clr_start_det - DesignWare I2C Clear Start DET - 0x64 - 32 - - clr_start_det - clr_start_det - [31:0] + u0_cdn_usb_xhci_main_power_off_req + u0_cdn_usb_xhci_main_power_off_req + [6:6] + read-only + + + u0_cdn_usb_xhci_main_power_on_ready + u0_cdn_usb_xhci_main_power_on_ready + [7:7] read-write - - - - clr_gen_call - DesignWare I2C Clear General Call - 0x68 - 32 - - clr_gen_call - clr_gen_call - [31:0] + u0_cdn_usb_xhci_main_power_on_req + u0_cdn_usb_xhci_main_power_on_req + [8:8] + read-only + + + u0_cdn_usb_xhci_main_power_on_valid + u0_cdn_usb_xhci_main_power_on_valid + [9:9] read-write - - - - enable - DesignWare I2C Enable - 0x6c - 32 - - abort - abort - [1:1] + u0_cdn_usb_xhci_power_off_ack + u0_cdn_usb_xhci_power_off_ack + [10:10] + read-only + + + u0_cdn_usb_xhci_power_off_ready + u0_cdn_usb_xhci_power_off_ready + [11:11] + read-only + + + u0_cdn_usb_xhci_power_off_req + u0_cdn_usb_xhci_power_off_req + [12:12] read-write - - - - status - DesignWare I2C Status - 0x70 - 32 - - activity - activity - [0:0] + u0_cdn_usb_xhci_power_on_ready + u0_cdn_usb_xhci_power_on_ready + [13:13] read-only - tfe - tfe - [2:2] + u0_cdn_usb_xhci_power_on_req + u0_cdn_usb_xhci_power_on_req + [14:14] read-only - rfne - rfne - [3:3] + u0_cdn_usb_xhci_power_on_valid + u0_cdn_usb_xhci_power_on_valid + [15:15] + read-write + + + u0_e2_sft7110_cease_from_tile_0 + u0_e2_sft7110_cease_from_tile_0 + [16:16] read-only - master_activity - master_activity - [5:5] + u0_e2_sft7110_debug_from_tile_0 + u0_e2_sft7110_debug_from_tile_0 + [17:17] read-only - slave_activity - slave_activity - [6:6] + u0_e2_sft7110_halt_from_tile_0 + u0_e2_sft7110_halt_from_tile_0 + [18:18] read-only - txflr - DesignWare I2C TX Failure - 0x74 + stg_sysconsaif_syscfg28 + STG SYSCONSAIF SYSCFG 28 + 0x1c 32 - txflr - txflr + u0_e2_sft7110_nmi_0_rnmi_exception_vector + u0_e2_sft7110_nmi_0_rnmi_exception_vector [31:0] read-write - rxflr - DesignWare I2C RX Failure - 0x78 + stg_sysconsaif_syscfg32 + STG SYSCONSAIF SYSCFG 32 + 0x20 32 - rxflr - rxflr + u0_e2_sft7110_nmi_0_rnmi_interrupt_vector + u0_e2_sft7110_nmi_0_rnmi_interrupt_vector [31:0] read-write - sda_hold - DesignWare I2C SDA Hold - 0x7c + stg_sysconsaif_syscfg36 + STG SYSCONSAIF SYSCFG 36 + 0x24 32 - sda_hold - sda_hold + u0_e2_sft7110_reset_vector_0 + u0_e2_sft7110_reset_vector_0 [31:0] read-write - tx_abrt_source - DesignWare I2C TX Abort Source - 0x80 + stg_sysconsaif_syscfg40 + STG SYSCONSAIF SYSCFG 40 + 0x28 32 - b7_addr_noack - b7_addr_noack + u0_e2_sft7110_wfi_from_tile_0 + u0_e2_sft7110_wfi_from_tile_0 [0:0] read-only + + + + stg_sysconsaif_syscfg44 + STG SYSCONSAIF SYSCFG 44 + 0x2c + 32 + - b10_addr1_noack - b10_addr1_noack - [1:1] - read-only - - - b10_addr2_noack - b10_addr2_noack - [2:2] - read-only + u0_hifi4_altresetvec + Reset Vector Address + [31:0] + read-write + + + + stg_sysconsaif_syscfg48 + STG SYSCONSAIF SYSCFG 48 + 0x30 + 32 + - txdata_noack - txdata_noack - [3:3] - read-only + u0_hifi4_breakin + Debug signal + [0:0] + read-write - gcall_noack - gcall_noack - [4:4] + u0_hifi4_breakinack + Debug signal + [1:1] read-only - gcall_read - gcall_read - [5:5] + u0_hifi4_breakout + Debug signal + [2:2] read-only - sbyte_ackdet - sbyte_ackdet - [7:7] - read-only + u0_hifi4_breakoutack + Debug signal + [3:3] + read-write - sbyte_norstrt - sbyte_norstrt - [9:9] + u0_hifi4_debugmode + Debug signal + [4:4] read-only - b10_rd_norstrt - b10_rd_norstrt - [10:10] + u0_hifi4_doubleexceptionerror + Fault Handling Signals + [5:5] read-only - master_dis - master_dis - [11:11] + u0_hifi4_iram0loadstore + Indicates that iram0 works + [6:6] read-only - arb_lost - arb_lost - [12:12] + u0_hifi4_iram1loadstore + Indicates that iram1 works + [7:7] read-only - slave_flush_txfifo - slave_flush_txfifo - [13:13] - read-only + u0_hifi4_ocdhaltonreset + Debug signal + [8:8] + read-write - slave_arblost - slave_arblost - [14:14] + u0_hifi4_pfatalerror + Fault Handling Signals + [9:9] read-only + + + + stg_sysconsaif_syscfg52 + STG SYSCONSAIF SYSCFG 52 + 0x34 + 32 + - slave_rd_intx - slave_rd_intx - [15:15] + u0_hifi4_pfaultinfo + Fault Handling Signals + [31:0] read-only - enable_status - DesignWare I2C Enable Status - 0x9c + stg_sysconsaif_syscfg56 + STG SYSCONSAIF SYSCFG 56 + 0x38 32 - activity - activity + u0_hifi4_pfaultinfovalid + Fault Handling Signals [0:0] - read-write - - - tfe - tfe - [2:2] - read-write + read-only - rfne - rfne - [3:3] + u0_hifi4_prid + Module ID + [16:1] read-write - master_activity - master_activity - [5:5] - read-write + u0_hifi4_pwaitmode + Wait Mode + [17:17] + read-only - slave_activity - slave_activity - [6:6] + u0_hifi4_runstall + Run Stall + [18:18] read-write - clr_restart_det - DesignWare I2C Clear Restart DET - 0xa8 + stg_sysconsaif_syscfg60 + STG SYSCONSAIF SYSCFG 60 + 0x3c 32 - clr_restart_det - clr_restart_det - [31:0] + u0_hifi4_scfg_dsp_mst_offset_master + Indicates that master port remap address + [11:0] read-write - - - - comp_param_1 - DesignWare I2C Compatibility Parameter 1 - 0xf4 - 32 - - speed - Speed mask - 01: Standard, 10: Full, 11: High - [3:2] - read-only + u0_hifi4_scfg_dsp_mst_offset_dma + Indicates the DMA port remap address + [27:16] + read-write - comp_version - DesignWare I2C Compatibility Version - 0xf8 + stg_sysconsaif_syscfg64 + STG SYSCONSAIF SYSCFG 64 + 0x40 32 - comp_version - comp_version + u0_hifi4_scfg_dsp_slv_offset + The value indicates the slave port remap address [31:0] - read-only + read-write - comp_type - DesignWare I2C Compatibility Type - 0xfc + stg_sysconsaif_syscfg68 + STG SYSCONSAIF SYSCFG 68 + 0x44 32 - comp_type - comp_type - [31:0] - read-only + u0_hifi4_scfg_sram_config_slp + SRAM/ROM configuration. SLP: sleep enable, high active, default is low. + [0:0] + read-write - - - - - - starfive_jh7110_stgcrg_0 - From starfive,jh7110-stgcrg, peripheral generator - 0x10230000 - - 0 - 0x10000 - registers - - - - clk_hifi4_core - Clock HIFI4 Core - 0x0 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + u0_hifi4_scfg_sram_config_sram_config_sd + SRAM/ROM configuration. SD: shutdown enable, high active, default is low. + [1:1] read-write - - - - clk_usb_apb - Clock USB APB - 0x4 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + u0_hifi4_scfg_sram_config_rtsel + SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. + [3:2] read-write - - - - clk_usb_utmi_apb - Clock USB UTMI APB - 0x8 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + u0_hifi4_scfg_sram_config_ptsel + SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. + [5:4] read-write - - - - clk_usb_axi - Clock USB AXI - 0xc - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + u0_hifi4_scfg_sram_config_trb + SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. + [7:6] read-write - - - - clk_usb_ipm - Clock USB AXI - 0x10 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + u0_hifi4_scfg_sram_config_wtsel + SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. + [9:8] + read-write + + + u0_hifi4_scfg_sram_config_vs + SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. + [10:10] + read-write + + + u0_hifi4_scfg_sram_config_vg + SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. + [11:11] + read-write + + + u0_hifi4_statvectorsel + When the value is 1, it indicates that the AltResetVec is valid + [12:12] read-write - clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 - [23:0] + u0_hifi4_trigin_idma + DMA port trigger + [13:13] read-write - - - - clk_usb_stb - Clock USB STB - 0x14 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_hifi4_trigout_idma + DMA port trigger + [14:14] + read-only - clk_divcfg - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 - [23:0] - read-write + u0_hifi4_xocdmode + Debug signal + [15:15] + read-only - - - - clk_usb_app125 - Clock USB APP 125 - 0x18 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_align_detect + u0_plda_pcie_align_detect + [16:16] + read-only - clk_usb_refclk - Clock USB Reference Clock - 0x1c + stg_sysconsaif_syscfg72 + STG SYSCONSAIF SYSCFG 72 + 0x48 32 - clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 - [23:0] - read-write + u0_plda_pcie_axi4_mst0_aratomop_31_0 + u0_plda_pcie_axi4_mst0_aratomop_31_0 + [31:0] + read-only - clk_u0_pcie_axi_mst0 - U0 Clock PCIe AXI MST 0 - 0x20 + stg_sysconsaif_syscfg76 + STG SYSCONSAIF SYSCFG 76 + 0x4c 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_aratomop_63_32 + u0_plda_pcie_axi4_mst0_aratomop_63_32 + [31:0] + read-only - clk_u0_pcie_apb - U0 Clock PCIe APB - 0x24 + stg_sysconsaif_syscfg80 + STG SYSCONSAIF SYSCFG 80 + 0x50 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_aratomop_95_64 + u0_plda_pcie_axi4_mst0_aratomop_95_64 + [31:0] + read-only - clk_u0_pcie_tl - U0 Clock PCIe TL - 0x28 + stg_sysconsaif_syscfg84 + STG SYSCONSAIF SYSCFG 84 + 0x54 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_aratomop_127_96 + u0_plda_pcie_axi4_mst0_aratomop_127_96 + [31:0] + read-only - clk_u1_pcie_axi_mst0 - U1 Clock PCIe AXI MST 0 - 0x2c + stg_sysconsaif_syscfg88 + STG SYSCONSAIF SYSCFG 88 + 0x58 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_aratomop_159_128 + u0_plda_pcie_axi4_mst0_aratomop_159_128 + [31:0] + read-only - clk_u1_pcie_apb - U1 Clock PCIe APB - 0x30 + stg_sysconsaif_syscfg92 + STG SYSCONSAIF SYSCFG 92 + 0x5c 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_aratomop_191_160 + u0_plda_pcie_axi4_mst0_aratomop_191_160 + [31:0] + read-only - clk_u1_pcie_tl - U1 Clock PCIe TL - 0x34 + stg_sysconsaif_syscfg96 + STG SYSCONSAIF SYSCFG 96 + 0x60 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_aratomop_223_192 + u0_plda_pcie_axi4_mst0_aratomop_223_192 + [31:0] + read-only - clk_pcie01_slv_dec_main - Clock PCIe 01 SLV DEC Main - 0x38 + stg_sysconsaif_syscfg100 + STG SYSCONSAIF SYSCFG 100 + 0x64 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_aratomop_255_224 + u0_plda_pcie_axi4_mst0_aratomop_255_224 + [31:0] + read-only - clk_sec_hclk - Clock Security HCLK - 0x3c + stg_sysconsaif_syscfg104 + STG SYSCONSAIF SYSCFG 104 + 0x68 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_aratomop_257_256 + u0_plda_pcie_axi4_mst0_aratomop_257_256 + [1:0] + read-only - - - - clk_sec_misc_ahb - Clock Security Miscellaneous AHB - 0x40 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_arfunc + u0_plda_pcie_axi4_mst0_arfunc + [16:2] + read-only + + + u0_plda_pcie_axi4_mst0_arregion + u0_plda_pcie_axi4_mst0_arregion + [20:17] + read-only - clk_stg_mtrx_group0_main - Clock STG MTRX Group 0 Main - 0x44 + stg_sysconsaif_syscfg108 + STG SYSCONSAIF SYSCFG 108 + 0x6c 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_aruser_31_0 + u0_plda_pcie_axi4_mst0_aruser_31_0 + [31:0] + read-only - clk_stg_mtrx_group0_bus - Clock STG MTRX Group 0 Bus - 0x48 + stg_sysconsaif_syscfg112 + STG SYSCONSAIF SYSCFG 112 + 0x70 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_aruser_63_32 + u0_plda_pcie_axi4_mst0_aruser_63_32 + [31:0] + read-only - clk_stg_mtrx_group0_stg - Clock STG MTRX Group 0 STG - 0x4c + stg_sysconsaif_syscfg116 + STG SYSCONSAIF SYSCFG 116 + 0x74 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_awfunc + u0_plda_pcie_axi4_mst0_awfunc + [14:0] + read-only + + + u0_plda_pcie_axi4_mst0_awregion + u0_plda_pcie_axi4_mst0_awregion + [18:15] + read-only - clk_stg_mtrx_group1_main - Clock STG MTRX Group 1 Main - 0x50 + stg_sysconsaif_syscfg120 + STG SYSCONSAIF SYSCFG 120 + 0x78 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_a2user_31_0 + u0_plda_pcie_axi4_mst0_a2user_31_0 + [31:0] + read-only - clk_stg_mtrx_group1_bus - Clock STG MTRX Group 1 Bus - 0x54 + stg_sysconsaif_syscfg124 + STG SYSCONSAIF SYSCFG 124 + 0x7c 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + u0_plda_pcie_axi4_mst0_awuser_42_32 + u0_plda_pcie_axi4_mst0_awuser_42_32 + [10:0] + read-only + + + u0_plda_pcie_axi4_mst0_rderr + u0_plda_pcie_axi4_mst0_rderr + [18:11] read-write - clk_stg_mtrx_group1_stg - Clock STG MTRX Group 1 STG - 0x58 + stg_sysconsaif_syscfg128 + STG SYSCONSAIF SYSCFG 128 + 0x80 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + u0_plda_pcie_axi4_mst0_ruser + u0_plda_pcie_axi4_mst0_ruser + [31:0] read-write - clk_stg_mtrx_group1_hifi - Clock STG MTRX Group 1 HIFI - 0x5c + stg_sysconsaif_syscfg132 + STG SYSCONSAIF SYSCFG 132 + 0x84 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write + u0_plda_pcie_axi4_mst0_wderr + u0_plda_pcie_axi4_mst0_wderr + [7:0] + read-only - clk_e2_rtc - Clock E2 RTC - 0x60 + stg_sysconsaif_syscfg136 + STG SYSCONSAIF SYSCFG 136 + 0x88 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write - - - clk_divcfg - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24 - [23:0] + u0_plda_pcie_axi4_slv0_aratomop_31_0 + u0_plda_pcie_axi4_slv0_aratomop_31_0 + [31:0] read-write - clk_e2_core - Clock E2 Core - 0x64 + stg_sysconsaif_syscfg140 + STG SYSCONSAIF SYSCFG 140 + 0x8c 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + u0_plda_pcie_axi4_slv0_aratomop_63_32 + u0_plda_pcie_axi4_slv0_aratomop_63_32 + [31:0] read-write - clk_e2_dbg - Clock E2 DBG - 0x68 + stg_sysconsaif_syscfg144 + STG SYSCONSAIF SYSCFG 144 + 0x90 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + u0_plda_pcie_axi4_slv0_aratomop_95_64 + u0_plda_pcie_axi4_slv0_aratomop_95_64 + [31:0] read-write - clk_dma_axi - Clock DMA AXI - 0x6c + stg_sysconsaif_syscfg148 + STG SYSCONSAIF SYSCFG 148 + 0x94 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + u0_plda_pcie_axi4_slv0_aratomop_127_96 + u0_plda_pcie_axi4_slv0_aratomop_127_96 + [31:0] read-write - clk_dma_ahb - Clock DMA AHB - 0x70 + stg_sysconsaif_syscfg152 + STG SYSCONSAIF SYSCFG 152 + 0x98 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + u0_plda_pcie_axi4_slv0_aratomop_159_128 + u0_plda_pcie_axi4_slv0_aratomop_159_128 + [31:0] read-write - soft_rst_addr_sel - Software RESET Address Selector - 0x74 + stg_sysconsaif_syscfg156 + STG SYSCONSAIF SYSCFG 156 + 0x9c 32 - rstn_u0_stg_syscon_presetn - 1: Assert reset, 0: De-assert reset - [0:0] - read-write - - - rst_u0_hifi4_rst_core - 1: Assert reset, 0: De-assert reset - [1:1] - read-write - - - rst_u0_hifi4_rst_axi - 1: Assert reset, 0: De-assert reset - [2:2] - read-write - - - rstn_u0_sec_top_hreesetn - 1: Assert reset, 0: De-assert reset - [3:3] - read-write - - - rst_u0_e2_sft7110_rst_core - 1: Assert reset, 0: De-assert reset - [4:4] - read-write - - - rstn_u0_dma1p_8ch_56hs_rstn_axi - 1: Assert reset, 0: De-assert reset - [5:5] - read-write - - - rstn_u0_dma1p_8ch_56hs_rstn_ahb - 1: Assert reset, 0: De-assert reset - [6:6] - read-write - - - rstn_u0_cdn_usb_rstn_axi - 1: Assert reset, 0: De-assert reset - [7:7] - read-write - - - rstn_u0_cdn_usb_rstn_usb_apb - 1: Assert reset, 0: De-assert reset - [8:8] - read-write - - - rstn_u0_cdn_usb_rstn_utmi_apb - 1: Assert reset, 0: De-assert reset - [9:9] - read-write - - - rstn_u0_cdn_usb_rstn_pwrup - 1: Assert reset, 0: De-assert reset - [10:10] - read-write - - - rstn_u0_plda_pcie_rstn_axi_mst0 - 1: Assert reset, 0: De-assert reset - [11:11] - read-write - - - rstn_u0_plda_pcie_rstn_axi_slv0 - 1: Assert reset, 0: De-assert reset - [12:12] - read-write - - - rstn_u0_plda_pcie_rstn_axi_slv - 1: Assert reset, 0: De-assert reset - [13:13] - read-write - - - rstn_u0_plda_pci_rstn_brg - 1: Assert reset, 0: De-assert reset - [14:14] - read-write - - - rstn_u0_plda_pcie_rstn_pcie - 1: Assert reset, 0: De-assert reset - [15:15] - read-write - - - rstn_u0_plda_pcie_rstn_apb - 1: Assert reset, 0: De-assert reset - [16:16] - read-write - - - rstn_u1_plda_pcie_rstn_axi_mst0 - 1: Assert reset, 0: De-assert reset - [17:17] - read-write - - - rstn_u1_plda_pcie_rstn_axi_slv0 - 1: Assert reset, 0: De-assert reset - [18:18] - read-write - - - rstn_u1_plda_pcie_rstn_axi_slv - 1: Assert reset, 0: De-assert reset - [19:19] - read-write - - - rstn_u1_plda_pcie_rstn_brg - 1: Assert reset, 0: De-assert reset - [20:20] + u0_plda_pcie_axi4_slv0_aratomop_191_160 + u0_plda_pcie_axi4_slv0_aratomop_191_160 + [31:0] read-write - - rstn_u1_plda_pcie_rstn_pcie - 1: Assert reset, 0: De-assert reset - [21:21] + + + + stg_sysconsaif_syscfg160 + STG SYSCONSAIF SYSCFG 160 + 0xa0 + 32 + + + u0_plda_pcie_axi4_slv0_aratomop_223_192 + u0_plda_pcie_axi4_slv0_aratomop_223_192 + [31:0] read-write + + + + stg_sysconsaif_syscfg164 + STG SYSCONSAIF SYSCFG 164 + 0xa4 + 32 + - rstn_u1_plda_pcie_rstn_apb - 1: Assert reset, 0: De-assert reset - [22:22] + u0_plda_pcie_axi4_slv0_aratomop_255_224 + u0_plda_pcie_axi4_slv0_aratomop_255_224 + [31:0] read-write - stgcrg_rst_stat - STGCRG RESET Status - 0x78 + stg_sysconsaif_syscfg168 + STG SYSCONSAIF SYSCFG 168 + 0xa8 32 - rstn_u0_stg_syscon_presetn - 1: Assert reset, 0: De-assert reset - [0:0] + u0_plda_pcie_axi4_slv0_aratomop_257_256 + u0_plda_pcie_axi4_slv0_aratomop_257_256 + [1:0] read-write - rst_u0_hifi4_rst_core - 1: Assert reset, 0: De-assert reset - [1:1] + u0_plda_pcie_axi4_slv0_arfunc + u0_plda_pcie_axi4_slv0_arfunc + [16:2] read-write - rst_u0_hifi4_rst_axi - 1: Assert reset, 0: De-assert reset - [2:2] + u0_plda_pcie_axi4_slv0_arregion + u0_plda_pcie_axi4_slv0_arregion + [20:17] read-write + + + + stg_sysconsaif_syscfg172 + STG SYSCONSAIF SYSCFG 172 + 0xac + 32 + - rstn_u0_sec_top_hreesetn - 1: Assert reset, 0: De-assert reset - [3:3] + u0_plda_pcie_axi4_slv0_aruser_31_0 + u0_plda_pcie_axi4_slv0_aruser_31_0 + [31:0] read-write + + + + stg_sysconsaif_syscfg176 + STG SYSCONSAIF SYSCFG 176 + 0xb0 + 32 + - rst_u0_e2_sft7110_rst_core - 1: Assert reset, 0: De-assert reset - [4:4] + u0_plda_pcie_axi4_slv0_aruser_40_32 + u0_plda_pcie_axi4_slv0_aruser_40_32 + [8:0] read-write - rstn_u0_dma1p_8ch_56hs_rstn_axi - 1: Assert reset, 0: De-assert reset - [5:5] + u0_plda_pcie_axi4_slv0_awfunc + u0_plda_pcie_axi4_slv0_awfunc + [23:9] read-write - rstn_u0_dma1p_8ch_56hs_rstn_ahb - 1: Assert reset, 0: De-assert reset - [6:6] + u0_plda_pcie_axi4_slv0_awregion + u0_plda_pcie_axi4_slv0_awregion + [27:24] read-write + + + + stg_sysconsaif_syscfg180 + STG SYSCONSAIF SYSCFG 180 + 0xb4 + 32 + - rstn_u0_cdn_usb_rstn_axi - 1: Assert reset, 0: De-assert reset - [7:7] + u0_plda_pcie_axi4_slv0_awuser_31_0 + u0_plda_pcie_axi4_slv0_awuser_31_0 + [31:0] read-write + + + + stg_sysconsaif_syscfg184 + STG SYSCONSAIF SYSCFG 184 + 0xb8 + 32 + - rstn_u0_cdn_usb_rstn_usb_apb - 1: Assert reset, 0: De-assert reset - [8:8] + u0_plda_pcie_axi4_slv0_awuser_40_32 + u0_plda_pcie_axi4_slv0_awuser_40_32 + [8:0] read-write - rstn_u0_cdn_usb_rstn_utmi_apb - 1: Assert reset, 0: De-assert reset - [9:9] - read-write + u0_plda_pcie_axi4_slv0_rderr + u0_plda_pcie_axi4_slv0_rderr + [16:9] + read-only + + + + stg_sysconsaif_syscfg188 + STG SYSCONSAIF SYSCFG 188 + 0xbc + 32 + - rstn_u0_cdn_usb_rstn_pwrup - 1: Assert reset, 0: De-assert reset - [10:10] - read-write + u0_plda_pcie_axi4_slv0_ruser + u0_plda_pcie_axi4_slv0_ruser + [31:0] + read-only + + + + stg_sysconsaif_syscfg192 + STG SYSCONSAIF SYSCFG 192 + 0xc0 + 32 + - rstn_u0_plda_pcie_rstn_axi_mst0 - 1: Assert reset, 0: De-assert reset - [11:11] + u0_plda_pcie_axi4_slv0_wderr + u0_plda_pcie_axi4_slv0_wderr + [7:0] read-write - rstn_u0_plda_pcie_rstn_axi_slv0 - 1: Assert reset, 0: De-assert reset - [12:12] - read-write + u0_plda_pcie_axi4_slvl_arfunc + u0_plda_pcie_axi4_slvl_arfunc + [22:8] + read-only + + + + stg_sysconsaif_syscfg196 + STG SYSCONSAIF SYSCFG 196 + 0xc4 + 32 + - rstn_u0_plda_pcie_rstn_axi_slv - 1: Assert reset, 0: De-assert reset - [13:13] + u0_plda_pcie_axi4_slvl_awfunc + u0_plda_pcie_axi4_slvl_awfunc + [14:0] read-write - rstn_u0_plda_pci_rstn_brg - 1: Assert reset, 0: De-assert reset - [14:14] + u0_plda_pcie_bus_width_o + u0_plda_pcie_bus_width_o + [16:15] + read-only + + + u0_plda_pcie_bypass_codec + u0_plda_pcie_bypass_codec + [17:17] read-write - rstn_u0_plda_pcie_rstn_pcie - 1: Assert reset, 0: De-assert reset - [15:15] + u0_plda_pcie_ckref_src + u0_plda_pcie_ckref_src + [19:18] read-write - rstn_u0_plda_pcie_rstn_apb - 1: Assert reset, 0: De-assert reset - [16:16] + u0_plda_pcie_clk_sel + u0_plda_pcie_clk_sel + [21:20] read-write - rstn_u1_plda_pcie_rstn_axi_mst0 - 1: Assert reset, 0: De-assert reset - [17:17] + u0_plda_pcie_clkreq + u0_plda_pcie_clkreq + [22:22] read-write + + + + stg_sysconsaif_syscfg200 + STG SYSCONSAIF SYSCFG 200 + 0xc8 + 32 + - rstn_u1_plda_pcie_rstn_axi_slv0 - 1: Assert reset, 0: De-assert reset - [18:18] + u0_plda_pcie_k_phyparam_31_0 + u0_plda_pcie_k_phyparam_31_0 + [31:0] read-write + + + + stg_sysconsaif_syscfg204 + STG SYSCONSAIF SYSCFG 204 + 0xcc + 32 + - rstn_u1_plda_pcie_rstn_axi_slv - 1: Assert reset, 0: De-assert reset - [19:19] + u0_plda_pcie_k_phyparam_63_32 + u0_plda_pcie_k_phyparam_63_32 + [31:0] read-write + + + + stg_sysconsaif_syscfg208 + STG SYSCONSAIF SYSCFG 208 + 0xd0 + 32 + - rstn_u1_plda_pcie_rstn_brg - 1: Assert reset, 0: De-assert reset - [20:20] + u0_plda_pcie_k_phyparam_95_64 + u0_plda_pcie_k_phyparam_95_64 + [31:0] read-write + + + + stg_sysconsaif_syscfg212 + STG SYSCONSAIF SYSCFG 212 + 0xd4 + 32 + - rstn_u1_plda_pcie_rstn_pcie - 1: Assert reset, 0: De-assert reset - [21:21] + u0_plda_pcie_k_phyparam_127_96 + u0_plda_pcie_k_phyparam_127_96 + [31:0] read-write + + + + stg_sysconsaif_syscfg216 + STG SYSCONSAIF SYSCFG 216 + 0xd8 + 32 + - rstn_u1_plda_pcie_rstn_apb - 1: Assert reset, 0: De-assert reset - [22:22] + u0_plda_pcie_k_phyparam_159_128 + u0_plda_pcie_k_phyparam_159_128 + [31:0] read-write - - - - starfive_jh7110_stg_syscon_0 - From starfive,jh7110-stg-syscon, peripheral generator - 0x10240000 - - 0 - 0x1000 - registers - - - stg_sysconsaif_syscfg0 - STG SYSCONSAIF SYSCFG 0 - 0x0 + stg_sysconsaif_syscfg220 + STG SYSCONSAIF SYSCFG 220 + 0xdc 32 - scfg_hprot_sd0 - scfg_hprot_sd0 - [3:0] + u0_plda_pcie_k_phyparam_191_160 + u0_plda_pcie_k_phyparam_191_160 + [31:0] read-write + + + + stg_sysconsaif_syscfg224 + STG SYSCONSAIF SYSCFG 224 + 0xe0 + 32 + - scfg_hprot_sd1 - scfg_hprot_sd1 - [7:4] + u0_plda_pcie_k_phyparam_223_192 + u0_plda_pcie_k_phyparam_223_192 + [31:0] read-write + + + + stg_sysconsaif_syscfg228 + STG SYSCONSAIF SYSCFG 228 + 0xe4 + 32 + - u0_cdn_usb_adp_en - u0_cdn_usb_adp_en - [8:8] - read-only - - - u0_cdn_usb_adp_probe_ana - u0_cdn_usb_adp_probe_ana - [9:9] + u0_plda_pcie_k_phyparam_255_224 + u0_plda_pcie_k_phyparam_255_224 + [31:0] read-write + + + + stg_sysconsaif_syscfg232 + STG SYSCONSAIF SYSCFG 232 + 0xe8 + 32 + - u0_cdn_usb_adp_probe_en - u0_cdn_usb_adp_probe_en - [10:10] - read-only - - - u0_cdn_usb_adp_sense_ana - u0_cdn_usb_adp_sense_ana - [11:11] + u0_plda_pcie_k_phyparam_287_256 + u0_plda_pcie_k_phyparam_287_256 + [31:0] read-write + + + + stg_sysconsaif_syscfg236 + STG SYSCONSAIF SYSCFG 236 + 0xec + 32 + - u0_cdn_usb_adp_sense_en - u0_cdn_usb_adp_sense_en - [12:12] - read-only - - - u0_cdn_usb_adp_sink_current_en - u0_cdn_usb_adp_sink_current_en - [13:13] - read-only - - - u0_cdn_usb_adp_source_current_en - u0_cdn_usb_adp_source_current_en - [14:14] - read-only - - - u0_cdn_usb_bc_en - u0_cdn_usb_bc_en - [15:15] - read-only + u0_plda_pcie_k_phyparam_319_288 + u0_plda_pcie_k_phyparam_319_288 + [31:0] + read-write + + + + stg_sysconsaif_syscfg240 + STG SYSCONSAIF SYSCFG 240 + 0xf0 + 32 + - u0_cdn_usb_chrg_vbus - u0_cdn_usb_chrg_vbus - [16:16] + u0_plda_pcie_k_phyparam_351_320 + u0_plda_pcie_k_phyparam_351_320 + [31:0] read-write + + + + stg_sysconsaif_syscfg244 + STG SYSCONSAIF SYSCFG 244 + 0xf4 + 32 + - u0_cdn_usb_dcd_comp_sts - u0_cdn_usb_dcd_comp_sts - [17:17] + u0_plda_pcie_k_phyparam_383_352 + u0_plda_pcie_k_phyparam_383_352 + [31:0] read-write + + + + stg_sysconsaif_syscfg248 + STG SYSCONSAIF SYSCFG 248 + 0xf8 + 32 + - u0_cdn_usb_dischrg_vbus - u0_cdn_usb_dischrg_vbus - [18:18] + u0_plda_pcie_k_phyparam_415_384 + u0_plda_pcie_k_phyparam_415_384 + [31:0] read-write + + + + stg_sysconsaif_syscfg252 + STG SYSCONSAIF SYSCFG 252 + 0xfc + 32 + - u0_cdn_usb_dm_vdat_ref_comp_en - u0_cdn_usb_dm_vdat_ref_comp_en - [19:19] - read-only + u0_plda_pcie_k_phyparam_447_416 + u0_plda_pcie_k_phyparam_447_416 + [31:0] + read-write + + + + stg_sysconsaif_syscfg256 + STG SYSCONSAIF SYSCFG 256 + 0x100 + 32 + - u0_cdn_usb_dm_vdat_ref_comp_sts - u0_cdn_usb_dm_vdat_ref_comp_sts - [20:20] + u0_plda_pcie_k_phyparam_479_448 + u0_plda_pcie_k_phyparam_479_448 + [31:0] read-write + + + + stg_sysconsaif_syscfg260 + STG SYSCONSAIF SYSCFG 260 + 0x104 + 32 + - u0_cdn_usb_dm_vlgc_comp_en - u0_cdn_usb_dm_vlgc_comp_en - [21:21] - read-only + u0_plda_pcie_k_phyparam_511_480 + u0_plda_pcie_k_phyparam_511_480 + [31:0] + read-write + + + + stg_sysconsaif_syscfg264 + STG SYSCONSAIF SYSCFG 264 + 0x108 + 32 + - u0_cdn_usb_dm_vlgc_comp_sts - u0_cdn_usb_dm_vlgc_comp_sts - [22:22] + u0_plda_pcie_k_phyparam_543_512 + u0_plda_pcie_k_phyparam_543_512 + [31:0] read-write + + + + stg_sysconsaif_syscfg268 + STG SYSCONSAIF SYSCFG 268 + 0x10c + 32 + - u0_cdn_usb_dp_vdat_ref_comp_en - u0_cdn_usb_dp_vdat_ref_comp_en - [23:23] - read-only + u0_plda_pcie_k_phyparam_575_544 + u0_plda_pcie_k_phyparam_575_544 + [31:0] + read-write - - u0_cdn_usb_dp_vdat_ref_comp_sts - u0_cdn_usb_dp_vdat_ref_comp_sts - [24:24] + + + + stg_sysconsaif_syscfg272 + STG SYSCONSAIF SYSCFG 272 + 0x110 + 32 + + + u0_plda_pcie_k_phyparam_607_576 + u0_plda_pcie_k_phyparam_607_576 + [31:0] read-write + + + + stg_sysconsaif_syscfg276 + STG SYSCONSAIF SYSCFG 276 + 0x114 + 32 + - u0_cdn_usb_host_system_err - u0_cdn_usb_host_system_err - [25:25] + u0_plda_pcie_k_phyparam_639_608 + u0_plda_pcie_k_phyparam_639_608 + [31:0] read-write + + + + stg_sysconsaif_syscfg280 + STG SYSCONSAIF SYSCFG 280 + 0x118 + 32 + - u0_cdn_usb_hsystem_err_ext - u0_cdn_usb_hsystem_err_ext - [26:26] - read-only + u0_plda_pcie_k_phyparam_671_640 + u0_plda_pcie_k_phyparam_671_640 + [31:0] + read-write + + + + stg_sysconsaif_syscfg284 + STG SYSCONSAIF SYSCFG 284 + 0x11c + 32 + - u0_cdn_usb_idm_sink_en - u0_cdn_usb_idm_sink_en - [27:27] - read-only + u0_plda_pcie_k_phyparam_703_672 + u0_plda_pcie_k_phyparam_703_672 + [31:0] + read-write + + + + stg_sysconsaif_syscfg288 + STG SYSCONSAIF SYSCFG 288 + 0x120 + 32 + - u0_cdn_usb_idp_sink_en - u0_cdn_usb_idp_sink_en - [28:28] - read-only + u0_plda_pcie_k_phyparam_735_704 + u0_plda_pcie_k_phyparam_735_704 + [31:0] + read-write + + + + stg_sysconsaif_syscfg292 + STG SYSCONSAIF SYSCFG 292 + 0x124 + 32 + - u0_cdn_usb_idp_src_en - u0_cdn_usb_idp_src_en - [29:29] - read-only + u0_plda_pcie_k_phyparam_767_736 + u0_plda_pcie_k_phyparam_767_736 + [31:0] + read-write - stg_sysconsaif_syscfg4 - STG SYSCONSAIF SYSCFG 4 - 0x4 + stg_sysconsaif_syscfg296 + STG SYSCONSAIF SYSCFG 296 + 0x128 32 - u0_cdn_usb_lowest_belt - LTM interface to software - [11:0] - read-only + u0_plda_pcie_k_phyparam_799_768 + u0_plda_pcie_k_phyparam_799_768 + [31:0] + read-write + + + + stg_sysconsaif_syscfg300 + STG SYSCONSAIF SYSCFG 300 + 0x12c + 32 + - u0_cdn_usb_ltm_host_req - LTM interface to software - [12:12] - read-only + u0_plda_pcie_k_phyparam_831_800 + u0_plda_pcie_k_phyparam_831_800 + [31:0] + read-write + + + + stg_sysconsaif_syscfg304 + STG SYSCONSAIF SYSCFG 304 + 0x130 + 32 + - u0_cdn_usb_ltm_host_req_halt - LTM interface to software - [13:13] + u0_plda_pcie_k_phyparam_839_832 + u0_plda_pcie_k_phyparam_839_832 + [7:0] read-write - u0_cdn_usb_mdctrl_clk_sel - u0_cdn_usb_mdctrl_clk_sel - [14:14] + u0_plda_pcie_k_rp_nep + u0_plda_pcie_k_rp_nep + [8:8] read-write - u0_cdn_usb_mdctrl_clk_status - u0_cdn_usb_mdctrl_clk_status - [15:15] + u0_plda_pcie_l1sub_entack + u0_plda_pcie_l1sub_entack + [9:9] read-only - u0_cdn_usb_mode_strap - Can onlly be changed when pwrup_rst_n is low - [18:16] - read-write - - - u0_cdn_usb_otg_suspendm - u0_cdn_usb_otg_suspendm - [19:19] + u0_plda_pcie_l1sub_entreq + u0_plda_pcie_l1sub_entreq + [10:10] read-write + + + + stg_sysconsaif_syscfg308 + STG SYSCONSAIF SYSCFG 308 + 0x134 + 32 + - u0_cdn_usb_otg_suspendm_byps - u0_cdn_usb_otg_suspendm_byps - [20:20] + u0_plda_pcie_local_interrupt_in + u0_plda_pcie_local_interrupt_in + [31:0] read-write + + + + stg_sysconsaif_syscfg312 + STG SYSCONSAIF SYSCFG 312 + 0x138 + 32 + - u0_cdn_usb_phy_bvalid - u0_cdn_usb_phy_bvalid - [21:21] - read-only - - - u0_cdn_usb_pll_en - u0_cdn_usb_pll_en - [22:22] + u0_plda_pcie_mperstn + u0_plda_pcie_mperstn + [0:0] read-write - u0_cdn_usb_refclk_mode - u0_cdn_usb_refclk_mode - [23:23] + u0_plda_pcie_pcie_ebuf_mode + u0_plda_pcie_pcie_ebuf_mode + [1:1] read-write - u0_cdn_usb_rid_a_comp_sts - u0_cdn_usb_rid_a_comp_sts - [24:24] + u0_plda_pcie_pcie_phy_test_cfg + u0_plda_pcie_pcie_phy_test_cfg + [24:2] read-write - u0_cdn_usb_rid_b_comp_sts - u0_cdn_usb_rid_b_comp_sts + u0_plda_pcie_pcie_rx_eq_training + u0_plda_pcie_pcie_rx_eq_training [25:25] read-write - u0_cdn_usb_rid_c_comp_sts - u0_cdn_usb_rid_c_comp_sts + u0_plda_pcie_pcie_rxterm_en + u0_plda_pcie_pcie_rxterm_en [26:26] read-write - u0_cdn_usb_rid_float_comp_en - u0_cdn_usb_rid_float_comp_en + u0_plda_pcie_pcie_tx_onezeros + u0_plda_pcie_pcie_tx_onezeros [27:27] - read-only - - - u0_cdn_usb_rid_float_comp_sts - u0_cdn_usb_rid_float_comp_sts - [28:28] read-write + + + + stg_sysconsaif_syscfg316 + STG SYSCONSAIF SYSCFG 316 + 0x13c + 32 + - u0_cdn_usb_rid_gnd_comp_sts - u0_cdn_usb_rid_gnd_comp_sts - [29:29] + u0_plda_pcie_pf0_offset + u0_plda_pcie_pf0_offset + [19:0] read-write + + + + stg_sysconsaif_syscfg320 + STG SYSCONSAIF SYSCFG 320 + 0x140 + 32 + - u0_cdn_usb_rid_nonfloat_comp_en - u0_cdn_usb_rid_nonfloat_comp_en - [30:30] - read-only + u0_plda_pcie_pf1_offset + u0_plda_pcie_pf1_offset + [19:0] + read-write - - u0_cdn_usb_rx_dm - u0_cdn_usb_rx_dm - [31:31] - read-only + + + + stg_sysconsaif_syscfg324 + STG SYSCONSAIF SYSCFG 324 + 0x144 + 32 + + + u0_plda_pcie_pf2_offset + u0_plda_pcie_pf2_offset + [19:0] + read-write - stg_sysconsaif_syscfg8 - STG SYSCONSAIF SYSCFG 8 - 0x8 + stg_sysconsaif_syscfg328 + STG SYSCONSAIF SYSCFG 328 + 0x148 32 - u0_cdn_usb_rx_dp - u0_cdn_usb_rx_dp - [0:0] - read-only + u0_plda_pcie_pf3_offset + u0_plda_pcie_pf3_offset + [19:0] + read-write - u0_cdn_usb_rx_rcv - u0_cdn_usb_rx_rcv - [1:1] - read-only + u0_plda_pcie_phy_mode + u0_plda_pcie_phy_mode + [21:20] + read-write - u0_cdn_usb_self_test - For software bist_test - [2:2] + u0_plda_pcie_pl_clkrem_allow + u0_plda_pcie_pl_clkrem_allow + [22:22] read-write - u0_cdn_usb_sessend - u0_cdn_usb_sessend - [3:3] + u0_plda_pcie_pl_clkreq_oen + u0_plda_pcie_pl_clkreq_oen + [23:23] read-only - u0_cdn_usb_sessvalid - u0_cdn_usb_sessvalid - [4:4] + u0_plda_pcie_pl_equ_phase + u0_plda_pcie_pl_equ_phase + [25:24] read-only - u0_cdn_usb_sof - u0_cdn_usb_sof - [5:5] + u0_plda_pcie_pl_ltssm + u0_plda_pcie_pl_ltssm + [30:26] read-only + + + + stg_sysconsaif_syscfg332 + STG SYSCONSAIF SYSCFG 332 + 0x14c + 32 + - u0_cdn_usb_test_bist - For software bist_test - [6:6] + u0_plda_pcie_pl_pclk_rate + u0_plda_pcie_pl_pclk_rate + [4:0] read-only + + + + stg_sysconsaif_syscfg336 + STG SYSCONSAIF SYSCFG 336 + 0x150 + 32 + - u0_cdn_usb_usbdev_main_power_off_ack - u0_cdn_usb_usbdev_main_power_off_ack - [7:7] + u0_plda_pcie_pl_sideband_in_31_0 + u0_plda_pcie_pl_sideband_in_31_0 + [31:0] read-only + + + + stg_sysconsaif_syscfg340 + STG SYSCONSAIF SYSCFG 340 + 0x154 + 32 + - u0_cdn_usb_usbdev_main_power_off_ready - u0_cdn_usb_usbdev_main_power_off_ready - [8:8] + u0_plda_pcie_pl_sideband_in_63_32 + u0_plda_pcie_pl_sideband_in_63_32 + [31:0] read-only + + + + stg_sysconsaif_syscfg344 + STG SYSCONSAIF SYSCFG 344 + 0x158 + 32 + - u0_cdn_usb_usbdev_main_power_off_req - u0_cdn_usb_usbdev_main_power_off_req - [9:9] - read-write - - - u0_cdn_usb_usbdev_main_power_on_ready - u0_cdn_usb_usbdev_main_power_on_ready - [10:10] + u0_plda_pcie_pl_sideband_out_31_0 + u0_plda_pcie_pl_sideband_out_31_0 + [31:0] read-only + + + + stg_sysconsaif_syscfg348 + STG SYSCONSAIF SYSCFG 348 + 0x15c + 32 + - u0_cdn_usb_usbdev_main_power_on_req - u0_cdn_usb_usbdev_main_power_on_req - [11:11] + u0_plda_pcie_pl_sideband_out_63_32 + u0_plda_pcie_pl_sideband_out_63_32 + [31:0] read-only + + + + stg_sysconsaif_syscfg352 + STG SYSCONSAIF SYSCFG 352 + 0x160 + 32 + - u0_cdn_usb_usbdev_main_power_on_valid - u0_cdn_usb_usbdev_main_power_on_valid - [12:12] + u0_plda_pcie_pl_wake_in + u0_plda_pcie_pl_wake_in + [0:0] read-write - u0_cdn_usb_usbdev_power_off_ack - u0_cdn_usb_usbdev_power_off_ack - [13:13] + u0_plda_pcie_pl_wake_oen + u0_plda_pcie_pl_wake_oen + [1:1] read-only - u0_cdn_usb_usbdev_power_off_ready - u0_cdn_usb_usbdev_power_off_ready - [14:14] + u0_plda_pcie_rx_standby_0 + u0_plda_pcie_rx_standby_0 + [2:2] read-only + + + + stg_sysconsaif_syscfg356 + STG SYSCONSAIF SYSCFG 356 + 0x164 + 32 + - u0_cdn_usb_usbdev_power_off_req - u0_cdn_usb_usbdev_power_off_req - [15:15] + u0_plda_pcie_test_in_31_0 + u0_plda_pcie_test_in_31_0 + [31:0] read-write + + + + stg_sysconsaif_syscfg360 + STG SYSCONSAIF SYSCFG 360 + 0x168 + 32 + - u0_cdn_usb_usbdev_power_on_ready - u0_cdn_usb_usbdev_power_on_ready - [16:16] + u0_plda_pcie_test_in_63_32 + u0_plda_pcie_test_in_63_32 + [31:0] + read-write + + + + + stg_sysconsaif_syscfg364 + STG SYSCONSAIF SYSCFG 364 + 0x16c + 32 + + + u0_plda_pcie_test_out_bridge_31_0 + u0_plda_pcie_test_out_bridge_31_0 + [31:0] read-only + + + + stg_sysconsaif_syscfg368 + STG SYSCONSAIF SYSCFG 368 + 0x170 + 32 + - u0_cdn_usb_usbdev_power_on_req - u0_cdn_usb_usbdev_power_on_req - [17:17] + u0_plda_pcie_test_out_bridge_63_32 + u0_plda_pcie_test_out_bridge_63_32 + [31:0] read-only + + + + stg_sysconsaif_syscfg372 + STG SYSCONSAIF SYSCFG 372 + 0x174 + 32 + - u0_cdn_usb_usbdev_power_on_valid - u0_cdn_usb_usbdev_power_on_valid - [18:18] - read-write + u0_plda_pcie_test_out_bridge_95_64 + u0_plda_pcie_test_out_bridge_95_64 + [31:0] + read-only + + + + stg_sysconsaif_syscfg376 + STG SYSCONSAIF SYSCFG 376 + 0x178 + 32 + - u0_cdn_usb_utmi_dmpulldown_sit - u0_cdn_usb_utmi_dmpulldown_sit - [19:19] - read-write + u0_plda_pcie_test_out_bridge_127_96 + u0_plda_pcie_test_out_bridge_127_96 + [31:0] + read-only + + + + stg_sysconsaif_syscfg380 + STG SYSCONSAIF SYSCFG 380 + 0x17c + 32 + - u0_cdn_usb_utmi_dppulldown_sit - u0_cdn_usb_utmi_dppulldown_sit - [20:20] - read-write + u0_plda_pcie_test_out_bridge_159_128 + u0_plda_pcie_test_out_bridge_159_128 + [31:0] + read-only + + + + stg_sysconsaif_syscfg384 + STG SYSCONSAIF SYSCFG 384 + 0x180 + 32 + - u0_cdn_usb_utmi_fslsserialmode_sit - u0_cdn_usb_utmi_fslsserialmode_sit - [21:21] - read-write + u0_plda_pcie_test_out_bridge_191_160 + u0_plda_pcie_test_out_bridge_191_160 + [31:0] + read-only + + + + stg_sysconsaif_syscfg388 + STG SYSCONSAIF SYSCFG 388 + 0x184 + 32 + - u0_cdn_usb_utmi_hostdisconnect_sit - u0_cdn_usb_utmi_hostdisconnect_sit - [22:22] + u0_plda_pcie_test_out_bridge_223_192 + u0_plda_pcie_test_out_bridge_223_192 + [31:0] read-only + + + + stg_sysconsaif_syscfg392 + STG SYSCONSAIF SYSCFG 392 + 0x188 + 32 + - u0_cdn_usb_utmi_iddig_sit - u0_cdn_usb_utmi_iddig_sit - [23:23] + u0_plda_pcie_test_out_bridge_255_224 + u0_plda_pcie_test_out_bridge_255_224 + [31:0] read-only + + + + stg_sysconsaif_syscfg396 + STG SYSCONSAIF SYSCFG 396 + 0x18c + 32 + - u0_cdn_usb_utmi_idpullup_sit - u0_cdn_usb_utmi_idpullup_sit - [24:24] - read-write + u0_plda_pcie_test_out_bridge_287_256 + u0_plda_pcie_test_out_bridge_287_256 + [31:0] + read-only + + + + stg_sysconsaif_syscfg400 + STG SYSCONSAIF SYSCFG 400 + 0x190 + 32 + - u0_cdn_usb_utmi_linestate_sit - u0_cdn_usb_utmi_linestate_sit - [26:25] + u0_plda_pcie_test_out_bridge_319_288 + u0_plda_pcie_test_out_bridge_319_288 + [31:0] read-only + + + + stg_sysconsaif_syscfg404 + STG SYSCONSAIF SYSCFG 404 + 0x194 + 32 + - u0_cdn_usb_utmi_opmode_sit - u0_cdn_usb_utmi_opmode_sit - [28:27] - read-write + u0_plda_pcie_test_out_bridge_351_320 + u0_plda_pcie_test_out_bridge_351_320 + [31:0] + read-only + + + + stg_sysconsaif_syscfg408 + STG SYSCONSAIF SYSCFG 408 + 0x198 + 32 + - u0_cdn_usb_utmi_rxactive_sit - u0_cdn_usb_utmi_rxactive_sit - [29:29] + u0_plda_pcie_test_out_bridge_383_352 + u0_plda_pcie_test_out_bridge_383_352 + [31:0] read-only + + + + stg_sysconsaif_syscfg412 + STG SYSCONSAIF SYSCFG 412 + 0x19c + 32 + - u0_cdn_usb_utmi_rxerror_sit - u0_cdn_usb_utmi_rxerror_sit - [30:30] + u0_plda_pcie_test_out_bridge_415_384 + u0_plda_pcie_test_out_bridge_415_384 + [31:0] read-only + + + + stg_sysconsaif_syscfg416 + STG SYSCONSAIF SYSCFG 416 + 0x1a0 + 32 + - u0_cdn_usb_utmi_rxvalid_sit - u0_cdn_usb_utmi_rxvalid_sit - [31:31] + u0_plda_pcie_test_out_bridge_447_416 + u0_plda_pcie_test_out_bridge_447_416 + [31:0] read-only - stg_sysconsaif_syscfg12 - STG SYSCONSAIF SYSCFG 12 - 0xc + stg_sysconsaif_syscfg420 + STG SYSCONSAIF SYSCFG 420 + 0x1a4 32 - u0_cdn_usb_utmi_rxvalidh_sit - u0_cdn_usb_utmi_rxvalidh_sit - [0:0] + u0_plda_pcie_test_out_bridge_479_448 + u0_plda_pcie_test_out_bridge_479_448 + [31:0] read-only + + + + stg_sysconsaif_syscfg424 + STG SYSCONSAIF SYSCFG 424 + 0x1a8 + 32 + - u0_cdn_usb_utmi_sessvld - u0_cdn_usb_utmi_sessvld - [1:1] - read-write + u0_plda_pcie_test_out_bridge_511_480 + u0_plda_pcie_test_out_bridge_511_480 + [31:0] + read-only + + + + stg_sysconsaif_syscfg428 + STG SYSCONSAIF SYSCFG 428 + 0x1ac + 32 + - u0_cdn_usb_utmi_termselect_sit - u0_cdn_usb_utmi_termselect_sit - [2:2] - read-write + u0_plda_pcie_test_out_pcie_31_0 + u0_plda_pcie_test_out_pcie_31_0 + [31:0] + read-only + + + + stg_sysconsaif_syscfg432 + STG SYSCONSAIF SYSCFG 432 + 0x1b0 + 32 + - u0_cdn_usb_utmi_tx_dat_sit - u0_cdn_usb_utmi_tx_dat_sit - [3:3] - read-write + u0_plda_pcie_test_out_pcie_63_32 + u0_plda_pcie_test_out_pcie_63_32 + [31:0] + read-only + + + + stg_sysconsaif_syscfg436 + STG SYSCONSAIF SYSCFG 436 + 0x1b4 + 32 + - u0_cdn_usb_utmi_tx_enable_n_sit - u0_cdn_usb_utmi_tx_enable_n_sit - [4:4] - read-write + u0_plda_pcie_test_out_pcie_95_64 + u0_plda_pcie_test_out_pcie_95_64 + [31:0] + read-only + + + + stg_sysconsaif_syscfg440 + STG SYSCONSAIF SYSCFG 440 + 0x1b8 + 32 + - u0_cdn_usb_utmi_tx_se0_sit - u0_cdn_usb_utmi_tx_se0_sit - [5:5] - read-write + u0_plda_pcie_test_out_pcie_127_96 + u0_plda_pcie_test_out_pcie_127_96 + [31:0] + read-only + + + + stg_sysconsaif_syscfg444 + STG SYSCONSAIF SYSCFG 444 + 0x1bc + 32 + - u0_cdn_usb_utmi_txbitstuffenable_sit - u0_cdn_usb_utmi_txbitstuffenable_sit - [6:6] - read-write + u0_plda_pcie_test_out_pcie_159_128 + u0_plda_pcie_test_out_pcie_159_128 + [31:0] + read-only + + + + stg_sysconsaif_syscfg448 + STG SYSCONSAIF SYSCFG 448 + 0x1c0 + 32 + - u0_cdn_usb_utmi_txready_sit - u0_cdn_usb_utmi_txready_sit - [7:7] + u0_plda_pcie_test_out_pcie_191_160 + u0_plda_pcie_test_out_pcie_191_160 + [31:0] read-only + + + + stg_sysconsaif_syscfg452 + STG SYSCONSAIF SYSCFG 452 + 0x1c4 + 32 + - u0_cdn_usb_utmi_txvalid_sit - u0_cdn_usb_utmi_txvalid_sit - [8:8] - read-write + u0_plda_pcie_test_out_pcie_223_192 + u0_plda_pcie_test_out_pcie_223_192 + [31:0] + read-only + + + + stg_sysconsaif_syscfg456 + STG SYSCONSAIF SYSCFG 456 + 0x1c8 + 32 + - u0_cdn_usb_utmi_txvalidh_sit - u0_cdn_usb_utmi_txvalidh_sit - [9:9] - read-write + u0_plda_pcie_test_out_pcie_255_224 + u0_plda_pcie_test_out_pcie_255_224 + [31:0] + read-only + + + + stg_sysconsaif_syscfg460 + STG SYSCONSAIF SYSCFG 460 + 0x1cc + 32 + - u0_cdn_usb_utmi_vbusvalid_sit - u0_cdn_usb_utmi_vbusvalid_sit - [10:10] + u0_plda_pcie_test_out_pcie_287_256 + u0_plda_pcie_test_out_pcie_287_256 + [31:0] read-only + + + + stg_sysconsaif_syscfg464 + STG SYSCONSAIF SYSCFG 464 + 0x1d0 + 32 + - u0_cdn_usb_utmi_xcvrselect_sit - u0_cdn_usb_utmi_xcvrselect_sit - [12:11] - read-write + u0_plda_pcie_test_out_pcie_319_288 + u0_plda_pcie_test_out_pcie_319_288 + [31:0] + read-only + + + + stg_sysconsaif_syscfg468 + STG SYSCONSAIF SYSCFG 468 + 0x1d4 + 32 + - u0_cdn_usb_utmi_vdm_src_en - u0_cdn_usb_utmi_vdm_src_en - [13:13] + u0_plda_pcie_test_out_pcie_351_320 + u0_plda_pcie_test_out_pcie_351_320 + [31:0] read-only + + + + stg_sysconsaif_syscfg472 + STG SYSCONSAIF SYSCFG 472 + 0x1d8 + 32 + - u0_cdn_usb_utmi_vdp_src_en - u0_cdn_usb_utmi_vdp_src_en - [14:14] + u0_plda_pcie_test_out_pcie_383_352 + u0_plda_pcie_test_out_pcie_383_352 + [31:0] read-only + + + + stg_sysconsaif_syscfg476 + STG SYSCONSAIF SYSCFG 476 + 0x1dc + 32 + - u0_cdn_usb_wakeup - u0_cdn_usb_wakeup - [15:15] - read-write + u0_plda_pcie_test_out_pcie_415_384 + u0_plda_pcie_test_out_pcie_415_384 + [31:0] + read-only + + + + stg_sysconsaif_syscfg480 + STG SYSCONSAIF SYSCFG 480 + 0x1e0 + 32 + - u0_cdn_usb_xhc_d0_ack - u0_cdn_usb_xhc_d0_ack - [16:16] + u0_plda_pcie_test_out_pcie_447_416 + u0_plda_pcie_test_out_pcie_447_416 + [31:0] read-only + + + + stg_sysconsaif_syscfg484 + STG SYSCONSAIF SYSCFG 484 + 0x1e4 + 32 + - u0_cdn_usb_xhc_d0_req - u0_cdn_usb_xhc_d0_req - [17:17] - read-write + u0_plda_pcie_test_out_pcie_479_448 + u0_plda_pcie_test_out_pcie_479_448 + [31:0] + read-only - stg_sysconsaif_syscfg16 - STG SYSCONSAIF SYSCFG 16 - 0x10 + stg_sysconsaif_syscfg488 + STG SYSCONSAIF SYSCFG 488 + 0x1e8 32 - u0_cdn_usb_xhci_debug_bus - u0_cdn_usb_xhci_debug_bus + u0_plda_pcie_test_out_pcie_511_480 + u0_plda_pcie_test_out_pcie_511_480 [31:0] read-only - stg_sysconsaif_syscfg20 - STG SYSCONSAIF SYSCFG 20 - 0x14 + stg_sysconsaif_syscfg492 + STG SYSCONSAIF SYSCFG 492 + 0x1ec 32 - u0_cdn_usb_xhci_debug_link_state - u0_cdn_usb_xhci_debug_link_state - [30:0] - read-only + u0_plda_pcie_test_sel + u0_plda_pcie_test_sel + [3:0] + read-write + + + u0_plda_pcie_tl_clock_freq + u0_plda_pcie_tl_clock_freq + [25:4] + read-write - stg_sysconsaif_syscfg24 - STG SYSCONSAIF SYSCFG 24 - 0x18 + stg_sysconsaif_syscfg500 + STG SYSCONSAIF SYSCFG 500 + 0x1f4 32 - u0_cdn_usb_xhci_debug_sel - u0_cdn_usb_xhci_debug_sel - [4:0] + u0_plda_pcie_tx_pattern + u0_plda_pcie_tx_pattern + [1:0] read-write - u0_cdn_usb_xhci_main_power_off_ack - u0_cdn_usb_xhci_main_power_off_ack - [5:5] - read-only + u0_plda_pcie_usb3_bus_width + u0_plda_pcie_usb3_bus_width + [3:2] + read-write - u0_cdn_usb_xhci_main_power_off_req - u0_cdn_usb_xhci_main_power_off_req - [6:6] - read-only + u0_plda_pcie_usb3_phy_enable + u0_plda_pcie_usb3_phy_enable + [4:4] + read-write - u0_cdn_usb_xhci_main_power_on_ready - u0_cdn_usb_xhci_main_power_on_ready + u0_plda_pcie_usb3_rate + u0_plda_pcie_usb3_rate + [6:5] + read-write + + + u0_plda_pcie_usb3_rx_standby + u0_plda_pcie_usb3_rx_standby [7:7] read-write - u0_cdn_usb_xhci_main_power_on_req - u0_cdn_usb_xhci_main_power_on_req + u0_plda_pcie_xwdecerr + u0_plda_pcie_xwdecerr [8:8] read-only - u0_cdn_usb_xhci_main_power_on_valid - u0_cdn_usb_xhci_main_power_on_valid + u0_plda_pcie_xwerrclr + u0_plda_pcie_xwerrclr [9:9] read-write - u0_cdn_usb_xhci_power_off_ack - u0_cdn_usb_xhci_power_off_ack + u0_plda_pcie_xwslverr + u0_plda_pcie_xwslverr [10:10] read-only - u0_cdn_usb_xhci_power_off_ready - u0_cdn_usb_xhci_power_off_ready + u0_sec_top_sramcfg_slp + SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [11:11] - read-only + read-write - u0_cdn_usb_xhci_power_off_req - u0_cdn_usb_xhci_power_off_req + u0_sec_top_sramcfg_sram_config_sd + SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [12:12] read-write - u0_cdn_usb_xhci_power_on_ready - u0_cdn_usb_xhci_power_on_ready - [13:13] - read-only + u0_sec_top_sramcfg_rtsel + SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. + [14:13] + read-write + + + u0_sec_top_sramcfg_ptsel + SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. + [16:15] + read-write + + + u0_sec_top_sramcfg_trb + SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. + [18:17] + read-write + + + u0_sec_top_sramcfg_wtsel + SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. + [20:19] + read-write + + + u0_sec_top_sramcfg_vs + SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. + [21:21] + read-write - u0_cdn_usb_xhci_power_on_req - u0_cdn_usb_xhci_power_on_req - [14:14] - read-only + u0_sec_top_sramcfg_vg + SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. + [22:22] + read-write - u0_cdn_usb_xhci_power_on_valid - u0_cdn_usb_xhci_power_on_valid - [15:15] - read-write + u0_plda_pcie_align_detect + u0_plda_pcie_align_detect + [23:23] + read-only + + + + stg_sysconsaif_syscfg504 + STG SYSCONSAIF SYSCFG 504 + 0x1f8 + 32 + - u0_e2_sft7110_cease_from_tile_0 - u0_e2_sft7110_cease_from_tile_0 - [16:16] + u0_plda_pcie_axi4_mst0_aratomop_31_0 + u0_plda_pcie_axi4_mst0_aratomop_31_0 + [31:0] read-only + + + + stg_sysconsaif_syscfg508 + STG SYSCONSAIF SYSCFG 508 + 0x1fc + 32 + - u0_e2_sft7110_debug_from_tile_0 - u0_e2_sft7110_debug_from_tile_0 - [17:17] + u0_plda_pcie_axi4_mst0_aratomop_63_32 + u0_plda_pcie_axi4_mst0_aratomop_63_32 + [31:0] read-only + + + + stg_sysconsaif_syscfg512 + STG SYSCONSAIF SYSCFG 512 + 0x200 + 32 + - u0_e2_sft7110_halt_from_tile_0 - u0_e2_sft7110_halt_from_tile_0 - [18:18] + u0_plda_pcie_axi4_mst0_aratomop_95_64 + u0_plda_pcie_axi4_mst0_aratomop_95_64 + [31:0] read-only - stg_sysconsaif_syscfg28 - STG SYSCONSAIF SYSCFG 28 - 0x1c + stg_sysconsaif_syscfg516 + STG SYSCONSAIF SYSCFG 516 + 0x204 32 - u0_e2_sft7110_nmi_0_rnmi_exception_vector - u0_e2_sft7110_nmi_0_rnmi_exception_vector + u0_plda_pcie_axi4_mst0_aratomop_127_96 + u0_plda_pcie_axi4_mst0_aratomop_127_96 [31:0] - read-write + read-only - stg_sysconsaif_syscfg32 - STG SYSCONSAIF SYSCFG 32 - 0x20 + stg_sysconsaif_syscfg520 + STG SYSCONSAIF SYSCFG 520 + 0x208 32 - u0_e2_sft7110_nmi_0_rnmi_interrupt_vector - u0_e2_sft7110_nmi_0_rnmi_interrupt_vector + u0_plda_pcie_axi4_mst0_aratomop_159_128 + u0_plda_pcie_axi4_mst0_aratomop_159_128 [31:0] - read-write + read-only - stg_sysconsaif_syscfg36 - STG SYSCONSAIF SYSCFG 36 - 0x24 + stg_sysconsaif_syscfg524 + STG SYSCONSAIF SYSCFG 524 + 0x20c 32 - u0_e2_sft7110_reset_vector_0 - u0_e2_sft7110_reset_vector_0 + u0_plda_pcie_axi4_mst0_aratomop_191_160 + u0_plda_pcie_axi4_mst0_aratomop_191_160 [31:0] - read-write + read-only - stg_sysconsaif_syscfg40 - STG SYSCONSAIF SYSCFG 40 - 0x28 + stg_sysconsaif_syscfg528 + STG SYSCONSAIF SYSCFG 528 + 0x210 32 - u0_e2_sft7110_wfi_from_tile_0 - u0_e2_sft7110_wfi_from_tile_0 - [0:0] + u0_plda_pcie_axi4_mst0_aratomop_223_192 + u0_plda_pcie_axi4_mst0_aratomop_223_192 + [31:0] read-only - stg_sysconsaif_syscfg44 - STG SYSCONSAIF SYSCFG 44 - 0x2c + stg_sysconsaif_syscfg532 + STG SYSCONSAIF SYSCFG 532 + 0x214 32 - u0_hifi4_altresetvec - Reset Vector Address + u0_plda_pcie_axi4_mst0_aratomop_255_224 + u0_plda_pcie_axi4_mst0_aratomop_255_224 [31:0] - read-write + read-only - stg_sysconsaif_syscfg48 - STG SYSCONSAIF SYSCFG 48 - 0x30 + stg_sysconsaif_syscfg536 + STG SYSCONSAIF SYSCFG 536 + 0x218 32 - u0_hifi4_breakin - Debug signal - [0:0] - read-write + u0_plda_pcie_axi4_mst0_aratomop_257_256 + u0_plda_pcie_axi4_mst0_aratomop_257_256 + [1:0] + read-only - u0_hifi4_breakinack - Debug signal - [1:1] + u0_plda_pcie_axi4_mst0_arfunc + u0_plda_pcie_axi4_mst0_arfunc + [16:2] read-only - u0_hifi4_breakout - Debug signal - [2:2] + u0_plda_pcie_axi4_mst0_arregion + u0_plda_pcie_axi4_mst0_arregion + [20:17] read-only + + + + stg_sysconsaif_syscfg540 + STG SYSCONSAIF SYSCFG 540 + 0x21c + 32 + - u0_hifi4_breakoutack - Debug signal - [3:3] - read-write + u1_plda_pcie_axi4_mst0_aruser_31_0 + u1_plda_pcie_axi4_mst0_aruser_31_0 + [31:0] + read-only + + + + stg_sysconsaif_syscfg544 + STG SYSCONSAIF SYSCFG 544 + 0x220 + 32 + - u0_hifi4_debugmode - Debug signal - [4:4] + u1_plda_pcie_axi4_mst0_aruser_52_32 + u1_plda_pcie_axi4_mst0_aruser_52_32 + [20:0] read-only + + + + stg_sysconsaif_syscfg548 + STG SYSCONSAIF SYSCFG 548 + 0x224 + 32 + - u0_hifi4_doubleexceptionerror - Fault Handling Signals - [5:5] + u1_plda_pcie_axi4_mst0_awfunc + u1_plda_pcie_axi4_mst0_awfunc + [14:0] read-only - u0_hifi4_iram0loadstore - Indicates that iram0 works - [6:6] + u1_plda_pcie_axi4_mst0_awregion + u1_plda_pcie_axi4_mst0_awregion + [18:15] read-only + + + + stg_sysconsaif_syscfg552 + STG SYSCONSAIF SYSCFG 552 + 0x228 + 32 + - u0_hifi4_iram1loadstore - Indicates that iram1 works - [7:7] + u1_plda_pcie_axi4_mst0_awuser_31_0 + u1_plda_pcie_axi4_mst0_awuser_31_0 + [31:0] read-only + + + + stg_sysconsaif_syscfg556 + STG SYSCONSAIF SYSCFG 556 + 0x22c + 32 + - u0_hifi4_ocdhaltonreset - Debug signal - [8:8] + u1_plda_pcie_axi4_mst0_awuser_42_32 + u1_plda_pcie_axi4_mst0_awuser_42_32 + [10:0] + read-only + + + u1_plda_pcie_axi4_mst0_rderr + u1_plda_pcie_axi4_mst0_rderr + [18:11] read-write + + + + stg_sysconsaif_syscfg560 + STG SYSCONSAIF SYSCFG 560 + 0x230 + 32 + - u0_hifi4_pfatalerror - Fault Handling Signals - [9:9] + u1_plda_pcie_axi4_mst0_ruser + u1_plda_pcie_axi4_mst0_ruser + [31:0] + read-write + + + + + stg_sysconsaif_syscfg564 + STG SYSCONSAIF SYSCFG 564 + 0x234 + 32 + + + u1_plda_pcie_axi4_mst0_wderr + u1_plda_pcie_axi4_mst0_wderr + [7:0] read-only - stg_sysconsaif_syscfg52 - STG SYSCONSAIF SYSCFG 52 - 0x34 + stg_sysconsaif_syscfg568 + STG SYSCONSAIF SYSCFG 568 + 0x238 32 - u0_hifi4_pfaultinfo - Fault Handling Signals + u1_plda_pcie_axi4_slv0_aratomop_31_0 + u1_plda_pcie_axi4_slv0_aratomop_31_0 [31:0] - read-only + read-write - stg_sysconsaif_syscfg56 - STG SYSCONSAIF SYSCFG 56 - 0x38 + stg_sysconsaif_syscfg572 + STG SYSCONSAIF SYSCFG 572 + 0x23c 32 - u0_hifi4_pfaultinfovalid - Fault Handling Signals - [0:0] - read-only - - - u0_hifi4_prid - Module ID - [16:1] - read-write - - - u0_hifi4_pwaitmode - Wait Mode - [17:17] - read-only - - - u0_hifi4_runstall - Run Stall - [18:18] + u1_plda_pcie_axi4_slv0_aratomop_63_32 + u1_plda_pcie_axi4_slv0_aratomop_63_32 + [31:0] read-write - stg_sysconsaif_syscfg60 - STG SYSCONSAIF SYSCFG 60 - 0x3c + stg_sysconsaif_syscfg576 + STG SYSCONSAIF SYSCFG 576 + 0x240 32 - u0_hifi4_scfg_dsp_mst_offset_master - Indicates that master port remap address - [11:0] + u1_plda_pcie_axi4_slv0_aratomop_95_64 + u1_plda_pcie_axi4_slv0_aratomop_95_64 + [31:0] read-write + + + + stg_sysconsaif_syscfg580 + STG SYSCONSAIF SYSCFG 580 + 0x244 + 32 + - u0_hifi4_scfg_dsp_mst_offset_dma - Indicates the DMA port remap address - [27:16] + u1_plda_pcie_axi4_slv0_aratomop_127_96 + u1_plda_pcie_axi4_slv0_aratomop_127_96 + [31:0] read-write - stg_sysconsaif_syscfg64 - STG SYSCONSAIF SYSCFG 64 - 0x40 + stg_sysconsaif_syscfg584 + STG SYSCONSAIF SYSCFG 584 + 0x248 32 - u0_hifi4_scfg_dsp_slv_offset - The value indicates the slave port remap address + u1_plda_pcie_axi4_slv0_aratomop_159_128 + u1_plda_pcie_axi4_slv0_aratomop_159_128 [31:0] read-write - stg_sysconsaif_syscfg68 - STG SYSCONSAIF SYSCFG 68 - 0x44 + stg_sysconsaif_syscfg588 + STG SYSCONSAIF SYSCFG 588 + 0x24c 32 - u0_hifi4_scfg_sram_config_slp - SRAM/ROM configuration. SLP: sleep enable, high active, default is low. - [0:0] + u1_plda_pcie_axi4_slv0_aratomop_191_160 + u1_plda_pcie_axi4_slv0_aratomop_191_160 + [31:0] read-write + + + + stg_sysconsaif_syscfg592 + STG SYSCONSAIF SYSCFG 592 + 0x250 + 32 + - u0_hifi4_scfg_sram_config_sram_config_sd - SRAM/ROM configuration. SD: shutdown enable, high active, default is low. - [1:1] + u1_plda_pcie_axi4_slv0_aratomop_223_192 + u1_plda_pcie_axi4_slv0_aratomop_223_192 + [31:0] read-write + + + + stg_sysconsaif_syscfg596 + STG SYSCONSAIF SYSCFG 596 + 0x254 + 32 + - u0_hifi4_scfg_sram_config_rtsel - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. - [3:2] + u1_plda_pcie_axi4_slv0_aratomop_255_224 + u1_plda_pcie_axi4_slv0_aratomop_255_224 + [31:0] read-write + + + + stg_sysconsaif_syscfg600 + STG SYSCONSAIF SYSCFG 600 + 0x258 + 32 + - u0_hifi4_scfg_sram_config_ptsel - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. - [5:4] + u1_plda_pcie_axi4_mst0_aratomop_257_256 + u1_plda_pcie_axi4_mst0_aratomop_257_256 + [1:0] read-write - u0_hifi4_scfg_sram_config_trb - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. - [7:6] + u1_plda_pcie_axi4_slv0_arfunc + u1_plda_pcie_axi4_slv0_arfunc + [16:2] read-write - u0_hifi4_scfg_sram_config_wtsel - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. - [9:8] + u1_plda_pcie_axi4_slv0_arregion + u1_plda_pcie_axi4_slv0_arregion + [20:17] read-write + + + + stg_sysconsaif_syscfg604 + STG SYSCONSAIF SYSCFG 604 + 0x25c + 32 + - u0_hifi4_scfg_sram_config_vs - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. - [10:10] + u1_plda_pcie_axi4_slv0_aruser_31_0 + u1_plda_pcie_axi4_slv0_aruser_31_0 + [31:0] read-write + + + + stg_sysconsaif_syscfg608 + STG SYSCONSAIF SYSCFG 608 + 0x260 + 32 + - u0_hifi4_scfg_sram_config_vg - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. - [11:11] + u1_plda_pcie_axi4_slv0_aruser_40_32 + u1_plda_pcie_axi4_slv0_aruser_40_32 + [8:0] read-write - u0_hifi4_statvectorsel - When the value is 1, it indicates that the AltResetVec is valid - [12:12] + u1_plda_pcie_axi4_slv0_awfunc + u1_plda_pcie_axi4_slv0_awfunc + [23:9] read-write - u0_hifi4_trigin_idma - DMA port trigger - [13:13] + u1_plda_pcie_axi4_slv0_awregion + u1_plda_pcie_axi4_slv0_awregion + [27:24] read-write - - u0_hifi4_trigout_idma - DMA port trigger - [14:14] - read-only - - - u0_hifi4_xocdmode - Debug signal - [15:15] - read-only - - - u0_plda_pcie_align_detect - u0_plda_pcie_align_detect - [16:16] - read-only - - stg_sysconsaif_syscfg72 - STG SYSCONSAIF SYSCFG 72 - 0x48 + stg_sysconsaif_syscfg612 + STG SYSCONSAIF SYSCFG 612 + 0x264 32 - u0_plda_pcie_axi4_mst0_aratomop_31_0 - u0_plda_pcie_axi4_mst0_aratomop_31_0 + u1_plda_pcie_axi4_slv0_awuser_31_0 + u1_plda_pcie_axi4_slv0_awuser_31_0 [31:0] - read-only + read-write - stg_sysconsaif_syscfg76 - STG SYSCONSAIF SYSCFG 76 - 0x4c + stg_sysconsaif_syscfg616 + STG SYSCONSAIF SYSCFG 616 + 0x268 32 - u0_plda_pcie_axi4_mst0_aratomop_63_32 - u0_plda_pcie_axi4_mst0_aratomop_63_32 - [31:0] + u1_plda_pcie_axi4_slv0_awuser_40_32 + u1_plda_pcie_axi4_slv0_awuser_40_32 + [8:0] + read-write + + + u1_plda_pcie_axi4_slv0_rderr + u1_plda_pcie_axi4_slv0_rderr + [16:9] read-only - stg_sysconsaif_syscfg80 - STG SYSCONSAIF SYSCFG 80 - 0x50 + stg_sysconsaif_syscfg620 + STG SYSCONSAIF SYSCFG 620 + 0x26c 32 - u0_plda_pcie_axi4_mst0_aratomop_95_64 - u0_plda_pcie_axi4_mst0_aratomop_95_64 + u1_plda_pcie_axi4_slv0_ruser + u1_plda_pcie_axi4_slv0_ruser [31:0] read-only - stg_sysconsaif_syscfg84 - STG SYSCONSAIF SYSCFG 84 - 0x54 + stg_sysconsaif_syscfg624 + STG SYSCONSAIF SYSCFG 624 + 0x270 32 - u0_plda_pcie_axi4_mst0_aratomop_127_96 - u0_plda_pcie_axi4_mst0_aratomop_127_96 - [31:0] - read-only + u1_plda_pcie_axi4_slv0_wderr + u1_plda_pcie_axi4_slv0_wderr + [7:0] + read-write + + + u1_plda_pcie_axi4_slvl_arfunc + u1_plda_pcie_axi4_slvl_arfunc + [22:8] + read-write - stg_sysconsaif_syscfg88 - STG SYSCONSAIF SYSCFG 88 - 0x58 + stg_sysconsaif_syscfg628 + STG SYSCONSAIF SYSCFG 628 + 0x274 32 - u0_plda_pcie_axi4_mst0_aratomop_159_128 - u0_plda_pcie_axi4_mst0_aratomop_159_128 - [31:0] + u1_plda_pcie_axi4_slvl_awfunc + u1_plda_pcie_axi4_slvl_awfunc + [14:0] + read-write + + + u1_plda_pcie_bus_width_o + u1_plda_pcie_bus_width_o + [16:15] read-only + + u1_plda_pcie_bypass_codec + u1_plda_pcie_bypass_codec + [17:17] + read-write + + + u1_plda_pcie_ckref_src + u1_plda_pcie_ckref_src + [19:18] + read-write + + + u1_plda_pcie_clk_sel + u1_plda_pcie_clk_sel + [21:20] + read-write + + + u1_plda_pcie_clkreq + u1_plda_pcie_clkreq + [22:22] + read-write + - stg_sysconsaif_syscfg92 - STG SYSCONSAIF SYSCFG 92 - 0x5c + stg_sysconsaif_syscfg632 + STG SYSCONSAIF SYSCFG 632 + 0x278 32 - u0_plda_pcie_axi4_mst0_aratomop_191_160 - u0_plda_pcie_axi4_mst0_aratomop_191_160 + u1_plda_pcie_k_phyparam_31_0 + u1_plda_pcie_k_phyparam_31_0 [31:0] - read-only + read-write - stg_sysconsaif_syscfg96 - STG SYSCONSAIF SYSCFG 96 - 0x60 + stg_sysconsaif_syscfg636 + STG SYSCONSAIF SYSCFG 636 + 0x27c 32 - u0_plda_pcie_axi4_mst0_aratomop_223_192 - u0_plda_pcie_axi4_mst0_aratomop_223_192 + u1_plda_pcie_k_phyparam_63_32 + u1_plda_pcie_k_phyparam_63_32 [31:0] - read-only + read-write - stg_sysconsaif_syscfg100 - STG SYSCONSAIF SYSCFG 100 - 0x64 + stg_sysconsaif_syscfg640 + STG SYSCONSAIF SYSCFG 640 + 0x280 32 - u0_plda_pcie_axi4_mst0_aratomop_255_224 - u0_plda_pcie_axi4_mst0_aratomop_255_224 + u1_plda_pcie_k_phyparam_95_64 + u1_plda_pcie_k_phyparam_95_64 [31:0] - read-only + read-write - stg_sysconsaif_syscfg104 - STG SYSCONSAIF SYSCFG 104 - 0x68 + stg_sysconsaif_syscfg644 + STG SYSCONSAIF SYSCFG 644 + 0x284 32 - u0_plda_pcie_axi4_mst0_aratomop_257_256 - u0_plda_pcie_axi4_mst0_aratomop_257_256 - [1:0] - read-only - - - u0_plda_pcie_axi4_mst0_arfunc - u0_plda_pcie_axi4_mst0_arfunc - [16:2] - read-only - - - u0_plda_pcie_axi4_mst0_arregion - u0_plda_pcie_axi4_mst0_arregion - [20:17] - read-only + u1_plda_pcie_k_phyparam_127_96 + u1_plda_pcie_k_phyparam_127_96 + [31:0] + read-write - stg_sysconsaif_syscfg108 - STG SYSCONSAIF SYSCFG 108 - 0x6c + stg_sysconsaif_syscfg648 + STG SYSCONSAIF SYSCFG 648 + 0x288 32 - u0_plda_pcie_axi4_mst0_aruser_31_0 - u0_plda_pcie_axi4_mst0_aruser_31_0 + u1_plda_pcie_k_phyparam_159_128 + u1_plda_pcie_k_phyparam_159_128 [31:0] - read-only + read-write - stg_sysconsaif_syscfg112 - STG SYSCONSAIF SYSCFG 112 - 0x70 + stg_sysconsaif_syscfg652 + STG SYSCONSAIF SYSCFG 652 + 0x28c 32 - u0_plda_pcie_axi4_mst0_aruser_63_32 - u0_plda_pcie_axi4_mst0_aruser_63_32 + u1_plda_pcie_k_phyparam_191_160 + u1_plda_pcie_k_phyparam_191_160 [31:0] - read-only + read-write - stg_sysconsaif_syscfg116 - STG SYSCONSAIF SYSCFG 116 - 0x74 + stg_sysconsaif_syscfg656 + STG SYSCONSAIF SYSCFG 656 + 0x290 32 - u0_plda_pcie_axi4_mst0_awfunc - u0_plda_pcie_axi4_mst0_awfunc - [14:0] - read-only - - - u0_plda_pcie_axi4_mst0_awregion - u0_plda_pcie_axi4_mst0_awregion - [18:15] - read-only + u1_plda_pcie_k_phyparam_223_192 + u1_plda_pcie_k_phyparam_223_192 + [31:0] + read-write - stg_sysconsaif_syscfg120 - STG SYSCONSAIF SYSCFG 120 - 0x78 + stg_sysconsaif_syscfg660 + STG SYSCONSAIF SYSCFG 660 + 0x294 32 - u0_plda_pcie_axi4_mst0_a2user_31_0 - u0_plda_pcie_axi4_mst0_a2user_31_0 + u1_plda_pcie_k_phyparam_255_224 + u1_plda_pcie_k_phyparam_255_224 [31:0] - read-only + read-write - stg_sysconsaif_syscfg124 - STG SYSCONSAIF SYSCFG 124 - 0x7c + stg_sysconsaif_syscfg664 + STG SYSCONSAIF SYSCFG 664 + 0x298 32 - u0_plda_pcie_axi4_mst0_awuser_42_32 - u0_plda_pcie_axi4_mst0_awuser_42_32 - [10:0] - read-only - - - u0_plda_pcie_axi4_mst0_rderr - u0_plda_pcie_axi4_mst0_rderr - [18:11] + u1_plda_pcie_k_phyparam_287_256 + u1_plda_pcie_k_phyparam_287_256 + [31:0] read-write - stg_sysconsaif_syscfg128 - STG SYSCONSAIF SYSCFG 128 - 0x80 + stg_sysconsaif_syscfg668 + STG SYSCONSAIF SYSCFG 668 + 0x29c 32 - u0_plda_pcie_axi4_mst0_ruser - u0_plda_pcie_axi4_mst0_ruser + u1_plda_pcie_k_phyparam_319_288 + u1_plda_pcie_k_phyparam_319_288 [31:0] read-write - stg_sysconsaif_syscfg132 - STG SYSCONSAIF SYSCFG 132 - 0x84 + stg_sysconsaif_syscfg672 + STG SYSCONSAIF SYSCFG 672 + 0x2a0 32 - u0_plda_pcie_axi4_mst0_wderr - u0_plda_pcie_axi4_mst0_wderr - [7:0] - read-only + u1_plda_pcie_k_phyparam_351_320 + u1_plda_pcie_k_phyparam_351_320 + [31:0] + read-write - stg_sysconsaif_syscfg136 - STG SYSCONSAIF SYSCFG 136 - 0x88 + stg_sysconsaif_syscfg676 + STG SYSCONSAIF SYSCFG 676 + 0x2a4 32 - u0_plda_pcie_axi4_slv0_aratomop_31_0 - u0_plda_pcie_axi4_slv0_aratomop_31_0 + u1_plda_pcie_k_phyparam_383_352 + u1_plda_pcie_k_phyparam_383_352 [31:0] read-write - stg_sysconsaif_syscfg140 - STG SYSCONSAIF SYSCFG 140 - 0x8c + stg_sysconsaif_syscfg680 + STG SYSCONSAIF SYSCFG 680 + 0x2a8 32 - u0_plda_pcie_axi4_slv0_aratomop_63_32 - u0_plda_pcie_axi4_slv0_aratomop_63_32 + u1_plda_pcie_k_phyparam_415_384 + u1_plda_pcie_k_phyparam_415_384 [31:0] read-write - stg_sysconsaif_syscfg144 - STG SYSCONSAIF SYSCFG 144 - 0x90 + stg_sysconsaif_syscfg684 + STG SYSCONSAIF SYSCFG 684 + 0x2ac 32 - u0_plda_pcie_axi4_slv0_aratomop_95_64 - u0_plda_pcie_axi4_slv0_aratomop_95_64 + u1_plda_pcie_k_phyparam_447_416 + u1_plda_pcie_k_phyparam_447_416 [31:0] read-write - stg_sysconsaif_syscfg148 - STG SYSCONSAIF SYSCFG 148 - 0x94 + stg_sysconsaif_syscfg688 + STG SYSCONSAIF SYSCFG 688 + 0x2b0 32 - u0_plda_pcie_axi4_slv0_aratomop_127_96 - u0_plda_pcie_axi4_slv0_aratomop_127_96 + u1_plda_pcie_k_phyparam_479_448 + u1_plda_pcie_k_phyparam_479_448 [31:0] read-write - stg_sysconsaif_syscfg152 - STG SYSCONSAIF SYSCFG 152 - 0x98 + stg_sysconsaif_syscfg692 + STG SYSCONSAIF SYSCFG 692 + 0x2b4 32 - u0_plda_pcie_axi4_slv0_aratomop_159_128 - u0_plda_pcie_axi4_slv0_aratomop_159_128 + u1_plda_pcie_k_phyparam_511_480 + u1_plda_pcie_k_phyparam_511_480 [31:0] read-write - stg_sysconsaif_syscfg156 - STG SYSCONSAIF SYSCFG 156 - 0x9c + stg_sysconsaif_syscfg696 + STG SYSCONSAIF SYSCFG 696 + 0x2b8 32 - u0_plda_pcie_axi4_slv0_aratomop_191_160 - u0_plda_pcie_axi4_slv0_aratomop_191_160 + u1_plda_pcie_k_phyparam_543_512 + u1_plda_pcie_k_phyparam_543_512 [31:0] read-write - stg_sysconsaif_syscfg160 - STG SYSCONSAIF SYSCFG 160 - 0xa0 + stg_sysconsaif_syscfg700 + STG SYSCONSAIF SYSCFG 700 + 0x2bc 32 - u0_plda_pcie_axi4_slv0_aratomop_223_192 - u0_plda_pcie_axi4_slv0_aratomop_223_192 + u1_plda_pcie_k_phyparam_575_544 + u1_plda_pcie_k_phyparam_575_544 [31:0] read-write - stg_sysconsaif_syscfg164 - STG SYSCONSAIF SYSCFG 164 - 0xa4 + stg_sysconsaif_syscfg704 + STG SYSCONSAIF SYSCFG 704 + 0x2c0 32 - u0_plda_pcie_axi4_slv0_aratomop_255_224 - u0_plda_pcie_axi4_slv0_aratomop_255_224 + u1_plda_pcie_k_phyparam_607_576 + u1_plda_pcie_k_phyparam_607_576 [31:0] read-write - stg_sysconsaif_syscfg168 - STG SYSCONSAIF SYSCFG 168 - 0xa8 + stg_sysconsaif_syscfg708 + STG SYSCONSAIF SYSCFG 708 + 0x2c4 32 - u0_plda_pcie_axi4_slv0_aratomop_257_256 - u0_plda_pcie_axi4_slv0_aratomop_257_256 - [1:0] - read-write - - - u0_plda_pcie_axi4_slv0_arfunc - u0_plda_pcie_axi4_slv0_arfunc - [16:2] - read-write - - - u0_plda_pcie_axi4_slv0_arregion - u0_plda_pcie_axi4_slv0_arregion - [20:17] + u1_plda_pcie_k_phyparam_639_608 + u1_plda_pcie_k_phyparam_639_608 + [31:0] read-write - stg_sysconsaif_syscfg172 - STG SYSCONSAIF SYSCFG 172 - 0xac + stg_sysconsaif_syscfg712 + STG SYSCONSAIF SYSCFG 712 + 0x2c8 32 - u0_plda_pcie_axi4_slv0_aruser_31_0 - u0_plda_pcie_axi4_slv0_aruser_31_0 + u1_plda_pcie_k_phyparam_671_640 + u1_plda_pcie_k_phyparam_671_640 [31:0] read-write - stg_sysconsaif_syscfg176 - STG SYSCONSAIF SYSCFG 176 - 0xb0 + stg_sysconsaif_syscfg716 + STG SYSCONSAIF SYSCFG 716 + 0x2cc 32 - u0_plda_pcie_axi4_slv0_aruser_40_32 - u0_plda_pcie_axi4_slv0_aruser_40_32 - [8:0] - read-write - - - u0_plda_pcie_axi4_slv0_awfunc - u0_plda_pcie_axi4_slv0_awfunc - [23:9] - read-write - - - u0_plda_pcie_axi4_slv0_awregion - u0_plda_pcie_axi4_slv0_awregion - [27:24] + u1_plda_pcie_k_phyparam_703_672 + u1_plda_pcie_k_phyparam_703_672 + [31:0] read-write - stg_sysconsaif_syscfg180 - STG SYSCONSAIF SYSCFG 180 - 0xb4 + stg_sysconsaif_syscfg720 + STG SYSCONSAIF SYSCFG 720 + 0x2d0 32 - u0_plda_pcie_axi4_slv0_awuser_31_0 - u0_plda_pcie_axi4_slv0_awuser_31_0 + u1_plda_pcie_k_phyparam_735_704 + u1_plda_pcie_k_phyparam_735_704 [31:0] read-write - stg_sysconsaif_syscfg184 - STG SYSCONSAIF SYSCFG 184 - 0xb8 + stg_sysconsaif_syscfg724 + STG SYSCONSAIF SYSCFG 724 + 0x2d4 32 - u0_plda_pcie_axi4_slv0_awuser_40_32 - u0_plda_pcie_axi4_slv0_awuser_40_32 - [8:0] + u1_plda_pcie_k_phyparam_767_736 + u1_plda_pcie_k_phyparam_767_736 + [31:0] read-write - - u0_plda_pcie_axi4_slv0_rderr - u0_plda_pcie_axi4_slv0_rderr - [16:9] - read-only - - stg_sysconsaif_syscfg188 - STG SYSCONSAIF SYSCFG 188 - 0xbc + stg_sysconsaif_syscfg728 + STG SYSCONSAIF SYSCFG 728 + 0x2d8 32 - u0_plda_pcie_axi4_slv0_ruser - u0_plda_pcie_axi4_slv0_ruser + u1_plda_pcie_k_phyparam_799_768 + u1_plda_pcie_k_phyparam_799_768 [31:0] - read-only + read-write - stg_sysconsaif_syscfg192 - STG SYSCONSAIF SYSCFG 192 - 0xc0 + stg_sysconsaif_syscfg732 + STG SYSCONSAIF SYSCFG 732 + 0x2dc 32 - u0_plda_pcie_axi4_slv0_wderr - u0_plda_pcie_axi4_slv0_wderr - [7:0] + u1_plda_pcie_k_phyparam_831_800 + u1_plda_pcie_k_phyparam_831_800 + [31:0] read-write - - u0_plda_pcie_axi4_slvl_arfunc - u0_plda_pcie_axi4_slvl_arfunc - [22:8] - read-only - - stg_sysconsaif_syscfg196 - STG SYSCONSAIF SYSCFG 196 - 0xc4 + stg_sysconsaif_syscfg736 + STG SYSCONSAIF SYSCFG 736 + 0x2e0 32 - u0_plda_pcie_axi4_slvl_awfunc - u0_plda_pcie_axi4_slvl_awfunc - [14:0] - read-write - - - u0_plda_pcie_bus_width_o - u0_plda_pcie_bus_width_o - [16:15] - read-only - - - u0_plda_pcie_bypass_codec - u0_plda_pcie_bypass_codec - [17:17] + u1_plda_pcie_k_phyparam_839_832 + u1_plda_pcie_k_phyparam_839_832 + [7:0] read-write - u0_plda_pcie_ckref_src - u0_plda_pcie_ckref_src - [19:18] + u1_plda_pcie_k_rp_nep + u1_plda_pcie_k_rp_nep + [8:8] read-write - u0_plda_pcie_clk_sel - u0_plda_pcie_clk_sel - [21:20] - read-write + u1_plda_pcie_l1sub_entack + u1_plda_pcie_l1sub_entack + [9:9] + read-only - u0_plda_pcie_clkreq - u0_plda_pcie_clkreq - [22:22] + u1_plda_pcie_l1sub_entreq + u1_plda_pcie_l1sub_entreq + [10:10] read-write - stg_sysconsaif_syscfg200 - STG SYSCONSAIF SYSCFG 200 - 0xc8 + stg_sysconsaif_syscfg740 + STG SYSCONSAIF SYSCFG 740 + 0x2e4 32 - u0_plda_pcie_k_phyparam_31_0 - u0_plda_pcie_k_phyparam_31_0 + u1_plda_pcie_local_interrupt_in + u1_plda_pcie_local_interrupt_in [31:0] read-write - stg_sysconsaif_syscfg204 - STG SYSCONSAIF SYSCFG 204 - 0xcc + stg_sysconsaif_syscfg744 + STG SYSCONSAIF SYSCFG 744 + 0x2e8 32 - u0_plda_pcie_k_phyparam_63_32 - u0_plda_pcie_k_phyparam_63_32 - [31:0] + u1_plda_pcie_mperstn + u1_plda_pcie_mperstn + [0:0] read-write - - - - stg_sysconsaif_syscfg208 - STG SYSCONSAIF SYSCFG 208 - 0xd0 - 32 - - u0_plda_pcie_k_phyparam_95_64 - u0_plda_pcie_k_phyparam_95_64 - [31:0] + u1_plda_pcie_pcie_ebuf_mode + u1_plda_pcie_pcie_ebuf_mode + [1:1] read-write - - - - stg_sysconsaif_syscfg212 - STG SYSCONSAIF SYSCFG 212 - 0xd4 - 32 - - u0_plda_pcie_k_phyparam_127_96 - u0_plda_pcie_k_phyparam_127_96 - [31:0] + u1_plda_pcie_pcie_phy_test_cfg + u1_plda_pcie_pcie_phy_test_cfg + [24:2] + read-write + + + u1_plda_pcie_pcie_rx_eq_training + u1_plda_pcie_pcie_rx_eq_training + [25:25] + read-write + + + u1_plda_pcie_pcie_rxterm_en + u1_plda_pcie_pcie_rxterm_en + [26:26] read-write - - - - stg_sysconsaif_syscfg216 - STG SYSCONSAIF SYSCFG 216 - 0xd8 - 32 - - u0_plda_pcie_k_phyparam_159_128 - u0_plda_pcie_k_phyparam_159_128 - [31:0] + u1_plda_pcie_pcie_tx_oneszeros + u1_plda_pcie_pcie_tx_oneszeros + [27:27] read-write - stg_sysconsaif_syscfg220 - STG SYSCONSAIF SYSCFG 220 - 0xdc + stg_sysconsaif_syscfg748 + STG SYSCONSAIF SYSCFG 748 + 0x2ec 32 - u0_plda_pcie_k_phyparam_191_160 - u0_plda_pcie_k_phyparam_191_160 - [31:0] + u1_plda_pcie_pf0_offset + u1_plda_pcie_pf0_offset + [19:0] read-write - stg_sysconsaif_syscfg224 - STG SYSCONSAIF SYSCFG 224 - 0xe0 + stg_sysconsaif_syscfg752 + STG SYSCONSAIF SYSCFG 752 + 0x2f0 32 - u0_plda_pcie_k_phyparam_223_192 - u0_plda_pcie_k_phyparam_223_192 - [31:0] + u1_plda_pcie_pf1_offset + u1_plda_pcie_pf1_offset + [19:0] read-write - stg_sysconsaif_syscfg228 - STG SYSCONSAIF SYSCFG 228 - 0xe4 + stg_sysconsaif_syscfg756 + STG SYSCONSAIF SYSCFG 756 + 0x2f4 32 - u0_plda_pcie_k_phyparam_255_224 - u0_plda_pcie_k_phyparam_255_224 - [31:0] + u1_plda_pcie_pf2_offset + u1_plda_pcie_pf2_offset + [19:0] read-write - stg_sysconsaif_syscfg232 - STG SYSCONSAIF SYSCFG 232 - 0xe8 + stg_sysconsaif_syscfg760 + STG SYSCONSAIF SYSCFG 760 + 0x2f8 32 - u0_plda_pcie_k_phyparam_287_256 - u0_plda_pcie_k_phyparam_287_256 - [31:0] + u1_plda_pcie_pf3_offset + u1_plda_pcie_pf3_offset + [19:0] read-write - - - - stg_sysconsaif_syscfg236 - STG SYSCONSAIF SYSCFG 236 - 0xec - 32 - - u0_plda_pcie_k_phyparam_319_288 - u0_plda_pcie_k_phyparam_319_288 - [31:0] + u1_plda_pcie_phy_mode + u1_plda_pcie_phy_mode + [21:20] read-write - - - - stg_sysconsaif_syscfg240 - STG SYSCONSAIF SYSCFG 240 - 0xf0 - 32 - - u0_plda_pcie_k_phyparam_351_320 - u0_plda_pcie_k_phyparam_351_320 - [31:0] + u1_plda_pcie_pl_clkrem_allow + u1_plda_pcie_pl_clkrem_allow + [22:22] read-write - - - - stg_sysconsaif_syscfg244 - STG SYSCONSAIF SYSCFG 244 - 0xf4 - 32 - - u0_plda_pcie_k_phyparam_383_352 - u0_plda_pcie_k_phyparam_383_352 - [31:0] - read-write + u1_plda_pcie_pl_clkreq_oen + u1_plda_pcie_pl_clkreq_oen + [23:23] + read-only + + + u1_plda_pcie_pl_equ_phase + u1_plda_pcie_pl_equ_phase + [25:24] + read-only + + + u1_plda_pcie_pl_ltssm + u1_plda_pcie_pl_ltssm + [30:26] + read-only - stg_sysconsaif_syscfg248 - STG SYSCONSAIF SYSCFG 248 - 0xf8 + stg_sysconsaif_syscfg764 + STG SYSCONSAIF SYSCFG 764 + 0x2fc 32 - u0_plda_pcie_k_phyparam_415_384 - u0_plda_pcie_k_phyparam_415_384 - [31:0] - read-write + u1_plda_pcie_pl_pclk_rate + u1_plda_pcie_pl_pclk_rate + [4:0] + read-only - stg_sysconsaif_syscfg252 - STG SYSCONSAIF SYSCFG 252 - 0xfc + stg_sysconsaif_syscfg768 + STG SYSCONSAIF SYSCFG 768 + 0x300 32 - u0_plda_pcie_k_phyparam_447_416 - u0_plda_pcie_k_phyparam_447_416 + u1_plda_pcie_pl_sideband_in_31_0 + u1_plda_pcie_pl_sideband_in_31_0 [31:0] read-write - stg_sysconsaif_syscfg256 - STG SYSCONSAIF SYSCFG 256 - 0x100 + stg_sysconsaif_syscfg772 + STG SYSCONSAIF SYSCFG 772 + 0x304 32 - u0_plda_pcie_k_phyparam_479_448 - u0_plda_pcie_k_phyparam_479_448 + u1_plda_pcie_pl_sideband_in_63_32 + u1_plda_pcie_pl_sideband_in_63_32 [31:0] read-write - stg_sysconsaif_syscfg260 - STG SYSCONSAIF SYSCFG 260 - 0x104 + stg_sysconsaif_syscfg776 + STG SYSCONSAIF SYSCFG 776 + 0x308 32 - u0_plda_pcie_k_phyparam_511_480 - u0_plda_pcie_k_phyparam_511_480 + u1_plda_pcie_pl_sideband_out_31_0 + u1_plda_pcie_pl_sideband_out_31_0 [31:0] read-write - stg_sysconsaif_syscfg264 - STG SYSCONSAIF SYSCFG 264 - 0x108 + stg_sysconsaif_syscfg780 + STG SYSCONSAIF SYSCFG 780 + 0x30c 32 - u0_plda_pcie_k_phyparam_543_512 - u0_plda_pcie_k_phyparam_543_512 + u1_plda_pcie_pl_sideband_out_63_32 + u1_plda_pcie_pl_sideband_out_63_32 [31:0] read-write - stg_sysconsaif_syscfg268 - STG SYSCONSAIF SYSCFG 268 - 0x10c + stg_sysconsaif_syscfg784 + STG SYSCONSAIF SYSCFG 784 + 0x310 32 - u0_plda_pcie_k_phyparam_575_544 - u0_plda_pcie_k_phyparam_575_544 - [31:0] + u1_plda_pcie_pl_wake_in + u1_plda_pcie_pl_wake_in + [0:0] read-write + + u1_plda_pcie_pl_wake_oen + u1_plda_pcie_pl_wake_oen + [1:1] + read-only + + + u1_plda_pcie_rx_standby_o + u1_plda_pcie_rx_standby_o + [2:2] + read-only + - stg_sysconsaif_syscfg272 - STG SYSCONSAIF SYSCFG 272 - 0x110 + stg_sysconsaif_syscfg788 + STG SYSCONSAIF SYSCFG 788 + 0x314 32 - u0_plda_pcie_k_phyparam_607_576 - u0_plda_pcie_k_phyparam_607_576 + u1_plda_pcie_test_in_31_0 + u1_plda_pcie_test_in_31_0 [31:0] read-write - stg_sysconsaif_syscfg276 - STG SYSCONSAIF SYSCFG 276 - 0x114 + stg_sysconsaif_syscfg792 + STG SYSCONSAIF SYSCFG 792 + 0x318 32 - u0_plda_pcie_k_phyparam_639_608 - u0_plda_pcie_k_phyparam_639_608 + u1_plda_pcie_test_in_63_32 + u1_plda_pcie_test_in_63_32 [31:0] read-write - stg_sysconsaif_syscfg280 - STG SYSCONSAIF SYSCFG 280 - 0x118 + stg_sysconsaif_syscfg796 + STG SYSCONSAIF SYSCFG 796 + 0x31c 32 - u0_plda_pcie_k_phyparam_671_640 - u0_plda_pcie_k_phyparam_671_640 + u1_plda_pcie_test_out_bridge_31_0 + u1_plda_pcie_test_out_bridge_31_0 [31:0] read-write - stg_sysconsaif_syscfg284 - STG SYSCONSAIF SYSCFG 284 - 0x11c + stg_sysconsaif_syscfg800 + STG SYSCONSAIF SYSCFG 800 + 0x320 32 - u0_plda_pcie_k_phyparam_703_672 - u0_plda_pcie_k_phyparam_703_672 + u1_plda_pcie_test_out_bridge_63_32 + u1_plda_pcie_test_out_bridge_63_32 [31:0] read-write - stg_sysconsaif_syscfg288 - STG SYSCONSAIF SYSCFG 288 - 0x120 + stg_sysconsaif_syscfg804 + STG SYSCONSAIF SYSCFG 804 + 0x324 32 - u0_plda_pcie_k_phyparam_735_704 - u0_plda_pcie_k_phyparam_735_704 + u1_plda_pcie_test_out_bridge_95_64 + u1_plda_pcie_test_out_bridge_95_64 [31:0] read-write - stg_sysconsaif_syscfg292 - STG SYSCONSAIF SYSCFG 292 - 0x124 + stg_sysconsaif_syscfg808 + STG SYSCONSAIF SYSCFG 808 + 0x328 32 - u0_plda_pcie_k_phyparam_767_736 - u0_plda_pcie_k_phyparam_767_736 + u1_plda_pcie_test_out_bridge_127_96 + u1_plda_pcie_test_out_bridge_127_96 [31:0] read-write - stg_sysconsaif_syscfg296 - STG SYSCONSAIF SYSCFG 296 - 0x128 + stg_sysconsaif_syscfg812 + STG SYSCONSAIF SYSCFG 812 + 0x32c 32 - u0_plda_pcie_k_phyparam_799_768 - u0_plda_pcie_k_phyparam_799_768 + u1_plda_pcie_test_out_bridge_159_128 + u1_plda_pcie_test_out_bridge_159_128 [31:0] read-write - stg_sysconsaif_syscfg300 - STG SYSCONSAIF SYSCFG 300 - 0x12c + stg_sysconsaif_syscfg816 + STG SYSCONSAIF SYSCFG 816 + 0x330 32 - u0_plda_pcie_k_phyparam_831_800 - u0_plda_pcie_k_phyparam_831_800 + u1_plda_pcie_test_out_bridge_191_160 + u1_plda_pcie_test_out_bridge_191_160 [31:0] read-write - stg_sysconsaif_syscfg304 - STG SYSCONSAIF SYSCFG 304 - 0x130 + stg_sysconsaif_syscfg820 + STG SYSCONSAIF SYSCFG 820 + 0x334 32 - u0_plda_pcie_k_phyparam_839_832 - u0_plda_pcie_k_phyparam_839_832 - [7:0] - read-write - - - u0_plda_pcie_k_rp_nep - u0_plda_pcie_k_rp_nep - [8:8] - read-write - - - u0_plda_pcie_l1sub_entack - u0_plda_pcie_l1sub_entack - [9:9] - read-only - - - u0_plda_pcie_l1sub_entreq - u0_plda_pcie_l1sub_entreq - [10:10] + u1_plda_pcie_test_out_bridge_223_192 + u1_plda_pcie_test_out_bridge_223_192 + [31:0] read-write - stg_sysconsaif_syscfg308 - STG SYSCONSAIF SYSCFG 308 - 0x134 + stg_sysconsaif_syscfg824 + STG SYSCONSAIF SYSCFG 824 + 0x338 32 - u0_plda_pcie_local_interrupt_in - u0_plda_pcie_local_interrupt_in + u1_plda_pcie_test_out_bridge_255_224 + u1_plda_pcie_test_out_bridge_255_224 [31:0] read-write - stg_sysconsaif_syscfg312 - STG SYSCONSAIF SYSCFG 312 - 0x138 + stg_sysconsaif_syscfg828 + STG SYSCONSAIF SYSCFG 828 + 0x33c 32 - u0_plda_pcie_mperstn - u0_plda_pcie_mperstn - [0:0] - read-write - - - u0_plda_pcie_pcie_ebuf_mode - u0_plda_pcie_pcie_ebuf_mode - [1:1] - read-write - - - u0_plda_pcie_pcie_phy_test_cfg - u0_plda_pcie_pcie_phy_test_cfg - [24:2] - read-write - - - u0_plda_pcie_pcie_rx_eq_training - u0_plda_pcie_pcie_rx_eq_training - [25:25] - read-write - - - u0_plda_pcie_pcie_rxterm_en - u0_plda_pcie_pcie_rxterm_en - [26:26] - read-write - - - u0_plda_pcie_pcie_tx_onezeros - u0_plda_pcie_pcie_tx_onezeros - [27:27] + u1_plda_pcie_test_out_bridge_287_256 + u1_plda_pcie_test_out_bridge_287_256 + [31:0] read-write - stg_sysconsaif_syscfg316 - STG SYSCONSAIF SYSCFG 316 - 0x13c + stg_sysconsaif_syscfg832 + STG SYSCONSAIF SYSCFG 832 + 0x340 32 - u0_plda_pcie_pf0_offset - u0_plda_pcie_pf0_offset - [19:0] + u1_plda_pcie_test_out_bridge_319_288 + u1_plda_pcie_test_out_bridge_319_288 + [31:0] read-write - stg_sysconsaif_syscfg320 - STG SYSCONSAIF SYSCFG 320 - 0x140 + stg_sysconsaif_syscfg836 + STG SYSCONSAIF SYSCFG 836 + 0x344 32 - u0_plda_pcie_pf1_offset - u0_plda_pcie_pf1_offset - [19:0] + u1_plda_pcie_test_out_bridge_351_320 + u1_plda_pcie_test_out_bridge_351_320 + [31:0] read-write - stg_sysconsaif_syscfg324 - STG SYSCONSAIF SYSCFG 324 - 0x144 + stg_sysconsaif_syscfg840 + STG SYSCONSAIF SYSCFG 840 + 0x348 32 - u0_plda_pcie_pf2_offset - u0_plda_pcie_pf2_offset - [19:0] + u1_plda_pcie_test_out_bridge_383_352 + u1_plda_pcie_test_out_bridge_383_352 + [31:0] read-write - stg_sysconsaif_syscfg328 - STG SYSCONSAIF SYSCFG 328 - 0x148 + stg_sysconsaif_syscfg844 + STG SYSCONSAIF SYSCFG 844 + 0x34c 32 - u0_plda_pcie_pf3_offset - u0_plda_pcie_pf3_offset - [19:0] - read-write - - - u0_plda_pcie_phy_mode - u0_plda_pcie_phy_mode - [21:20] - read-write - - - u0_plda_pcie_pl_clkrem_allow - u0_plda_pcie_pl_clkrem_allow - [22:22] + u1_plda_pcie_test_out_bridge_415_384 + u1_plda_pcie_test_out_bridge_415_384 + [31:0] read-write - - u0_plda_pcie_pl_clkreq_oen - u0_plda_pcie_pl_clkreq_oen - [23:23] - read-only - - - u0_plda_pcie_pl_equ_phase - u0_plda_pcie_pl_equ_phase - [25:24] - read-only - - - u0_plda_pcie_pl_ltssm - u0_plda_pcie_pl_ltssm - [30:26] - read-only - - stg_sysconsaif_syscfg332 - STG SYSCONSAIF SYSCFG 332 - 0x14c + stg_sysconsaif_syscfg848 + STG SYSCONSAIF SYSCFG 848 + 0x350 32 - u0_plda_pcie_pl_pclk_rate - u0_plda_pcie_pl_pclk_rate - [4:0] - read-only + u1_plda_pcie_test_out_bridge_447_416 + u1_plda_pcie_test_out_bridge_447_416 + [31:0] + read-write - stg_sysconsaif_syscfg336 - STG SYSCONSAIF SYSCFG 336 - 0x150 + stg_sysconsaif_syscfg852 + STG SYSCONSAIF SYSCFG 852 + 0x354 32 - u0_plda_pcie_pl_sideband_in_31_0 - u0_plda_pcie_pl_sideband_in_31_0 + u1_plda_pcie_test_out_bridge_479_448 + u1_plda_pcie_test_out_bridge_479_448 [31:0] - read-only + read-write - stg_sysconsaif_syscfg340 - STG SYSCONSAIF SYSCFG 340 - 0x154 + stg_sysconsaif_syscfg856 + STG SYSCONSAIF SYSCFG 856 + 0x358 32 - u0_plda_pcie_pl_sideband_in_63_32 - u0_plda_pcie_pl_sideband_in_63_32 + u1_plda_pcie_test_out_bridge_511_480 + u1_plda_pcie_test_out_bridge_511_480 [31:0] - read-only + read-write - stg_sysconsaif_syscfg344 - STG SYSCONSAIF SYSCFG 344 - 0x158 + stg_sysconsaif_syscfg860 + STG SYSCONSAIF SYSCFG 860 + 0x35c 32 - u0_plda_pcie_pl_sideband_out_31_0 - u0_plda_pcie_pl_sideband_out_31_0 + u1_plda_pcie_test_out_pcie_31_0 + u1_plda_pcie_test_out_pcie_31_0 [31:0] read-only - stg_sysconsaif_syscfg348 - STG SYSCONSAIF SYSCFG 348 - 0x15c + stg_sysconsaif_syscfg864 + STG SYSCONSAIF SYSCFG 864 + 0x360 32 - u0_plda_pcie_pl_sideband_out_63_32 - u0_plda_pcie_pl_sideband_out_63_32 + u1_plda_pcie_test_out_pcie_63_32 + u1_plda_pcie_test_out_pcie_63_32 [31:0] read-only - stg_sysconsaif_syscfg352 - STG SYSCONSAIF SYSCFG 352 - 0x160 + stg_sysconsaif_syscfg868 + STG SYSCONSAIF SYSCFG 868 + 0x364 32 - u0_plda_pcie_pl_wake_in - u0_plda_pcie_pl_wake_in - [0:0] - read-write - - - u0_plda_pcie_pl_wake_oen - u0_plda_pcie_pl_wake_oen - [1:1] + u1_plda_pcie_test_out_pcie_95_64 + u1_plda_pcie_test_out_pcie_95_64 + [31:0] read-only + + + + stg_sysconsaif_syscfg872 + STG SYSCONSAIF SYSCFG 872 + 0x368 + 32 + - u0_plda_pcie_rx_standby_0 - u0_plda_pcie_rx_standby_0 - [2:2] + u1_plda_pcie_test_out_pcie_127_96 + u1_plda_pcie_test_out_pcie_127_96 + [31:0] read-only - stg_sysconsaif_syscfg356 - STG SYSCONSAIF SYSCFG 356 - 0x164 + stg_sysconsaif_syscfg876 + STG SYSCONSAIF SYSCFG 876 + 0x36c 32 - u0_plda_pcie_test_in_31_0 - u0_plda_pcie_test_in_31_0 + u1_plda_pcie_test_out_pcie_159_128 + u1_plda_pcie_test_out_pcie_159_128 [31:0] - read-write + read-only - stg_sysconsaif_syscfg360 - STG SYSCONSAIF SYSCFG 360 - 0x168 + stg_sysconsaif_syscfg880 + STG SYSCONSAIF SYSCFG 880 + 0x370 32 - u0_plda_pcie_test_in_63_32 - u0_plda_pcie_test_in_63_32 + u1_plda_pcie_test_out_pcie_191_160 + u1_plda_pcie_test_out_pcie_191_160 [31:0] - read-write + read-only - stg_sysconsaif_syscfg364 - STG SYSCONSAIF SYSCFG 364 - 0x16c + stg_sysconsaif_syscfg884 + STG SYSCONSAIF SYSCFG 884 + 0x374 32 - u0_plda_pcie_test_out_bridge_31_0 - u0_plda_pcie_test_out_bridge_31_0 + u1_plda_pcie_test_out_pcie_223_192 + u1_plda_pcie_test_out_pcie_223_192 [31:0] read-only - stg_sysconsaif_syscfg368 - STG SYSCONSAIF SYSCFG 368 - 0x170 + stg_sysconsaif_syscfg888 + STG SYSCONSAIF SYSCFG 888 + 0x378 32 - u0_plda_pcie_test_out_bridge_63_32 - u0_plda_pcie_test_out_bridge_63_32 + u1_plda_pcie_test_out_pcie_255_224 + u1_plda_pcie_test_out_pcie_255_224 [31:0] read-only - stg_sysconsaif_syscfg372 - STG SYSCONSAIF SYSCFG 372 - 0x174 + stg_sysconsaif_syscfg892 + STG SYSCONSAIF SYSCFG 892 + 0x37c 32 - u0_plda_pcie_test_out_bridge_95_64 - u0_plda_pcie_test_out_bridge_95_64 + u1_plda_pcie_test_out_pcie_287_256 + u1_plda_pcie_test_out_pcie_287_256 [31:0] read-only - stg_sysconsaif_syscfg376 - STG SYSCONSAIF SYSCFG 376 - 0x178 + stg_sysconsaif_syscfg896 + STG SYSCONSAIF SYSCFG 896 + 0x380 32 - u0_plda_pcie_test_out_bridge_127_96 - u0_plda_pcie_test_out_bridge_127_96 + u1_plda_pcie_test_out_pcie_319_288 + u1_plda_pcie_test_out_pcie_319_288 [31:0] read-only - stg_sysconsaif_syscfg380 - STG SYSCONSAIF SYSCFG 380 - 0x17c + stg_sysconsaif_syscfg900 + STG SYSCONSAIF SYSCFG 900 + 0x384 32 - u0_plda_pcie_test_out_bridge_159_128 - u0_plda_pcie_test_out_bridge_159_128 + u1_plda_pcie_test_out_pcie_351_320 + u1_plda_pcie_test_out_pcie_351_320 [31:0] read-only - stg_sysconsaif_syscfg384 - STG SYSCONSAIF SYSCFG 384 - 0x180 + stg_sysconsaif_syscfg904 + STG SYSCONSAIF SYSCFG 904 + 0x388 32 - u0_plda_pcie_test_out_bridge_191_160 - u0_plda_pcie_test_out_bridge_191_160 + u1_plda_pcie_test_out_pcie_383_352 + u1_plda_pcie_test_out_pcie_383_352 [31:0] read-only - stg_sysconsaif_syscfg388 - STG SYSCONSAIF SYSCFG 388 - 0x184 + stg_sysconsaif_syscfg908 + STG SYSCONSAIF SYSCFG 908 + 0x38c 32 - u0_plda_pcie_test_out_bridge_223_192 - u0_plda_pcie_test_out_bridge_223_192 + u1_plda_pcie_test_out_pcie_415_384 + u1_plda_pcie_test_out_pcie_415_384 [31:0] read-only - stg_sysconsaif_syscfg392 - STG SYSCONSAIF SYSCFG 392 - 0x188 + stg_sysconsaif_syscfg912 + STG SYSCONSAIF SYSCFG 912 + 0x390 32 - u0_plda_pcie_test_out_bridge_255_224 - u0_plda_pcie_test_out_bridge_255_224 + u1_plda_pcie_test_out_pcie_447_416 + u1_plda_pcie_test_out_pcie_447_416 [31:0] read-only - stg_sysconsaif_syscfg396 - STG SYSCONSAIF SYSCFG 396 - 0x18c + stg_sysconsaif_syscfg916 + STG SYSCONSAIF SYSCFG 916 + 0x394 32 - u0_plda_pcie_test_out_bridge_287_256 - u0_plda_pcie_test_out_bridge_287_256 + u1_plda_pcie_test_out_pcie_479_448 + u1_plda_pcie_test_out_pcie_479_448 [31:0] read-only - stg_sysconsaif_syscfg400 - STG SYSCONSAIF SYSCFG 400 - 0x190 + stg_sysconsaif_syscfg920 + STG SYSCONSAIF SYSCFG 920 + 0x398 32 - u0_plda_pcie_test_out_bridge_319_288 - u0_plda_pcie_test_out_bridge_319_288 + u1_plda_pcie_test_out_pcie_511_480 + u1_plda_pcie_test_out_pcie_511_480 [31:0] read-only - stg_sysconsaif_syscfg404 - STG SYSCONSAIF SYSCFG 404 - 0x194 + stg_sysconsaif_syscfg924 + STG SYSCONSAIF SYSCFG 924 + 0x39c 32 - u0_plda_pcie_test_out_bridge_351_320 - u0_plda_pcie_test_out_bridge_351_320 - [31:0] - read-only + u1_plda_pcie_test_sel + u1_plda_pcie_test_sel + [3:0] + read-write + + + u1_plda_pcie_tl_clock_freq + u1_plda_pcie_tl_clock_freq + [25:4] + read-write - stg_sysconsaif_syscfg408 - STG SYSCONSAIF SYSCFG 408 - 0x198 + stg_sysconsaif_syscfg928 + STG SYSCONSAIF SYSCFG 928 + 0x3a0 32 - u0_plda_pcie_test_out_bridge_383_352 - u0_plda_pcie_test_out_bridge_383_352 - [31:0] + u1_plda_pcie_tl_ctrl_hotplug + u1_plda_pcie_tl_ctrl_hotplug + [15:0] read-only + + u1_plda_pcie_tl_report_hotplug + u1_plda_pcie_tl_report_hotplug + [31:16] + read-write + - stg_sysconsaif_syscfg412 - STG SYSCONSAIF SYSCFG 412 - 0x19c + stg_sysconsaif_syscfg932 + STG SYSCONSAIF SYSCFG 932 + 0x3a4 32 - u0_plda_pcie_test_out_bridge_415_384 - u0_plda_pcie_test_out_bridge_415_384 - [31:0] + u1_plda_pcie_tx_pattern + u1_plda_pcie_tx_pattern + [1:0] + read-write + + + u1_plda_pcie_usb3_bus_width + u1_plda_pcie_usb3_bus_width + [3:2] + read-write + + + u1_plda_pcie_usb3_phy_enable + u1_plda_pcie_usb3_phy_enable + [4:4] + read-write + + + u1_plda_pcie_usb3_rate + u1_plda_pcie_usb3_rate + [6:5] + read-write + + + u1_plda_pcie_usb3_rx_standby + u1_plda_pcie_usb3_rx_standby + [7:7] + read-write + + + u1_plda_pcie_xwdecerr + u1_plda_pcie_xwdecerr + [8:8] + read-only + + + u1_plda_pcie_xwerrclr + u1_plda_pcie_xwerrclr + [9:9] + read-write + + + u1_plda_pcie_xwslverr + u1_plda_pcie_xwslverr + [10:10] read-only + + + + syscon_0 + From syscon, peripheral generator + 0x10240000 + + 0 + 0x1000 + registers + + + + snps_dw_apb_uart_3 + From snps,dw-apb-uart, peripheral generator + 0x12000000 + + 0 + 0x10000 + registers + + + + snps_dw_apb_uart_4 + From snps,dw-apb-uart, peripheral generator + 0x12010000 + + 0 + 0x10000 + registers + + + + snps_dw_apb_uart_5 + From snps,dw-apb-uart, peripheral generator + 0x12020000 + + 0 + 0x10000 + registers + + + + snps_designware_i2c_3 + From snps,designware-i2c, peripheral generator + 0x12030000 + + 0 + 0x10000 + registers + + - stg_sysconsaif_syscfg416 - STG SYSCONSAIF SYSCFG 416 - 0x1a0 + con + DesignWare I2C CON + 0x0 32 - u0_plda_pcie_test_out_bridge_447_416 - u0_plda_pcie_test_out_bridge_447_416 - [31:0] - read-only + master + I2C Master Connection - 0: Slave, 1: Master + [0:0] + read-write - - - - stg_sysconsaif_syscfg420 - STG SYSCONSAIF SYSCFG 420 - 0x1a4 - 32 - - u0_plda_pcie_test_out_bridge_479_448 - u0_plda_pcie_test_out_bridge_479_448 - [31:0] - read-only + speed + I2C Speed - 01: Standard, 10: Fast, 11: High + [2:1] + read-write - - - - stg_sysconsaif_syscfg424 - STG SYSCONSAIF SYSCFG 424 - 0x1a8 - 32 - - u0_plda_pcie_test_out_bridge_511_480 - u0_plda_pcie_test_out_bridge_511_480 - [31:0] - read-only + slave_10bitaddr + I2C Slave 10-bit Address - 0: False, 1: True + [3:3] + read-write - - - - stg_sysconsaif_syscfg428 - STG SYSCONSAIF SYSCFG 428 - 0x1ac - 32 - - u0_plda_pcie_test_out_pcie_31_0 - u0_plda_pcie_test_out_pcie_31_0 - [31:0] - read-only + master_10bitaddr + I2C Master 10-bit Address - 0: False, 1: True + [4:4] + read-write - - - - stg_sysconsaif_syscfg432 - STG SYSCONSAIF SYSCFG 432 - 0x1b0 - 32 - - u0_plda_pcie_test_out_pcie_63_32 - u0_plda_pcie_test_out_pcie_63_32 - [31:0] - read-only + restart_en + I2C Restart Enable - 0: False, 1: True + [5:5] + read-write - - - - stg_sysconsaif_syscfg436 - STG SYSCONSAIF SYSCFG 436 - 0x1b4 - 32 - - u0_plda_pcie_test_out_pcie_95_64 - u0_plda_pcie_test_out_pcie_95_64 - [31:0] - read-only + slave_disable + I2C Slave Disable - 0: False, 1: True + [6:6] + read-write - - - - stg_sysconsaif_syscfg440 - STG SYSCONSAIF SYSCFG 440 - 0x1b8 - 32 - - u0_plda_pcie_test_out_pcie_127_96 - u0_plda_pcie_test_out_pcie_127_96 - [31:0] - read-only + stop_det_ifaddressed + I2C Stop DET If Addressed - 0: False, 1: True + [7:7] + read-write - - - - stg_sysconsaif_syscfg444 - STG SYSCONSAIF SYSCFG 444 - 0x1bc - 32 - - u0_plda_pcie_test_out_pcie_159_128 - u0_plda_pcie_test_out_pcie_159_128 - [31:0] - read-only + tx_empty_ctrl + I2C TX Empty Control - 0: False, 1: True + [8:8] + read-write - - - - stg_sysconsaif_syscfg448 - STG SYSCONSAIF SYSCFG 448 - 0x1c0 - 32 - - u0_plda_pcie_test_out_pcie_191_160 - u0_plda_pcie_test_out_pcie_191_160 - [31:0] - read-only + rx_fifo_full_hld_ctrl + I2C RX FIFO Full Hold Control - 0: False, 1: True + [9:9] + read-write - - - - stg_sysconsaif_syscfg452 - STG SYSCONSAIF SYSCFG 452 - 0x1c4 - 32 - - u0_plda_pcie_test_out_pcie_223_192 - u0_plda_pcie_test_out_pcie_223_192 - [31:0] - read-only + bus_clear_ctrl + I2C Bus Clear Control - 0: False, 1: True + [11:11] + read-write - stg_sysconsaif_syscfg456 - STG SYSCONSAIF SYSCFG 456 - 0x1c8 + tar + DesignWare I2C TAR + 0x4 32 - u0_plda_pcie_test_out_pcie_255_224 - u0_plda_pcie_test_out_pcie_255_224 + tar + tar [31:0] - read-only + read-write - stg_sysconsaif_syscfg460 - STG SYSCONSAIF SYSCFG 460 - 0x1cc + sar + DesignWare I2C SAR + 0x8 32 - u0_plda_pcie_test_out_pcie_287_256 - u0_plda_pcie_test_out_pcie_287_256 + sar + sar [31:0] - read-only + read-write - stg_sysconsaif_syscfg464 - STG SYSCONSAIF SYSCFG 464 - 0x1d0 + data_cmd + DesignWare I2C Data Command + 0x10 32 - u0_plda_pcie_test_out_pcie_319_288 - u0_plda_pcie_test_out_pcie_319_288 - [31:0] - read-only + dat + Data Command Data Byte + [7:0] + read-write - - - - stg_sysconsaif_syscfg468 - STG SYSCONSAIF SYSCFG 468 - 0x1d4 - 32 - - u0_plda_pcie_test_out_pcie_351_320 - u0_plda_pcie_test_out_pcie_351_320 - [31:0] - read-only + first_data_byte + Data Command First Data Byte - 0: False, 1: True + [11:11] + read-write - stg_sysconsaif_syscfg472 - STG SYSCONSAIF SYSCFG 472 - 0x1d8 + ss_scl_hcnt + DesignWare I2C SS SCL HCNT + 0x14 32 - u0_plda_pcie_test_out_pcie_383_352 - u0_plda_pcie_test_out_pcie_383_352 + ss_scl_hcnt + ss_scl_hcnt [31:0] - read-only + read-write - stg_sysconsaif_syscfg476 - STG SYSCONSAIF SYSCFG 476 - 0x1dc + ss_scl_lcnt + DesignWare I2C SS SCL LCNT + 0x18 32 - u0_plda_pcie_test_out_pcie_415_384 - u0_plda_pcie_test_out_pcie_415_384 + ss_scl_lcnt + ss_scl_lcnt [31:0] - read-only + read-write - stg_sysconsaif_syscfg480 - STG SYSCONSAIF SYSCFG 480 - 0x1e0 + fs_scl_hcnt + DesignWare I2C FS SCL HCNT + 0x1c 32 - u0_plda_pcie_test_out_pcie_447_416 - u0_plda_pcie_test_out_pcie_447_416 + fs_scl_hcnt + fs_scl_hcnt [31:0] - read-only + read-write - stg_sysconsaif_syscfg484 - STG SYSCONSAIF SYSCFG 484 - 0x1e4 + fs_scl_lcnt + DesignWare I2C FS SCL LCNT + 0x20 32 - u0_plda_pcie_test_out_pcie_479_448 - u0_plda_pcie_test_out_pcie_479_448 + fs_scl_lcnt + fs_scl_lcnt [31:0] - read-only + read-write - stg_sysconsaif_syscfg488 - STG SYSCONSAIF SYSCFG 488 - 0x1e8 + hs_scl_hcnt + DesignWare I2C HS SCL HCNT + 0x24 32 - u0_plda_pcie_test_out_pcie_511_480 - u0_plda_pcie_test_out_pcie_511_480 + hs_scl_hcnt + hs_scl_hcnt [31:0] - read-only + read-write - stg_sysconsaif_syscfg492 - STG SYSCONSAIF SYSCFG 492 - 0x1ec + hs_scl_lcnt + DesignWare I2C HS SCL LCNT + 0x28 32 - u0_plda_pcie_test_sel - u0_plda_pcie_test_sel - [3:0] - read-write - - - u0_plda_pcie_tl_clock_freq - u0_plda_pcie_tl_clock_freq - [25:4] + hs_scl_lcnt + hs_scl_lcnt + [31:0] read-write - stg_sysconsaif_syscfg500 - STG SYSCONSAIF SYSCFG 500 - 0x1f4 + intr_stat + DesignWare I2C Interrupt Status + 0x2c 32 - u0_plda_pcie_tx_pattern - u0_plda_pcie_tx_pattern - [1:0] - read-write + rx_under + RX FIFO Underrun + [0:0] + read-only - u0_plda_pcie_usb3_bus_width - u0_plda_pcie_usb3_bus_width - [3:2] - read-write + rx_over + RX FIFO Overrun + [1:1] + read-only - u0_plda_pcie_usb3_phy_enable - u0_plda_pcie_usb3_phy_enable + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty [4:4] - read-write + read-only - u0_plda_pcie_usb3_rate - u0_plda_pcie_usb3_rate - [6:5] - read-write + rd_req + Read Request + [5:5] + read-only - u0_plda_pcie_usb3_rx_standby - u0_plda_pcie_usb3_rx_standby + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done [7:7] - read-write + read-only - u0_plda_pcie_xwdecerr - u0_plda_pcie_xwdecerr + activity + Activity [8:8] read-only - u0_plda_pcie_xwerrclr - u0_plda_pcie_xwerrclr + stop_det + Stop DET [9:9] - read-write + read-only - u0_plda_pcie_xwslverr - u0_plda_pcie_xwslverr + start_det + Start DET [10:10] read-only - u0_sec_top_sramcfg_slp - SRAM/ROM configuration. SLP: sleep enable, high active, default is low. + gen_call + General Call [11:11] - read-write + read-only - u0_sec_top_sramcfg_sram_config_sd - SRAM/ROM configuration. SD: shutdown enable, high active, default is low. + restart_det + Restart DET [12:12] - read-write + read-only - u0_sec_top_sramcfg_rtsel - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. - [14:13] - read-write + mst_on_hold + Master on Hold + [13:13] + read-only + + + + intr_mask + DesignWare I2C Interrupt Mask + 0x30 + 32 + - u0_sec_top_sramcfg_ptsel - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. - [16:15] + rx_under + RX FIFO Underrun + [0:0] read-write - u0_sec_top_sramcfg_trb - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. - [18:17] + rx_over + RX FIFO Overrun + [1:1] read-write - u0_sec_top_sramcfg_wtsel - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. - [20:19] + rx_full + RX FIFO Full + [2:2] read-write - u0_sec_top_sramcfg_vs - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. - [21:21] + tx_over + TX FIFO Overrun + [3:3] read-write - u0_sec_top_sramcfg_vg - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. - [22:22] + tx_empty + TX FIFO Empty + [4:4] read-write - u0_plda_pcie_align_detect - u0_plda_pcie_align_detect - [23:23] - read-only + rd_req + Read Request + [5:5] + read-write - - - - stg_sysconsaif_syscfg504 - STG SYSCONSAIF SYSCFG 504 - 0x1f8 - 32 - - u0_plda_pcie_axi4_mst0_aratomop_31_0 - u0_plda_pcie_axi4_mst0_aratomop_31_0 - [31:0] - read-only + tx_abrt + TX Abort + [6:6] + read-write - - - - stg_sysconsaif_syscfg508 - STG SYSCONSAIF SYSCFG 508 - 0x1fc - 32 - - u0_plda_pcie_axi4_mst0_aratomop_63_32 - u0_plda_pcie_axi4_mst0_aratomop_63_32 - [31:0] - read-only + rx_done + RX Done + [7:7] + read-write - - - - stg_sysconsaif_syscfg512 - STG SYSCONSAIF SYSCFG 512 - 0x200 - 32 - - u0_plda_pcie_axi4_mst0_aratomop_95_64 - u0_plda_pcie_axi4_mst0_aratomop_95_64 - [31:0] - read-only - - - - - stg_sysconsaif_syscfg516 - STG SYSCONSAIF SYSCFG 516 - 0x204 - 32 - + activity + Activity + [8:8] + read-write + - u0_plda_pcie_axi4_mst0_aratomop_127_96 - u0_plda_pcie_axi4_mst0_aratomop_127_96 - [31:0] - read-only + stop_det + Stop DET + [9:9] + read-write - - - - stg_sysconsaif_syscfg520 - STG SYSCONSAIF SYSCFG 520 - 0x208 - 32 - - u0_plda_pcie_axi4_mst0_aratomop_159_128 - u0_plda_pcie_axi4_mst0_aratomop_159_128 - [31:0] - read-only + start_det + Start DET + [10:10] + read-write - - - - stg_sysconsaif_syscfg524 - STG SYSCONSAIF SYSCFG 524 - 0x20c - 32 - - u0_plda_pcie_axi4_mst0_aratomop_191_160 - u0_plda_pcie_axi4_mst0_aratomop_191_160 - [31:0] - read-only + gen_call + General Call + [11:11] + read-write - - - - stg_sysconsaif_syscfg528 - STG SYSCONSAIF SYSCFG 528 - 0x210 - 32 - - u0_plda_pcie_axi4_mst0_aratomop_223_192 - u0_plda_pcie_axi4_mst0_aratomop_223_192 - [31:0] - read-only + restart_det + Restart DET + [12:12] + read-write - - - - stg_sysconsaif_syscfg532 - STG SYSCONSAIF SYSCFG 532 - 0x214 - 32 - - u0_plda_pcie_axi4_mst0_aratomop_255_224 - u0_plda_pcie_axi4_mst0_aratomop_255_224 - [31:0] - read-only + mst_on_hold + Master on Hold + [13:13] + read-write - stg_sysconsaif_syscfg536 - STG SYSCONSAIF SYSCFG 536 - 0x218 + raw_intr_stat + DesignWare I2C Raw Interrupt Status + 0x34 32 - u0_plda_pcie_axi4_mst0_aratomop_257_256 - u0_plda_pcie_axi4_mst0_aratomop_257_256 - [1:0] + rx_under + RX FIFO Underrun + [0:0] read-only - u0_plda_pcie_axi4_mst0_arfunc - u0_plda_pcie_axi4_mst0_arfunc - [16:2] + rx_over + RX FIFO Overrun + [1:1] read-only - u0_plda_pcie_axi4_mst0_arregion - u0_plda_pcie_axi4_mst0_arregion - [20:17] + rx_full + RX FIFO Full + [2:2] read-only - - - - stg_sysconsaif_syscfg540 - STG SYSCONSAIF SYSCFG 540 - 0x21c - 32 - - u1_plda_pcie_axi4_mst0_aruser_31_0 - u1_plda_pcie_axi4_mst0_aruser_31_0 - [31:0] + tx_over + TX FIFO Overrun + [3:3] read-only - - - - stg_sysconsaif_syscfg544 - STG SYSCONSAIF SYSCFG 544 - 0x220 - 32 - - u1_plda_pcie_axi4_mst0_aruser_52_32 - u1_plda_pcie_axi4_mst0_aruser_52_32 - [20:0] + tx_empty + TX FIFO Empty + [4:4] read-only - - - - stg_sysconsaif_syscfg548 - STG SYSCONSAIF SYSCFG 548 - 0x224 - 32 - - u1_plda_pcie_axi4_mst0_awfunc - u1_plda_pcie_axi4_mst0_awfunc - [14:0] + rd_req + Read Request + [5:5] read-only - u1_plda_pcie_axi4_mst0_awregion - u1_plda_pcie_axi4_mst0_awregion - [18:15] + tx_abrt + TX Abort + [6:6] read-only - - - - stg_sysconsaif_syscfg552 - STG SYSCONSAIF SYSCFG 552 - 0x228 - 32 - - u1_plda_pcie_axi4_mst0_awuser_31_0 - u1_plda_pcie_axi4_mst0_awuser_31_0 - [31:0] + rx_done + RX Done + [7:7] read-only - - - - stg_sysconsaif_syscfg556 - STG SYSCONSAIF SYSCFG 556 - 0x22c - 32 - - u1_plda_pcie_axi4_mst0_awuser_42_32 - u1_plda_pcie_axi4_mst0_awuser_42_32 - [10:0] + activity + Activity + [8:8] read-only - u1_plda_pcie_axi4_mst0_rderr - u1_plda_pcie_axi4_mst0_rderr - [18:11] - read-write - - - - - stg_sysconsaif_syscfg560 - STG SYSCONSAIF SYSCFG 560 - 0x230 - 32 - - - u1_plda_pcie_axi4_mst0_ruser - u1_plda_pcie_axi4_mst0_ruser - [31:0] - read-write - - - - - stg_sysconsaif_syscfg564 - STG SYSCONSAIF SYSCFG 564 - 0x234 - 32 - - - u1_plda_pcie_axi4_mst0_wderr - u1_plda_pcie_axi4_mst0_wderr - [7:0] + stop_det + Stop DET + [9:9] read-only - - - - stg_sysconsaif_syscfg568 - STG SYSCONSAIF SYSCFG 568 - 0x238 - 32 - - u1_plda_pcie_axi4_slv0_aratomop_31_0 - u1_plda_pcie_axi4_slv0_aratomop_31_0 - [31:0] - read-write + start_det + Start DET + [10:10] + read-only - - - - stg_sysconsaif_syscfg572 - STG SYSCONSAIF SYSCFG 572 - 0x23c - 32 - - u1_plda_pcie_axi4_slv0_aratomop_63_32 - u1_plda_pcie_axi4_slv0_aratomop_63_32 - [31:0] - read-write + gen_call + General Call + [11:11] + read-only - - - - stg_sysconsaif_syscfg576 - STG SYSCONSAIF SYSCFG 576 - 0x240 - 32 - - u1_plda_pcie_axi4_slv0_aratomop_95_64 - u1_plda_pcie_axi4_slv0_aratomop_95_64 - [31:0] - read-write + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only - stg_sysconsaif_syscfg580 - STG SYSCONSAIF SYSCFG 580 - 0x244 + rx_tl + DesignWare I2C RX TL + 0x38 32 - u1_plda_pcie_axi4_slv0_aratomop_127_96 - u1_plda_pcie_axi4_slv0_aratomop_127_96 + rx_tl + rx_tl [31:0] read-write - stg_sysconsaif_syscfg584 - STG SYSCONSAIF SYSCFG 584 - 0x248 + tx_tl + DesignWare I2C TX TL + 0x3c 32 - u1_plda_pcie_axi4_slv0_aratomop_159_128 - u1_plda_pcie_axi4_slv0_aratomop_159_128 + tx_tl + tx_tl [31:0] read-write - stg_sysconsaif_syscfg588 - STG SYSCONSAIF SYSCFG 588 - 0x24c + clr_intr + DesignWare I2C Clear Interrrupt + 0x40 32 - u1_plda_pcie_axi4_slv0_aratomop_191_160 - u1_plda_pcie_axi4_slv0_aratomop_191_160 - [31:0] + rx_under + RX FIFO Underrun + [0:0] read-write - - - - stg_sysconsaif_syscfg592 - STG SYSCONSAIF SYSCFG 592 - 0x250 - 32 - - u1_plda_pcie_axi4_slv0_aratomop_223_192 - u1_plda_pcie_axi4_slv0_aratomop_223_192 - [31:0] + rx_over + RX FIFO Overrun + [1:1] read-write - - - - stg_sysconsaif_syscfg596 - STG SYSCONSAIF SYSCFG 596 - 0x254 - 32 - - u1_plda_pcie_axi4_slv0_aratomop_255_224 - u1_plda_pcie_axi4_slv0_aratomop_255_224 - [31:0] + rx_full + RX FIFO Full + [2:2] read-write - - - - stg_sysconsaif_syscfg600 - STG SYSCONSAIF SYSCFG 600 - 0x258 - 32 - - u1_plda_pcie_axi4_mst0_aratomop_257_256 - u1_plda_pcie_axi4_mst0_aratomop_257_256 - [1:0] + tx_over + TX FIFO Overrun + [3:3] read-write - u1_plda_pcie_axi4_slv0_arfunc - u1_plda_pcie_axi4_slv0_arfunc - [16:2] + tx_empty + TX FIFO Empty + [4:4] read-write - u1_plda_pcie_axi4_slv0_arregion - u1_plda_pcie_axi4_slv0_arregion - [20:17] + rd_req + Read Request + [5:5] read-write - - - - stg_sysconsaif_syscfg604 - STG SYSCONSAIF SYSCFG 604 - 0x25c - 32 - - u1_plda_pcie_axi4_slv0_aruser_31_0 - u1_plda_pcie_axi4_slv0_aruser_31_0 - [31:0] + tx_abrt + TX Abort + [6:6] read-write - - - - stg_sysconsaif_syscfg608 - STG SYSCONSAIF SYSCFG 608 - 0x260 - 32 - - u1_plda_pcie_axi4_slv0_aruser_40_32 - u1_plda_pcie_axi4_slv0_aruser_40_32 - [8:0] + rx_done + RX Done + [7:7] read-write - u1_plda_pcie_axi4_slv0_awfunc - u1_plda_pcie_axi4_slv0_awfunc - [23:9] + activity + Activity + [8:8] read-write - u1_plda_pcie_axi4_slv0_awregion - u1_plda_pcie_axi4_slv0_awregion - [27:24] + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] read-write - stg_sysconsaif_syscfg612 - STG SYSCONSAIF SYSCFG 612 - 0x264 + clr_rx_under + DesignWare I2C Clear RX Underrun + 0x44 32 - u1_plda_pcie_axi4_slv0_awuser_31_0 - u1_plda_pcie_axi4_slv0_awuser_31_0 + clr_rx_under + clr_rx_under [31:0] read-write - stg_sysconsaif_syscfg616 - STG SYSCONSAIF SYSCFG 616 - 0x268 + clr_rx_over + DesignWare I2C Clear RX Overrun + 0x48 32 - u1_plda_pcie_axi4_slv0_awuser_40_32 - u1_plda_pcie_axi4_slv0_awuser_40_32 - [8:0] + clr_rx_over + clr_rx_over + [31:0] read-write - - u1_plda_pcie_axi4_slv0_rderr - u1_plda_pcie_axi4_slv0_rderr - [16:9] - read-only - - stg_sysconsaif_syscfg620 - STG SYSCONSAIF SYSCFG 620 - 0x26c + clr_tx_over + DesignWare I2C Clear TX Overrun + 0x4c 32 - u1_plda_pcie_axi4_slv0_ruser - u1_plda_pcie_axi4_slv0_ruser + clr_tx_over + clr_tx_over [31:0] - read-only + read-write - stg_sysconsaif_syscfg624 - STG SYSCONSAIF SYSCFG 624 - 0x270 + clr_rd_req + DesignWare I2C Clear Read Request + 0x50 32 - u1_plda_pcie_axi4_slv0_wderr - u1_plda_pcie_axi4_slv0_wderr - [7:0] - read-write - - - u1_plda_pcie_axi4_slvl_arfunc - u1_plda_pcie_axi4_slvl_arfunc - [22:8] + clr_rd_req + clr_rd_req + [31:0] read-write - stg_sysconsaif_syscfg628 - STG SYSCONSAIF SYSCFG 628 - 0x274 + clr_tx_abrt + DesignWare I2C Clear TX Abort + 0x54 32 - - - u1_plda_pcie_axi4_slvl_awfunc - u1_plda_pcie_axi4_slvl_awfunc - [14:0] - read-write - - - u1_plda_pcie_bus_width_o - u1_plda_pcie_bus_width_o - [16:15] - read-only - - - u1_plda_pcie_bypass_codec - u1_plda_pcie_bypass_codec - [17:17] - read-write - - - u1_plda_pcie_ckref_src - u1_plda_pcie_ckref_src - [19:18] - read-write - - - u1_plda_pcie_clk_sel - u1_plda_pcie_clk_sel - [21:20] - read-write - - - u1_plda_pcie_clkreq - u1_plda_pcie_clkreq - [22:22] + + + clr_tx_abrt + clr_tx_abrt + [31:0] read-write - stg_sysconsaif_syscfg632 - STG SYSCONSAIF SYSCFG 632 - 0x278 + clr_rx_done + DesignWare I2C Clear RX Done + 0x58 32 - u1_plda_pcie_k_phyparam_31_0 - u1_plda_pcie_k_phyparam_31_0 + clr_rx_done + clr_rx_done [31:0] read-write - stg_sysconsaif_syscfg636 - STG SYSCONSAIF SYSCFG 636 - 0x27c + clr_activity + DesignWare I2C Clear Activity + 0x5c 32 - u1_plda_pcie_k_phyparam_63_32 - u1_plda_pcie_k_phyparam_63_32 + clr_activity + clr_activity [31:0] read-write - stg_sysconsaif_syscfg640 - STG SYSCONSAIF SYSCFG 640 - 0x280 + clr_stop_det + DesignWare I2C Clear Stop DET + 0x60 32 - u1_plda_pcie_k_phyparam_95_64 - u1_plda_pcie_k_phyparam_95_64 + clr_stop_det + clr_stop_det [31:0] read-write - stg_sysconsaif_syscfg644 - STG SYSCONSAIF SYSCFG 644 - 0x284 + clr_start_det + DesignWare I2C Clear Start DET + 0x64 32 - u1_plda_pcie_k_phyparam_127_96 - u1_plda_pcie_k_phyparam_127_96 + clr_start_det + clr_start_det [31:0] read-write - stg_sysconsaif_syscfg648 - STG SYSCONSAIF SYSCFG 648 - 0x288 + clr_gen_call + DesignWare I2C Clear General Call + 0x68 32 - u1_plda_pcie_k_phyparam_159_128 - u1_plda_pcie_k_phyparam_159_128 + clr_gen_call + clr_gen_call [31:0] read-write - stg_sysconsaif_syscfg652 - STG SYSCONSAIF SYSCFG 652 - 0x28c + enable + DesignWare I2C Enable + 0x6c 32 - u1_plda_pcie_k_phyparam_191_160 - u1_plda_pcie_k_phyparam_191_160 - [31:0] + abort + abort + [1:1] read-write - stg_sysconsaif_syscfg656 - STG SYSCONSAIF SYSCFG 656 - 0x290 + status + DesignWare I2C Status + 0x70 32 - u1_plda_pcie_k_phyparam_223_192 - u1_plda_pcie_k_phyparam_223_192 - [31:0] - read-write + activity + activity + [0:0] + read-only + + + tfe + tfe + [2:2] + read-only + + + rfne + rfne + [3:3] + read-only + + + master_activity + master_activity + [5:5] + read-only + + + slave_activity + slave_activity + [6:6] + read-only - stg_sysconsaif_syscfg660 - STG SYSCONSAIF SYSCFG 660 - 0x294 + txflr + DesignWare I2C TX Failure + 0x74 32 - u1_plda_pcie_k_phyparam_255_224 - u1_plda_pcie_k_phyparam_255_224 + txflr + txflr [31:0] read-write - stg_sysconsaif_syscfg664 - STG SYSCONSAIF SYSCFG 664 - 0x298 + rxflr + DesignWare I2C RX Failure + 0x78 32 - u1_plda_pcie_k_phyparam_287_256 - u1_plda_pcie_k_phyparam_287_256 + rxflr + rxflr [31:0] read-write - stg_sysconsaif_syscfg668 - STG SYSCONSAIF SYSCFG 668 - 0x29c + sda_hold + DesignWare I2C SDA Hold + 0x7c 32 - u1_plda_pcie_k_phyparam_319_288 - u1_plda_pcie_k_phyparam_319_288 + sda_hold + sda_hold [31:0] read-write - stg_sysconsaif_syscfg672 - STG SYSCONSAIF SYSCFG 672 - 0x2a0 + tx_abrt_source + DesignWare I2C TX Abort Source + 0x80 32 - u1_plda_pcie_k_phyparam_351_320 - u1_plda_pcie_k_phyparam_351_320 - [31:0] - read-write + b7_addr_noack + b7_addr_noack + [0:0] + read-only + + + b10_addr1_noack + b10_addr1_noack + [1:1] + read-only + + + b10_addr2_noack + b10_addr2_noack + [2:2] + read-only + + + txdata_noack + txdata_noack + [3:3] + read-only + + + gcall_noack + gcall_noack + [4:4] + read-only + + + gcall_read + gcall_read + [5:5] + read-only + + + sbyte_ackdet + sbyte_ackdet + [7:7] + read-only + + + sbyte_norstrt + sbyte_norstrt + [9:9] + read-only + + + b10_rd_norstrt + b10_rd_norstrt + [10:10] + read-only + + + master_dis + master_dis + [11:11] + read-only + + + arb_lost + arb_lost + [12:12] + read-only + + + slave_flush_txfifo + slave_flush_txfifo + [13:13] + read-only + + + slave_arblost + slave_arblost + [14:14] + read-only + + + slave_rd_intx + slave_rd_intx + [15:15] + read-only - stg_sysconsaif_syscfg676 - STG SYSCONSAIF SYSCFG 676 - 0x2a4 + enable_status + DesignWare I2C Enable Status + 0x9c 32 - u1_plda_pcie_k_phyparam_383_352 - u1_plda_pcie_k_phyparam_383_352 - [31:0] + activity + activity + [0:0] + read-write + + + tfe + tfe + [2:2] + read-write + + + rfne + rfne + [3:3] + read-write + + + master_activity + master_activity + [5:5] + read-write + + + slave_activity + slave_activity + [6:6] read-write - stg_sysconsaif_syscfg680 - STG SYSCONSAIF SYSCFG 680 - 0x2a8 + clr_restart_det + DesignWare I2C Clear Restart DET + 0xa8 32 - u1_plda_pcie_k_phyparam_415_384 - u1_plda_pcie_k_phyparam_415_384 + clr_restart_det + clr_restart_det [31:0] read-write - stg_sysconsaif_syscfg684 - STG SYSCONSAIF SYSCFG 684 - 0x2ac + comp_param_1 + DesignWare I2C Compatibility Parameter 1 + 0xf4 32 - u1_plda_pcie_k_phyparam_447_416 - u1_plda_pcie_k_phyparam_447_416 - [31:0] - read-write + speed + Speed mask - 01: Standard, 10: Full, 11: High + [3:2] + read-only - stg_sysconsaif_syscfg688 - STG SYSCONSAIF SYSCFG 688 - 0x2b0 + comp_version + DesignWare I2C Compatibility Version + 0xf8 32 - u1_plda_pcie_k_phyparam_479_448 - u1_plda_pcie_k_phyparam_479_448 + comp_version + comp_version [31:0] - read-write + read-only - stg_sysconsaif_syscfg692 - STG SYSCONSAIF SYSCFG 692 - 0x2b4 + comp_type + DesignWare I2C Compatibility Type + 0xfc 32 - u1_plda_pcie_k_phyparam_511_480 - u1_plda_pcie_k_phyparam_511_480 + comp_type + comp_type [31:0] - read-write + read-only + + + + snps_designware_i2c_4 + From snps,designware-i2c, peripheral generator + 0x12040000 + + 0 + 0x10000 + registers + + - stg_sysconsaif_syscfg696 - STG SYSCONSAIF SYSCFG 696 - 0x2b8 + con + DesignWare I2C CON + 0x0 32 - u1_plda_pcie_k_phyparam_543_512 - u1_plda_pcie_k_phyparam_543_512 - [31:0] + master + I2C Master Connection - 0: Slave, 1: Master + [0:0] read-write - - - - stg_sysconsaif_syscfg700 - STG SYSCONSAIF SYSCFG 700 - 0x2bc - 32 - - u1_plda_pcie_k_phyparam_575_544 - u1_plda_pcie_k_phyparam_575_544 - [31:0] + speed + I2C Speed - 01: Standard, 10: Fast, 11: High + [2:1] read-write - - - - stg_sysconsaif_syscfg704 - STG SYSCONSAIF SYSCFG 704 - 0x2c0 - 32 - - u1_plda_pcie_k_phyparam_607_576 - u1_plda_pcie_k_phyparam_607_576 - [31:0] + slave_10bitaddr + I2C Slave 10-bit Address - 0: False, 1: True + [3:3] + read-write + + + master_10bitaddr + I2C Master 10-bit Address - 0: False, 1: True + [4:4] + read-write + + + restart_en + I2C Restart Enable - 0: False, 1: True + [5:5] + read-write + + + slave_disable + I2C Slave Disable - 0: False, 1: True + [6:6] + read-write + + + stop_det_ifaddressed + I2C Stop DET If Addressed - 0: False, 1: True + [7:7] + read-write + + + tx_empty_ctrl + I2C TX Empty Control - 0: False, 1: True + [8:8] + read-write + + + rx_fifo_full_hld_ctrl + I2C RX FIFO Full Hold Control - 0: False, 1: True + [9:9] + read-write + + + bus_clear_ctrl + I2C Bus Clear Control - 0: False, 1: True + [11:11] read-write - stg_sysconsaif_syscfg708 - STG SYSCONSAIF SYSCFG 708 - 0x2c4 + tar + DesignWare I2C TAR + 0x4 32 - u1_plda_pcie_k_phyparam_639_608 - u1_plda_pcie_k_phyparam_639_608 + tar + tar [31:0] read-write - stg_sysconsaif_syscfg712 - STG SYSCONSAIF SYSCFG 712 - 0x2c8 + sar + DesignWare I2C SAR + 0x8 32 - u1_plda_pcie_k_phyparam_671_640 - u1_plda_pcie_k_phyparam_671_640 + sar + sar [31:0] read-write - stg_sysconsaif_syscfg716 - STG SYSCONSAIF SYSCFG 716 - 0x2cc + data_cmd + DesignWare I2C Data Command + 0x10 32 - u1_plda_pcie_k_phyparam_703_672 - u1_plda_pcie_k_phyparam_703_672 - [31:0] + dat + Data Command Data Byte + [7:0] + read-write + + + first_data_byte + Data Command First Data Byte - 0: False, 1: True + [11:11] read-write - stg_sysconsaif_syscfg720 - STG SYSCONSAIF SYSCFG 720 - 0x2d0 + ss_scl_hcnt + DesignWare I2C SS SCL HCNT + 0x14 32 - u1_plda_pcie_k_phyparam_735_704 - u1_plda_pcie_k_phyparam_735_704 + ss_scl_hcnt + ss_scl_hcnt [31:0] read-write - stg_sysconsaif_syscfg724 - STG SYSCONSAIF SYSCFG 724 - 0x2d4 + ss_scl_lcnt + DesignWare I2C SS SCL LCNT + 0x18 32 - u1_plda_pcie_k_phyparam_767_736 - u1_plda_pcie_k_phyparam_767_736 + ss_scl_lcnt + ss_scl_lcnt [31:0] read-write - stg_sysconsaif_syscfg728 - STG SYSCONSAIF SYSCFG 728 - 0x2d8 + fs_scl_hcnt + DesignWare I2C FS SCL HCNT + 0x1c 32 - u1_plda_pcie_k_phyparam_799_768 - u1_plda_pcie_k_phyparam_799_768 + fs_scl_hcnt + fs_scl_hcnt [31:0] read-write - stg_sysconsaif_syscfg732 - STG SYSCONSAIF SYSCFG 732 - 0x2dc + fs_scl_lcnt + DesignWare I2C FS SCL LCNT + 0x20 32 - u1_plda_pcie_k_phyparam_831_800 - u1_plda_pcie_k_phyparam_831_800 + fs_scl_lcnt + fs_scl_lcnt [31:0] read-write - stg_sysconsaif_syscfg736 - STG SYSCONSAIF SYSCFG 736 - 0x2e0 + hs_scl_hcnt + DesignWare I2C HS SCL HCNT + 0x24 32 - u1_plda_pcie_k_phyparam_839_832 - u1_plda_pcie_k_phyparam_839_832 - [7:0] - read-write - - - u1_plda_pcie_k_rp_nep - u1_plda_pcie_k_rp_nep - [8:8] - read-write - - - u1_plda_pcie_l1sub_entack - u1_plda_pcie_l1sub_entack - [9:9] - read-only - - - u1_plda_pcie_l1sub_entreq - u1_plda_pcie_l1sub_entreq - [10:10] + hs_scl_hcnt + hs_scl_hcnt + [31:0] read-write - stg_sysconsaif_syscfg740 - STG SYSCONSAIF SYSCFG 740 - 0x2e4 + hs_scl_lcnt + DesignWare I2C HS SCL LCNT + 0x28 32 - u1_plda_pcie_local_interrupt_in - u1_plda_pcie_local_interrupt_in + hs_scl_lcnt + hs_scl_lcnt [31:0] read-write - stg_sysconsaif_syscfg744 - STG SYSCONSAIF SYSCFG 744 - 0x2e8 + intr_stat + DesignWare I2C Interrupt Status + 0x2c 32 - u1_plda_pcie_mperstn - u1_plda_pcie_mperstn + rx_under + RX FIFO Underrun [0:0] - read-write + read-only - u1_plda_pcie_pcie_ebuf_mode - u1_plda_pcie_pcie_ebuf_mode + rx_over + RX FIFO Overrun [1:1] - read-write + read-only - u1_plda_pcie_pcie_phy_test_cfg - u1_plda_pcie_pcie_phy_test_cfg - [24:2] - read-write + rx_full + RX FIFO Full + [2:2] + read-only - u1_plda_pcie_pcie_rx_eq_training - u1_plda_pcie_pcie_rx_eq_training - [25:25] - read-write + tx_over + TX FIFO Overrun + [3:3] + read-only - u1_plda_pcie_pcie_rxterm_en - u1_plda_pcie_pcie_rxterm_en - [26:26] - read-write + tx_empty + TX FIFO Empty + [4:4] + read-only - u1_plda_pcie_pcie_tx_oneszeros - u1_plda_pcie_pcie_tx_oneszeros - [27:27] - read-write + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only - stg_sysconsaif_syscfg748 - STG SYSCONSAIF SYSCFG 748 - 0x2ec + intr_mask + DesignWare I2C Interrupt Mask + 0x30 32 - u1_plda_pcie_pf0_offset - u1_plda_pcie_pf0_offset - [19:0] + rx_under + RX FIFO Underrun + [0:0] read-write - - - - stg_sysconsaif_syscfg752 - STG SYSCONSAIF SYSCFG 752 - 0x2f0 - 32 - - u1_plda_pcie_pf1_offset - u1_plda_pcie_pf1_offset - [19:0] + rx_over + RX FIFO Overrun + [1:1] read-write - - - - stg_sysconsaif_syscfg756 - STG SYSCONSAIF SYSCFG 756 - 0x2f4 - 32 - - u1_plda_pcie_pf2_offset - u1_plda_pcie_pf2_offset - [19:0] + rx_full + RX FIFO Full + [2:2] read-write - - - - stg_sysconsaif_syscfg760 - STG SYSCONSAIF SYSCFG 760 - 0x2f8 - 32 - - u1_plda_pcie_pf3_offset - u1_plda_pcie_pf3_offset - [19:0] + tx_over + TX FIFO Overrun + [3:3] read-write - u1_plda_pcie_phy_mode - u1_plda_pcie_phy_mode - [21:20] + tx_empty + TX FIFO Empty + [4:4] read-write - u1_plda_pcie_pl_clkrem_allow - u1_plda_pcie_pl_clkrem_allow - [22:22] + rd_req + Read Request + [5:5] read-write - u1_plda_pcie_pl_clkreq_oen - u1_plda_pcie_pl_clkreq_oen - [23:23] - read-only + tx_abrt + TX Abort + [6:6] + read-write - u1_plda_pcie_pl_equ_phase - u1_plda_pcie_pl_equ_phase - [25:24] - read-only + rx_done + RX Done + [7:7] + read-write - u1_plda_pcie_pl_ltssm - u1_plda_pcie_pl_ltssm - [30:26] - read-only + activity + Activity + [8:8] + read-write - - - - stg_sysconsaif_syscfg764 - STG SYSCONSAIF SYSCFG 764 - 0x2fc - 32 - - u1_plda_pcie_pl_pclk_rate - u1_plda_pcie_pl_pclk_rate - [4:0] - read-only + stop_det + Stop DET + [9:9] + read-write - - - - stg_sysconsaif_syscfg768 - STG SYSCONSAIF SYSCFG 768 - 0x300 - 32 - - u1_plda_pcie_pl_sideband_in_31_0 - u1_plda_pcie_pl_sideband_in_31_0 - [31:0] + start_det + Start DET + [10:10] read-write - - - - stg_sysconsaif_syscfg772 - STG SYSCONSAIF SYSCFG 772 - 0x304 - 32 - - u1_plda_pcie_pl_sideband_in_63_32 - u1_plda_pcie_pl_sideband_in_63_32 - [31:0] + gen_call + General Call + [11:11] read-write - - - - stg_sysconsaif_syscfg776 - STG SYSCONSAIF SYSCFG 776 - 0x308 - 32 - - u1_plda_pcie_pl_sideband_out_31_0 - u1_plda_pcie_pl_sideband_out_31_0 - [31:0] + restart_det + Restart DET + [12:12] read-write - - - - stg_sysconsaif_syscfg780 - STG SYSCONSAIF SYSCFG 780 - 0x30c - 32 - - u1_plda_pcie_pl_sideband_out_63_32 - u1_plda_pcie_pl_sideband_out_63_32 - [31:0] + mst_on_hold + Master on Hold + [13:13] read-write - stg_sysconsaif_syscfg784 - STG SYSCONSAIF SYSCFG 784 - 0x310 + raw_intr_stat + DesignWare I2C Raw Interrupt Status + 0x34 32 - u1_plda_pcie_pl_wake_in - u1_plda_pcie_pl_wake_in + rx_under + RX FIFO Underrun [0:0] - read-write + read-only - u1_plda_pcie_pl_wake_oen - u1_plda_pcie_pl_wake_oen + rx_over + RX FIFO Overrun [1:1] read-only - u1_plda_pcie_rx_standby_o - u1_plda_pcie_rx_standby_o + rx_full + RX FIFO Full [2:2] read-only + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + - stg_sysconsaif_syscfg788 - STG SYSCONSAIF SYSCFG 788 - 0x314 + rx_tl + DesignWare I2C RX TL + 0x38 32 - u1_plda_pcie_test_in_31_0 - u1_plda_pcie_test_in_31_0 + rx_tl + rx_tl [31:0] read-write - stg_sysconsaif_syscfg792 - STG SYSCONSAIF SYSCFG 792 - 0x318 + tx_tl + DesignWare I2C TX TL + 0x3c 32 - u1_plda_pcie_test_in_63_32 - u1_plda_pcie_test_in_63_32 + tx_tl + tx_tl [31:0] read-write - stg_sysconsaif_syscfg796 - STG SYSCONSAIF SYSCFG 796 - 0x31c + clr_intr + DesignWare I2C Clear Interrrupt + 0x40 32 - u1_plda_pcie_test_out_bridge_31_0 - u1_plda_pcie_test_out_bridge_31_0 - [31:0] + rx_under + RX FIFO Underrun + [0:0] read-write - - - - stg_sysconsaif_syscfg800 - STG SYSCONSAIF SYSCFG 800 - 0x320 - 32 - - u1_plda_pcie_test_out_bridge_63_32 - u1_plda_pcie_test_out_bridge_63_32 - [31:0] + rx_over + RX FIFO Overrun + [1:1] read-write - - - - stg_sysconsaif_syscfg804 - STG SYSCONSAIF SYSCFG 804 - 0x324 - 32 - - u1_plda_pcie_test_out_bridge_95_64 - u1_plda_pcie_test_out_bridge_95_64 - [31:0] + rx_full + RX FIFO Full + [2:2] read-write - - - - stg_sysconsaif_syscfg808 - STG SYSCONSAIF SYSCFG 808 - 0x328 - 32 - - u1_plda_pcie_test_out_bridge_127_96 - u1_plda_pcie_test_out_bridge_127_96 - [31:0] + tx_over + TX FIFO Overrun + [3:3] read-write - - - - stg_sysconsaif_syscfg812 - STG SYSCONSAIF SYSCFG 812 - 0x32c - 32 - - u1_plda_pcie_test_out_bridge_159_128 - u1_plda_pcie_test_out_bridge_159_128 - [31:0] + tx_empty + TX FIFO Empty + [4:4] read-write - - - - stg_sysconsaif_syscfg816 - STG SYSCONSAIF SYSCFG 816 - 0x330 - 32 - - u1_plda_pcie_test_out_bridge_191_160 - u1_plda_pcie_test_out_bridge_191_160 - [31:0] + rd_req + Read Request + [5:5] read-write - - - - stg_sysconsaif_syscfg820 - STG SYSCONSAIF SYSCFG 820 - 0x334 - 32 - - u1_plda_pcie_test_out_bridge_223_192 - u1_plda_pcie_test_out_bridge_223_192 - [31:0] + tx_abrt + TX Abort + [6:6] read-write - - - - stg_sysconsaif_syscfg824 - STG SYSCONSAIF SYSCFG 824 - 0x338 - 32 - - u1_plda_pcie_test_out_bridge_255_224 - u1_plda_pcie_test_out_bridge_255_224 - [31:0] + rx_done + RX Done + [7:7] read-write - - - - stg_sysconsaif_syscfg828 - STG SYSCONSAIF SYSCFG 828 - 0x33c - 32 - - u1_plda_pcie_test_out_bridge_287_256 - u1_plda_pcie_test_out_bridge_287_256 - [31:0] + activity + Activity + [8:8] + read-write + + + stop_det + Stop DET + [9:9] read-write - - - - stg_sysconsaif_syscfg832 - STG SYSCONSAIF SYSCFG 832 - 0x340 - 32 - - u1_plda_pcie_test_out_bridge_319_288 - u1_plda_pcie_test_out_bridge_319_288 - [31:0] + start_det + Start DET + [10:10] read-write - - - - stg_sysconsaif_syscfg836 - STG SYSCONSAIF SYSCFG 836 - 0x344 - 32 - - u1_plda_pcie_test_out_bridge_351_320 - u1_plda_pcie_test_out_bridge_351_320 - [31:0] + gen_call + General Call + [11:11] read-write - - - - stg_sysconsaif_syscfg840 - STG SYSCONSAIF SYSCFG 840 - 0x348 - 32 - - u1_plda_pcie_test_out_bridge_383_352 - u1_plda_pcie_test_out_bridge_383_352 - [31:0] + restart_det + Restart DET + [12:12] read-write - - - - stg_sysconsaif_syscfg844 - STG SYSCONSAIF SYSCFG 844 - 0x34c - 32 - - u1_plda_pcie_test_out_bridge_415_384 - u1_plda_pcie_test_out_bridge_415_384 - [31:0] + mst_on_hold + Master on Hold + [13:13] read-write - stg_sysconsaif_syscfg848 - STG SYSCONSAIF SYSCFG 848 - 0x350 + clr_rx_under + DesignWare I2C Clear RX Underrun + 0x44 32 - u1_plda_pcie_test_out_bridge_447_416 - u1_plda_pcie_test_out_bridge_447_416 + clr_rx_under + clr_rx_under [31:0] read-write - stg_sysconsaif_syscfg852 - STG SYSCONSAIF SYSCFG 852 - 0x354 + clr_rx_over + DesignWare I2C Clear RX Overrun + 0x48 32 - u1_plda_pcie_test_out_bridge_479_448 - u1_plda_pcie_test_out_bridge_479_448 + clr_rx_over + clr_rx_over [31:0] read-write - stg_sysconsaif_syscfg856 - STG SYSCONSAIF SYSCFG 856 - 0x358 + clr_tx_over + DesignWare I2C Clear TX Overrun + 0x4c 32 - u1_plda_pcie_test_out_bridge_511_480 - u1_plda_pcie_test_out_bridge_511_480 + clr_tx_over + clr_tx_over [31:0] read-write - stg_sysconsaif_syscfg860 - STG SYSCONSAIF SYSCFG 860 - 0x35c + clr_rd_req + DesignWare I2C Clear Read Request + 0x50 32 - u1_plda_pcie_test_out_pcie_31_0 - u1_plda_pcie_test_out_pcie_31_0 + clr_rd_req + clr_rd_req [31:0] - read-only + read-write - stg_sysconsaif_syscfg864 - STG SYSCONSAIF SYSCFG 864 - 0x360 + clr_tx_abrt + DesignWare I2C Clear TX Abort + 0x54 32 - u1_plda_pcie_test_out_pcie_63_32 - u1_plda_pcie_test_out_pcie_63_32 + clr_tx_abrt + clr_tx_abrt [31:0] - read-only + read-write - stg_sysconsaif_syscfg868 - STG SYSCONSAIF SYSCFG 868 - 0x364 + clr_rx_done + DesignWare I2C Clear RX Done + 0x58 32 - u1_plda_pcie_test_out_pcie_95_64 - u1_plda_pcie_test_out_pcie_95_64 + clr_rx_done + clr_rx_done [31:0] - read-only + read-write - stg_sysconsaif_syscfg872 - STG SYSCONSAIF SYSCFG 872 - 0x368 + clr_activity + DesignWare I2C Clear Activity + 0x5c 32 - u1_plda_pcie_test_out_pcie_127_96 - u1_plda_pcie_test_out_pcie_127_96 + clr_activity + clr_activity [31:0] - read-only + read-write - stg_sysconsaif_syscfg876 - STG SYSCONSAIF SYSCFG 876 - 0x36c + clr_stop_det + DesignWare I2C Clear Stop DET + 0x60 32 - u1_plda_pcie_test_out_pcie_159_128 - u1_plda_pcie_test_out_pcie_159_128 + clr_stop_det + clr_stop_det [31:0] - read-only + read-write - stg_sysconsaif_syscfg880 - STG SYSCONSAIF SYSCFG 880 - 0x370 + clr_start_det + DesignWare I2C Clear Start DET + 0x64 32 - u1_plda_pcie_test_out_pcie_191_160 - u1_plda_pcie_test_out_pcie_191_160 + clr_start_det + clr_start_det [31:0] - read-only + read-write - stg_sysconsaif_syscfg884 - STG SYSCONSAIF SYSCFG 884 - 0x374 + clr_gen_call + DesignWare I2C Clear General Call + 0x68 32 - u1_plda_pcie_test_out_pcie_223_192 - u1_plda_pcie_test_out_pcie_223_192 + clr_gen_call + clr_gen_call [31:0] - read-only + read-write - stg_sysconsaif_syscfg888 - STG SYSCONSAIF SYSCFG 888 - 0x378 + enable + DesignWare I2C Enable + 0x6c 32 - u1_plda_pcie_test_out_pcie_255_224 - u1_plda_pcie_test_out_pcie_255_224 - [31:0] - read-only + abort + abort + [1:1] + read-write - stg_sysconsaif_syscfg892 - STG SYSCONSAIF SYSCFG 892 - 0x37c + status + DesignWare I2C Status + 0x70 32 - u1_plda_pcie_test_out_pcie_287_256 - u1_plda_pcie_test_out_pcie_287_256 - [31:0] + activity + activity + [0:0] read-only - - - - stg_sysconsaif_syscfg896 - STG SYSCONSAIF SYSCFG 896 - 0x380 - 32 - - u1_plda_pcie_test_out_pcie_319_288 - u1_plda_pcie_test_out_pcie_319_288 - [31:0] + tfe + tfe + [2:2] read-only - - - - stg_sysconsaif_syscfg900 - STG SYSCONSAIF SYSCFG 900 - 0x384 - 32 - - u1_plda_pcie_test_out_pcie_351_320 - u1_plda_pcie_test_out_pcie_351_320 - [31:0] + rfne + rfne + [3:3] read-only - - - - stg_sysconsaif_syscfg904 - STG SYSCONSAIF SYSCFG 904 - 0x388 - 32 - - u1_plda_pcie_test_out_pcie_383_352 - u1_plda_pcie_test_out_pcie_383_352 - [31:0] + master_activity + master_activity + [5:5] read-only - - - - stg_sysconsaif_syscfg908 - STG SYSCONSAIF SYSCFG 908 - 0x38c - 32 - - u1_plda_pcie_test_out_pcie_415_384 - u1_plda_pcie_test_out_pcie_415_384 - [31:0] + slave_activity + slave_activity + [6:6] read-only - stg_sysconsaif_syscfg912 - STG SYSCONSAIF SYSCFG 912 - 0x390 + txflr + DesignWare I2C TX Failure + 0x74 32 - - u1_plda_pcie_test_out_pcie_447_416 - u1_plda_pcie_test_out_pcie_447_416 + + txflr + txflr [31:0] - read-only + read-write - stg_sysconsaif_syscfg916 - STG SYSCONSAIF SYSCFG 916 - 0x394 + rxflr + DesignWare I2C RX Failure + 0x78 32 - u1_plda_pcie_test_out_pcie_479_448 - u1_plda_pcie_test_out_pcie_479_448 + rxflr + rxflr [31:0] - read-only + read-write - stg_sysconsaif_syscfg920 - STG SYSCONSAIF SYSCFG 920 - 0x398 + sda_hold + DesignWare I2C SDA Hold + 0x7c 32 - u1_plda_pcie_test_out_pcie_511_480 - u1_plda_pcie_test_out_pcie_511_480 + sda_hold + sda_hold [31:0] - read-only + read-write - stg_sysconsaif_syscfg924 - STG SYSCONSAIF SYSCFG 924 - 0x39c + tx_abrt_source + DesignWare I2C TX Abort Source + 0x80 32 - u1_plda_pcie_test_sel - u1_plda_pcie_test_sel - [3:0] - read-write + b7_addr_noack + b7_addr_noack + [0:0] + read-only - u1_plda_pcie_tl_clock_freq - u1_plda_pcie_tl_clock_freq - [25:4] - read-write + b10_addr1_noack + b10_addr1_noack + [1:1] + read-only - - - - stg_sysconsaif_syscfg928 - STG SYSCONSAIF SYSCFG 928 - 0x3a0 - 32 - - u1_plda_pcie_tl_ctrl_hotplug - u1_plda_pcie_tl_ctrl_hotplug - [15:0] + b10_addr2_noack + b10_addr2_noack + [2:2] read-only - u1_plda_pcie_tl_report_hotplug - u1_plda_pcie_tl_report_hotplug - [31:16] - read-write + txdata_noack + txdata_noack + [3:3] + read-only + + + gcall_noack + gcall_noack + [4:4] + read-only + + + gcall_read + gcall_read + [5:5] + read-only + + + sbyte_ackdet + sbyte_ackdet + [7:7] + read-only + + + sbyte_norstrt + sbyte_norstrt + [9:9] + read-only + + + b10_rd_norstrt + b10_rd_norstrt + [10:10] + read-only + + + master_dis + master_dis + [11:11] + read-only + + + arb_lost + arb_lost + [12:12] + read-only + + + slave_flush_txfifo + slave_flush_txfifo + [13:13] + read-only + + + slave_arblost + slave_arblost + [14:14] + read-only + + + slave_rd_intx + slave_rd_intx + [15:15] + read-only - stg_sysconsaif_syscfg932 - STG SYSCONSAIF SYSCFG 932 - 0x3a4 + enable_status + DesignWare I2C Enable Status + 0x9c 32 - u1_plda_pcie_tx_pattern - u1_plda_pcie_tx_pattern - [1:0] + activity + activity + [0:0] read-write - u1_plda_pcie_usb3_bus_width - u1_plda_pcie_usb3_bus_width - [3:2] + tfe + tfe + [2:2] read-write - u1_plda_pcie_usb3_phy_enable - u1_plda_pcie_usb3_phy_enable - [4:4] + rfne + rfne + [3:3] read-write - u1_plda_pcie_usb3_rate - u1_plda_pcie_usb3_rate - [6:5] + master_activity + master_activity + [5:5] read-write - u1_plda_pcie_usb3_rx_standby - u1_plda_pcie_usb3_rx_standby - [7:7] + slave_activity + slave_activity + [6:6] read-write + + + + clr_restart_det + DesignWare I2C Clear Restart DET + 0xa8 + 32 + - u1_plda_pcie_xwdecerr - u1_plda_pcie_xwdecerr - [8:8] - read-only - - - u1_plda_pcie_xwerrclr - u1_plda_pcie_xwerrclr - [9:9] + clr_restart_det + clr_restart_det + [31:0] read-write + + + + comp_param_1 + DesignWare I2C Compatibility Parameter 1 + 0xf4 + 32 + - u1_plda_pcie_xwslverr - u1_plda_pcie_xwslverr - [10:10] + speed + Speed mask - 01: Standard, 10: Full, 11: High + [3:2] read-only - - - - syscon_0 - From syscon, peripheral generator - 0x10240000 - - 0 - 0x1000 - registers - - - - snps_dw_apb_uart_3 - From snps,dw-apb-uart, peripheral generator - 0x12000000 - - 0 - 0x10000 - registers - - - - snps_dw_apb_uart_4 - From snps,dw-apb-uart, peripheral generator - 0x12010000 - - 0 - 0x10000 - registers - - - - snps_dw_apb_uart_5 - From snps,dw-apb-uart, peripheral generator - 0x12020000 - - 0 - 0x10000 - registers - + + comp_version + DesignWare I2C Compatibility Version + 0xf8 + 32 + + + comp_version + comp_version + [31:0] + read-only + + + + + comp_type + DesignWare I2C Compatibility Type + 0xfc + 32 + + + comp_type + comp_type + [31:0] + read-only + + + + - snps_designware_i2c_3 + snps_designware_i2c_5 From snps,designware-i2c, peripheral generator - 0x12030000 + 0x12050000 0 0x10000 @@ -10474,9 +12952,19 @@ - snps_designware_i2c_4 + x_powers_axp15060_0 + From x-powers,axp15060, peripheral generator + 0x36 + + 0 + 0x36 + registers + + + + snps_designware_i2c_6 From snps,designware-i2c, peripheral generator - 0x12040000 + 0x12060000 0 0x10000 @@ -10586,107 +13074,291 @@ 32 - dat - Data Command Data Byte - [7:0] + dat + Data Command Data Byte + [7:0] + read-write + + + first_data_byte + Data Command First Data Byte - 0: False, 1: True + [11:11] + read-write + + + + + ss_scl_hcnt + DesignWare I2C SS SCL HCNT + 0x14 + 32 + + + ss_scl_hcnt + ss_scl_hcnt + [31:0] + read-write + + + + + ss_scl_lcnt + DesignWare I2C SS SCL LCNT + 0x18 + 32 + + + ss_scl_lcnt + ss_scl_lcnt + [31:0] + read-write + + + + + fs_scl_hcnt + DesignWare I2C FS SCL HCNT + 0x1c + 32 + + + fs_scl_hcnt + fs_scl_hcnt + [31:0] + read-write + + + + + fs_scl_lcnt + DesignWare I2C FS SCL LCNT + 0x20 + 32 + + + fs_scl_lcnt + fs_scl_lcnt + [31:0] + read-write + + + + + hs_scl_hcnt + DesignWare I2C HS SCL HCNT + 0x24 + 32 + + + hs_scl_hcnt + hs_scl_hcnt + [31:0] + read-write + + + + + hs_scl_lcnt + DesignWare I2C HS SCL LCNT + 0x28 + 32 + + + hs_scl_lcnt + hs_scl_lcnt + [31:0] + read-write + + + + + intr_stat + DesignWare I2C Interrupt Status + 0x2c + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-only + + + rx_over + RX FIFO Overrun + [1:1] + read-only + + + rx_full + RX FIFO Full + [2:2] + read-only + + + tx_over + TX FIFO Overrun + [3:3] + read-only + + + tx_empty + TX FIFO Empty + [4:4] + read-only + + + rd_req + Read Request + [5:5] + read-only + + + tx_abrt + TX Abort + [6:6] + read-only + + + rx_done + RX Done + [7:7] + read-only + + + activity + Activity + [8:8] + read-only + + + stop_det + Stop DET + [9:9] + read-only + + + start_det + Start DET + [10:10] + read-only + + + gen_call + General Call + [11:11] + read-only + + + restart_det + Restart DET + [12:12] + read-only + + + mst_on_hold + Master on Hold + [13:13] + read-only + + + + + intr_mask + DesignWare I2C Interrupt Mask + 0x30 + 32 + + + rx_under + RX FIFO Underrun + [0:0] + read-write + + + rx_over + RX FIFO Overrun + [1:1] + read-write + + + rx_full + RX FIFO Full + [2:2] + read-write + + + tx_over + TX FIFO Overrun + [3:3] + read-write + + + tx_empty + TX FIFO Empty + [4:4] + read-write + + + rd_req + Read Request + [5:5] read-write - first_data_byte - Data Command First Data Byte - 0: False, 1: True - [11:11] + tx_abrt + TX Abort + [6:6] read-write - - - - ss_scl_hcnt - DesignWare I2C SS SCL HCNT - 0x14 - 32 - - ss_scl_hcnt - ss_scl_hcnt - [31:0] + rx_done + RX Done + [7:7] read-write - - - - ss_scl_lcnt - DesignWare I2C SS SCL LCNT - 0x18 - 32 - - ss_scl_lcnt - ss_scl_lcnt - [31:0] + activity + Activity + [8:8] read-write - - - - fs_scl_hcnt - DesignWare I2C FS SCL HCNT - 0x1c - 32 - - fs_scl_hcnt - fs_scl_hcnt - [31:0] + stop_det + Stop DET + [9:9] read-write - - - - fs_scl_lcnt - DesignWare I2C FS SCL LCNT - 0x20 - 32 - - fs_scl_lcnt - fs_scl_lcnt - [31:0] + start_det + Start DET + [10:10] read-write - - - - hs_scl_hcnt - DesignWare I2C HS SCL HCNT - 0x24 - 32 - - hs_scl_hcnt - hs_scl_hcnt - [31:0] + gen_call + General Call + [11:11] read-write - - - - hs_scl_lcnt - DesignWare I2C HS SCL LCNT - 0x28 - 32 - - hs_scl_lcnt - hs_scl_lcnt - [31:0] + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] read-write - intr_stat - DesignWare I2C Interrupt Status - 0x2c + raw_intr_stat + DesignWare I2C Raw Interrupt Status + 0x34 32 @@ -10776,9 +13448,37 @@ - intr_mask - DesignWare I2C Interrupt Mask - 0x30 + rx_tl + DesignWare I2C RX TL + 0x38 + 32 + + + rx_tl + rx_tl + [31:0] + read-write + + + + + tx_tl + DesignWare I2C TX TL + 0x3c + 32 + + + tx_tl + tx_tl + [31:0] + read-write + + + + + clr_intr + DesignWare I2C Clear Interrrupt + 0x40 32 @@ -10836,665 +13536,861 @@ read-write - stop_det - Stop DET - [9:9] + stop_det + Stop DET + [9:9] + read-write + + + start_det + Start DET + [10:10] + read-write + + + gen_call + General Call + [11:11] + read-write + + + restart_det + Restart DET + [12:12] + read-write + + + mst_on_hold + Master on Hold + [13:13] + read-write + + + + + clr_rx_under + DesignWare I2C Clear RX Underrun + 0x44 + 32 + + + clr_rx_under + clr_rx_under + [31:0] + read-write + + + + + clr_rx_over + DesignWare I2C Clear RX Overrun + 0x48 + 32 + + + clr_rx_over + clr_rx_over + [31:0] + read-write + + + + + clr_tx_over + DesignWare I2C Clear TX Overrun + 0x4c + 32 + + + clr_tx_over + clr_tx_over + [31:0] + read-write + + + + + clr_rd_req + DesignWare I2C Clear Read Request + 0x50 + 32 + + + clr_rd_req + clr_rd_req + [31:0] + read-write + + + + + clr_tx_abrt + DesignWare I2C Clear TX Abort + 0x54 + 32 + + + clr_tx_abrt + clr_tx_abrt + [31:0] + read-write + + + + + clr_rx_done + DesignWare I2C Clear RX Done + 0x58 + 32 + + + clr_rx_done + clr_rx_done + [31:0] + read-write + + + + + clr_activity + DesignWare I2C Clear Activity + 0x5c + 32 + + + clr_activity + clr_activity + [31:0] read-write + + + + clr_stop_det + DesignWare I2C Clear Stop DET + 0x60 + 32 + - start_det - Start DET - [10:10] + clr_stop_det + clr_stop_det + [31:0] read-write + + + + clr_start_det + DesignWare I2C Clear Start DET + 0x64 + 32 + - gen_call - General Call - [11:11] + clr_start_det + clr_start_det + [31:0] read-write + + + + clr_gen_call + DesignWare I2C Clear General Call + 0x68 + 32 + - restart_det - Restart DET - [12:12] + clr_gen_call + clr_gen_call + [31:0] read-write + + + + enable + DesignWare I2C Enable + 0x6c + 32 + - mst_on_hold - Master on Hold - [13:13] + abort + abort + [1:1] read-write - raw_intr_stat - DesignWare I2C Raw Interrupt Status - 0x34 + status + DesignWare I2C Status + 0x70 32 - rx_under - RX FIFO Underrun + activity + activity [0:0] read-only - rx_over - RX FIFO Overrun - [1:1] - read-only - - - rx_full - RX FIFO Full + tfe + tfe [2:2] read-only - tx_over - TX FIFO Overrun + rfne + rfne [3:3] read-only - tx_empty - TX FIFO Empty - [4:4] - read-only - - - rd_req - Read Request + master_activity + master_activity [5:5] read-only - tx_abrt - TX Abort + slave_activity + slave_activity [6:6] read-only + + + + txflr + DesignWare I2C TX Failure + 0x74 + 32 + - rx_done - RX Done - [7:7] - read-only - - - activity - Activity - [8:8] - read-only - - - stop_det - Stop DET - [9:9] - read-only - - - start_det - Start DET - [10:10] - read-only - - - gen_call - General Call - [11:11] - read-only - - - restart_det - Restart DET - [12:12] - read-only - - - mst_on_hold - Master on Hold - [13:13] - read-only + txflr + txflr + [31:0] + read-write - rx_tl - DesignWare I2C RX TL - 0x38 + rxflr + DesignWare I2C RX Failure + 0x78 32 - rx_tl - rx_tl + rxflr + rxflr [31:0] read-write - tx_tl - DesignWare I2C TX TL - 0x3c + sda_hold + DesignWare I2C SDA Hold + 0x7c 32 - tx_tl - tx_tl + sda_hold + sda_hold [31:0] read-write - clr_intr - DesignWare I2C Clear Interrrupt - 0x40 + tx_abrt_source + DesignWare I2C TX Abort Source + 0x80 32 - rx_under - RX FIFO Underrun + b7_addr_noack + b7_addr_noack [0:0] - read-write + read-only - rx_over - RX FIFO Overrun + b10_addr1_noack + b10_addr1_noack [1:1] - read-write + read-only - rx_full - RX FIFO Full + b10_addr2_noack + b10_addr2_noack [2:2] - read-write + read-only - tx_over - TX FIFO Overrun + txdata_noack + txdata_noack [3:3] - read-write + read-only - tx_empty - TX FIFO Empty + gcall_noack + gcall_noack [4:4] - read-write + read-only - rd_req - Read Request + gcall_read + gcall_read [5:5] - read-write + read-only + + + sbyte_ackdet + sbyte_ackdet + [7:7] + read-only + + + sbyte_norstrt + sbyte_norstrt + [9:9] + read-only + + + b10_rd_norstrt + b10_rd_norstrt + [10:10] + read-only + + + master_dis + master_dis + [11:11] + read-only + + + arb_lost + arb_lost + [12:12] + read-only + + + slave_flush_txfifo + slave_flush_txfifo + [13:13] + read-only - tx_abrt - TX Abort - [6:6] - read-write + slave_arblost + slave_arblost + [14:14] + read-only - rx_done - RX Done - [7:7] - read-write + slave_rd_intx + slave_rd_intx + [15:15] + read-only + + + + enable_status + DesignWare I2C Enable Status + 0x9c + 32 + activity - Activity - [8:8] - read-write - - - stop_det - Stop DET - [9:9] + activity + [0:0] read-write - start_det - Start DET - [10:10] + tfe + tfe + [2:2] read-write - gen_call - General Call - [11:11] + rfne + rfne + [3:3] read-write - restart_det - Restart DET - [12:12] + master_activity + master_activity + [5:5] read-write - mst_on_hold - Master on Hold - [13:13] + slave_activity + slave_activity + [6:6] read-write - clr_rx_under - DesignWare I2C Clear RX Underrun - 0x44 + clr_restart_det + DesignWare I2C Clear Restart DET + 0xa8 32 - clr_rx_under - clr_rx_under + clr_restart_det + clr_restart_det [31:0] read-write - clr_rx_over - DesignWare I2C Clear RX Overrun - 0x48 + comp_param_1 + DesignWare I2C Compatibility Parameter 1 + 0xf4 32 - clr_rx_over - clr_rx_over - [31:0] - read-write + speed + Speed mask - 01: Standard, 10: Full, 11: High + [3:2] + read-only - clr_tx_over - DesignWare I2C Clear TX Overrun - 0x4c + comp_version + DesignWare I2C Compatibility Version + 0xf8 32 - clr_tx_over - clr_tx_over + comp_version + comp_version [31:0] - read-write + read-only - clr_rd_req - DesignWare I2C Clear Read Request - 0x50 + comp_type + DesignWare I2C Compatibility Type + 0xfc 32 - clr_rd_req - clr_rd_req + comp_type + comp_type [31:0] - read-write + read-only + + + + arm_pl022_3 + From arm,pl022, peripheral generator + 0x12070000 + + 0 + 0x10000 + registers + + - clr_tx_abrt - DesignWare I2C Clear TX Abort - 0x54 - 32 + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. + 0x0 + 16 - clr_tx_abrt - clr_tx_abrt - [31:0] + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] read-write - - - - clr_rx_done - DesignWare I2C Clear RX Done - 0x58 - 32 - - clr_rx_done - clr_rx_done - [31:0] + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] read-write - - - - clr_activity - DesignWare I2C Clear Activity - 0x5c - 32 - - clr_activity - clr_activity - [31:0] + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. + [6:6] read-write - - - - clr_stop_det - DesignWare I2C Clear Stop DET - 0x60 - 32 - - clr_stop_det - clr_stop_det - [31:0] + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] read-write - - - - clr_start_det - DesignWare I2C Clear Start DET - 0x64 - 32 - - clr_start_det - clr_start_det - [31:0] + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] read-write - clr_gen_call - DesignWare I2C Clear General Call - 0x68 - 32 + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. + 0x4 + 16 - clr_gen_call - clr_gen_call - [31:0] + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally + [0:0] + read-write + + + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled + [1:1] + read-write + + + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave + [2:2] + read-write + + + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode + [3:3] read-write - enable - DesignWare I2C Enable - 0x6c - 32 + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 - abort - abort - [1:1] + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] read-write - status - DesignWare I2C Status - 0x70 - 32 + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 - activity - activity + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. [0:0] read-only - tfe - tfe - [2:2] + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. + [1:1] read-only - rfne - rfne - [3:3] + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. + [2:2] read-only - master_activity - master_activity - [5:5] + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. + [3:3] read-only - slave_activity - slave_activity - [6:6] + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] read-only - txflr - DesignWare I2C TX Failure - 0x74 - 32 + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 - txflr - txflr - [31:0] + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] read-write - rxflr - DesignWare I2C RX Failure - 0x78 - 32 + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 - rxflr - rxflr - [31:0] + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked + [0:0] + read-write + + + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked + [1:1] read-write - - - - sda_hold - DesignWare I2C SDA Hold - 0x7c - 32 - - sda_hold - sda_hold - [31:0] + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked + [2:2] + read-write + + + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] read-write - tx_abrt_source - DesignWare I2C TX Abort Source - 0x80 - 32 + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 - b7_addr_noack - b7_addr_noack + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only - b10_addr1_noack - b10_addr1_noack + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only - b10_addr2_noack - b10_addr2_noack + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only - txdata_noack - txdata_noack + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only + + + + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 + - gcall_noack - gcall_noack - [4:4] - read-only - - - gcall_read - gcall_read - [5:5] + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] read-only - sbyte_ackdet - sbyte_ackdet - [7:7] + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] read-only - sbyte_norstrt - sbyte_norstrt - [9:9] + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] read-only - b10_rd_norstrt - b10_rd_norstrt - [10:10] + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] read-only + + + + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 + - master_dis - master_dis - [11:11] - read-only + roric + Clears the SSPRORINTR interrupt + [0:0] + read-write - arb_lost - arb_lost - [12:12] - read-only + rtic + Clears the SSPRTINTR interrupt + [1:1] + read-write + + + + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 + - slave_flush_txfifo - slave_flush_txfifo - [13:13] - read-only + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write - slave_arblost - slave_arblost - [14:14] - read-only + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 + - slave_rd_intx - slave_rd_intx - [15:15] + part_number0 + These bits read back as 0x22 + [7:0] read-only - enable_status - DesignWare I2C Enable Status - 0x9c - 32 + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 - activity - activity - [0:0] - read-write + part_number1 + These bits read back as 0x0 + [3:0] + read-only - tfe - tfe - [2:2] - read-write + designer0 + These bits read back as 0x1 + [7:4] + read-only + + + + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 + - rfne - rfne - [3:3] - read-write + designer1 + These bits read back as 0x4 + [3:0] + read-only - master_activity - master_activity - [5:5] - read-write + revision + These bits return the peripheral revision + [7:4] + read-only + + + + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 + - slave_activity - slave_activity - [6:6] - read-write + configuration + These bits read back as 0x80 + [7:0] + read-only - clr_restart_det - DesignWare I2C Clear Restart DET - 0xa8 - 32 + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 - clr_restart_det - clr_restart_det - [31:0] - read-write + ssp_pcell_id0 + The bits are read as 0xD + [7:0] + read-only - comp_param_1 - DesignWare I2C Compatibility Parameter 1 - 0xf4 - 32 + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 - speed - Speed mask - 01: Standard, 10: Full, 11: High - [3:2] + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] read-only - comp_version - DesignWare I2C Compatibility Version - 0xf8 - 32 + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 - comp_version - comp_version - [31:0] + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] read-only - comp_type - DesignWare I2C Compatibility Type - 0xfc - 32 + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 - comp_type - comp_type - [31:0] + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] read-only @@ -11502,9 +14398,19 @@ - snps_designware_i2c_5 - From snps,designware-i2c, peripheral generator - 0x12050000 + arm_primecell_3 + From arm,primecell, peripheral generator + 0x12070000 + + 0 + 0x10000 + registers + + + + arm_pl022_4 + From arm,pl022, peripheral generator + 0x12080000 0 0x10000 @@ -11512,1017 +14418,1233 @@ - con - DesignWare I2C CON + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 - 32 + 16 - master - I2C Master Connection - 0: Slave, 1: Master - [0:0] - read-write - - - speed - I2C Speed - 01: Standard, 10: Fast, 11: High - [2:1] - read-write - - - slave_10bitaddr - I2C Slave 10-bit Address - 0: False, 1: True - [3:3] - read-write - - - master_10bitaddr - I2C Master 10-bit Address - 0: False, 1: True - [4:4] + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] read-write - restart_en - I2C Restart Enable - 0: False, 1: True - [5:5] + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] read-write - slave_disable - I2C Slave Disable - 0: False, 1: True + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write - stop_det_ifaddressed - I2C Stop DET If Addressed - 0: False, 1: True - [7:7] - read-write - - - tx_empty_ctrl - I2C TX Empty Control - 0: False, 1: True - [8:8] - read-write - - - rx_fifo_full_hld_ctrl - I2C RX FIFO Full Hold Control - 0: False, 1: True - [9:9] + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] read-write - bus_clear_ctrl - I2C Bus Clear Control - 0: False, 1: True - [11:11] + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] read-write - tar - DesignWare I2C TAR + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 - 32 + 16 - tar - tar - [31:0] + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally + [0:0] read-write - - - - sar - DesignWare I2C SAR - 0x8 - 32 - - sar - sar - [31:0] + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled + [1:1] read-write - - - - - data_cmd - DesignWare I2C Data Command - 0x10 - 32 - + - dat - Data Command Data Byte - [7:0] + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave + [2:2] read-write - first_data_byte - Data Command First Data Byte - 0: False, 1: True - [11:11] + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode + [3:3] read-write - ss_scl_hcnt - DesignWare I2C SS SCL HCNT - 0x14 - 32 + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 - ss_scl_hcnt - ss_scl_hcnt - [31:0] + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] read-write - ss_scl_lcnt - DesignWare I2C SS SCL LCNT - 0x18 - 32 + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 - ss_scl_lcnt - ss_scl_lcnt - [31:0] - read-write + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. + [0:0] + read-only + + + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. + [1:1] + read-only + + + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. + [2:2] + read-only + + + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. + [3:3] + read-only + + + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only - fs_scl_hcnt - DesignWare I2C FS SCL HCNT - 0x1c - 32 + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 - fs_scl_hcnt - fs_scl_hcnt - [31:0] + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] read-write - fs_scl_lcnt - DesignWare I2C FS SCL LCNT - 0x20 - 32 + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 - fs_scl_lcnt - fs_scl_lcnt - [31:0] + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked + [0:0] read-write - - - - hs_scl_hcnt - DesignWare I2C HS SCL HCNT - 0x24 - 32 - - hs_scl_hcnt - hs_scl_hcnt - [31:0] + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked + [1:1] read-write - - - - hs_scl_lcnt - DesignWare I2C HS SCL LCNT - 0x28 - 32 - - hs_scl_lcnt - hs_scl_lcnt - [31:0] + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked + [2:2] + read-write + + + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] read-write - intr_stat - DesignWare I2C Interrupt Status - 0x2c - 32 + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 - rx_under - RX FIFO Underrun + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only - rx_over - RX FIFO Overrun + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only - rx_full - RX FIFO Full + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only - tx_over - TX FIFO Overrun + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only + + + + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 + - tx_empty - TX FIFO Empty - [4:4] + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] read-only - rd_req - Read Request - [5:5] + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] read-only - tx_abrt - TX Abort - [6:6] + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] read-only - rx_done - RX Done - [7:7] + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] read-only + + + + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 + + + roric + Clears the SSPRORINTR interrupt + [0:0] + read-write + - activity - Activity - [8:8] - read-only + rtic + Clears the SSPRTINTR interrupt + [1:1] + read-write + + + + + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 + + + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write - stop_det - Stop DET - [9:9] + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + + + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 + + + part_number0 + These bits read back as 0x22 + [7:0] read-only + + + + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 + - start_det - Start DET - [10:10] + part_number1 + These bits read back as 0x0 + [3:0] read-only - gen_call - General Call - [11:11] + designer0 + These bits read back as 0x1 + [7:4] read-only + + + + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 + - restart_det - Restart DET - [12:12] + designer1 + These bits read back as 0x4 + [3:0] read-only - mst_on_hold - Master on Hold - [13:13] + revision + These bits return the peripheral revision + [7:4] read-only - intr_mask - DesignWare I2C Interrupt Mask - 0x30 - 32 + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 - rx_under - RX FIFO Underrun - [0:0] - read-write + configuration + These bits read back as 0x80 + [7:0] + read-only + + + + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 + - rx_over - RX FIFO Overrun - [1:1] - read-write + ssp_pcell_id0 + The bits are read as 0xD + [7:0] + read-only + + + + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 + - rx_full - RX FIFO Full - [2:2] - read-write + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] + read-only + + + + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 + - tx_over - TX FIFO Overrun - [3:3] - read-write + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] + read-only + + + + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 + - tx_empty - TX FIFO Empty - [4:4] + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] + read-only + + + + + + + arm_primecell_4 + From arm,primecell, peripheral generator + 0x12080000 + + 0 + 0x10000 + registers + + + + arm_pl022_5 + From arm,pl022, peripheral generator + 0x12090000 + + 0 + 0x10000 + registers + + + + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. + 0x0 + 16 + + + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] read-write - rd_req - Read Request - [5:5] + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] read-write - tx_abrt - TX Abort + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write - rx_done - RX Done - [7:7] + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] read-write - activity - Activity - [8:8] + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] read-write + + + + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. + 0x4 + 16 + - stop_det - Stop DET - [9:9] + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally + [0:0] read-write - start_det - Start DET - [10:10] + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled + [1:1] read-write - gen_call - General Call - [11:11] + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave + [2:2] read-write - restart_det - Restart DET - [12:12] + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode + [3:3] read-write + + + + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 + - mst_on_hold - Master on Hold - [13:13] + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] read-write - raw_intr_stat - DesignWare I2C Raw Interrupt Status - 0x34 - 32 + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 - rx_under - RX FIFO Underrun + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. [0:0] read-only - rx_over - RX FIFO Overrun + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. [1:1] read-only - rx_full - RX FIFO Full + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. [2:2] read-only - tx_over - TX FIFO Overrun + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. [3:3] read-only - tx_empty - TX FIFO Empty + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [4:4] read-only - - rd_req - Read Request - [5:5] - read-only - - - tx_abrt - TX Abort - [6:6] - read-only - - - rx_done - RX Done - [7:7] - read-only - - - activity - Activity - [8:8] - read-only - - - stop_det - Stop DET - [9:9] - read-only - - - start_det - Start DET - [10:10] - read-only - - - gen_call - General Call - [11:11] - read-only - - - restart_det - Restart DET - [12:12] - read-only - - - mst_on_hold - Master on Hold - [13:13] - read-only - - - - - rx_tl - DesignWare I2C RX TL - 0x38 - 32 - - - rx_tl - rx_tl - [31:0] - read-write - - tx_tl - DesignWare I2C TX TL - 0x3c - 32 + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 - tx_tl - tx_tl - [31:0] + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] read-write - clr_intr - DesignWare I2C Clear Interrrupt - 0x40 - 32 + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 - rx_under - RX FIFO Underrun + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked [0:0] read-write - rx_over - RX FIFO Overrun + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked [1:1] read-write - rx_full - RX FIFO Full + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked [2:2] read-write - tx_over - TX FIFO Overrun - [3:3] - read-write - - - tx_empty - TX FIFO Empty - [4:4] - read-write - - - rd_req - Read Request - [5:5] + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] read-write + + + + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 + - tx_abrt - TX Abort - [6:6] - read-write + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only - rx_done - RX Done - [7:7] - read-write + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only - activity - Activity - [8:8] - read-write + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only - stop_det - Stop DET - [9:9] - read-write + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 + - start_det - Start DET - [10:10] - read-write + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only - gen_call - General Call - [11:11] - read-write + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only - restart_det - Restart DET - [12:12] - read-write + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only - mst_on_hold - Master on Hold - [13:13] - read-write + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only - clr_rx_under - DesignWare I2C Clear RX Underrun - 0x44 - 32 + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 - clr_rx_under - clr_rx_under - [31:0] + roric + Clears the SSPRORINTR interrupt + [0:0] read-write - - - - clr_rx_over - DesignWare I2C Clear RX Overrun - 0x48 - 32 - - clr_rx_over - clr_rx_over - [31:0] + rtic + Clears the SSPRTINTR interrupt + [1:1] read-write - clr_tx_over - DesignWare I2C Clear TX Overrun - 0x4c - 32 + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 - clr_tx_over - clr_tx_over - [31:0] + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] read-write - clr_rd_req - DesignWare I2C Clear Read Request - 0x50 - 32 + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 - clr_rd_req - clr_rd_req - [31:0] - read-write + part_number0 + These bits read back as 0x22 + [7:0] + read-only - clr_tx_abrt - DesignWare I2C Clear TX Abort - 0x54 - 32 + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 - clr_tx_abrt - clr_tx_abrt - [31:0] - read-write + part_number1 + These bits read back as 0x0 + [3:0] + read-only + + + designer0 + These bits read back as 0x1 + [7:4] + read-only - clr_rx_done - DesignWare I2C Clear RX Done - 0x58 - 32 + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 - clr_rx_done - clr_rx_done - [31:0] - read-write + designer1 + These bits read back as 0x4 + [3:0] + read-only + + + revision + These bits return the peripheral revision + [7:4] + read-only - clr_activity - DesignWare I2C Clear Activity - 0x5c - 32 + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 - clr_activity - clr_activity - [31:0] - read-write + configuration + These bits read back as 0x80 + [7:0] + read-only - clr_stop_det - DesignWare I2C Clear Stop DET - 0x60 - 32 + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 - clr_stop_det - clr_stop_det - [31:0] - read-write + ssp_pcell_id0 + The bits are read as 0xD + [7:0] + read-only - clr_start_det - DesignWare I2C Clear Start DET - 0x64 - 32 + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 - clr_start_det - clr_start_det - [31:0] - read-write + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] + read-only - clr_gen_call - DesignWare I2C Clear General Call - 0x68 - 32 + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 - clr_gen_call - clr_gen_call - [31:0] - read-write + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] + read-only - enable - DesignWare I2C Enable - 0x6c - 32 + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 - abort - abort - [1:1] - read-write + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] + read-only + + + + arm_primecell_5 + From arm,primecell, peripheral generator + 0x12090000 + + 0 + 0x10000 + registers + + + + arm_pl022_6 + From arm,pl022, peripheral generator + 0x120A0000 + + 0 + 0x10000 + registers + + - status - DesignWare I2C Status - 0x70 - 32 + ssp_cr0 + SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. + 0x0 + 16 - activity - activity - [0:0] - read-only + scr + Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data + [3:0] + read-write - tfe - tfe - [2:2] - read-only + frf + Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved + [5:4] + read-write - rfne - rfne - [3:3] - read-only + spo + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. + [6:6] + read-write - master_activity - master_activity - [5:5] - read-only + sph + SSPCLKOUT phase, applicable to Motorola SPI frame format only. + [6:6] + read-write - slave_activity - slave_activity - [6:6] - read-only + scr + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] + [15:8] + read-write - txflr - DesignWare I2C TX Failure - 0x74 - 32 + ssp_cr1 + SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. + 0x4 + 16 - txflr - txflr - [31:0] + lbm + Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally + [0:0] read-write - - - - rxflr - DesignWare I2C RX Failure - 0x78 - 32 - - rxflr - rxflr - [31:0] + sse + Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled + [1:1] + read-write + + + ms + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave + [2:2] + read-write + + + sod + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode + [3:3] read-write - sda_hold - DesignWare I2C SDA Hold - 0x7c - 32 + ssp_dr + SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. + 0x8 + 16 - sda_hold - sda_hold - [31:0] + data + Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] read-write - tx_abrt_source - DesignWare I2C TX Abort Source - 0x80 - 32 + ssp_sr + SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. + 0xc + 16 - b7_addr_noack - b7_addr_noack + tfe + Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. [0:0] read-only - b10_addr1_noack - b10_addr1_noack + tnf + Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. [1:1] read-only - b10_addr2_noack - b10_addr2_noack + rne + Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. [2:2] read-only - txdata_noack - txdata_noack + rff + Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. [3:3] read-only - gcall_noack - gcall_noack + bsy + PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [4:4] read-only + + + + ssp_cpsr + SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. + 0x10 + 16 + - gcall_read - gcall_read - [5:5] - read-only + cpsdvsr + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] + read-write + + + + + ssp_imsc + The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. + 0x14 + 16 + + + rorim + Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked + [0:0] + read-write - sbyte_ackdet - sbyte_ackdet - [7:7] + rtim + Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked + [1:1] + read-write + + + rxim + Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked + [2:2] + read-write + + + txim + Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked + [2:2] + read-write + + + + + ssp_ris + The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. + 0x18 + 16 + + + rorris + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] read-only - sbyte_norstrt - sbyte_norstrt - [9:9] + rtris + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] read-only - b10_rd_norstrt - b10_rd_norstrt - [10:10] + rxris + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] read-only - master_dis - master_dis - [11:11] + txris + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] read-only + + + + ssp_mis + The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. + 0x1c + 16 + - arb_lost - arb_lost - [12:12] + rormis + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] read-only - slave_flush_txfifo - slave_flush_txfifo - [13:13] + rtmis + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] read-only - slave_arblost - slave_arblost - [14:14] + rxmis + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] read-only - slave_rd_intx - slave_rd_intx - [15:15] + txmis + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] read-only - enable_status - DesignWare I2C Enable Status - 0x9c - 32 + ssp_icr + The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. + 0x20 + 16 - activity - activity + roric + Clears the SSPRORINTR interrupt [0:0] read-write - tfe - tfe - [2:2] + rtic + Clears the SSPRTINTR interrupt + [1:1] read-write + + + + ssp_dmacr + The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. + 0x24 + 16 + - rfne - rfne - [3:3] + rxdmae + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] read-write - master_activity - master_activity - [5:5] + txdmae + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] read-write + + + + ssp_periph_id0 + The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe0 + 16 + - slave_activity - slave_activity - [6:6] - read-write + part_number0 + These bits read back as 0x22 + [7:0] + read-only - clr_restart_det - DesignWare I2C Clear Restart DET - 0xa8 - 32 + ssp_periph_id1 + The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe4 + 16 - clr_restart_det - clr_restart_det - [31:0] - read-write + part_number1 + These bits read back as 0x0 + [3:0] + read-only + + + designer0 + These bits read back as 0x1 + [7:4] + read-only - comp_param_1 - DesignWare I2C Compatibility Parameter 1 - 0xf4 - 32 + ssp_periph_id2 + The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfe8 + 16 - speed - Speed mask - 01: Standard, 10: Full, 11: High - [3:2] + designer1 + These bits read back as 0x4 + [3:0] + read-only + + + revision + These bits return the peripheral revision + [7:4] read-only - comp_version - DesignWare I2C Compatibility Version - 0xf8 - 32 + ssp_periph_id3 + The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. + 0xfec + 16 - comp_version - comp_version - [31:0] + configuration + These bits read back as 0x80 + [7:0] read-only - comp_type - DesignWare I2C Compatibility Type - 0xfc - 32 + ssp_pcell_id0 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff0 + 16 - comp_type - comp_type - [31:0] + ssp_pcell_id0 + The bits are read as 0xD + [7:0] + read-only + + + + + ssp_pcell_id1 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff4 + 16 + + + ssp_pcell_id1 + The bits are read as 0xF0 + [7:0] + read-only + + + + + ssp_pcell_id2 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xff8 + 16 + + + ssp_pcell_id2 + The bits are read as 0x5 + [7:0] + read-only + + + + + ssp_pcell_id3 + The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. + 0xffc + 16 + + + ssp_pcell_id3 + The bits are read as 0xB1 + [7:0] read-only @@ -12530,19 +15652,39 @@ - atmel_24c04_0 - From atmel,24c04, peripheral generator - 0x50 + arm_primecell_6 + From arm,primecell, peripheral generator + 0x120A0000 0 - 0x50 + 0x10000 registers - snps_designware_i2c_6 - From snps,designware-i2c, peripheral generator - 0x12060000 + starfive_jh7110_temp_0 + From starfive,jh7110-temp, peripheral generator + 0x120E0000 + + 0 + 0x10000 + registers + + + + jedec_spi_nor_0 + From jedec,spi-nor, peripheral generator + 0x0 + + 0 + 0x0 + registers + + + + starfive_jh7110_syscrg_0 + From starfive,jh7110-syscrg, peripheral generator + 0x13020000 0 0x10000 @@ -12550,1291 +15692,1521 @@ - con - DesignWare I2C CON + clk_cpu_root + Clock CPU Root 0x0 32 - master - I2C Master Connection - 0: Slave, 1: Master - [0:0] + clk_mux_sel + Clock multiplexing selector: clk_osc, clk_pll0 + [29:24] read-write + + + + clk_cpu_core + Clock CPU Core + 0x4 + 32 + - speed - I2C Speed - 01: Standard, 10: Fast, 11: High - [2:1] + clk_divcfg + Clock divider coefficient: Max=7, Default=1, Min=1, Typical=1 + [23:0] read-write + + + + clk_cpu_bus + Clock CPU Bus + 0x8 + 32 + - slave_10bitaddr - I2C Slave 10-bit Address - 0: False, 1: True - [3:3] + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] read-write + + + + clk_gpu_root + Clock GPU Root + 0xc + 32 + - master_10bitaddr - I2C Master 10-bit Address - 0: False, 1: True - [4:4] + clk_mux_sel + Clock multiplexing selector: clk_pll2, clk_pll1 + [29:24] read-write + + + + clk_peripheral_root + Clock Peripheral Root + 0x10 + 32 + - restart_en - I2C Restart Enable - 0: False, 1: True - [5:5] + clk_mux_sel + Clock multiplexing selector: clk_pll0, clk_pll2 + [29:24] read-write - slave_disable - I2C Slave Disable - 0: False, 1: True - [6:6] + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] read-write + + + + clk_bus_root + Clock Bus Root + 0x14 + 32 + - stop_det_ifaddressed - I2C Stop DET If Addressed - 0: False, 1: True - [7:7] + clk_mux_sel + Clock multiplexing selector: clk_osc, clk_pll2 + [29:24] read-write + + + + clk_nocstg_bus + Clock NOCSTG Bus + 0x18 + 32 + - tx_empty_ctrl - I2C TX Empty Control - 0: False, 1: True - [8:8] + clk_divcfg + Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3 + [23:0] read-write + + + + clk_axi_cfg0 + Clock AXI Configuration 0 + 0x1c + 32 + - rx_fifo_full_hld_ctrl - I2C RX FIFO Full Hold Control - 0: False, 1: True - [9:9] + clk_divcfg + Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3 + [23:0] read-write + + + + clk_stg_axiahb + Clock STG AXI AHB + 0x20 + 32 + - bus_clear_ctrl - I2C Bus Clear Control - 0: False, 1: True - [11:11] + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] read-write - tar - DesignWare I2C TAR - 0x4 + clk_ahb0 + Clock AHB 0 + 0x24 32 - tar - tar - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - sar - DesignWare I2C SAR - 0x8 + clk_ahb1 + Clock AHB 1 + 0x28 32 - sar - sar - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - data_cmd - DesignWare I2C Data Command - 0x10 + clk_apb_bus + Clock APB Bus + 0x2c 32 - dat - Data Command Data Byte - [7:0] + clk_divcfg + Clock divider coefficient: Max=8, Default=4, Min=4, Typical=4 + [23:0] read-write + + + + clk_apb0 + Clock APB 0 + 0x30 + 32 + - first_data_byte - Data Command First Data Byte - 0: False, 1: True - [11:11] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - ss_scl_hcnt - DesignWare I2C SS SCL HCNT - 0x14 + clk_pll0_div2 + Clock PLL 0 Divider 2 + 0x34 32 - ss_scl_hcnt - ss_scl_hcnt - [31:0] + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] read-write - ss_scl_lcnt - DesignWare I2C SS SCL LCNT - 0x18 + clk_pll1_div2 + Clock PLL 1 Divider 2 + 0x38 32 - ss_scl_lcnt - ss_scl_lcnt - [31:0] + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] read-write - fs_scl_hcnt - DesignWare I2C FS SCL HCNT - 0x1c + clk_pll2_div2 + Clock PLL 2 Divider 2 + 0x3c 32 - fs_scl_hcnt - fs_scl_hcnt - [31:0] + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] read-write - fs_scl_lcnt - DesignWare I2C FS SCL LCNT - 0x20 + clk_audio_root + Clock Audio Root + 0x40 32 - fs_scl_lcnt - fs_scl_lcnt - [31:0] + clk_divcfg + Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2 + [23:0] read-write - hs_scl_hcnt - DesignWare I2C HS SCL HCNT - 0x24 + clk_mclk_inner + Clock MCLK Inner + 0x44 32 - hs_scl_hcnt - hs_scl_hcnt - [31:0] + clk_divcfg + Clock divider coefficient: Max=64, Default=12, Min=12, Typical=12 + [23:0] read-write - hs_scl_lcnt - DesignWare I2C HS SCL LCNT - 0x28 + clk_mclk + Clock MCLK + 0x48 32 - hs_scl_lcnt - hs_scl_lcnt - [31:0] + clk_mux_sel + Clock multiplexing selector: clk_mclk_inner, clk_mclk_ext + [29:24] read-write - intr_stat - DesignWare I2C Interrupt Status - 0x2c + clk_mclk_out + Clock MCLK Out + 0x4c 32 - rx_under - RX FIFO Underrun - [0:0] - read-only - - - rx_over - RX FIFO Overrun - [1:1] - read-only - - - rx_full - RX FIFO Full - [2:2] - read-only - - - tx_over - TX FIFO Overrun - [3:3] - read-only - - - tx_empty - TX FIFO Empty - [4:4] - read-only - - - rd_req - Read Request - [5:5] - read-only - - - tx_abrt - TX Abort - [6:6] - read-only - - - rx_done - RX Done - [7:7] - read-only - - - activity - Activity - [8:8] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + + clk_isp_2x + Clock ISP 2x + 0x50 + 32 + - stop_det - Stop DET - [9:9] - read-only + clk_mux_sel + Clock multiplexing selector: clk_pll2, clk_pll1 + [29:24] + read-write - start_det - Start DET - [10:10] - read-only + clk_divcfg + Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2 + [23:0] + read-write + + + + clk_isp_axi + Clock ISP AXI + 0x54 + 32 + - gen_call - General Call - [11:11] - read-only + clk_divcfg + Clock divider coefficient: Max=4, Default=2, Min=2, Typical=2 + [23:0] + read-write + + + + clk_gclk0 + Clock GCLK 0 + 0x58 + 32 + - restart_det - Restart DET - [12:12] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write - mst_on_hold - Master on Hold - [13:13] - read-only + clk_divcfg + Clock divider coefficient: Max=62, Default=20, Min=16, Typical=20 + [23:0] + read-write - intr_mask - DesignWare I2C Interrupt Mask - 0x30 + clk_gclk1 + Clock GCLK 1 + 0x5c 32 - rx_under - RX FIFO Underrun - [0:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - rx_over - RX FIFO Overrun - [1:1] + clk_divcfg + Clock divider coefficient: Max=62, Default=16, Min=16, Typical=16 + [23:0] read-write + + + + clk_gclk2 + Clock GCLK 2 + 0x60 + 32 + - rx_full - RX FIFO Full - [2:2] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - tx_over - TX FIFO Overrun - [3:3] + clk_divcfg + Clock divider coefficient: Max=62, Default=12, Min=12, Typical=12 + [23:0] read-write + + + + clk_u7mc_core0 + U7MC Core Clock 0 + 0x64 + 32 + - tx_empty - TX FIFO Empty - [4:4] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u7mc_core1 + U7MC Core Clock 1 + 0x68 + 32 + - rd_req - Read Request - [5:5] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u7mc_core2 + U7MC Core Clock 2 + 0x6c + 32 + - tx_abrt - TX Abort - [6:6] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u7mc_core3 + U7MC Core Clock 3 + 0x70 + 32 + - rx_done - RX Done - [7:7] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u7mc_core4 + U7MC Core Clock 4 + 0x74 + 32 + - activity - Activity - [8:8] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u7mc_debug + U7MC Debug Clock + 0x78 + 32 + - stop_det - Stop DET - [9:9] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + u7mc_rtc_toggle + U7MC RTC Toggle + 0x7c + 32 + - start_det - Start DET - [10:10] + clk_divcfg + Clock divider coefficient: Max=6, Default=6, Min=6, Typical=6 + [23:0] read-write + + + + clk_u7mc_trace0 + U7MC Trace Clock 0 + 0x80 + 32 + - gen_call - General Call - [11:11] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u7mc_trace1 + U7MC Trace Clock 1 + 0x84 + 32 + - restart_det - Restart DET - [12:12] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u7mc_trace2 + U7MC Trace Clock 2 + 0x88 + 32 + - mst_on_hold - Master on Hold - [13:13] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - raw_intr_stat - DesignWare I2C Raw Interrupt Status - 0x34 + clk_u7mc_trace3 + U7MC Trace Clock 3 + 0x8c 32 - rx_under - RX FIFO Underrun - [0:0] - read-only - - - rx_over - RX FIFO Overrun - [1:1] - read-only - - - rx_full - RX FIFO Full - [2:2] - read-only - - - tx_over - TX FIFO Overrun - [3:3] - read-only - - - tx_empty - TX FIFO Empty - [4:4] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + + clk_u7mc_trace4 + U7MC Trace Clock 4 + 0x90 + 32 + - rd_req - Read Request - [5:5] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + + clk_u7mc_trace_com + U7MC Trace Clock COM + 0x94 + 32 + - tx_abrt - TX Abort - [6:6] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + + clk_u0_sft7110_noc_bus_clk_cpu_axi + clk_u0_sft7110_noc_bus_clk_cpu_axi + 0x98 + 32 + - rx_done - RX Done - [7:7] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + + clk_u0_sft7110_noc_bus_clk_axicfg0_axi + clk_u0_sft7110_noc_bus_clk_axicfg0_axi + 0x9c + 32 + - activity - Activity - [8:8] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + + clk_osc_div2 + clk_osc_div2 + 0xa0 + 32 + - stop_det - Stop DET - [9:9] - read-only + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] + read-write + + + + clk_pll1_div4 + clk_pll1_div4 + 0xa4 + 32 + - start_det - Start DET - [10:10] - read-only + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] + read-write + + + + clk_pll1_div8 + clk_pll1_div8 + 0xa8 + 32 + - gen_call - General Call - [11:11] - read-only + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] + read-write + + + + clk_ddr_bus + clk_ddr_bus + 0xac + 32 + - restart_det - Restart DET - [12:12] - read-only + clk_mux_sel + Clock multiplexing selector: clk_osc_div2, clk_pll1_div4, clk_pll1_div8 + [29:24] + read-write + + + + clk_u0_ddr_sft7110_clk_axi + clk_u0_ddr_sfft7110_clk_axi + 0xb0 + 32 + - mst_on_hold - Master on Hold - [13:13] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write - rx_tl - DesignWare I2C RX TL - 0x38 + clk_gpu_core + clk_gpu_core + 0xb4 32 - rx_tl - rx_tl - [31:0] + clk_divcfg + Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3 + [23:0] read-write - tx_tl - DesignWare I2C TX TL - 0x3c + clk_u0_img_gpu_core_clk + clk_u0_img_gpu_core_clk + 0xb8 32 - tx_tl - tx_tl - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_intr - DesignWare I2C Clear Interrrupt - 0x40 + clk_u0_img_gpu_sys_clk + clk_u0_img_gpu_sys_clk + 0xbc 32 - rx_under - RX FIFO Underrun - [0:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u0_img_gpu_clk_apb + clk_u0_img_gpu_clk_apb + 0xc0 + 32 + - rx_over - RX FIFO Overrun - [1:1] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u0_gpu_rtc_toggle + clk_u0_gpu_rtc_toggle + 0xc4 + 32 + - rx_full - RX FIFO Full - [2:2] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - tx_over - TX FIFO Overrun - [3:3] + clk_divcfg + Clock divider coefficient: Max=12, Default=12, Min=12, Typical=12 + [23:0] read-write + + + + clk_u0_sft7110_noc_bus_clk_gpu_axi + clk_u0_sft7110_noc_bus_clk_gpu_axi + 0xc8 + 32 + - tx_empty - TX FIFO Empty - [4:4] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x + clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x + 0xcc + 32 + - rd_req - Read Request - [5:5] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi + clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi + 0xd0 + 32 + - tx_abrt - TX Abort - [6:6] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u0_sft7110_noc_bux_clk_isp_axi + clk_u0_sft7110_noc_bux_clk_isp_axi + 0xd4 + 32 + - rx_done - RX Done - [7:7] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_hifi4_core + clk_hifi4_core + 0xd8 + 32 + - activity - Activity - [8:8] + clk_divcfg + Clock divider coefficient: Max=15, Default=3, Min=3, Typical=3 + [23:0] read-write - - stop_det - Stop DET - [9:9] + + + + clk_hifi4_axi + clk_hifi4_axi + 0xdc + 32 + + + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] read-write + + + + clk_u0_axi_cfg1_dec_clk_main + clk_u0_axi_cfg1_dec_clk_main + 0xe0 + 32 + - start_det - Start DET - [10:10] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u0_axi_cfg1_dec_clk_ahb + clk_u0_axi_cfg1_dec_clk_ahb + 0xe4 + 32 + - gen_call - General Call - [11:11] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src + clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src + 0xe8 + 32 + - restart_det - Restart DET - [12:12] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_vout_axi_divcfg + Clock Video Output AXI DIVCFG + 0xec + 32 + - mst_on_hold - Master on Hold - [13:13] + clk_divcfg + Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2 + [23:0] read-write - clr_rx_under - DesignWare I2C Clear RX Underrun - 0x44 + clk_noc_display_axi + Clock NOC Display AXI + 0xf0 32 - clr_rx_under - clr_rx_under - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_rx_over - DesignWare I2C Clear RX Overrun - 0x48 + clk_vout_ahb + Clock Video Output AHB + 0xf4 32 - clr_rx_over - clr_rx_over - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_tx_over - DesignWare I2C Clear TX Overrun - 0x4c + clk_vout_axi_icg + Clock Video Output AXI ICG + 0xf8 32 - clr_tx_over - clr_tx_over - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_rd_req - DesignWare I2C Clear Read Request - 0x50 + clk_vout_hdmi_tx0_mclk + Clock Video Output HDMI TX0 MCLK + 0xfc 32 - clr_rd_req - clr_rd_req - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_tx_abrt - DesignWare I2C Clear TX Abort - 0x54 + clk_vout_mipi_phy + Clock Video Output MIPI PHY Reference + 0x100 32 - clr_tx_abrt - clr_tx_abrt - [31:0] + clk_divcfg + Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + [23:0] read-write - clr_rx_done - DesignWare I2C Clear RX Done - 0x58 + clk_jpeg_codec_axi + Clock JPEG Codec AXI + 0x104 32 - clr_rx_done - clr_rx_done - [31:0] + clk_divcfg + Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6 + [23:0] read-write - clr_activity - DesignWare I2C Clear Activity - 0x5c + clk_codaj12_axi + CODAJ12 Clock AXI + 0x108 32 - clr_activity - clr_activity - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_stop_det - DesignWare I2C Clear Stop DET - 0x60 + clk_codaj12_core + CODAJ12 Clock Core + 0x10c 32 - clr_stop_det - clr_stop_det - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + clk_divcfg + Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6 + [23:0] read-write - clr_start_det - DesignWare I2C Clear Start DET - 0x64 + clk_codaj12_apb + CODAJ12 Clock APB + 0x110 32 - clr_start_det - clr_start_det - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clr_gen_call - DesignWare I2C Clear General Call - 0x68 + clk_vdec_axi + Clock Video Decoder AXI + 0x114 32 - clr_gen_call - clr_gen_call - [31:0] + clk_divcfg + Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3 + [23:0] read-write - enable - DesignWare I2C Enable - 0x6c + clk_wave511_axi + Clock WAVE511 AXI + 0x118 32 - abort - abort - [1:1] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - status - DesignWare I2C Status - 0x70 + clk_wave511_bpu + Clock WAVE511 BPU + 0x11c 32 - activity - activity - [0:0] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write - tfe - tfe - [2:2] - read-only + clk_divcfg + Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3 + [23:0] + read-write + + + + clk_wave511_vce + Clock WAVE511 VCE + 0x120 + 32 + - rfne - rfne - [3:3] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write - master_activity - master_activity - [5:5] - read-only + clk_divcfg + Clock divider coefficient: Max=7, Default=2, Min=3, Typical=2 + [23:0] + read-write + + + + clk_wave511_apb + Clock WAVE511 APB + 0x124 + 32 + - slave_activity - slave_activity - [6:6] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write - txflr - DesignWare I2C TX Failure - 0x74 + clk_wave511_jpg_arb + Clock WAVE511 JPG ARB + 0x128 32 - txflr - txflr - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - rxflr - DesignWare I2C RX Failure - 0x78 + clk_wave511_jpg_main + Clock WAVE511 JPG Main + 0x12c 32 - rxflr - rxflr - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - sda_hold - DesignWare I2C SDA Hold - 0x7c + clk_noc_vdec_axi + Clock NOC Video Decoder AXI + 0x130 32 - sda_hold - sda_hold - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - tx_abrt_source - DesignWare I2C TX Abort Source - 0x80 + clk_venc_axi + Clock Video Encoder AXI + 0x134 32 - b7_addr_noack - b7_addr_noack - [0:0] - read-only - - - b10_addr1_noack - b10_addr1_noack - [1:1] - read-only - - - b10_addr2_noack - b10_addr2_noack - [2:2] - read-only - - - txdata_noack - txdata_noack - [3:3] - read-only - - - gcall_noack - gcall_noack - [4:4] - read-only - - - gcall_read - gcall_read - [5:5] - read-only - - - sbyte_ackdet - sbyte_ackdet - [7:7] - read-only - - - sbyte_norstrt - sbyte_norstrt - [9:9] - read-only - - - b10_rd_norstrt - b10_rd_norstrt - [10:10] - read-only - - - master_dis - master_dis - [11:11] - read-only - - - arb_lost - arb_lost - [12:12] - read-only - - - slave_flush_txfifo - slave_flush_txfifo - [13:13] - read-only - - - slave_arblost - slave_arblost - [14:14] - read-only - - - slave_rd_intx - slave_rd_intx - [15:15] - read-only + clk_divcfg + Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5 + [23:0] + read-write - enable_status - DesignWare I2C Enable Status - 0x9c + clk_wave420l_axi + Clock WAVE420L AXI + 0x138 32 - activity - activity - [0:0] - read-write - - - tfe - tfe - [2:2] - read-write - - - rfne - rfne - [3:3] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_wave420l_bpu + Clock WAVE420L BPU + 0x13c + 32 + - master_activity - master_activity - [5:5] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - slave_activity - slave_activity - [6:6] + clk_divcfg + Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5 + [23:0] read-write - clr_restart_det - DesignWare I2C Clear Restart DET - 0xa8 + clk_wave420l_vce + Clock WAVE420L VCE + 0x140 32 - clr_restart_det - clr_restart_det - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + + + clk_divcfg + Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5 + [23:0] read-write - comp_param_1 - DesignWare I2C Compatibility Parameter 1 - 0xf4 + clk_wave420l_apb + Clock WAVE420L APB + 0x144 32 - speed - Speed mask - 01: Standard, 10: Full, 11: High - [3:2] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write - comp_version - DesignWare I2C Compatibility Version - 0xf8 + clk_noc_venc_axi + Clock NOC Video Encoder AXI + 0x148 32 - comp_version - comp_version - [31:0] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write - comp_type - DesignWare I2C Compatibility Type - 0xfc + clk_axi_cfg0_dec_main_div + Clock AXI Config 0 DEC Main Divider + 0x14c 32 - comp_type - comp_type - [31:0] - read-only + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write - - - - - jedec_spi_nor_0 - From jedec,spi-nor, peripheral generator - 0x0 - - 0 - 0x0 - registers - - - - starfive_jh7110_pwm_0 - From starfive,jh7110-pwm, peripheral generator - 0x120D0000 - - 0 - 0x10000 - registers - - + - cntr - PTC counter register - 0x0 + clk_axi_cfg0_dec_main + Clock AXI Config 0 DEC Main + 0x150 + 32 - cntr - PWM PTC counter - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - hrc - PTC duty-cycle register - 0x4 + clk_axi_cfg0_dec_hifi4 + Clock AXI Config 0 DEC HIFI4 + 0x154 + 32 - hrc - PWM PTC duty-cycle value - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - lrc - PTC period register - 0x8 + clk_aximem_128b_axi + Clock AXIMEM 128B AXI + 0x158 + 32 - lrc - PWM PTC period value - [31:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - ctrl - PTC control register - 0xc + clk_qspi_ahb + Clock QSPI AHB + 0x15c + 32 - en - PWM PTC enable - [0:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_qspi_apb + Clock QSPI APB + 0x160 + 32 + - eclk - PWM PTC enable clock - [1:1] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_qspi_ref_src + Clock QSPI Reference Source + 0x164 + 32 + - nec - PWM PTC nec - [2:2] + clk_divcfg + Clock divider coefficient: Max=16, Default=10, Min=10, Typical=10 + [23:0] read-write + + + + clk_qspi_ref + Clock QSPI Reference + 0x168 + 32 + - oe - PWM PTC oe - [3:3] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - single - PWM PTC single - [4:4] + clk_mux_sel + Clock multiplexing selector: clk_osc, clk_qspi_ref_src + [29:24] read-write + + + + clk_u0_sd_ahb + U0 SD Clock AHB + 0x16c + 32 + - inte - PWM PTC interrupt enable - [5:5] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u1_sd_ahb + U1 SD Clock AHB + 0x170 + 32 + - int - PWM PTC interrupt - [6:6] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_u0_sd_card + U0 SD Card Clock + 0x174 + 32 + - cntrrst - PWM PTC counter reset - [7:7] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - capte - PWM PTC capte - [8:8] + clk_divcfg + Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2 + [23:0] read-write - - - - starfive_jh7110_syscrg_0 - From starfive,jh7110-syscrg, peripheral generator - 0x13020000 - - 0 - 0x10000 - registers - - - clk_cpu_root - Clock CPU Root - 0x0 + clk_u1_sd_card + U1 SD Card Clock + 0x178 32 - clk_mux_sel - Clock multiplexing selector: clk_osc, clk_pll0 - [29:24] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - - - - clk_cpu_core - Clock CPU Core - 0x4 - 32 - clk_divcfg - Clock divider coefficient: Max=7, Default=1, Min=1, Typical=1 + Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2 [23:0] read-write - clk_cpu_bus - Clock CPU Bus - 0x8 + clk_usb_125m + Clock USB 125M + 0x17c 32 clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10 [23:0] read-write - clk_gpu_root - Clock GPU Root - 0xc + clk_noc_stg_axi + Clock NOC STG AXI + 0x180 32 - clk_mux_sel - Clock multiplexing selector: clk_pll2, clk_pll1 - [29:24] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_peripheral_root - Clock Peripheral Root - 0x10 + clk_gmac5_axi64_ahb + Clock GMAC 5 AXI 64 AHB + 0x184 32 - clk_mux_sel - Clock multiplexing selector: clk_pll0, clk_pll2 - [29:24] - read-write - - - clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 - [23:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_bus_root - Clock Bus Root - 0x14 + clk_gmac5_axi64_axi + Clock GMAC 5 AXI 64 AXI + 0x188 32 - clk_mux_sel - Clock multiplexing selector: clk_osc, clk_pll2 - [29:24] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_nocstg_bus - Clock NOCSTG Bus - 0x18 + clk_gmac_src + Clock GMAC Source + 0x18c 32 clk_divcfg - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3 + Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2 [23:0] read-write - clk_axi_cfg0 - Clock AXI Configuration 0 - 0x1c + clk_gmac1_gtx + Clock GMAC 1 GTX + 0x190 32 clk_divcfg - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3 + Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10 [23:0] read-write - clk_stg_axiahb - Clock STG AXI AHB - 0x20 + clk_gmac1_rmii_rtx + Clock GMAC 1 RMII RTX + 0x194 32 clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2 [23:0] read-write - clk_ahb0 - Clock AHB 0 - 0x24 + clk_gmac5_axi64_ptp + Clock GMAC 5 AXI 64 PTP + 0x198 32 @@ -13843,40 +17215,46 @@ [31:31] read-write + + clk_divcfg + Clock divider coefficient: Max=31, Default=10, Min=15, Typical=10 + [23:0] + read-write + - clk_ahb1 - Clock AHB 1 - 0x28 + clk_gmac5_axi64_rx + Clock GMAC 5 AXI 64 RX + 0x19c 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + dly_chain_sel + Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. + [23:0] read-write - clk_apb_bus - Clock APB Bus - 0x2c + clk_gmac5_axi64_rxi + Clock GMAC 5 AXI 64 RX Inverter + 0x1a0 32 - clk_divcfg - Clock divider coefficient: Max=8, Default=4, Min=4, Typical=4 - [23:0] + clk_polarity + 1: Clock inverter, 0: Clock buffer + [30:30] read-write - clk_apb0 - Clock APB 0 - 0x30 + clk_gmac5_axi64_tx + Clock GMAC 5 AXI 64 TX + 0x1a4 32 @@ -13885,96 +17263,120 @@ [31:31] read-write + + clk_mux_sel + Clock multiplexing selector: clk_gmac1_gtxclk, clk_gmac1_rmii_rtx + [29:24] + read-write + - clk_pll0_div2 - Clock PLL 0 Divider 2 - 0x34 + clk_gmac5_axi64_txi + Clock GMAC 5 AXI 64 TX Inverter + 0x1a8 32 - clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 - [23:0] + clk_polarity + 1: Clock inverter, 0: Clock buffer + [30:30] read-write - clk_pll1_div2 - Clock PLL 1 Divider 2 - 0x38 + clk_gmac1_gtxclk + Clock GMAC 1 GTXC + 0x1ac 32 - clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + dly_chain_sel + Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. [23:0] read-write - clk_pll2_div2 - Clock PLL 2 Divider 2 - 0x3c + clk_gmac0_gtx + Clock GMAC 0 GTX + 0x1b0 32 + + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 + Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10 [23:0] read-write - clk_audio_root - Clock Audio Root - 0x40 + clk_gmac0_ptp + Clock GMAC 0 PTP + 0x1b4 32 + + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + clk_divcfg - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2 + Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25 [23:0] read-write - clk_mclk_inner - Clock MCLK Inner - 0x44 + clk_gmac_phy + Clock GMAC PHY + 0x1b8 32 + + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] + read-write + clk_divcfg - Clock divider coefficient: Max=64, Default=12, Min=12, Typical=12 + Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25 [23:0] read-write - clk_mclk - Clock MCLK - 0x48 + clk_gmac0_gtxclk + Clock GMAC 0 GTXC + 0x1bc 32 - clk_mux_sel - Clock multiplexing selector: clk_mclk_inner, clk_mclk_ext - [29:24] + dly_chain_sel + Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. + [23:0] read-write - clk_mclk_out - Clock MCLK Out - 0x4c + clk_sys_iomux_pclk + Clock SYS IOMUX PCLK + 0x1c0 32 @@ -13986,43 +17388,37 @@ - clk_isp_2x - Clock ISP 2x - 0x50 + clk_mbox_apb + Clock Mailbox APB + 0x1c4 32 - clk_mux_sel - Clock multiplexing selector: clk_pll2, clk_pll1 - [29:24] - read-write - - - clk_divcfg - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2 - [23:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_isp_axi - Clock ISP AXI - 0x54 + clk_internal_ctrl_apb + Clock Internal Controller APB + 0x1c8 32 - clk_divcfg - Clock divider coefficient: Max=4, Default=2, Min=2, Typical=2 - [23:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_gclk0 - Clock GCLK 0 - 0x58 + clk_u0_can_ctrl_apb + U0 Clock CAN Controller APB + 0x1cc 32 @@ -14031,18 +17427,12 @@ [31:31] read-write - - clk_divcfg - Clock divider coefficient: Max=62, Default=20, Min=16, Typical=20 - [23:0] - read-write - - clk_gclk1 - Clock GCLK 1 - 0x5c + clk_u0_can_ctrl_tim + U0 Clock CAN Controller Timer + 0x1d0 32 @@ -14053,16 +17443,16 @@ clk_divcfg - Clock divider coefficient: Max=62, Default=16, Min=16, Typical=16 + Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24 [23:0] read-write - clk_gclk2 - Clock GCLK 2 - 0x60 + clk_u0_can_ctrl_can + U0 Clock CAN Controller CAN + 0x1d4 32 @@ -14073,16 +17463,16 @@ clk_divcfg - Clock divider coefficient: Max=62, Default=12, Min=12, Typical=12 + Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8 [23:0] read-write - clk_u7mc_core0 - U7MC Core Clock 0 - 0x64 + clk_u1_can_ctrl_apb + U1 Clock CAN Controller APB + 0x1d8 32 @@ -14094,9 +17484,9 @@ - clk_u7mc_core1 - U7MC Core Clock 1 - 0x68 + clk_u1_can_ctrl_tim + U1 Clock CAN Controller Timer + 0x1dc 32 @@ -14105,26 +17495,18 @@ [31:31] read-write - - - - clk_u7mc_core2 - U7MC Core Clock 2 - 0x6c - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_divcfg + Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24 + [23:0] read-write - clk_u7mc_core3 - U7MC Core Clock 3 - 0x70 + clk_u1_can_ctrl_can + U1 Clock CAN Controller CAN + 0x1e0 32 @@ -14133,12 +17515,18 @@ [31:31] read-write + + clk_divcfg + Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8 + [23:0] + read-write + - clk_u7mc_core4 - U7MC Core Clock 4 - 0x74 + clk_pwm_apb + Clock PWM APB + 0x1e4 32 @@ -14150,9 +17538,9 @@ - clk_u7mc_debug - U7MC Debug Clock - 0x78 + clk_wdt_apb + Clock WDT APB + 0x1e8 32 @@ -14164,23 +17552,23 @@ - u7mc_rtc_toggle - U7MC RTC Toggle - 0x7c + clk_wdt + Clock WDT + 0x1ec 32 - clk_divcfg - Clock divider coefficient: Max=6, Default=6, Min=6, Typical=6 - [23:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_u7mc_trace0 - U7MC Trace Clock 0 - 0x80 + clk_tim_apb + Clock Timer APB + 0x1f0 32 @@ -14192,9 +17580,9 @@ - clk_u7mc_trace1 - U7MC Trace Clock 1 - 0x84 + clk_tim0 + Clock Timer 0 + 0x1f4 32 @@ -14206,9 +17594,9 @@ - clk_u7mc_trace2 - U7MC Trace Clock 2 - 0x88 + clk_tim1 + Clock Timer 1 + 0x1f8 32 @@ -14220,9 +17608,9 @@ - clk_u7mc_trace3 - U7MC Trace Clock 3 - 0x8c + clk_tim2 + Clock Timer 2 + 0x1fc 32 @@ -14234,9 +17622,9 @@ - clk_u7mc_trace4 - U7MC Trace Clock 4 - 0x90 + clk_tim3 + Clock Timer 3 + 0x200 32 @@ -14248,9 +17636,9 @@ - clk_u7mc_trace_com - U7MC Trace Clock COM - 0x94 + clk_temp_sensor_apb + Clock Temperature Sensor APB + 0x204 32 @@ -14262,9 +17650,9 @@ - clk_u0_sft7110_noc_bus_clk_cpu_axi - clk_u0_sft7110_noc_bus_clk_cpu_axi - 0x98 + clk_temp_sensor + Clock Temperature Sensor + 0x208 32 @@ -14273,12 +17661,18 @@ [31:31] read-write + + clk_divcfg + Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24 + [23:0] + read-write + - clk_u0_sft7110_noc_bus_clk_axicfg0_axi - clk_u0_sft7110_noc_bus_clk_axicfg0_axi - 0x9c + clk_u0_spi_apb + U0 Clock SPI APB + 0x20c 32 @@ -14290,65 +17684,65 @@ - clk_osc_div2 - clk_osc_div2 - 0xa0 + clk_u1_spi_apb + U1 Clock SPI APB + 0x210 32 - clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 - [23:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_pll1_div4 - clk_pll1_div4 - 0xa4 + clk_u2_spi_apb + U2 Clock SPI APB + 0x214 32 - clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 - [23:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_pll1_div8 - clk_pll1_div8 - 0xa8 + clk_u3_spi_apb + U3 Clock SPI APB + 0x218 32 - clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 - [23:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_ddr_bus - clk_ddr_bus - 0xac + clk_u4_spi_apb + U4 Clock SPI APB + 0x21c 32 - clk_mux_sel - Clock multiplexing selector: clk_osc_div2, clk_pll1_div4, clk_pll1_div8 - [29:24] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_u0_ddr_sft7110_clk_axi - clk_u0_ddr_sfft7110_clk_axi - 0xb0 + clk_u5_spi_apb + U5 Clock SPI APB + 0x220 32 @@ -14360,23 +17754,23 @@ - clk_gpu_core - clk_gpu_core - 0xb4 + clk_u6_spi_apb + U6 Clock SPI APB + 0x224 32 - clk_divcfg - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3 - [23:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_u0_img_gpu_core_clk - clk_u0_img_gpu_core_clk - 0xb8 + clk_u0_i2c_apb + U0 Clock I2C APB + 0x228 32 @@ -14388,9 +17782,9 @@ - clk_u0_img_gpu_sys_clk - clk_u0_img_gpu_sys_clk - 0xbc + clk_u1_i2c_apb + U1 Clock I2C APB + 0x22c 32 @@ -14402,9 +17796,9 @@ - clk_u0_img_gpu_clk_apb - clk_u0_img_gpu_clk_apb - 0xc0 + clk_u2_i2c_apb + U2 Clock I2C APB + 0x230 32 @@ -14416,9 +17810,9 @@ - clk_u0_gpu_rtc_toggle - clk_u0_gpu_rtc_toggle - 0xc4 + clk_u3_i2c_apb + U3 Clock I2C APB + 0x234 32 @@ -14427,18 +17821,12 @@ [31:31] read-write - - clk_divcfg - Clock divider coefficient: Max=12, Default=12, Min=12, Typical=12 - [23:0] - read-write - - clk_u0_sft7110_noc_bus_clk_gpu_axi - clk_u0_sft7110_noc_bus_clk_gpu_axi - 0xc8 + clk_u4_i2c_apb + U4 Clock I2C APB + 0x238 32 @@ -14450,9 +17838,9 @@ - clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x - clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x - 0xcc + clk_u5_i2c_apb + U5 Clock I2C APB + 0x23c 32 @@ -14464,9 +17852,9 @@ - clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi - clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi - 0xd0 + clk_u6_i2c_apb + U6 Clock I2C APB + 0x240 32 @@ -14478,9 +17866,9 @@ - clk_u0_sft7110_noc_bux_clk_isp_axi - clk_u0_sft7110_noc_bux_clk_isp_axi - 0xd4 + clk_u0_uart_apb + U0 Clock UART APB + 0x244 32 @@ -14492,37 +17880,37 @@ - clk_hifi4_core - clk_hifi4_core - 0xd8 + clk_u0_uart_core + U0 Clock UART Core + 0x248 32 - clk_divcfg - Clock divider coefficient: Max=15, Default=3, Min=3, Typical=3 - [23:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_hifi4_axi - clk_hifi4_axi - 0xdc + clk_u1_uart_apb + U1 Clock UART APB + 0x24c 32 - clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 - [23:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_u0_axi_cfg1_dec_clk_main - clk_u0_axi_cfg1_dec_clk_main - 0xe0 + clk_u1_uart_core + U1 Clock UART Core + 0x250 32 @@ -14534,9 +17922,9 @@ - clk_u0_axi_cfg1_dec_clk_ahb - clk_u0_axi_cfg1_dec_clk_ahb - 0xe4 + clk_u2_uart_apb + U2 Clock UART APB + 0x254 32 @@ -14548,9 +17936,9 @@ - clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src - clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src - 0xe8 + clk_u2_uart_core + U2 Clock UART Core + 0x258 32 @@ -14562,23 +17950,23 @@ - clk_vout_axi_divcfg - Clock Video Output AXI DIVCFG - 0xec + clk_u3_uart_apb + U3 Clock UART APB + 0x25c 32 - clk_divcfg - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2 - [23:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - clk_noc_display_axi - Clock NOC Display AXI - 0xf0 + clk_u3_uart_core + U3 Clock UART Core + 0x260 32 @@ -14587,12 +17975,18 @@ [31:31] read-write + + clk_divcfg + Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560 + [23:0] + read-write + - clk_vout_ahb - Clock Video Output AHB - 0xf4 + clk_u4_uart_apb + U4 Clock UART APB + 0x264 32 @@ -14604,9 +17998,9 @@ - clk_vout_axi_icg - Clock Video Output AXI ICG - 0xf8 + clk_u4_uart_core + U4 Clock UART Core + 0x268 32 @@ -14615,12 +18009,18 @@ [31:31] read-write + + clk_divcfg + Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560 + [23:0] + read-write + - clk_vout_hdmi_tx0_mclk - Clock Video Output HDMI TX0 MCLK - 0xfc + clk_u5_uart_apb + U5 Clock UART APB + 0x26c 32 @@ -14632,37 +18032,29 @@ - clk_vout_mipi_phy - Clock Video Output MIPI PHY Reference - 0x100 + clk_u5_uart_core + U5 Clock UART Core + 0x270 32 - clk_divcfg - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 - [23:0] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - - - - clk_jpeg_codec_axi - Clock JPEG Codec AXI - 0x104 - 32 - clk_divcfg - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6 + Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560 [23:0] read-write - clk_codaj12_axi - CODAJ12 Clock AXI - 0x108 + clk_pwmdac_apb + Clock PWMDAC APB + 0x274 32 @@ -14674,9 +18066,9 @@ - clk_codaj12_core - CODAJ12 Clock Core - 0x10c + clk_pwmdac_core + Clock PWMDAC Core + 0x278 32 @@ -14687,16 +18079,16 @@ clk_divcfg - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6 + Clock divider coefficient: Max=256, Default=12, Min=12, Typical=12 [23:0] read-write - clk_codaj12_apb - CODAJ12 Clock APB - 0x110 + clk_spdif_apb + Clock SPDIF APB + 0x27c 32 @@ -14708,23 +18100,9 @@ - clk_vdec_axi - Clock Video Decoder AXI - 0x114 - 32 - - - clk_divcfg - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3 - [23:0] - read-write - - - - - clk_wave511_axi - Clock WAVE511 AXI - 0x118 + clk_spdif_core + Clock SPDIF Core + 0x280 32 @@ -14736,9 +18114,9 @@ - clk_wave511_bpu - Clock WAVE511 BPU - 0x11c + clk_u0_i2s_tx_apb + U0 Clock I2S TX APB + 0x284 32 @@ -14747,18 +18125,12 @@ [31:31] read-write - - clk_divcfg - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3 - [23:0] - read-write - - clk_wave511_vce - Clock WAVE511 VCE - 0x120 + clk_u0_i2stx_4ch0_bclk_mst + U0 Clock I2S TX 0 BCLK MST + 0x288 32 @@ -14769,100 +18141,92 @@ clk_divcfg - Clock divider coefficient: Max=7, Default=2, Min=3, Typical=2 + Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4 [23:0] read-write - clk_wave511_apb - Clock WAVE511 APB - 0x124 + clk_u0_i2stx_4ch0_bclk_mst_inv + U0 Clock I2S TX 0 BCLK MST Inverter + 0x28c 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_polarity + 1: Clock inverter, 0: Clock buffer + [30:30] read-write - clk_wave511_jpg_arb - Clock WAVE511 JPG ARB - 0x128 + clk_i2stx0_lrck_mst + Clock I2S TX 0 LRCK MST + 0x290 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_mux_sel + Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst + [29:24] read-write - - - - clk_wave511_jpg_main - Clock WAVE511 JPG Main - 0x12c - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_divcfg + Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64 + [23:0] read-write - clk_noc_vdec_axi - Clock NOC Video Decoder AXI - 0x130 + clk_u0_i2stx_bclk + U0 Clock I2S TX BCLK + 0x294 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_mux_sel + Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst, clk_i2stx_bclk_ext + [29:24] read-write - clk_venc_axi - Clock Video Encoder AXI - 0x134 + clk_u0_i2stx_bclk_neg + U0 Clock I2S TX BCLK Negative + 0x298 32 - clk_divcfg - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5 - [23:0] + clk_polarity + 1: Clock inverter, 0: Clock buffer + [30:30] read-write - clk_wave420l_axi - Clock WAVE420L AXI - 0x138 + clk_u0_i2stx_lrck + U0 Clock I2S TX LRCK + 0x29c 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_mux_sel + Clock multiplexing selector: clk_i2stx_4ch0_lrck_mst, clk_i2stx_lrck_ext + [29:24] read-write - clk_wave420l_bpu - Clock WAVE420L BPU - 0x13c + clk_u1_i2s_tx_apb + U1 Clock I2S TX APB + 0x2a0 32 @@ -14871,18 +18235,12 @@ [31:31] read-write - - clk_divcfg - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5 - [23:0] - read-write - - clk_wave420l_vce - Clock WAVE420L VCE - 0x140 + clk_u1_i2stx_4ch1_bclk_mst + U1 Clock I2S TX 1 BCLK MST + 0x2a4 32 @@ -14893,86 +18251,92 @@ clk_divcfg - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5 + Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4 [23:0] read-write - clk_wave420l_apb - Clock WAVE420L APB - 0x144 + clk_u1_i2stx_4ch1_bclk_mst_inv + U1 Clock I2S TX 1 BCLK MST Inverter + 0x2a8 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_polarity + 1: Clock inverter, 0: Clock buffer + [30:30] read-write - clk_noc_venc_axi - Clock NOC Video Encoder AXI - 0x148 + clk_i2stx1_lrck_mst + Clock I2S TX 1 LRCK MST + 0x2ac 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_mux_sel + Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst + [29:24] + read-write + + + clk_divcfg + Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64 + [23:0] read-write - clk_axi_cfg0_dec_main_div - Clock AXI Config 0 DEC Main Divider - 0x14c + clk_u1_i2stx_bclk + U1 Clock I2S TX BCLK + 0x2b0 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_mux_sel + Clock multiplexing selector: clk_i2stx_4ch1_bclk_mst, clk_i2stx_bclk_ext + [29:24] read-write - clk_axi_cfg0_dec_main - Clock AXI Config 0 DEC Main - 0x150 + clk_u1_i2stx_bclk_neg + U1 Clock I2S TX BCLK Negative + 0x2b4 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_polarity + 1: Clock inverter, 0: Clock buffer + [30:30] read-write - clk_axi_cfg0_dec_hifi4 - Clock AXI Config 0 DEC HIFI4 - 0x154 + clk_u1_i2stx_lrck + U1 Clock I2S TX LRCK + 0x2b8 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_mux_sel + Clock multiplexing selector: clk_i2stx_4ch1_lrck_mst, clk_i2stx_lrck_ext + [29:24] read-write - clk_aximem_128b_axi - Clock AXIMEM 128B AXI - 0x158 + clk_i2s_apb + Clock I2S APB + 0x2bc 32 @@ -14984,9 +18348,9 @@ - clk_qspi_ahb - Clock QSPI AHB - 0x15c + clk_i2s_bclk_mst + Clock I2S BCLK MST + 0x2c0 32 @@ -14995,88 +18359,94 @@ [31:31] read-write + + clk_divcfg + Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4 + [23:0] + read-write + - clk_qspi_apb - Clock QSPI APB - 0x160 + clk_i2s_bclk_mst_inv + Clock I2S BCLK MST Inverter + 0x2c4 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_polarity + 1: Clock inverter, 0: Clock buffer + [30:30] read-write - clk_qspi_ref_src - Clock QSPI Reference Source - 0x164 + clk_i2s_lrck_mst + Clock I2S LRCK MST + 0x2c8 32 + + clk_mux_sel + Clock multiplexing selector: clk_i2srx_3ch_bclk_mst_inv, clk_i2srx_3ch_bclk_mst + [29:24] + read-write + clk_divcfg - Clock divider coefficient: Max=16, Default=10, Min=10, Typical=10 + Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64 [23:0] read-write - clk_qspi_ref - Clock QSPI Reference - 0x168 + clk_i2s_bclk + Clock I2S BCLK + 0x2cc 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] - read-write - clk_mux_sel - Clock multiplexing selector: clk_osc, clk_qspi_ref_src + Clock multiplexing selector: clk_i2srx_3ch_bclk_mst, clk_i2srx_3ch_bclk_ext [29:24] read-write - clk_u0_sd_ahb - U0 SD Clock AHB - 0x16c + clk_i2s_bclk_neg + Clock I2S BCLK Negative + 0x2d0 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_polarity + 1: Clock inverter, 0: Clock buffer + [30:30] read-write - clk_u1_sd_ahb - U1 SD Clock AHB - 0x170 + clk_i2s_lrck + Clock I2S LRCK + 0x2d4 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + clk_mux_sel + Clock multiplexing selector: clk_i2srx_3ch_lrck_mst, clk_i2srx_3ch_lrck_ext + [29:24] read-write - clk_u0_sd_card - U0 SD Card Clock - 0x174 + clk_pdm_dmic + Clock PDM DMIC + 0x2d8 32 @@ -15087,16 +18457,16 @@ clk_divcfg - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2 + Clock divider coefficient: Max=64, Default=8, Min=8, Typical=8 [23:0] read-write - clk_u1_sd_card - U1 SD Card Clock - 0x178 + clk_pdm_apb + Clock PDM APB + 0x2dc 32 @@ -15105,32 +18475,12 @@ [31:31] read-write - - clk_divcfg - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2 - [23:0] - read-write - - - - - clk_usb_125m - Clock USB 125M - 0x17c - 32 - - - clk_divcfg - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10 - [23:0] - read-write - - clk_noc_stg_axi - Clock NOC STG AXI - 0x180 + clk_tdm_ahb + Clock TDM AHB + 0x2e0 32 @@ -15142,9 +18492,9 @@ - clk_gmac5_axi64_ahb - Clock GMAC 5 AXI 64 AHB - 0x184 + clk_tdm_apb + Clock TDM APB + 0x2e4 32 @@ -15156,9 +18506,9 @@ - clk_gmac5_axi64_axi - Clock GMAC 5 AXI 64 AXI - 0x188 + clk_tdm_internal + Clock TDM Internal + 0x2e8 32 @@ -15167,1418 +18517,848 @@ [31:31] read-write + + clk_divcfg + Clock divider coefficient: Max=64, Default=1, Min=1, Typical=1 + [23:0] + read-write + - clk_gmac_src - Clock GMAC Source - 0x18c + clk_tdm + Clock TDM + 0x2ec 32 - clk_divcfg - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2 - [23:0] + clk_mux_sel + Clock multiplexing selector: clk_tdm_internal, clk_tdm_ext + [29:24] read-write - clk_gmac1_gtx - Clock GMAC 1 GTX - 0x190 + clk_tdm_neg + Clock TDM Negative + 0x2f0 32 - clk_divcfg - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10 - [23:0] + clk_polarity + 1: Clock inverter, 0: Clock buffer + [30:30] read-write - clk_gmac1_rmii_rtx - Clock GMAC 1 RMII RTX - 0x194 + clk_jtag_cert_trng + Clock JTAG Certification TRNG + 0x2f4 32 clk_divcfg - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2 + Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 [23:0] read-write - clk_gmac5_axi64_ptp - Clock GMAC 5 AXI 64 PTP - 0x198 + soft_rst0_addr_sel + Software RESET 0 Address Selector + 0x2f8 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_jtag2apb_presetn + 1: Assert reset, 0: De-assert reset + [0:0] read-write - clk_divcfg - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=10 - [23:0] + rstn_u0_sys_syscon_presetn + 1: Assert reset, 0: De-assert reset + [1:1] read-write - - - - clk_gmac5_axi64_rx - Clock GMAC 5 AXI 64 RX - 0x19c - 32 - - dly_chain_sel - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. - [23:0] + rstn_u0_sys_iomux_presetn + 1: Assert reset, 0: De-assert reset + [2:2] + read-write + + + rst_u0_u7mc_sft7110_rst_bus + 1: Assert reset, 0: De-assert reset + [3:3] + read-write + + + rst_u0_u7mc_sft7110_debug_reset + 1: Assert reset, 0: De-assert reset + [4:4] + read-write + + + rst_u0_u7mc_sft7110_rst_core0 + 1: Assert reset, 0: De-assert reset + [5:5] + read-write + + + rst_u0_u7mc_sft7110_rst_core1 + 1: Assert reset, 0: De-assert reset + [6:6] + read-write + + + rst_u0_u7mc_sft7110_rst_core2 + 1: Assert reset, 0: De-assert reset + [7:7] + read-write + + + rst_u0_u7mc_sft7110_rst_core3 + 1: Assert reset, 0: De-assert reset + [8:8] + read-write + + + rst_u0_u7mc_sft7110_rst_core4 + 1: Assert reset, 0: De-assert reset + [9:9] + read-write + + + rst_u0_u7mc_sft7110_rst_core0_st + 1: Assert reset, 0: De-assert reset + [10:10] + read-write + + + rst_u0_u7mc_sft7110_rst_core1_st + 1: Assert reset, 0: De-assert reset + [11:11] + read-write + + + rst_u0_u7mc_sft7110_rst_core2_st + 1: Assert reset, 0: De-assert reset + [12:12] + read-write + + + rst_u0_u7mc_sft7110_rst_core3_st + 1: Assert reset, 0: De-assert reset + [13:13] + read-write + + + rst_u0_u7mc_sft7110_rst_core4_st + 1: Assert reset, 0: De-assert reset + [14:14] + read-write + + + rst_u0_u7mc_sft7110_trace_rst0 + 1: Assert reset, 0: De-assert reset + [15:15] + read-write + + + rst_u0_u7mc_sft7110_trace_rst1 + 1: Assert reset, 0: De-assert reset + [16:16] + read-write + + + rst_u0_u7mc_sft7110_trace_rst2 + 1: Assert reset, 0: De-assert reset + [17:17] + read-write + + + rst_u0_u7mc_sft7110_trace_rst3 + 1: Assert reset, 0: De-assert reset + [18:18] read-write - - - - clk_gmac5_axi64_rxi - Clock GMAC 5 AXI 64 RX Inverter - 0x1a0 - 32 - - clk_polarity - 1: Clock inverter, 0: Clock buffer - [30:30] + rst_u0_u7mc_sft7110_trace_rst4 + 1: Assert reset, 0: De-assert reset + [19:19] read-write - - - - clk_gmac5_axi64_tx - Clock GMAC 5 AXI 64 TX - 0x1a4 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rst_u0_u7mc_sft7110_trace_com_rst + 1: Assert reset, 0: De-assert reset + [20:20] read-write - clk_mux_sel - Clock multiplexing selector: clk_gmac1_gtxclk, clk_gmac1_rmii_rtx - [29:24] + rst_u0_img_gpu_rstn_apb + 1: Assert reset, 0: De-assert reset + [21:21] read-write - - - - clk_gmac5_axi64_txi - Clock GMAC 5 AXI 64 TX Inverter - 0x1a8 - 32 - - clk_polarity - 1: Clock inverter, 0: Clock buffer - [30:30] + rst_u0_img_gpu_rstn_doma + 1: Assert reset, 0: De-assert reset + [22:22] read-write - - - - clk_gmac1_gtxclk - Clock GMAC 1 GTXC - 0x1ac - 32 - - dly_chain_sel - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. - [23:0] + rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n + 1: Assert reset, 0: De-assert reset + [23:23] read-write - - - - clk_gmac0_gtx - Clock GMAC 0 GTX - 0x1b0 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n + 1: Assert reset, 0: De-assert reset + [24:24] read-write - clk_divcfg - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10 - [23:0] + rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n + 1: Assert reset, 0: De-assert reset + [25:25] read-write - - - - clk_gmac0_ptp - Clock GMAC 0 PTP - 0x1b4 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n + 1: Assert reset, 0: De-assert reset + [26:26] read-write - clk_divcfg - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25 - [23:0] + rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n + 1: Assert reset, 0: De-assert reset + [27:27] read-write - - - - clk_gmac_phy - Clock GMAC PHY - 0x1b8 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n + 1: Assert reset, 0: De-assert reset + [28:28] read-write - clk_divcfg - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25 - [23:0] + rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n + 1: Assert reset, 0: De-assert reset + [29:29] read-write - - - - clk_gmac0_gtxclk - Clock GMAC 0 GTXC - 0x1bc - 32 - - dly_chain_sel - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. - [23:0] + rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n + 1: Assert reset, 0: De-assert reset + [30:30] read-write - - - - clk_sys_iomux_pclk - Clock SYS IOMUX PCLK - 0x1c0 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable + rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n + 1: Assert reset, 0: De-assert reset [31:31] read-write - clk_mbox_apb - Clock Mailbox APB - 0x1c4 + soft_rst1_addr_sel + Software RESET 1 Address Selector + 0x2fc 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_sft7100_noc_bus_reset_venc_axi_n + 1: Assert reset, 0: De-assert reset + [0:0] read-write - - - - clk_internal_ctrl_apb - Clock Internal Controller APB - 0x1c8 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_axi_cfg1_dec_rstn_ahb + 1: Assert reset, 0: De-assert reset + [1:1] read-write - - - - clk_u0_can_ctrl_apb - U0 Clock CAN Controller APB - 0x1cc - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_axi_cfg1_dec_rstn_main + 1: Assert reset, 0: De-assert reset + [2:2] read-write - - - - clk_u0_can_ctrl_tim - U0 Clock CAN Controller Timer - 0x1d0 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_axi_cfg0_dec_rstn_main + 1: Assert reset, 0: De-assert reset + [3:3] read-write - clk_divcfg - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24 - [23:0] + rstn_u0_axi_cfg0_dec_rstn_main_div + 1: Assert reset, 0: De-assert reset + [4:4] read-write - - - - clk_u0_can_ctrl_can - U0 Clock CAN Controller CAN - 0x1d4 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_axi_cfg0_dec_rstn_hifi4 + 1: Assert reset, 0: De-assert reset + [5:5] read-write - clk_divcfg - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8 - [23:0] + rstn_u0_ddr_sft7110_rstn_axi + 1: Assert reset, 0: De-assert reset + [6:6] read-write - - - - clk_u1_can_ctrl_apb - U1 Clock CAN Controller APB - 0x1d8 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_ddr_sft7110_rstn_osc + 1: Assert reset, 0: De-assert reset + [7:7] read-write - - - - clk_u1_can_ctrl_tim - U1 Clock CAN Controller Timer - 0x1dc - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_ddr_sft7110_rstn_apb + 1: Assert reset, 0: De-assert reset + [8:8] read-write - clk_divcfg - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24 - [23:0] + rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n + 1: Assert reset, 0: De-assert reset + [9:9] read-write - - - - clk_u1_can_ctrl_can - U1 Clock CAN Controller CAN - 0x1e0 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi + 1: Assert reset, 0: De-assert reset + [10:10] read-write - clk_divcfg - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8 - [23:0] + rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src + 1: Assert reset, 0: De-assert reset + [11:11] read-write - - - - clk_pwm_apb - Clock PWM APB - 0x1e4 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_codaj12_rstn_axi + 1: Assert reset, 0: De-assert reset + [12:12] read-write - - - - clk_wdt_apb - Clock WDT APB - 0x1e8 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_codaj12_rstn_core + 1: Assert reset, 0: De-assert reset + [13:13] read-write - - - - clk_wdt - Clock WDT - 0x1ec - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_codaj12_rstn_apb + 1: Assert reset, 0: De-assert reset + [14:14] read-write - - - - clk_tim_apb - Clock Timer APB - 0x1f0 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_wave511_rstn_axi + 1: Assert reset, 0: De-assert reset + [15:15] read-write - - - - clk_tim0 - Clock Timer 0 - 0x1f4 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_wave511_rstn_bpu + 1: Assert reset, 0: De-assert reset + [16:16] read-write - - - - clk_tim1 - Clock Timer 1 - 0x1f8 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_wave511_rstn_vce + 1: Assert reset, 0: De-assert reset + [17:17] read-write - - - - clk_tim2 - Clock Timer 2 - 0x1fc - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_wave511_rstn_apb + 1: Assert reset, 0: De-assert reset + [18:18] read-write - - - - clk_tim3 - Clock Timer 3 - 0x200 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_vdec_jpg_arb_jpgresetn + 1: Assert reset, 0: De-assert reset + [19:19] read-write - - - - clk_temp_sensor_apb - Clock Temperature Sensor APB - 0x204 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_vdec_jpg_arb_mainresetn + 1: Assert reset, 0: De-assert reset + [20:20] read-write - - - - clk_temp_sensor - Clock Temperature Sensor - 0x208 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_aximem_128b_rstn_axi + 1: Assert reset, 0: De-assert reset + [21:21] read-write - clk_divcfg - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24 - [23:0] + rstn_u0_wave420l_rstn_axi + 1: Assert reset, 0: De-assert reset + [22:22] read-write - - - - clk_u0_spi_apb - U0 Clock SPI APB - 0x20c - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_wave420l_rstn_bpu + 1: Assert reset, 0: De-assert reset + [23:23] read-write - - - - clk_u1_spi_apb - U1 Clock SPI APB - 0x210 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_wave420l_rstn_vce + 1: Assert reset, 0: De-assert reset + [24:24] read-write - - - - clk_u2_spi_apb - U2 Clock SPI APB - 0x214 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_wave420l_rstn_apb + 1: Assert reset, 0: De-assert reset + [25:25] read-write - - - - clk_u3_spi_apb - U3 Clock SPI APB - 0x218 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u1_aximem_128b_rstn_axi + 1: Assert reset, 0: De-assert reset + [26:26] read-write - - - - clk_u4_spi_apb - U4 Clock SPI APB - 0x21c - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u2_aximem_128b_rstn_axi + 1: Assert reset, 0: De-assert reset + [27:27] read-write - - - - clk_u5_spi_apb - U5 Clock SPI APB - 0x220 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_intmem_rom_sram_rstn_rom + 1: Assert reset, 0: De-assert reset + [28:28] read-write - - - - clk_u6_spi_apb - U6 Clock SPI APB - 0x224 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_cdns_qspi_rstn_ahb + 1: Assert reset, 0: De-assert reset + [29:29] read-write - - - - clk_u0_i2c_apb - U0 Clock I2C APB - 0x228 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_cdns_qspi_rstn_apb + 1: Assert reset, 0: De-assert reset + [30:30] read-write - - - - clk_u1_i2c_apb - U1 Clock I2C APB - 0x22c - 32 - - clk_icg - 1: Clock enable, 0: Clock disable + rstn_u0_cdns_qspi_rstn_ref + 1: Assert reset, 0: De-assert reset [31:31] read-write - clk_u2_i2c_apb - U2 Clock I2C APB - 0x230 + soft_rst2_addr_sel + Software RESET 2 Address Selector + 0x300 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_sdio_rstn_ahb + 1: Assert reset, 0: De-assert reset + [0:0] read-write - - - - clk_u3_i2c_apb - U3 Clock I2C APB - 0x234 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u1_sdi_rstn_ahb + 1: Assert reset, 0: De-assert reset + [1:1] read-write - - - - clk_u4_i2c_apb - U4 Clock I2C APB - 0x238 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u1_gmac5_axi64_aresetn_i + 1: Assert reset, 0: De-assert reset + [2:2] read-write - - - - clk_u5_i2c_apb - U5 Clock I2C APB - 0x23c - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u1_gmac5_axi64_hresetn_n + 1: Assert reset, 0: De-assert reset + [3:3] read-write - - - - clk_u6_i2c_apb - U6 Clock I2C APB - 0x240 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_mailbox_presetn + 1: Assert reset, 0: De-assert reset + [4:4] read-write - - - - clk_u0_uart_apb - U0 Clock UART APB - 0x244 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_ssp_spi_rstn_apb + 1: Assert reset, 0: De-assert reset + [5:5] read-write - - - - clk_u0_uart_core - U0 Clock UART Core - 0x248 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u1_ssp_spi_rstn_apb + 1: Assert reset, 0: De-assert reset + [6:6] read-write - - - - clk_u1_uart_apb - U1 Clock UART APB - 0x24c - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u2_ssp_spi_rstn_apb + 1: Assert reset, 0: De-assert reset + [7:7] read-write - - - - clk_u1_uart_core - U1 Clock UART Core - 0x250 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u3_ssp_spi_rstn_apb + 1: Assert reset, 0: De-assert reset + [8:8] read-write - - - - clk_u2_uart_apb - U2 Clock UART APB - 0x254 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u4_ssp_spi_rstn_apb + 1: Assert reset, 0: De-assert reset + [9:9] read-write - - - - clk_u2_uart_core - U2 Clock UART Core - 0x258 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u5_ssp_spi_rstn_apb + 1: Assert reset, 0: De-assert reset + [10:10] read-write - - - - clk_u3_uart_apb - U3 Clock UART APB - 0x25c - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u6_ssp_spi_rstn_apb + 1: Assert reset, 0: De-assert reset + [11:11] read-write - - - - clk_u3_uart_core - U3 Clock UART Core - 0x260 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_i2c_rstn_apb + 1: Assert reset, 0: De-assert reset + [12:12] read-write - clk_divcfg - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560 - [23:0] + rstn_u1_i2c_rstn_apb + 1: Assert reset, 0: De-assert reset + [13:13] read-write - - - - clk_u4_uart_apb - U4 Clock UART APB - 0x264 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u2_i2c_rstn_apb + 1: Assert reset, 0: De-assert reset + [14:14] read-write - - - - clk_u4_uart_core - U4 Clock UART Core - 0x268 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u3_i2c_rstn_apb + 1: Assert reset, 0: De-assert reset + [15:15] read-write - clk_divcfg - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560 - [23:0] + rstn_u4_i2c_rstn_apb + 1: Assert reset, 0: De-assert reset + [16:16] read-write - - - - clk_u5_uart_apb - U5 Clock UART APB - 0x26c - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u5_i2c_rstn_apb + 1: Assert reset, 0: De-assert reset + [17:17] read-write - - - - clk_u5_uart_core - U5 Clock UART Core - 0x270 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u6_i2c_rstn_apb + 1: Assert reset, 0: De-assert reset + [18:18] read-write - clk_divcfg - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560 - [23:0] + rstn_u0_uart_rstn_apb + 1: Assert reset, 0: De-assert reset + [19:19] read-write - - - - clk_pwmdac_apb - Clock PWMDAC APB - 0x274 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_uart_rstn_core + 1: Assert reset, 0: De-assert reset + [20:20] read-write - - - - clk_pwmdac_core - Clock PWMDAC Core - 0x278 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u1_uart_rstn_apb + 1: Assert reset, 0: De-assert reset + [21:21] read-write - clk_divcfg - Clock divider coefficient: Max=256, Default=12, Min=12, Typical=12 - [23:0] + rstn_u1_uart_rstn_core + 1: Assert reset, 0: De-assert reset + [22:22] read-write - - - - clk_spdif_apb - Clock SPDIF APB - 0x27c - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u2_uart_rstn_apb + 1: Assert reset, 0: De-assert reset + [23:23] read-write - - - - clk_spdif_core - Clock SPDIF Core - 0x280 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u2_uart_rstn_core + 1: Assert reset, 0: De-assert reset + [24:24] read-write - - - - clk_u0_i2s_tx_apb - U0 Clock I2S TX APB - 0x284 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u3_uart_rstn_apb + 1: Assert reset, 0: De-assert reset + [25:25] read-write - - - - clk_u0_i2stx_4ch0_bclk_mst - U0 Clock I2S TX 0 BCLK MST - 0x288 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u3_uart_rstn_core + 1: Assert reset, 0: De-assert reset + [26:26] read-write - clk_divcfg - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4 - [23:0] + rstn_u4_uart_rstn_apb + 1: Assert reset, 0: De-assert reset + [27:27] read-write - - - - clk_u0_i2stx_4ch0_bclk_mst_inv - U0 Clock I2S TX 0 BCLK MST Inverter - 0x28c - 32 - - clk_polarity - 1: Clock inverter, 0: Clock buffer - [30:30] + rstn_u4_uart_rstn_core + 1: Assert reset, 0: De-assert reset + [28:28] read-write - - - - clk_i2stx0_lrck_mst - Clock I2S TX 0 LRCK MST - 0x290 - 32 - - clk_mux_sel - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst - [29:24] + rstn_u5_uart_rstn_apb + 1: Assert reset, 0: De-assert reset + [29:29] read-write - clk_divcfg - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64 - [23:0] + rstn_u6_uart_rstn_core + 1: Assert reset, 0: De-assert reset + [30:30] read-write - - - - clk_u0_i2stx_bclk - U0 Clock I2S TX BCLK - 0x294 - 32 - - clk_mux_sel - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst, clk_i2stx_bclk_ext - [29:24] + rstn_u0_cdns_spdif_rstn_apb + 1: Assert reset, 0: De-assert reset + [31:31] read-write - clk_u0_i2stx_bclk_neg - U0 Clock I2S TX BCLK Negative - 0x298 + soft_rst3_addr_sel + Software RESET 3 Address Selector + 0x304 32 - clk_polarity - 1: Clock inverter, 0: Clock buffer - [30:30] + rstn_u0_pwmdac_rstn_apb + 1: Assert reset, 0: De-assert reset + [0:0] read-write - - - - clk_u0_i2stx_lrck - U0 Clock I2S TX LRCK - 0x29c - 32 - - clk_mux_sel - Clock multiplexing selector: clk_i2stx_4ch0_lrck_mst, clk_i2stx_lrck_ext - [29:24] + rstn_u0_pdm_4mic_rstn_dmic + 1: Assert reset, 0: De-assert reset + [1:1] read-write - - - - clk_u1_i2s_tx_apb - U1 Clock I2S TX APB - 0x2a0 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_pdm_4mic_rstn_apb + 1: Assert reset, 0: De-assert reset + [2:2] read-write - - - - clk_u1_i2stx_4ch1_bclk_mst - U1 Clock I2S TX 1 BCLK MST - 0x2a4 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_i2srx_3ch_rstn_apb + 1: Assert reset, 0: De-assert reset + [3:3] read-write - clk_divcfg - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4 - [23:0] + rstn_u0_i2srx_3ch_rstn_bclk + 1: Assert reset, 0: De-assert reset + [4:4] read-write - - - - clk_u1_i2stx_4ch1_bclk_mst_inv - U1 Clock I2S TX 1 BCLK MST Inverter - 0x2a8 - 32 - - - clk_polarity - 1: Clock inverter, 0: Clock buffer - [30:30] + + rstn_u0_i2stx_4ch_rstn_apb + 1: Assert reset, 0: De-assert reset + [5:5] read-write - - - - clk_i2stx1_lrck_mst - Clock I2S TX 1 LRCK MST - 0x2ac - 32 - - clk_mux_sel - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst - [29:24] + rstn_u0_i2stx_4ch_rstn_bclk + 1: Assert reset, 0: De-assert reset + [6:6] read-write - clk_divcfg - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64 - [23:0] + rstn_u1_i2stx_4ch_rstn_apb + 1: Assert reset, 0: De-assert reset + [7:7] read-write - - - - clk_u1_i2stx_bclk - U1 Clock I2S TX BCLK - 0x2b0 - 32 - - clk_mux_sel - Clock multiplexing selector: clk_i2stx_4ch1_bclk_mst, clk_i2stx_bclk_ext - [29:24] + rstn_u1_i2stx_4ch_rstn_bclk + 1: Assert reset, 0: De-assert reset + [8:8] read-write - - - - clk_u1_i2stx_bclk_neg - U1 Clock I2S TX BCLK Negative - 0x2b4 - 32 - - clk_polarity - 1: Clock inverter, 0: Clock buffer - [30:30] + rstn_u0_tdm16slot_rstn_ahb + 1: Assert reset, 0: De-assert reset + [9:9] read-write - - - - clk_u1_i2stx_lrck - U1 Clock I2S TX LRCK - 0x2b8 - 32 - - clk_mux_sel - Clock multiplexing selector: clk_i2stx_4ch1_lrck_mst, clk_i2stx_lrck_ext - [29:24] + rstn_u0_tdm16slot_rstn_tdm + 1: Assert reset, 0: De-assert reset + [10:10] read-write - - - - clk_i2s_apb - Clock I2S APB - 0x2bc - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_tdm16slot_rstn_apb + 1: Assert reset, 0: De-assert reset + [11:11] read-write - - - - clk_i2s_bclk_mst - Clock I2S BCLK MST - 0x2c0 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_pwm_8ch_rstn_apb + 1: Assert reset, 0: De-assert reset + [12:12] read-write - clk_divcfg - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4 - [23:0] + rstn_u0_dskit_wdt_rstn_apb + 1: Assert reset, 0: De-assert reset + [13:13] read-write - - - - clk_i2s_bclk_mst_inv - Clock I2S BCLK MST Inverter - 0x2c4 - 32 - - clk_polarity - 1: Clock inverter, 0: Clock buffer - [30:30] + rstn_u0_dskit_wdt_rstn_wdt + 1: Assert reset, 0: De-assert reset + [14:14] read-write - - - - clk_i2s_lrck_mst - Clock I2S LRCK MST - 0x2c8 - 32 - - clk_mux_sel - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst_inv, clk_i2srx_3ch_bclk_mst - [29:24] + rstn_u0_can_ctrl_rstn_apb + 1: Assert reset, 0: De-assert reset + [15:15] read-write - clk_divcfg - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64 - [23:0] + rstn_u0_can_ctrl_rstn_can + 1: Assert reset, 0: De-assert reset + [16:16] read-write - - - - clk_i2s_bclk - Clock I2S BCLK - 0x2cc - 32 - - clk_mux_sel - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst, clk_i2srx_3ch_bclk_ext - [29:24] + rstn_u0_can_ctrl_rstn_timer + 1: Assert reset, 0: De-assert reset + [17:17] read-write - - - - clk_i2s_bclk_neg - Clock I2S BCLK Negative - 0x2d0 - 32 - - clk_polarity - 1: Clock inverter, 0: Clock buffer - [30:30] + rstn_u1_can_ctrl_rstn_apb + 1: Assert reset, 0: De-assert reset + [18:18] read-write - - - - clk_i2s_lrck - Clock I2S LRCK - 0x2d4 - 32 - - clk_mux_sel - Clock multiplexing selector: clk_i2srx_3ch_lrck_mst, clk_i2srx_3ch_lrck_ext - [29:24] + rstn_u1_can_ctrl_rstn_can + 1: Assert reset, 0: De-assert reset + [19:19] read-write - - - - clk_pdm_dmic - Clock PDM DMIC - 0x2d8 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u1_can_ctrl_rstn_timer + 1: Assert reset, 0: De-assert reset + [20:20] read-write - clk_divcfg - Clock divider coefficient: Max=64, Default=8, Min=8, Typical=8 - [23:0] + rstn_u0_si5_timer_rstn_apb + 1: Assert reset, 0: De-assert reset + [21:21] read-write - - - - clk_pdm_apb - Clock PDM APB - 0x2dc - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_si5_timer_rstn_timer0 + 1: Assert reset, 0: De-assert reset + [22:22] read-write - - - - clk_tdm_ahb - Clock TDM AHB - 0x2e0 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_si5_timer_rstn_time10 + 1: Assert reset, 0: De-assert reset + [23:23] read-write - - - - clk_tdm_apb - Clock TDM APB - 0x2e4 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_si5_timer_rstn_timer2 + 1: Assert reset, 0: De-assert reset + [24:24] read-write - - - - clk_tdm_internal - Clock TDM Internal - 0x2e8 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + rstn_u0_si5_timer_rstn_timer3 + 1: Assert reset, 0: De-assert reset + [25:25] read-write - clk_divcfg - Clock divider coefficient: Max=64, Default=1, Min=1, Typical=1 - [23:0] + rstn_u0_int_ctrl_rstn_apb + 1: Assert reset, 0: De-assert reset + [26:26] read-write - - - - clk_tdm - Clock TDM - 0x2ec - 32 - - clk_mux_sel - Clock multiplexing selector: clk_tdm_internal, clk_tdm_ext - [29:24] + rstn_u0_temp_sensor_rstn_apb + 1: Assert reset, 0: De-assert reset + [27:27] read-write - - - - clk_tdm_neg - Clock TDM Negative - 0x2f0 - 32 - - clk_polarity - 1: Clock inverter, 0: Clock buffer - [30:30] + rstn_u0_temp_sensor_rstn_temp + 1: Assert reset, 0: De-assert reset + [28:28] read-write - - - - clk_jtag_cert_trng - Clock JTAG Certification TRNG - 0x2f4 - 32 - - clk_divcfg - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 - [23:0] + rstn_u0_jtag_certification_rst_n + 1: Assert reset, 0: De-assert reset + [29:29] read-write - soft_rst0_addr_sel - Software RESET 0 Address Selector - 0x2f8 + syscrg_rst0_status + SYSCRG RESET Status 0 + 0x308 32 @@ -16776,9 +19556,9 @@ - soft_rst1_addr_sel - Software RESET 1 Address Selector - 0x2fc + syscrg_rst1_status + SYSCRG RESET Status 1 + 0x30c 32 @@ -16976,9 +19756,9 @@ - soft_rst2_addr_sel - Software RESET 2 Address Selector - 0x300 + syscrg_rst2_status + SYSCRG RESET Status 2 + 0x310 32 @@ -17176,9 +19956,9 @@ - soft_rst3_addr_sel - Software RESET 3 Address Selector - 0x304 + syscrg_rst3_status + SYSCRG RESET Status 3 + 0x314 32 @@ -17248,4561 +20028,4423 @@ read-write - rstn_u0_tdm16slot_rstn_apb - 1: Assert reset, 0: De-assert reset - [11:11] - read-write - - - rstn_u0_pwm_8ch_rstn_apb - 1: Assert reset, 0: De-assert reset - [12:12] - read-write - - - rstn_u0_dskit_wdt_rstn_apb - 1: Assert reset, 0: De-assert reset - [13:13] - read-write - - - rstn_u0_dskit_wdt_rstn_wdt - 1: Assert reset, 0: De-assert reset - [14:14] - read-write - - - rstn_u0_can_ctrl_rstn_apb - 1: Assert reset, 0: De-assert reset - [15:15] - read-write - - - rstn_u0_can_ctrl_rstn_can - 1: Assert reset, 0: De-assert reset - [16:16] - read-write - - - rstn_u0_can_ctrl_rstn_timer - 1: Assert reset, 0: De-assert reset - [17:17] - read-write - - - rstn_u1_can_ctrl_rstn_apb - 1: Assert reset, 0: De-assert reset - [18:18] - read-write - - - rstn_u1_can_ctrl_rstn_can - 1: Assert reset, 0: De-assert reset - [19:19] - read-write - - - rstn_u1_can_ctrl_rstn_timer - 1: Assert reset, 0: De-assert reset - [20:20] - read-write - - - rstn_u0_si5_timer_rstn_apb - 1: Assert reset, 0: De-assert reset - [21:21] - read-write - - - rstn_u0_si5_timer_rstn_timer0 - 1: Assert reset, 0: De-assert reset - [22:22] - read-write - - - rstn_u0_si5_timer_rstn_time10 - 1: Assert reset, 0: De-assert reset - [23:23] - read-write - - - rstn_u0_si5_timer_rstn_timer2 - 1: Assert reset, 0: De-assert reset - [24:24] - read-write - - - rstn_u0_si5_timer_rstn_timer3 - 1: Assert reset, 0: De-assert reset - [25:25] - read-write - - - rstn_u0_int_ctrl_rstn_apb - 1: Assert reset, 0: De-assert reset - [26:26] - read-write - - - rstn_u0_temp_sensor_rstn_apb - 1: Assert reset, 0: De-assert reset - [27:27] - read-write - - - rstn_u0_temp_sensor_rstn_temp - 1: Assert reset, 0: De-assert reset - [28:28] - read-write - - - rstn_u0_jtag_certification_rst_n - 1: Assert reset, 0: De-assert reset - [29:29] - read-write - - - - - syscrg_rst0_status - SYSCRG RESET Status 0 - 0x308 - 32 - - - rstn_u0_jtag2apb_presetn - 1: Assert reset, 0: De-assert reset - [0:0] - read-write - - - rstn_u0_sys_syscon_presetn - 1: Assert reset, 0: De-assert reset - [1:1] - read-write - - - rstn_u0_sys_iomux_presetn - 1: Assert reset, 0: De-assert reset - [2:2] - read-write - - - rst_u0_u7mc_sft7110_rst_bus - 1: Assert reset, 0: De-assert reset - [3:3] - read-write - - - rst_u0_u7mc_sft7110_debug_reset - 1: Assert reset, 0: De-assert reset - [4:4] - read-write - - - rst_u0_u7mc_sft7110_rst_core0 - 1: Assert reset, 0: De-assert reset - [5:5] - read-write - - - rst_u0_u7mc_sft7110_rst_core1 - 1: Assert reset, 0: De-assert reset - [6:6] - read-write - - - rst_u0_u7mc_sft7110_rst_core2 - 1: Assert reset, 0: De-assert reset - [7:7] - read-write - - - rst_u0_u7mc_sft7110_rst_core3 - 1: Assert reset, 0: De-assert reset - [8:8] - read-write - - - rst_u0_u7mc_sft7110_rst_core4 - 1: Assert reset, 0: De-assert reset - [9:9] - read-write - - - rst_u0_u7mc_sft7110_rst_core0_st - 1: Assert reset, 0: De-assert reset - [10:10] - read-write - - - rst_u0_u7mc_sft7110_rst_core1_st + rstn_u0_tdm16slot_rstn_apb 1: Assert reset, 0: De-assert reset [11:11] read-write - rst_u0_u7mc_sft7110_rst_core2_st + rstn_u0_pwm_8ch_rstn_apb 1: Assert reset, 0: De-assert reset [12:12] read-write - rst_u0_u7mc_sft7110_rst_core3_st + rstn_u0_dskit_wdt_rstn_apb 1: Assert reset, 0: De-assert reset [13:13] read-write - rst_u0_u7mc_sft7110_rst_core4_st + rstn_u0_dskit_wdt_rstn_wdt 1: Assert reset, 0: De-assert reset [14:14] read-write - rst_u0_u7mc_sft7110_trace_rst0 + rstn_u0_can_ctrl_rstn_apb 1: Assert reset, 0: De-assert reset [15:15] read-write - rst_u0_u7mc_sft7110_trace_rst1 + rstn_u0_can_ctrl_rstn_can 1: Assert reset, 0: De-assert reset [16:16] read-write - rst_u0_u7mc_sft7110_trace_rst2 + rstn_u0_can_ctrl_rstn_timer 1: Assert reset, 0: De-assert reset [17:17] read-write - rst_u0_u7mc_sft7110_trace_rst3 + rstn_u1_can_ctrl_rstn_apb 1: Assert reset, 0: De-assert reset [18:18] read-write - rst_u0_u7mc_sft7110_trace_rst4 + rstn_u1_can_ctrl_rstn_can 1: Assert reset, 0: De-assert reset [19:19] read-write - rst_u0_u7mc_sft7110_trace_com_rst + rstn_u1_can_ctrl_rstn_timer 1: Assert reset, 0: De-assert reset [20:20] read-write - rst_u0_img_gpu_rstn_apb + rstn_u0_si5_timer_rstn_apb 1: Assert reset, 0: De-assert reset [21:21] read-write - rst_u0_img_gpu_rstn_doma + rstn_u0_si5_timer_rstn_timer0 1: Assert reset, 0: De-assert reset [22:22] read-write - rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n + rstn_u0_si5_timer_rstn_time10 1: Assert reset, 0: De-assert reset [23:23] read-write - rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n + rstn_u0_si5_timer_rstn_timer2 1: Assert reset, 0: De-assert reset [24:24] read-write - rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n + rstn_u0_si5_timer_rstn_timer3 1: Assert reset, 0: De-assert reset [25:25] read-write - rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n + rstn_u0_int_ctrl_rstn_apb 1: Assert reset, 0: De-assert reset [26:26] read-write - rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n + rstn_u0_temp_sensor_rstn_apb 1: Assert reset, 0: De-assert reset [27:27] read-write - rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n + rstn_u0_temp_sensor_rstn_temp 1: Assert reset, 0: De-assert reset [28:28] read-write - rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n + rstn_u0_jtag_certification_rst_n 1: Assert reset, 0: De-assert reset [29:29] read-write + + + + + + starfive_jh7110_sys_syscon_0 + From starfive,jh7110-sys-syscon, peripheral generator + 0x13030000 + + 0 + 0x1000 + registers + + + + sys_sysconsaif_syscfg0 + SYS SYSCONSAIF SYSCFG 0 + 0x0 + 32 + - rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n - 1: Assert reset, 0: De-assert reset - [30:30] + scfg_e24_remap_haddr + scfg_e24_remap_haddr + [3:0] read-write - rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n - 1: Assert reset, 0: De-assert reset - [31:31] + scfg_hifi4_idma_remap_araddr + scfg_hifi4_idma_remap_araddr + [7:4] + read-write + + + scfg_hifi4_idma_remap_awaddr + scfg_hifi4_idma_remap_awaddr + [11:8] + read-write + + + scfg_hifi4_sys_remap_araddr + scfg_hifi4_sys_remap_araddr + [15:12] + read-write + + + scfg_hifi4_sys_remap_awaddr + scfg_hifi4_sys_remap_awaddr + [19:16] + read-write + + + scfg_jpg_remap_araddr + scfg_jpg_remap_araddr + [23:20] + read-write + + + scfg_jpg_remap_awaddr + scfg_jpg_remap_awaddr + [27:24] + read-write + + + scfg_sd0_remap_araddr + scfg_sd0_remap_araddr + [31:28] read-write - syscrg_rst1_status - SYSCRG RESET Status 1 - 0x30c + sys_sysconsaif_syscfg4 + SYS SYSCONSAIF SYSCFG 4 + 0x4 32 - rstn_u0_sft7100_noc_bus_reset_venc_axi_n - 1: Assert reset, 0: De-assert reset + scfg_sd1_remap_awaddr + scfg_sd1_remap_awaddr + [3:0] + read-write + + + scfg_sec_haddr_remap + scfg_sec_haddr_remap + [7:4] + read-write + + + scfg_usb_araddr_remap + scfg_usb_araddr_remap + [11:8] + read-write + + + scfg_usb_awaddr_remap + scfg_usb_awaddr_remap + [15:12] + read-write + + + scfg_vdec_remap_awaddr + scfg_vdec_remap_awaddr + [19:16] + read-write + + + scfg_venc_remap_araddr + scfg_venc_remap_araddr + [23:20] + read-write + + + scfg_venc_remap_awaddr + scfg_venc_remap_awaddr + [27:24] + read-write + + + scfg_vout0_remap_araddr + scfg_vout0_remap_araddr + [31:28] + read-write + + + + + sys_sysconsaif_syscfg8 + SYS SYSCONSAIF SYSCFG 8 + 0x8 + 32 + + + scfg_vout0_remap_awaddr + scfg_vout0_remap_awaddr + [3:0] + read-write + + + scfg_vout1_remap_araddr + scfg_vout1_remap_araddr + [7:4] + read-write + + + scfg_vout1_remap_awaddr + scfg_vout1_remap_awaddr + [11:8] + read-write + + + + + sys_sysconsaif_syscfg12 + SYS SYSCONSAIF SYSCFG 12: Set the GPIO voltage of all the 4 GPIO groups in this register + 0xc + 32 + + + scfg_vout0_remap_awaddr_gpio0 + 0: GPIO Group 0 (GPIO21-35) voltage select 3.3V, 1: GPIO Group 0 (GPIO21-35) voltage select 1.8V [0:0] read-write - rstn_u0_axi_cfg1_dec_rstn_ahb - 1: Assert reset, 0: De-assert reset + scfg_vout0_remap_awaddr_gpio1 + 0: GPIO Group 1 (GPIO36-63) voltage select 3.3V, 1: GPIO Group 1 (GPIO36-63) voltage select 1.8V [1:1] read-write - rstn_u0_axi_cfg1_dec_rstn_main - 1: Assert reset, 0: De-assert reset + scfg_vout0_remap_awaddr_gpio2 + 0: GPIO Group 2 (GPIO0-6) voltage select 3.3V, 1: GPIO Group 2 (GPIO0-6) voltage select 1.8V [2:2] read-write - rstn_u0_axi_cfg0_dec_rstn_main - 1: Assert reset, 0: De-assert reset + scfg_vout0_remap_awaddr_gpio3 + 0: GPIO Group 3 (GPIO7-20) voltage select 3.3V, 1: GPIO Group 3 (GPIO7-20) voltage select 1.8V + [3:3] + read-write + + + + + sys_sysconsaif_syscfg16 + SYS SYSCONSAIF SYSCFG 16 + 0x10 + 32 + + + u0_coda12_o_cur_inst_a + Tie 0 in JPU internal, do not care + [1:0] + read-only + + + u0_wave511_o_vpu_idle + VPU monitoring signal + [2:2] + read-only + + + u0_can_ctrl_can_fd_enable + u0_can_ctrl_can_fd_enable [3:3] read-write - rstn_u0_axi_cfg0_dec_rstn_main_div - 1: Assert reset, 0: De-assert reset - [4:4] + u0_can_ctrl_host_ecc_disable + u0_can_ctrl_host_ecc_disable + [4:4] + read-write + + + u0_can_ctrl_host_if + u0_can_ctrl_host_if + [23:5] + read-only + + + u0_cdns_qspi_scfg_qspi_sclk_dlychain_sel + des_qspi_sclk_dla: clock delay + [28:24] + read-only + + + + + sys_sysconsaif_syscfg20 + SYS SYSCONSAIF SYSCFG 20 + 0x14 + 32 + + + u0_cdns_qspi_scfg_sram_config_slp + SRAM/ROM configuration. SLP: sleep enable, high active, default is low. + [0:0] read-write - rstn_u0_axi_cfg0_dec_rstn_hifi4 - 1: Assert reset, 0: De-assert reset - [5:5] + u0_cdns_qspi_scfg_sram_config_sram_config_sd + SRAM/ROM configuration. SD: shutdown enable, high active, default is low. + [1:1] read-write - rstn_u0_ddr_sft7110_rstn_axi - 1: Assert reset, 0: De-assert reset - [6:6] + u0_cdns_qspi_scfg_sram_config_rtsel + SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. + [3:2] read-write - rstn_u0_ddr_sft7110_rstn_osc - 1: Assert reset, 0: De-assert reset - [7:7] + u0_cdns_qspi_scfg_sram_config_ptsel + SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. + [5:4] read-write - rstn_u0_ddr_sft7110_rstn_apb - 1: Assert reset, 0: De-assert reset - [8:8] + u0_cdns_qspi_scfg_sram_config_trb + SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. + [7:6] read-write - rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n - 1: Assert reset, 0: De-assert reset - [9:9] + u0_cdns_qspi_scfg_sram_config_wtsel + SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. + [9:8] read-write - rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi - 1: Assert reset, 0: De-assert reset + u0_cdns_qspi_scfg_sram_config_vs + SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [10:10] read-write - rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src - 1: Assert reset, 0: De-assert reset + u0_cdns_qspi_scfg_sram_config_vg + SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [11:11] read-write - rstn_u0_codaj12_rstn_axi - 1: Assert reset, 0: De-assert reset + u0_cdns_spdif_scfg_sram_config_slp + SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [12:12] read-write - rstn_u0_codaj12_rstn_core - 1: Assert reset, 0: De-assert reset + u0_cdns_spdif_scfg_sram_config_sram_config_sd + SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [13:13] read-write - rstn_u0_codaj12_rstn_apb - 1: Assert reset, 0: De-assert reset - [14:14] + u0_cdns_spdif_scfg_sram_config_rtsel + SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. + [15:14] read-write - rstn_u0_wave511_rstn_axi - 1: Assert reset, 0: De-assert reset - [15:15] + u0_cdns_spdif_scfg_sram_config_ptsel + SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. + [17:16] read-write - rstn_u0_wave511_rstn_bpu - 1: Assert reset, 0: De-assert reset - [16:16] + u0_cdns_spdif_scfg_sram_config_trb + SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. + [19:18] read-write - rstn_u0_wave511_rstn_vce - 1: Assert reset, 0: De-assert reset - [17:17] + u0_cdns_spdif_scfg_sram_config_wtsel + SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. + [21:20] read-write - rstn_u0_wave511_rstn_apb - 1: Assert reset, 0: De-assert reset - [18:18] + u0_cdns_spdif_scfg_sram_config_vs + SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. + [22:22] read-write - rstn_u0_vdec_jpg_arb_jpgresetn - 1: Assert reset, 0: De-assert reset - [19:19] + u0_cdns_spdif_scfg_sram_config_vg + SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. + [23:23] read-write - rstn_u0_vdec_jpg_arb_mainresetn - 1: Assert reset, 0: De-assert reset - [20:20] - read-write + u0_cdns_spdif_trmodeo + 1 for transmitter 0 for receiver + [24:24] + read-only - rstn_u0_aximem_128b_rstn_axi - 1: Assert reset, 0: De-assert reset - [21:21] - read-write + u0_i2c_ic_en + I2C interface enable + [25:25] + read-only - rstn_u0_wave420l_rstn_axi - 1: Assert reset, 0: De-assert reset - [22:22] + u0_sdio_data_strobe_phase_ctrl + Data strobe delay chain select + [30:26] read-write - rstn_u0_wave420l_rstn_bpu - 1: Assert reset, 0: De-assert reset - [23:23] + u0_sdio_hbig_endian + AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface + [31:31] read-write + + + + sys_sysconsaif_syscfg24 + SYS SYSCONSAIF SYSCFG 24 + 0x18 + 32 + - rstn_u0_wave420l_rstn_vce - 1: Assert reset, 0: De-assert reset - [24:24] + u0_sdio_m_hbig_endian + AHB master bus interface endianess: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface + [0:0] read-write - rstn_u0_wave420l_rstn_apb - 1: Assert reset, 0: De-assert reset - [25:25] + u0_i2srx_3ch_adc_ena + u0_i2srx_3ch_adc_ena + [1:1] read-write - rstn_u1_aximem_128b_rstn_axi - 1: Assert reset, 0: De-assert reset - [26:26] + u0_intmem_rom_sram_scfg_disable_rom + u0_intmem_rom_sram_scfg_disable_rom + [2:2] read-write - rstn_u2_aximem_128b_rstn_axi - 1: Assert reset, 0: De-assert reset - [27:27] + u0_intmem_rom_sram_sram_config_slp + SRAM/ROM configuration. SLP: sleep enable, high active, default is low. + [3:3] read-write - rstn_u0_intmem_rom_sram_rstn_rom - 1: Assert reset, 0: De-assert reset - [28:28] + u0_intmem_rom_sram_sram_config_sram_config_sd + SRAM/ROM configuration. SD: shutdown enable, high active, default is low. + [4:4] read-write - rstn_u0_cdns_qspi_rstn_ahb - 1: Assert reset, 0: De-assert reset - [29:29] + u0_intmem_rom_sram_sram_config_rtsel + SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. + [6:5] read-write - rstn_u0_cdns_qspi_rstn_apb - 1: Assert reset, 0: De-assert reset - [30:30] + u0_intmem_rom_sram_sram_config_ptsel + SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. + [8:7] read-write - rstn_u0_cdns_qspi_rstn_ref - 1: Assert reset, 0: De-assert reset - [31:31] + u0_intmem_rom_sram_sram_config_trb + SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. + [10:9] read-write - - - - syscrg_rst2_status - SYSCRG RESET Status 2 - 0x310 - 32 - - rstn_u0_sdio_rstn_ahb - 1: Assert reset, 0: De-assert reset - [0:0] + u0_intmem_rom_sram_sram_config_wtsel + SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. + [12:11] read-write - rstn_u1_sdi_rstn_ahb - 1: Assert reset, 0: De-assert reset - [1:1] + u0_intmem_rom_sram_sram_config_vs + SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. + [13:13] read-write - rstn_u1_gmac5_axi64_aresetn_i - 1: Assert reset, 0: De-assert reset - [2:2] + u0_intmem_rom_sram_sram_config_vg + SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. + [14:14] read-write - rstn_u1_gmac5_axi64_hresetn_n - 1: Assert reset, 0: De-assert reset - [3:3] + u0_jtag_daisy_chain_jtag_en_0 + u0_jtag_daisy_chain_jtag_en_0 + [15:15] read-write - rstn_u0_mailbox_presetn - 1: Assert reset, 0: De-assert reset - [4:4] + u0_jtag_daisy_chain_jtag_en_1 + u0_jtag_daisy_chain_jtag_en_1 + [16:16] read-write - rstn_u0_ssp_spi_rstn_apb - 1: Assert reset, 0: De-assert reset - [5:5] + u0_pdrstn_split_sw_usbpipe_plugen + u0_pdrstn_split_sw_usbpipe_plugen + [17:17] read-write - rstn_u1_ssp_spi_rstn_apb - 1: Assert reset, 0: De-assert reset - [6:6] + u0_pll_wrap_pll0_cpi_bias + u0_pll_wrap_pll0_cpi_bias + [20:18] read-write - rstn_u2_ssp_spi_rstn_apb - 1: Assert reset, 0: De-assert reset - [7:7] + u0_pll_wrap_pll0_cpp_bias + u0_pll_wrap_pll0_cpp_bias + [23:21] read-write - rstn_u3_ssp_spi_rstn_apb - 1: Assert reset, 0: De-assert reset - [8:8] + u0_pll_wrap_pll0_dacpd + u0_pll_wrap_pll0_dacpd + [24:24] read-write - rstn_u4_ssp_spi_rstn_apb - 1: Assert reset, 0: De-assert reset - [9:9] + u0_pll_wrap_pll0_dsmpd + u0_pll_wrap_pll0_dsmpd + [25:25] + read-write + + + + + sys_sysconsaif_syscfg28 + SYS SYSCONSAIF SYSCFG 28 + 0x1c + 32 + + + u0_pll_wrap_pll0_fbdiv + u0_pll_wrap_pll0_fbdiv + [11:0] read-write + + + + sys_sysconsaif_syscfg32 + SYS SYSCONSAIF SYSCFG 32 + 0x20 + 32 + - rstn_u5_ssp_spi_rstn_apb - 1: Assert reset, 0: De-assert reset - [10:10] + u0_pll_wrap_pll0_frac + u0_pll_wrap_pll0_frac + [23:0] read-write - rstn_u6_ssp_spi_rstn_apb - 1: Assert reset, 0: De-assert reset - [11:11] + u0_pll_wrap_pll0_gvco_bias + u0_pll_wrap_pll0_gvco_bias + [25:24] read-write - rstn_u0_i2c_rstn_apb - 1: Assert reset, 0: De-assert reset - [12:12] - read-write + u0_pll_wrap_pll0_lock + u0_pll_wrap_pll0_lock + [26:26] + read-only - rstn_u1_i2c_rstn_apb - 1: Assert reset, 0: De-assert reset - [13:13] + u0_pll_wrap_pll0_pd + u0_pll_wrap_pll0_pd + [27:27] read-write - rstn_u2_i2c_rstn_apb - 1: Assert reset, 0: De-assert reset - [14:14] + u0_pll_wrap_pll0_postdiv1 + u0_pll_wrap_pll0_postdiv1 + [29:28] read-write - rstn_u3_i2c_rstn_apb - 1: Assert reset, 0: De-assert reset - [15:15] + u0_pll_wrap_pll0_postdiv2 + u0_pll_wrap_pll0_postdiv2 + [31:30] read-write + + + + sys_sysconsaif_syscfg36 + SYS SYSCONSAIF SYSCFG 36 + 0x24 + 32 + - rstn_u4_i2c_rstn_apb - 1: Assert reset, 0: De-assert reset - [16:16] + u0_pll_wrap_pll0_prediv + u0_pll_wrap_pll0_prediv + [5:0] read-write - rstn_u5_i2c_rstn_apb - 1: Assert reset, 0: De-assert reset - [17:17] + u0_pll_wrap_pll0_testen + u0_pll_wrap_pll0_testen + [6:6] read-write - rstn_u6_i2c_rstn_apb - 1: Assert reset, 0: De-assert reset - [18:18] + u0_pll_wrap_pll0_testsel + u0_pll_wrap_pll0_testsel + [8:7] read-write - rstn_u0_uart_rstn_apb - 1: Assert reset, 0: De-assert reset - [19:19] + u0_pll_wrap_pll1_cpi_bias + u0_pll_wrap_pll1_cpi_bias + [11:9] read-write - rstn_u0_uart_rstn_core - 1: Assert reset, 0: De-assert reset - [20:20] + u0_pll_wrap_pll1_cpp_bias + u0_pll_wrap_pll1_cpp_bias + [14:12] read-write - rstn_u1_uart_rstn_apb - 1: Assert reset, 0: De-assert reset - [21:21] + u0_pll_wrap_pll1_dacpd + u0_pll_wrap_pll1_dacpd + [15:15] read-write - rstn_u1_uart_rstn_core - 1: Assert reset, 0: De-assert reset - [22:22] + u0_pll_wrap_pll1_dsmpd + u0_pll_wrap_pll1_dsmpd + [16:16] read-write - rstn_u2_uart_rstn_apb - 1: Assert reset, 0: De-assert reset - [23:23] + u0_pll_wrap_pll1_fbdiv + u0_pll_wrap_pll1_fbdiv + [28:17] read-write + + + + sys_sysconsaif_syscfg40 + SYS SYSCONSAIF SYSCFG 40 + 0x28 + 32 + - rstn_u2_uart_rstn_core - 1: Assert reset, 0: De-assert reset - [24:24] + u0_pll_wrap_pll1_frac + u0_pll_wrap_pll1_frac + [23:0] read-write - rstn_u3_uart_rstn_apb - 1: Assert reset, 0: De-assert reset - [25:25] + u0_pll_wrap_pll1_gvco_bias + u0_pll_wrap_pll1_gvco_bias + [25:24] read-write - rstn_u3_uart_rstn_core - 1: Assert reset, 0: De-assert reset + u0_pll_wrap_pll1_lock + u0_pll_wrap_pll1_lock [26:26] - read-write + read-only - rstn_u4_uart_rstn_apb - 1: Assert reset, 0: De-assert reset + u0_pll_wrap_pll1_pd + u0_pll_wrap_pll1_pd [27:27] read-write - rstn_u4_uart_rstn_core - 1: Assert reset, 0: De-assert reset - [28:28] - read-write - - - rstn_u5_uart_rstn_apb - 1: Assert reset, 0: De-assert reset - [29:29] - read-write - - - rstn_u6_uart_rstn_core - 1: Assert reset, 0: De-assert reset - [30:30] + u0_pll_wrap_pll1_postdiv1 + u0_pll_wrap_pll1_postdiv1 + [29:28] read-write - rstn_u0_cdns_spdif_rstn_apb - 1: Assert reset, 0: De-assert reset - [31:31] + u0_pll_wrap_pll1_postdiv2 + u0_pll_wrap_pll1_postdiv2 + [31:30] read-write - syscrg_rst3_status - SYSCRG RESET Status 3 - 0x314 + sys_sysconsaif_syscfg44 + SYS SYSCONSAIF SYSCFG 44 + 0x2c 32 - rstn_u0_pwmdac_rstn_apb - 1: Assert reset, 0: De-assert reset - [0:0] + u0_pll_wrap_pll1_prediv + u0_pll_wrap_pll1_prediv + [5:0] read-write - rstn_u0_pdm_4mic_rstn_dmic - 1: Assert reset, 0: De-assert reset - [1:1] + u0_pll_wrap_pll1_testen + u0_pll_wrap_pll1_testen + [6:6] read-write - rstn_u0_pdm_4mic_rstn_apb - 1: Assert reset, 0: De-assert reset - [2:2] + u0_pll_wrap_pll1_testsel + u0_pll_wrap_pll1_testsel + [8:7] read-write - rstn_u0_i2srx_3ch_rstn_apb - 1: Assert reset, 0: De-assert reset - [3:3] + u0_pll_wrap_pll2_cpi_bias + u0_pll_wrap_pll2_cpi_bias + [11:9] read-write - rstn_u0_i2srx_3ch_rstn_bclk - 1: Assert reset, 0: De-assert reset - [4:4] + u0_pll_wrap_pll2_cpp_bias + u0_pll_wrap_pll2_cpp_bias + [14:12] read-write - rstn_u0_i2stx_4ch_rstn_apb - 1: Assert reset, 0: De-assert reset - [5:5] + u0_pll_wrap_pll2_dacpd + u0_pll_wrap_pll2_dacpd + [15:15] read-write - rstn_u0_i2stx_4ch_rstn_bclk - 1: Assert reset, 0: De-assert reset - [6:6] + u0_pll_wrap_pll2_dsmpd + u0_pll_wrap_pll2_dsmpd + [16:16] read-write - rstn_u1_i2stx_4ch_rstn_apb - 1: Assert reset, 0: De-assert reset - [7:7] + u0_pll_wrap_pll2_fbdiv + u0_pll_wrap_pll2_fbdiv + [28:17] read-write + + + + sys_sysconsaif_syscfg48 + SYS SYSCONSAIF SYSCFG 48 + 0x30 + 32 + - rstn_u1_i2stx_4ch_rstn_bclk - 1: Assert reset, 0: De-assert reset - [8:8] + u0_pll_wrap_pll2_frac + u0_pll_wrap_pll2_frac + [23:0] read-write - rstn_u0_tdm16slot_rstn_ahb - 1: Assert reset, 0: De-assert reset - [9:9] + u0_pll_wrap_pll2_gvco_bias + u0_pll_wrap_pll2_gvco_bias + [25:24] read-write - rstn_u0_tdm16slot_rstn_tdm - 1: Assert reset, 0: De-assert reset - [10:10] - read-write + u0_pll_wrap_pll2_lock + u0_pll_wrap_pll2_lock + [26:26] + read-only - rstn_u0_tdm16slot_rstn_apb - 1: Assert reset, 0: De-assert reset - [11:11] + u0_pll_wrap_pll2_pd + u0_pll_wrap_pll2_pd + [27:27] read-write - rstn_u0_pwm_8ch_rstn_apb - 1: Assert reset, 0: De-assert reset - [12:12] + u0_pll_wrap_pll2_postdiv1 + u0_pll_wrap_pll2_postdiv1 + [29:28] + read-write + + + u0_pll_wrap_pll2_postdiv2 + u0_pll_wrap_pll2_postdiv2 + [31:30] read-write + + + + sys_sysconsaif_syscfg52 + SYS SYSCONSAIF SYSCFG 52 + 0x34 + 32 + - rstn_u0_dskit_wdt_rstn_apb - 1: Assert reset, 0: De-assert reset - [13:13] + u0_pll_wrap_pll2_prediv + u0_pll_wrap_pll2_prediv + [5:0] read-write - rstn_u0_dskit_wdt_rstn_wdt - 1: Assert reset, 0: De-assert reset - [14:14] + u0_pll_wrap_pll2_testen + u0_pll_wrap_pll2_testen + [6:6] read-write - rstn_u0_can_ctrl_rstn_apb - 1: Assert reset, 0: De-assert reset - [15:15] + u0_pll_wrap_pll2_testsel + u0_pll_wrap_pll2_testsel + [8:7] read-write - rstn_u0_can_ctrl_rstn_can - 1: Assert reset, 0: De-assert reset - [16:16] + u0_pll_wrap_syscfg_test_pll_mode + PLL test mode, only used for PLL BIST through jtag2apb + [9:9] read-write - rstn_u0_can_ctrl_rstn_timer - 1: Assert reset, 0: De-assert reset - [17:17] + u0_saif_audio_sdin_mux_scfg_i2sdin_sel + u0_saif_audio_sdin_mux_scfg_i2sdin_sel + [17:10] read-write - rstn_u1_can_ctrl_rstn_apb - 1: Assert reset, 0: De-assert reset + u0_sft7110_noc_bus_clock_gating_off + u0_sft7110_noc_bus_clock_gating_off [18:18] read-write - rstn_u1_can_ctrl_rstn_can - 1: Assert reset, 0: De-assert reset + u0_sft7110_noc_bus_oic_evemon_0_start + u0_sft7110_noc_bus_oic_evemon_0_start [19:19] read-write - rstn_u1_can_ctrl_rstn_timer - 1: Assert reset, 0: De-assert reset + u0_sft7110_noc_bus_oic_evemon_0_trigger + u0_sft7110_noc_bus_oic_evemon_0_trigger [20:20] - read-write + read-only - rstn_u0_si5_timer_rstn_apb - 1: Assert reset, 0: De-assert reset + u0_sft7110_noc_bus_oic_evemon_1_start + u0_sft7110_noc_bus_oic_evemon_1_start [21:21] read-write - rstn_u0_si5_timer_rstn_timer0 - 1: Assert reset, 0: De-assert reset + u0_sft7110_noc_bus_oic_evemon_1_trigger + u0_sft7110_noc_bus_oic_evemon_1_trigger [22:22] - read-write + read-only - rstn_u0_si5_timer_rstn_time10 - 1: Assert reset, 0: De-assert reset + u0_sft7110_noc_bus_oic_evemon_2_start + u0_sft7110_noc_bus_oic_evemon_2_start [23:23] read-write - rstn_u0_si5_timer_rstn_timer2 - 1: Assert reset, 0: De-assert reset + u0_sft7110_noc_bus_oic_evemon_2_trigger + u0_sft7110_noc_bus_oic_evemon_2_trigger [24:24] - read-write + read-only - rstn_u0_si5_timer_rstn_timer3 - 1: Assert reset, 0: De-assert reset + u0_sft7110_noc_bus_oic_evemon_3_start + u0_sft7110_noc_bus_oic_evemon_3_start [25:25] read-write - rstn_u0_int_ctrl_rstn_apb - 1: Assert reset, 0: De-assert reset + u0_sft7110_noc_bus_oic_evemon_3_trigger + u0_sft7110_noc_bus_oic_evemon_3_trigger [26:26] - read-write + read-only - rstn_u0_temp_sensor_rstn_apb - 1: Assert reset, 0: De-assert reset + u0_sft7110_noc_bus_oic_evemon_4_start + u0_sft7110_noc_bus_oic_evemon_4_start [27:27] read-write - rstn_u0_temp_sensor_rstn_temp - 1: Assert reset, 0: De-assert reset + u0_sft7110_noc_bus_oic_evemon_4_trigger + u0_sft7110_noc_bus_oic_evemon_4_trigger [28:28] - read-write + read-only - rstn_u0_jtag_certification_rst_n - 1: Assert reset, 0: De-assert reset + u0_sft7110_noc_bus_oic_evemon_5_start + u0_sft7110_noc_bus_oic_evemon_5_start [29:29] read-write + + u0_sft7110_noc_bus_oic_evemon_5_trigger + u0_sft7110_noc_bus_oic_evemon_5_trigger + [30:30] + read-only + + + u0_sft7110_noc_bus_oic_evemon_6_start + u0_sft7110_noc_bus_oic_evemon_6_start + [31:31] + read-write + - - - - starfive_jh7110_sys_syscon_0 - From starfive,jh7110-sys-syscon, peripheral generator - 0x13030000 - - 0 - 0x1000 - registers - - - sys_sysconsaif_syscfg0 - SYS SYSCONSAIF SYSCFG 0 - 0x0 + sys_sysconsaif_syscfg56 + SYS SYSCONSAIF SYSCFG 56 + 0x38 32 - scfg_e24_remap_haddr - scfg_e24_remap_haddr - [3:0] - read-write + u0_sft7110_noc_bus_oic_evemon_6_trigger + u0_sft7110_noc_bus_oic_evemon_6_trigger + [0:0] + read-only - scfg_hifi4_idma_remap_araddr - scfg_hifi4_idma_remap_araddr - [7:4] + u0_sft7110_noc_bus_oic_evemon_7_start + u0_sft7110_noc_bus_oic_evemon_7_start + [15:15] read-write - scfg_hifi4_idma_remap_awaddr - scfg_hifi4_idma_remap_awaddr - [11:8] + u0_sft7110_noc_bus_oic_evemon_7_trigger + u0_sft7110_noc_bus_oic_evemon_7_trigger + [16:16] + read-only + + + u0_sft7110_noc_bus_oic_evemon_8_start + u0_sft7110_noc_bus_oic_evemon_8_start + [17:17] read-write - scfg_hifi4_sys_remap_araddr - scfg_hifi4_sys_remap_araddr - [15:12] + u0_sft7110_noc_bus_oic_evemon_8_trigger + u0_sft7110_noc_bus_oic_evemon_8_trigger + [18:18] + read-only + + + u0_sft7110_noc_bus_oic_ignore_modifiable_0 + u0_sft7110_noc_bus_oic_ignore_modifiable_0 + [5:5] read-write - scfg_hifi4_sys_remap_awaddr - scfg_hifi4_sys_remap_awaddr - [19:16] + u0_sft7110_noc_bus_oic_ignore_modifiable_1 + u0_sft7110_noc_bus_oic_ignore_modifiable_1 + [6:6] read-write - scfg_jpg_remap_araddr - scfg_jpg_remap_araddr - [23:20] + u0_sft7110_noc_bus_oic_ignore_modifiable_2 + u0_sft7110_noc_bus_oic_ignore_modifiable_2 + [7:7] read-write - scfg_jpg_remap_awaddr - scfg_jpg_remap_awaddr - [27:24] + u0_sft7110_noc_bus_oic_ignore_modifiable_3 + u0_sft7110_noc_bus_oic_ignore_modifiable_3 + [8:8] read-write - scfg_sd0_remap_araddr - scfg_sd0_remap_araddr - [31:28] + u0_sft7110_noc_bus_oic_ignore_modifiable_4 + u0_sft7110_noc_bus_oic_ignore_modifiable_4 + [9:9] read-write - sys_sysconsaif_syscfg4 - SYS SYSCONSAIF SYSCFG 4 - 0x4 + sys_sysconsaif_syscfg60 + SYS SYSCONSAIF SYSCFG 60 + 0x3c 32 - scfg_sd1_remap_awaddr - scfg_sd1_remap_awaddr - [3:0] - read-write - - - scfg_sec_haddr_remap - scfg_sec_haddr_remap - [7:4] - read-write - - - scfg_usb_araddr_remap - scfg_usb_araddr_remap - [11:8] - read-write - - - scfg_usb_awaddr_remap - scfg_usb_awaddr_remap - [15:12] - read-write - - - scfg_vdec_remap_awaddr - scfg_vdec_remap_awaddr - [19:16] - read-write - - - scfg_venc_remap_araddr - scfg_venc_remap_araddr - [23:20] + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0 + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0 + [31:0] read-write + + + + sys_sysconsaif_syscfg64 + SYS SYSCONSAIF SYSCFG 64 + 0x40 + 32 + - scfg_venc_remap_awaddr - scfg_venc_remap_awaddr - [27:24] + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1 + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1 + [31:0] read-write + + + + sys_sysconsaif_syscfg68 + SYS SYSCONSAIF SYSCFG 68 + 0x44 + 32 + - scfg_vout0_remap_araddr - scfg_vout0_remap_araddr - [31:28] + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2 + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2 + [31:0] read-write - sys_sysconsaif_syscfg8 - SYS SYSCONSAIF SYSCFG 8 - 0x8 + sys_sysconsaif_syscfg72 + SYS SYSCONSAIF SYSCFG 72 + 0x48 32 - scfg_vout0_remap_awaddr - scfg_vout0_remap_awaddr - [3:0] - read-write - - - scfg_vout1_remap_araddr - scfg_vout1_remap_araddr - [7:4] - read-write - - - scfg_vout1_remap_awaddr - scfg_vout1_remap_awaddr - [11:8] + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3 + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3 + [31:0] read-write - sys_sysconsaif_syscfg12 - SYS SYSCONSAIF SYSCFG 12: Set the GPIO voltage of all the 4 GPIO groups in this register - 0xc + sys_sysconsaif_syscfg76 + SYS SYSCONSAIF SYSCFG 76 + 0x4c 32 - scfg_vout0_remap_awaddr_gpio0 - 0: GPIO Group 0 (GPIO21-35) voltage select 3.3V, 1: GPIO Group 0 (GPIO21-35) voltage select 1.8V - [0:0] - read-write - - - scfg_vout0_remap_awaddr_gpio1 - 0: GPIO Group 1 (GPIO36-63) voltage select 3.3V, 1: GPIO Group 1 (GPIO36-63) voltage select 1.8V - [1:1] + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4 + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4 + [31:0] read-write + + + + sys_sysconsaif_syscfg80 + SYS SYSCONSAIF SYSCFG 80 + 0x50 + 32 + - scfg_vout0_remap_awaddr_gpio2 - 0: GPIO Group 2 (GPIO0-6) voltage select 3.3V, 1: GPIO Group 2 (GPIO0-6) voltage select 1.8V - [2:2] + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5 + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5 + [31:0] read-write + + + + sys_sysconsaif_syscfg84 + SYS SYSCONSAIF SYSCFG 84 + 0x54 + 32 + - scfg_vout0_remap_awaddr_gpio3 - 0: GPIO Group 3 (GPIO7-20) voltage select 3.3V, 1: GPIO Group 3 (GPIO7-20) voltage select 1.8V - [3:3] + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6 + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6 + [31:0] read-write - sys_sysconsaif_syscfg16 - SYS SYSCONSAIF SYSCFG 16 - 0x10 + sys_sysconsaif_syscfg88 + SYS SYSCONSAIF SYSCFG 88 + 0x58 32 - u0_coda12_o_cur_inst_a - Tie 0 in JPU internal, do not care - [1:0] - read-only - - - u0_wave511_o_vpu_idle - VPU monitoring signal - [2:2] - read-only - - - u0_can_ctrl_can_fd_enable - u0_can_ctrl_can_fd_enable - [3:3] + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7 + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7 + [31:0] read-write + + + + sys_sysconsaif_syscfg92 + SYS SYSCONSAIF SYSCFG 92 + 0x5c + 32 + - u0_can_ctrl_host_ecc_disable - u0_can_ctrl_host_ecc_disable - [4:4] + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8 + u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8 + [31:0] read-write - - u0_can_ctrl_host_if - u0_can_ctrl_host_if - [23:5] - read-only - - - u0_cdns_qspi_scfg_qspi_sclk_dlychain_sel - des_qspi_sclk_dla: clock delay - [28:24] - read-only - - sys_sysconsaif_syscfg20 - SYS SYSCONSAIF SYSCFG 20 - 0x14 + sys_sysconsaif_syscfg96 + SYS SYSCONSAIF SYSCFG 96 + 0x60 32 - u0_cdns_qspi_scfg_sram_config_slp - SRAM/ROM configuration. SLP: sleep enable, high active, default is low. + u0_tdm16slot_clkpol + u0_tdm16slot_clkpol [0:0] - read-write + read-only - u0_cdns_qspi_scfg_sram_config_sram_config_sd - SRAM/ROM configuration. SD: shutdown enable, high active, default is low. + u0_tdm16slot_pcm_ms + u0_tdm16slot_pcm_ms [1:1] - read-write + read-only - u0_cdns_qspi_scfg_sram_config_rtsel - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. - [3:2] + u0_trace_mtx_scfg_c0_in0_ctl + u0_trace_mtx_scfg_c0_in0_ctl + [6:2] read-write - u0_cdns_qspi_scfg_sram_config_ptsel - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. - [5:4] + u0_trace_mtx_scfg_c0_in1_ctl + u0_trace_mtx_scfg_c0_in1_ctl + [11:7] read-write - u0_cdns_qspi_scfg_sram_config_trb - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. - [7:6] + u0_trace_mtx_scfg_c1_in0_ctl + u0_trace_mtx_scfg_c1_in0_ctl + [16:12] read-write - u0_cdns_qspi_scfg_sram_config_wtsel - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. - [9:8] + u0_trace_mtx_scfg_c1_in1_ctl + u0_trace_mtx_scfg_c1_in1_ctl + [21:17] read-write - u0_cdns_qspi_scfg_sram_config_vs - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. - [10:10] + u0_trace_mtx_scfg_c2_in0_ctl + u0_trace_mtx_scfg_c2_in0_ctl + [26:22] read-write - u0_cdns_qspi_scfg_sram_config_vg - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. - [11:11] + u0_trace_mtx_scfg_c2_in1_ctl + u0_trace_mtx_scfg_c2_in1_ctl + [31:27] read-write + + + + sys_sysconsaif_syscfg100 + SYS SYSCONSAIF SYSCFG 100 + 0x64 + 32 + - u0_cdns_spdif_scfg_sram_config_slp - SRAM/ROM configuration. SLP: sleep enable, high active, default is low. - [12:12] + u0_trace_mtx_scfg_c3_in0_ctl + u0_trace_mtx_scfg_c3_in0_ctl + [4:0] read-write - u0_cdns_spdif_scfg_sram_config_sram_config_sd - SRAM/ROM configuration. SD: shutdown enable, high active, default is low. - [13:13] + u0_trace_mtx_scfg_c3_in1_ctl + u0_trace_mtx_scfg_c3_in1_ctl + [9:5] read-write - u0_cdns_spdif_scfg_sram_config_rtsel - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. - [15:14] + u0_trace_mtx_scfg_c4_in0_ctl + u0_trace_mtx_scfg_c4_in0_ctl + [14:10] read-write - u0_cdns_spdif_scfg_sram_config_ptsel - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. - [17:16] + u0_trace_mtx_scfg_c4_in1_ctl + u0_trace_mtx_scfg_c4_in1_ctl + [19:15] read-write - u0_cdns_spdif_scfg_sram_config_trb - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. - [19:18] - read-write + u0_u7mc_sft7110_cease_from_tile_0 + u0_u7mc_sft7110_cease_from_tile_0 + [20:20] + read-only - u0_cdns_spdif_scfg_sram_config_wtsel - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. - [21:20] - read-write + u0_u7mc_sft7110_cease_from_tile_1 + u0_u7mc_sft7110_cease_from_tile_1 + [21:21] + read-only - u0_cdns_spdif_scfg_sram_config_vs - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. + u0_u7mc_sft7110_cease_from_tile_2 + u0_u7mc_sft7110_cease_from_tile_2 [22:22] - read-write + read-only - u0_cdns_spdif_scfg_sram_config_vg - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. + u0_u7mc_sft7110_cease_from_tile_3 + u0_u7mc_sft7110_cease_from_tile_3 [23:23] - read-write + read-only - u0_cdns_spdif_trmodeo - 1 for transmitter 0 for receiver + u0_u7mc_sft7110_cease_from_tile_4 + u0_u7mc_sft7110_cease_from_tile_4 [24:24] read-only - u0_i2c_ic_en - I2C interface enable - [25:25] + u0_u7mc_sft7110_halt_from_tile_0 + u0_u7mc_sft7110_halt_from_tile_0 + [25:25] + read-only + + + u0_u7mc_sft7110_halt_from_tile_1 + u0_u7mc_sft7110_halt_from_tile_1 + [26:26] + read-only + + + u0_u7mc_sft7110_halt_from_tile_2 + u0_u7mc_sft7110_halt_from_tile_2 + [27:27] read-only - u0_sdio_data_strobe_phase_ctrl - Data strobe delay chain select - [30:26] - read-write + u0_u7mc_sft7110_halt_from_tile_3 + u0_u7mc_sft7110_halt_from_tile_3 + [28:28] + read-only - u0_sdio_hbig_endian - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface - [31:31] - read-write + u0_u7mc_sft7110_halt_from_tile_4 + u0_u7mc_sft7110_halt_from_tile_4 + [29:29] + read-only - sys_sysconsaif_syscfg24 - SYS SYSCONSAIF SYSCFG 24 - 0x18 + sys_sysconsaif_syscfg104 + SYS SYSCONSAIF SYSCFG 104 + 0x68 32 - u0_sdio_m_hbig_endian - AHB master bus interface endianess: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface - [0:0] - read-write - - - u0_i2srx_3ch_adc_ena - u0_i2srx_3ch_adc_ena - [1:1] - read-write - - - u0_intmem_rom_sram_scfg_disable_rom - u0_intmem_rom_sram_scfg_disable_rom - [2:2] - read-write - - - u0_intmem_rom_sram_sram_config_slp - SRAM/ROM configuration. SLP: sleep enable, high active, default is low. - [3:3] + u0_u7mc_sft7110_reset_vector_1_31_0 + u0_u7mc_sft7110_reset_vector_1_31_0 + [31:0] read-write + + + + sys_sysconsaif_syscfg108 + SYS SYSCONSAIF SYSCFG 108 + 0x6c + 32 + - u0_intmem_rom_sram_sram_config_sram_config_sd - SRAM/ROM configuration. SD: shutdown enable, high active, default is low. - [4:4] + u0_u7mc_sft7110_reset_vector_1_35_32 + u0_u7mc_sft7110_reset_vector_1_35_32 + [3:0] read-write + + + + sys_sysconsaif_syscfg112 + SYS SYSCONSAIF SYSCFG 112 + 0x70 + 32 + - u0_intmem_rom_sram_sram_config_rtsel - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. - [6:5] + u0_u7mc_sft7110_reset_vector_2_31_0 + u0_u7mc_sft7110_reset_vector_2_31_0 + [31:0] read-write + + + + sys_sysconsaif_syscfg116 + SYS SYSCONSAIF SYSCFG 116 + 0x74 + 32 + - u0_intmem_rom_sram_sram_config_ptsel - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. - [8:7] + u0_u7mc_sft7110_reset_vector_2_35_32 + u0_u7mc_sft7110_reset_vector_2_35_32 + [3:0] read-write + + + + sys_sysconsaif_syscfg120 + SYS SYSCONSAIF SYSCFG 120 + 0x78 + 32 + - u0_intmem_rom_sram_sram_config_trb - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. - [10:9] + u0_u7mc_sft7110_reset_vector_3_31_0 + u0_u7mc_sft7110_reset_vector_3_31_0 + [31:0] read-write + + + + sys_sysconsaif_syscfg124 + SYS SYSCONSAIF SYSCFG 124 + 0x7c + 32 + - u0_intmem_rom_sram_sram_config_wtsel - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. - [12:11] + u0_u7mc_sft7110_reset_vector_3_35_32 + u0_u7mc_sft7110_reset_vector_3_35_32 + [3:0] read-write + + + + sys_sysconsaif_syscfg128 + SYS SYSCONSAIF SYSCFG 128 + 0x80 + 32 + - u0_intmem_rom_sram_sram_config_vs - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. - [13:13] + u0_u7mc_sft7110_reset_vector_4_31_0 + u0_u7mc_sft7110_reset_vector_4_31_0 + [31:0] read-write + + + + sys_sysconsaif_syscfg136 + SYS SYSCONSAIF SYSCFG 136 + 0x88 + 32 + - u0_intmem_rom_sram_sram_config_vg - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. - [14:14] + u0_venc_intsram_sram_config_slp + SRAM/ROM configuration. SLP: sleep enable, high active, default is low. + [0:0] read-write - u0_jtag_daisy_chain_jtag_en_0 - u0_jtag_daisy_chain_jtag_en_0 - [15:15] + u0_venc_intsram_sram_config_sram_config_sd + SRAM/ROM configuration. SD: shutdown enable, high active, default is low. + [1:1] read-write - u0_jtag_daisy_chain_jtag_en_1 - u0_jtag_daisy_chain_jtag_en_1 - [16:16] + u0_venc_intsram_sram_config_rtsel + SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. + [3:2] read-write - u0_pdrstn_split_sw_usbpipe_plugen - u0_pdrstn_split_sw_usbpipe_plugen - [17:17] + u0_venc_intsram_sram_config_ptsel + SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. + [5:4] read-write - u0_pll_wrap_pll0_cpi_bias - u0_pll_wrap_pll0_cpi_bias - [20:18] + u0_venc_intsram_sram_config_trb + SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. + [7:6] read-write - u0_pll_wrap_pll0_cpp_bias - u0_pll_wrap_pll0_cpp_bias - [23:21] + u0_venc_intsram_sram_config_wtsel + SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. + [9:8] read-write - u0_pll_wrap_pll0_dacpd - u0_pll_wrap_pll0_dacpd - [24:24] + u0_venc_intsram_sram_config_vs + SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. + [10:10] read-write - u0_pll_wrap_pll0_dsmpd - u0_pll_wrap_pll0_dsmpd - [25:25] + u0_venc_intsram_sram_config_vg + SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. + [11:11] read-write - - - - sys_sysconsaif_syscfg28 - SYS SYSCONSAIF SYSCFG 28 - 0x1c - 32 - - u0_pll_wrap_pll0_fbdiv - u0_pll_wrap_pll0_fbdiv - [11:0] + u0_wave420l_i_ipu_current_buffer + This signal indicates which buffer is currently active so that the VPU can correctly use the ipu_end_of_row signal for row counter. + [14:12] read-write - - - - sys_sysconsaif_syscfg32 - SYS SYSCONSAIF SYSCFG 32 - 0x20 - 32 - - u0_pll_wrap_pll0_frac - u0_pll_wrap_pll0_frac - [23:0] + u0_wave420l_i_ipu_end_of_row + This signal is flipped every time when the IPU completes writing a row. + [15:15] read-write - u0_pll_wrap_pll0_gvco_bias - u0_pll_wrap_pll0_gvco_bias - [25:24] + u0_wave420l_i_ipu_new_frame + This signal is flipped every time when the IPU completes writing a new frame. + [16:16] read-write - u0_pll_wrap_pll0_lock - u0_pll_wrap_pll0_lock - [26:26] + u0_wave420l_o_vpu_idle + VPU monitoring signal. This signal gives out an opposite value of VPU_BUSY register. + [17:17] read-only - u0_pll_wrap_pll0_pd - u0_pll_wrap_pll0_pd - [27:27] - read-write - - - u0_pll_wrap_pll0_postdiv1 - u0_pll_wrap_pll0_postdiv1 - [29:28] + u1_can_ctrl_can_fd_enable + u1_can_ctrl_can_fd_enable + [18:18] read-write - u0_pll_wrap_pll0_postdiv2 - u0_pll_wrap_pll0_postdiv2 - [31:30] + u1_can_ctrl_host_ecc_disable + u1_can_ctrl_host_ecc_disable + [19:19] read-write - sys_sysconsaif_syscfg36 - SYS SYSCONSAIF SYSCFG 36 - 0x24 + sys_sysconsaif_syscfg140 + SYS SYSCONSAIF SYSCFG 140 + 0x8c 32 - u0_pll_wrap_pll0_prediv - u0_pll_wrap_pll0_prediv - [5:0] + u1_can_ctrl_host_if + u1_can_ctrl_host_if + [18:0] + read-only + + + u1_gmac5_axi64_scfg_ram_cfg_slp + SRAM/ROM configuration. SLP: sleep enable, high active, default is low. + [19:19] read-write - u0_pll_wrap_pll0_testen - u0_pll_wrap_pll0_testen - [6:6] + u1_gmac5_axi64_scfg_ram_cfg_sram_config_sd + SRAM/ROM configuration. SD: shutdown enable, high active, default is low. + [20:20] read-write - u0_pll_wrap_pll0_testsel - u0_pll_wrap_pll0_testsel - [8:7] + u1_gmac5_axi64_scfg_ram_cfg_rtsel + SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. + [22:21] read-write - u0_pll_wrap_pll1_cpi_bias - u0_pll_wrap_pll1_cpi_bias - [11:9] + u1_gmac5_axi64_scfg_ram_cfg_ptsel + SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. + [24:23] read-write - u0_pll_wrap_pll1_cpp_bias - u0_pll_wrap_pll1_cpp_bias - [14:12] + u1_gmac5_axi64_scfg_ram_cfg_trb + SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. + [26:25] read-write - u0_pll_wrap_pll1_dacpd - u0_pll_wrap_pll1_dacpd - [15:15] + u1_gmac5_axi64_scfg_ram_cfg_wtsel + SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. + [28:27] read-write - u0_pll_wrap_pll1_dsmpd - u0_pll_wrap_pll1_dsmpd - [16:16] + u1_gmac5_axi64_scfg_ram_cfg_vs + SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. + [29:29] read-write - u0_pll_wrap_pll1_fbdiv - u0_pll_wrap_pll1_fbdiv - [28:17] + u1_gmac5_axi64_scfg_ram_cfg_vg + SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. + [30:30] read-write - sys_sysconsaif_syscfg40 - SYS SYSCONSAIF SYSCFG 40 - 0x28 + sys_sysconsaif_syscfg144 + SYS SYSCONSAIF SYSCFG 144 + 0x90 32 - u0_pll_wrap_pll1_frac - u0_pll_wrap_pll1_frac - [23:0] - read-write - - - u0_pll_wrap_pll1_gvco_bias - u0_pll_wrap_pll1_gvco_bias - [25:24] - read-write - - - u0_pll_wrap_pll1_lock - u0_pll_wrap_pll1_lock - [26:26] + u1_gmac5_axi64_mac_speed_0 + u1_gmac5_axi64_mac_speed_0 + [1:0] read-only - u0_pll_wrap_pll1_pd - u0_pll_wrap_pll1_pd - [27:27] - read-write - - - u0_pll_wrap_pll1_postdiv1 - u0_pll_wrap_pll1_postdiv1 - [29:28] + u1_gmac5_axi64_phy_intf_sel_i + Active PHY Selected | When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. | Values: 0x0:(GMII or MII), 0x01:RGMII, 0x2:SGMII, 0x3:TBI, 0x4:RMII, 0x5:RTBI, 0x6:SMII, 0x7:REVMII + [4:2] read-write + + + + sys_sysconsaif_syscfg148 + SYS SYSCONSAIF SYSCFG 148 + 0x94 + 32 + - u0_pll_wrap_pll1_postdiv2 - u0_pll_wrap_pll1_postdiv2 - [31:30] - read-write + u1_gmac5_axi64_ptp_timestamp_o_31_0 + u1_gmac5_axi64_ptp_timestamp_o_31_0 + [31:0] + read-only - sys_sysconsaif_syscfg44 - SYS SYSCONSAIF SYSCFG 44 - 0x2c + sys_sysconsaif_syscfg152 + SYS SYSCONSAIF SYSCFG 152 + 0x98 32 - u0_pll_wrap_pll1_prediv - u0_pll_wrap_pll1_prediv - [5:0] - read-write + u1_gmac5_axi64_ptp_timestamp_o_63_32 + u1_gmac5_axi64_ptp_timestamp_o_63_32 + [31:0] + read-only + + + + sys_sysconsaif_syscfg156 + SYS SYSCONSAIF SYSCFG 156 + 0x9c + 32 + - u0_pll_wrap_pll1_testen - u0_pll_wrap_pll1_testen - [6:6] - read-write + u1_i2c_ic_en + I2C interface enable. + [0:0] + read-only - u0_pll_wrap_pll1_testsel - u0_pll_wrap_pll1_testsel - [8:7] + u1_sdio_data_strobe_phase_ctrl + Data strobe delay chain select. + [5:1] read-write - u0_pll_wrap_pll2_cpi_bias - u0_pll_wrap_pll2_cpi_bias - [11:9] + u1_sdio_hbig_endian + AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface + [6:6] read-write - u0_pll_wrap_pll2_cpp_bias - u0_pll_wrap_pll2_cpp_bias - [14:12] + u1_sdio_m_hbig_endian + AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface + [7:7] read-write - u0_pll_wrap_pll2_dacpd - u0_pll_wrap_pll2_dacpd - [15:15] + u1_reset_ctrl_clr_reset_status + u1_reset_ctrl_clr_reset_status + [8:8] read-write - u0_pll_wrap_pll2_dsmpd - u0_pll_wrap_pll2_dsmpd - [16:16] - read-write + u1_reset_ctrl_pll_timecnt_finish + u1_reset_ctrl_pll_timecnt_finish + [9:9] + read-only - u0_pll_wrap_pll2_fbdiv - u0_pll_wrap_pll2_fbdiv - [28:17] + u1_reset_ctrl_rstn_sw + u1_reset_ctrl_rstn_sw + [10:10] read-write - - - - sys_sysconsaif_syscfg48 - SYS SYSCONSAIF SYSCFG 48 - 0x30 - 32 - - u0_pll_wrap_pll2_frac - u0_pll_wrap_pll2_frac - [23:0] - read-write + u1_reset_ctrl_sys_reset_status + u1_reset_ctrl_sys_reset_status + [14:11] + read-only - u0_pll_wrap_pll2_gvco_bias - u0_pll_wrap_pll2_gvco_bias - [25:24] - read-write + u2_i2c_ic_en + I2C interface enable. + [15:15] + read-only - u0_pll_wrap_pll2_lock - u0_pll_wrap_pll2_lock - [26:26] + u3_i2c_ic_en + I2C interface enable. + [16:16] read-only - u0_pll_wrap_pll2_pd - u0_pll_wrap_pll2_pd - [27:27] - read-write + u4_i2c_ic_en + I2C interface enable. + [17:17] + read-only - u0_pll_wrap_pll2_postdiv1 - u0_pll_wrap_pll2_postdiv1 - [29:28] - read-write + u5_i2c_ic_en + I2C interface enable. + [18:18] + read-only - u0_pll_wrap_pll2_postdiv2 - u0_pll_wrap_pll2_postdiv2 - [31:30] - read-write + u6_i2c_ic_en + I2C interface enable. + [19:19] + read-only + + + + syscon_1 + From syscon, peripheral generator + 0x13030000 + + 0 + 0x1000 + registers + + + + simple_mfd_0 + From simple-mfd, peripheral generator + 0x13030000 + + 0 + 0x1000 + registers + + + + starfive_jh7110_sys_pinctrl_0 + From starfive,jh7110-sys-pinctrl, peripheral generator + 0x13040000 + + 0 + 0x10000 + registers + + - sys_sysconsaif_syscfg52 - SYS SYSCONSAIF SYSCFG 52 - 0x34 + sys_iomux_cfgsaif_syscfg_fmux0 + SYS IOMUX CFG SAIF SYSCFG FMUX 0 + 0x0 32 - u0_pll_wrap_pll2_prediv - u0_pll_wrap_pll2_prediv + sys_iomux_gpo0_doen_cfg + The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - u0_pll_wrap_pll2_testen - u0_pll_wrap_pll2_testen - [6:6] - read-write - - - u0_pll_wrap_pll2_testsel - u0_pll_wrap_pll2_testsel - [8:7] + sys_iomux_gpo1_doen_cfg + The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u0_pll_wrap_syscfg_test_pll_mode - PLL test mode, only used for PLL BIST through jtag2apb - [9:9] + sys_iomux_gpo2_doen_cfg + The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - u0_saif_audio_sdin_mux_scfg_i2sdin_sel - u0_saif_audio_sdin_mux_scfg_i2sdin_sel - [17:10] + sys_iomux_gpo3_doen_cfg + The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write + + + + sys_iomux_cfgsaif_syscfg_fmux1 + SYS IOMUX CFG SAIF SYSCFG FMUX 1 + 0x4 + 32 + - u0_sft7110_noc_bus_clock_gating_off - u0_sft7110_noc_bus_clock_gating_off - [18:18] + sys_iomux_gpo4_doen_cfg + The selected OEN signal for GPIO4. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - u0_sft7110_noc_bus_oic_evemon_0_start - u0_sft7110_noc_bus_oic_evemon_0_start - [19:19] + sys_iomux_gpo5_doen_cfg + The selected OEN signal for GPIO5. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u0_sft7110_noc_bus_oic_evemon_0_trigger - u0_sft7110_noc_bus_oic_evemon_0_trigger - [20:20] - read-only - - - u0_sft7110_noc_bus_oic_evemon_1_start - u0_sft7110_noc_bus_oic_evemon_1_start - [21:21] + sys_iomux_gpo6_doen_cfg + The selected OEN signal for GPIO6. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - u0_sft7110_noc_bus_oic_evemon_1_trigger - u0_sft7110_noc_bus_oic_evemon_1_trigger - [22:22] - read-only - - - u0_sft7110_noc_bus_oic_evemon_2_start - u0_sft7110_noc_bus_oic_evemon_2_start - [23:23] + sys_iomux_gpo7_doen_cfg + The selected OEN signal for GPIO7. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write + + + + sys_iomux_cfgsaif_syscfg_fmux2 + SYS IOMUX CFG SAIF SYSCFG FMUX 2 + 0x8 + 32 + - u0_sft7110_noc_bus_oic_evemon_2_trigger - u0_sft7110_noc_bus_oic_evemon_2_trigger - [24:24] - read-only - - - u0_sft7110_noc_bus_oic_evemon_3_start - u0_sft7110_noc_bus_oic_evemon_3_start - [25:25] + sys_iomux_gpo8_doen_cfg + The selected OEN signal for GPIO8. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - u0_sft7110_noc_bus_oic_evemon_3_trigger - u0_sft7110_noc_bus_oic_evemon_3_trigger - [26:26] - read-only - - - u0_sft7110_noc_bus_oic_evemon_4_start - u0_sft7110_noc_bus_oic_evemon_4_start - [27:27] + sys_iomux_gpo9_doen_cfg + The selected OEN signal for GPIO9. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u0_sft7110_noc_bus_oic_evemon_4_trigger - u0_sft7110_noc_bus_oic_evemon_4_trigger - [28:28] - read-only - - - u0_sft7110_noc_bus_oic_evemon_5_start - u0_sft7110_noc_bus_oic_evemon_5_start - [29:29] + sys_iomux_gpo10_doen_cfg + The selected OEN signal for GPIO10. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - u0_sft7110_noc_bus_oic_evemon_5_trigger - u0_sft7110_noc_bus_oic_evemon_5_trigger - [30:30] - read-only - - - u0_sft7110_noc_bus_oic_evemon_6_start - u0_sft7110_noc_bus_oic_evemon_6_start - [31:31] + sys_iomux_gpo11_doen_cfg + The selected OEN signal for GPIO11. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write - sys_sysconsaif_syscfg56 - SYS SYSCONSAIF SYSCFG 56 - 0x38 + sys_iomux_cfgsaif_syscfg_fmux3 + SYS IOMUX CFG SAIF SYSCFG FMUX 3 + 0xc 32 - u0_sft7110_noc_bus_oic_evemon_6_trigger - u0_sft7110_noc_bus_oic_evemon_6_trigger - [0:0] - read-only - - - u0_sft7110_noc_bus_oic_evemon_7_start - u0_sft7110_noc_bus_oic_evemon_7_start - [15:15] + sys_iomux_gpo12_doen_cfg + The selected OEN signal for GPIO12. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - u0_sft7110_noc_bus_oic_evemon_7_trigger - u0_sft7110_noc_bus_oic_evemon_7_trigger - [16:16] - read-only - - - u0_sft7110_noc_bus_oic_evemon_8_start - u0_sft7110_noc_bus_oic_evemon_8_start - [17:17] + sys_iomux_gpo13_doen_cfg + The selected OEN signal for GPIO13. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u0_sft7110_noc_bus_oic_evemon_8_trigger - u0_sft7110_noc_bus_oic_evemon_8_trigger - [18:18] - read-only + sys_iomux_gpo14_doen_cfg + The selected OEN signal for GPIO14. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] + read-write - u0_sft7110_noc_bus_oic_ignore_modifiable_0 - u0_sft7110_noc_bus_oic_ignore_modifiable_0 - [5:5] + sys_iomux_gpo15_doen_cfg + The selected OEN signal for GPIO15. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write + + + + sys_iomux_cfgsaif_syscfg_fmux4 + SYS IOMUX CFG SAIF SYSCFG FMUX 4 + 0x10 + 32 + - u0_sft7110_noc_bus_oic_ignore_modifiable_1 - u0_sft7110_noc_bus_oic_ignore_modifiable_1 - [6:6] + sys_iomux_gpo16_doen_cfg + The selected OEN signal for GPIO16. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - u0_sft7110_noc_bus_oic_ignore_modifiable_2 - u0_sft7110_noc_bus_oic_ignore_modifiable_2 - [7:7] + sys_iomux_gpo17_doen_cfg + The selected OEN signal for GPIO17. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u0_sft7110_noc_bus_oic_ignore_modifiable_3 - u0_sft7110_noc_bus_oic_ignore_modifiable_3 - [8:8] + sys_iomux_gpo18_doen_cfg + The selected OEN signal for GPIO18. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - u0_sft7110_noc_bus_oic_ignore_modifiable_4 - u0_sft7110_noc_bus_oic_ignore_modifiable_4 - [9:9] + sys_iomux_gpo19_doen_cfg + The selected OEN signal for GPIO19. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write - sys_sysconsaif_syscfg60 - SYS SYSCONSAIF SYSCFG 60 - 0x3c + sys_iomux_cfgsaif_syscfg_fmux5 + SYS IOMUX CFG SAIF SYSCFG FMUX 5 + 0x14 32 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0 - [31:0] + sys_iomux_gpo20_doen_cfg + The selected OEN signal for GPIO20. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - - - - sys_sysconsaif_syscfg64 - SYS SYSCONSAIF SYSCFG 64 - 0x40 - 32 - - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1 - [31:0] + sys_iomux_gpo21_doen_cfg + The selected OEN signal for GPIO21. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - - - - sys_sysconsaif_syscfg68 - SYS SYSCONSAIF SYSCFG 68 - 0x44 - 32 - - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2 - [31:0] + sys_iomux_gpo22_doen_cfg + The selected OEN signal for GPIO22. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] + read-write + + + sys_iomux_gpo23_doen_cfg + The selected OEN signal for GPIO23. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write - sys_sysconsaif_syscfg72 - SYS SYSCONSAIF SYSCFG 72 - 0x48 + sys_iomux_cfgsaif_syscfg_fmux6 + SYS IOMUX CFG SAIF SYSCFG FMUX 6 + 0x18 32 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3 - [31:0] + sys_iomux_gpo24_doen_cfg + The selected OEN signal for GPIO24. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - - - - sys_sysconsaif_syscfg76 - SYS SYSCONSAIF SYSCFG 76 - 0x4c - 32 - - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4 - [31:0] + sys_iomux_gpo25_doen_cfg + The selected OEN signal for GPIO25. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - - - - sys_sysconsaif_syscfg80 - SYS SYSCONSAIF SYSCFG 80 - 0x50 - 32 - - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5 - [31:0] + sys_iomux_gpo26_doen_cfg + The selected OEN signal for GPIO26. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - - - - sys_sysconsaif_syscfg84 - SYS SYSCONSAIF SYSCFG 84 - 0x54 - 32 - - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6 - [31:0] + sys_iomux_gpo27_doen_cfg + The selected OEN signal for GPIO27. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write - sys_sysconsaif_syscfg88 - SYS SYSCONSAIF SYSCFG 88 - 0x58 + sys_iomux_cfgsaif_syscfg_fmux7 + SYS IOMUX CFG SAIF SYSCFG FMUX 7 + 0x1c 32 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7 - [31:0] + sys_iomux_gpo28_doen_cfg + The selected OEN signal for GPIO28. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - - - - sys_sysconsaif_syscfg92 - SYS SYSCONSAIF SYSCFG 92 - 0x5c - 32 - - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8 - [31:0] + sys_iomux_gpo29_doen_cfg + The selected OEN signal for GPIO29. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] + read-write + + + sys_iomux_gpo30_doen_cfg + The selected OEN signal for GPIO30. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] + read-write + + + sys_iomux_gpo31_doen_cfg + The selected OEN signal for GPIO31. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write - sys_sysconsaif_syscfg96 - SYS SYSCONSAIF SYSCFG 96 - 0x60 + sys_iomux_cfgsaif_syscfg_fmux8 + SYS IOMUX CFG SAIF SYSCFG FMUX 8 + 0x20 32 - u0_tdm16slot_clkpol - u0_tdm16slot_clkpol - [0:0] - read-only + sys_iomux_gpo32_doen_cfg + The selected OEN signal for GPIO32. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] + read-write - u0_tdm16slot_pcm_ms - u0_tdm16slot_pcm_ms - [1:1] - read-only + sys_iomux_gpo33_doen_cfg + The selected OEN signal for GPIO33. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] + read-write - u0_trace_mtx_scfg_c0_in0_ctl - u0_trace_mtx_scfg_c0_in0_ctl - [6:2] + sys_iomux_gpo34_doen_cfg + The selected OEN signal for GPIO34. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - u0_trace_mtx_scfg_c0_in1_ctl - u0_trace_mtx_scfg_c0_in1_ctl - [11:7] + sys_iomux_gpo35_doen_cfg + The selected OEN signal for GPIO35. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write + + + + sys_iomux_cfgsaif_syscfg_fmux9 + SYS IOMUX CFG SAIF SYSCFG FMUX 9 + 0x24 + 32 + - u0_trace_mtx_scfg_c1_in0_ctl - u0_trace_mtx_scfg_c1_in0_ctl - [16:12] + sys_iomux_gpo36_doen_cfg + The selected OEN signal for GPIO36. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - u0_trace_mtx_scfg_c1_in1_ctl - u0_trace_mtx_scfg_c1_in1_ctl - [21:17] + sys_iomux_gpo37_doen_cfg + The selected OEN signal for GPIO37. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u0_trace_mtx_scfg_c2_in0_ctl - u0_trace_mtx_scfg_c2_in0_ctl - [26:22] + sys_iomux_gpo38_doen_cfg + The selected OEN signal for GPIO38. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - u0_trace_mtx_scfg_c2_in1_ctl - u0_trace_mtx_scfg_c2_in1_ctl - [31:27] + sys_iomux_gpo39_doen_cfg + The selected OEN signal for GPIO39. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write - sys_sysconsaif_syscfg100 - SYS SYSCONSAIF SYSCFG 100 - 0x64 + sys_iomux_cfgsaif_syscfg_fmux10 + SYS IOMUX CFG SAIF SYSCFG FMUX 10 + 0x28 32 - u0_trace_mtx_scfg_c3_in0_ctl - u0_trace_mtx_scfg_c3_in0_ctl - [4:0] + sys_iomux_gpo40_doen_cfg + The selected OEN signal for GPIO40. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - u0_trace_mtx_scfg_c3_in1_ctl - u0_trace_mtx_scfg_c3_in1_ctl - [9:5] + sys_iomux_gpo41_doen_cfg + The selected OEN signal for GPIO41. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u0_trace_mtx_scfg_c4_in0_ctl - u0_trace_mtx_scfg_c4_in0_ctl - [14:10] + sys_iomux_gpo42_doen_cfg + The selected OEN signal for GPIO42. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - u0_trace_mtx_scfg_c4_in1_ctl - u0_trace_mtx_scfg_c4_in1_ctl - [19:15] + sys_iomux_gpo43_doen_cfg + The selected OEN signal for GPIO43. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write + + + + sys_iomux_cfgsaif_syscfg_fmux11 + SYS IOMUX CFG SAIF SYSCFG FMUX 11 + 0x2c + 32 + - u0_u7mc_sft7110_cease_from_tile_0 - u0_u7mc_sft7110_cease_from_tile_0 - [20:20] - read-only - - - u0_u7mc_sft7110_cease_from_tile_1 - u0_u7mc_sft7110_cease_from_tile_1 - [21:21] - read-only - - - u0_u7mc_sft7110_cease_from_tile_2 - u0_u7mc_sft7110_cease_from_tile_2 - [22:22] - read-only + sys_iomux_gpo44_doen_cfg + The selected OEN signal for GPIO44. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] + read-write - u0_u7mc_sft7110_cease_from_tile_3 - u0_u7mc_sft7110_cease_from_tile_3 - [23:23] - read-only + sys_iomux_gpo45_doen_cfg + The selected OEN signal for GPIO45. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] + read-write - u0_u7mc_sft7110_cease_from_tile_4 - u0_u7mc_sft7110_cease_from_tile_4 - [24:24] - read-only + sys_iomux_gpo46_doen_cfg + The selected OEN signal for GPIO46. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] + read-write - u0_u7mc_sft7110_halt_from_tile_0 - u0_u7mc_sft7110_halt_from_tile_0 - [25:25] - read-only + sys_iomux_gpo47_doen_cfg + The selected OEN signal for GPIO47. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] + read-write + + + + sys_iomux_cfgsaif_syscfg_fmux12 + SYS IOMUX CFG SAIF SYSCFG FMUX 12 + 0x30 + 32 + - u0_u7mc_sft7110_halt_from_tile_1 - u0_u7mc_sft7110_halt_from_tile_1 - [26:26] - read-only + sys_iomux_gpo48_doen_cfg + The selected OEN signal for GPIO48. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] + read-write - u0_u7mc_sft7110_halt_from_tile_2 - u0_u7mc_sft7110_halt_from_tile_2 - [27:27] - read-only + sys_iomux_gpo49_doen_cfg + The selected OEN signal for GPIO49. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] + read-write - u0_u7mc_sft7110_halt_from_tile_3 - u0_u7mc_sft7110_halt_from_tile_3 - [28:28] - read-only + sys_iomux_gpo50_doen_cfg + The selected OEN signal for GPIO50. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] + read-write - u0_u7mc_sft7110_halt_from_tile_4 - u0_u7mc_sft7110_halt_from_tile_4 - [29:29] - read-only + sys_iomux_gpo51_doen_cfg + The selected OEN signal for GPIO51. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] + read-write - sys_sysconsaif_syscfg104 - SYS SYSCONSAIF SYSCFG 104 - 0x68 + sys_iomux_cfgsaif_syscfg_fmux13 + SYS IOMUX CFG SAIF SYSCFG FMUX 13 + 0x34 32 - u0_u7mc_sft7110_reset_vector_1_31_0 - u0_u7mc_sft7110_reset_vector_1_31_0 - [31:0] + sys_iomux_gpo52_doen_cfg + The selected OEN signal for GPIO52. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - - - - sys_sysconsaif_syscfg108 - SYS SYSCONSAIF SYSCFG 108 - 0x6c - 32 - - u0_u7mc_sft7110_reset_vector_1_35_32 - u0_u7mc_sft7110_reset_vector_1_35_32 - [3:0] + sys_iomux_gpo53_doen_cfg + The selected OEN signal for GPIO53. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - - - - sys_sysconsaif_syscfg112 - SYS SYSCONSAIF SYSCFG 112 - 0x70 - 32 - - u0_u7mc_sft7110_reset_vector_2_31_0 - u0_u7mc_sft7110_reset_vector_2_31_0 - [31:0] + sys_iomux_gpo54_doen_cfg + The selected OEN signal for GPIO54. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - - - - sys_sysconsaif_syscfg116 - SYS SYSCONSAIF SYSCFG 116 - 0x74 - 32 - - u0_u7mc_sft7110_reset_vector_2_35_32 - u0_u7mc_sft7110_reset_vector_2_35_32 - [3:0] + sys_iomux_gpo55_doen_cfg + The selected OEN signal for GPIO55. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write - sys_sysconsaif_syscfg120 - SYS SYSCONSAIF SYSCFG 120 - 0x78 + sys_iomux_cfgsaif_syscfg_fmux14 + SYS IOMUX CFG SAIF SYSCFG FMUX 14 + 0x38 32 - u0_u7mc_sft7110_reset_vector_3_31_0 - u0_u7mc_sft7110_reset_vector_3_31_0 - [31:0] + sys_iomux_gpo56_doen_cfg + The selected OEN signal for GPIO56. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - - - - sys_sysconsaif_syscfg124 - SYS SYSCONSAIF SYSCFG 124 - 0x7c - 32 - - u0_u7mc_sft7110_reset_vector_3_35_32 - u0_u7mc_sft7110_reset_vector_3_35_32 - [3:0] + sys_iomux_gpo57_doen_cfg + The selected OEN signal for GPIO57. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - - - - sys_sysconsaif_syscfg128 - SYS SYSCONSAIF SYSCFG 128 - 0x80 - 32 - - u0_u7mc_sft7110_reset_vector_4_31_0 - u0_u7mc_sft7110_reset_vector_4_31_0 - [31:0] + sys_iomux_gpo58_doen_cfg + The selected OEN signal for GPIO58. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] + read-write + + + sys_iomux_gpo59_doen_cfg + The selected OEN signal for GPIO59. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write - sys_sysconsaif_syscfg136 - SYS SYSCONSAIF SYSCFG 136 - 0x88 + sys_iomux_cfgsaif_syscfg_fmux15 + SYS IOMUX CFG SAIF SYSCFG FMUX 15 + 0x3c 32 - u0_venc_intsram_sram_config_slp - SRAM/ROM configuration. SLP: sleep enable, high active, default is low. - [0:0] - read-write - - - u0_venc_intsram_sram_config_sram_config_sd - SRAM/ROM configuration. SD: shutdown enable, high active, default is low. - [1:1] + sys_iomux_gpo60_doen_cfg + The selected OEN signal for GPIO60. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - u0_venc_intsram_sram_config_rtsel - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. - [3:2] + sys_iomux_gpo61_doen_cfg + The selected OEN signal for GPIO61. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u0_venc_intsram_sram_config_ptsel - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. - [5:4] + sys_iomux_gpo62_doen_cfg + The selected OEN signal for GPIO62. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - u0_venc_intsram_sram_config_trb - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. - [7:6] + sys_iomux_gpo63_doen_cfg + The selected OEN signal for GPIO63. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write + + + + sys_iomux_cfgsaif_syscfg_fmux16 + SYS IOMUX CFG SAIF SYSCFG FMUX 16 + 0x40 + 32 + - u0_venc_intsram_sram_config_wtsel - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. - [9:8] + sys_iomux_gpo64_doen_cfg + The selected OEN signal for GPIO64. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - u0_venc_intsram_sram_config_vs - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. - [10:10] + sys_iomux_gpo65_doen_cfg + The selected OEN signal for GPIO65. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u0_venc_intsram_sram_config_vg - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. - [11:11] + sys_iomux_gpo66_doen_cfg + The selected OEN signal for GPIO66. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - u0_wave420l_i_ipu_current_buffer - This signal indicates which buffer is currently active so that the VPU can correctly use the ipu_end_of_row signal for row counter. - [14:12] + sys_iomux_gpo67_doen_cfg + The selected OEN signal for GPIO67. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write + + + + sys_iomux_cfgsaif_syscfg_fmux17 + SYS IOMUX CFG SAIF SYSCFG FMUX 17 + 0x44 + 32 + - u0_wave420l_i_ipu_end_of_row - This signal is flipped every time when the IPU completes writing a row. - [15:15] + sys_iomux_gpo68_doen_cfg + The selected OEN signal for GPIO68. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - u0_wave420l_i_ipu_new_frame - This signal is flipped every time when the IPU completes writing a new frame. - [16:16] + sys_iomux_gpo69_doen_cfg + The selected OEN signal for GPIO69. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u0_wave420l_o_vpu_idle - VPU monitoring signal. This signal gives out an opposite value of VPU_BUSY register. - [17:17] - read-only - - - u1_can_ctrl_can_fd_enable - u1_can_ctrl_can_fd_enable - [18:18] + sys_iomux_gpo70_doen_cfg + The selected OEN signal for GPIO70. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - u1_can_ctrl_host_ecc_disable - u1_can_ctrl_host_ecc_disable - [19:19] + sys_iomux_gpo71_doen_cfg + The selected OEN signal for GPIO71. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write - sys_sysconsaif_syscfg140 - SYS SYSCONSAIF SYSCFG 140 - 0x8c + sys_iomux_cfgsaif_syscfg_fmux18 + SYS IOMUX CFG SAIF SYSCFG FMUX 18 + 0x48 32 - u1_can_ctrl_host_if - u1_can_ctrl_host_if - [18:0] - read-only - - - u1_gmac5_axi64_scfg_ram_cfg_slp - SRAM/ROM configuration. SLP: sleep enable, high active, default is low. - [19:19] + sys_iomux_gpo72_doen_cfg + The selected OEN signal for GPIO72. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - u1_gmac5_axi64_scfg_ram_cfg_sram_config_sd - SRAM/ROM configuration. SD: shutdown enable, high active, default is low. - [20:20] + sys_iomux_gpo73_doen_cfg + The selected OEN signal for GPIO73. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u1_gmac5_axi64_scfg_ram_cfg_rtsel - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. - [22:21] + sys_iomux_gpo74_doen_cfg + The selected OEN signal for GPIO74. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - u1_gmac5_axi64_scfg_ram_cfg_ptsel - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. - [24:23] + sys_iomux_gpo75_doen_cfg + The selected OEN signal for GPIO75. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write + + + + sys_iomux_cfgsaif_syscfg_fmux19 + SYS IOMUX CFG SAIF SYSCFG FMUX 19 + 0x4c + 32 + - u1_gmac5_axi64_scfg_ram_cfg_trb - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. - [26:25] + sys_iomux_gpo76_doen_cfg + The selected OEN signal for GPIO76. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - u1_gmac5_axi64_scfg_ram_cfg_wtsel - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. - [28:27] + sys_iomux_gpo77_doen_cfg + The selected OEN signal for GPIO77. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u1_gmac5_axi64_scfg_ram_cfg_vs - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. - [29:29] + sys_iomux_gpo78_doen_cfg + The selected OEN signal for GPIO78. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - u1_gmac5_axi64_scfg_ram_cfg_vg - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. - [30:30] + sys_iomux_gpo79_doen_cfg + The selected OEN signal for GPIO79. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write - sys_sysconsaif_syscfg144 - SYS SYSCONSAIF SYSCFG 144 - 0x90 + sys_iomux_cfgsaif_syscfg_fmux20 + SYS IOMUX CFG SAIF SYSCFG FMUX 20 + 0x50 32 - u1_gmac5_axi64_mac_speed_0 - u1_gmac5_axi64_mac_speed_0 - [1:0] - read-only + sys_iomux_gpo80_doen_cfg + The selected OEN signal for GPIO80. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] + read-write - u1_gmac5_axi64_phy_intf_sel_i - Active PHY Selected | When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. | Values: 0x0:(GMII or MII), 0x01:RGMII, 0x2:SGMII, 0x3:TBI, 0x4:RMII, 0x5:RTBI, 0x6:SMII, 0x7:REVMII - [4:2] + sys_iomux_gpo81_doen_cfg + The selected OEN signal for GPIO81. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - - - - sys_sysconsaif_syscfg148 - SYS SYSCONSAIF SYSCFG 148 - 0x94 - 32 - - u1_gmac5_axi64_ptp_timestamp_o_31_0 - u1_gmac5_axi64_ptp_timestamp_o_31_0 - [31:0] - read-only + sys_iomux_gpo82_doen_cfg + The selected OEN signal for GPIO82. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] + read-write - - - - sys_sysconsaif_syscfg152 - SYS SYSCONSAIF SYSCFG 152 - 0x98 - 32 - - u1_gmac5_axi64_ptp_timestamp_o_63_32 - u1_gmac5_axi64_ptp_timestamp_o_63_32 - [31:0] - read-only + sys_iomux_gpo83_doen_cfg + The selected OEN signal for GPIO83. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] + read-write - sys_sysconsaif_syscfg156 - SYS SYSCONSAIF SYSCFG 156 - 0x9c + sys_iomux_cfgsaif_syscfg_fmux21 + SYS IOMUX CFG SAIF SYSCFG FMUX 21 + 0x54 32 - u1_i2c_ic_en - I2C interface enable. - [0:0] - read-only - - - u1_sdio_data_strobe_phase_ctrl - Data strobe delay chain select. - [5:1] + sys_iomux_gpo84_doen_cfg + The selected OEN signal for GPIO84. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] read-write - u1_sdio_hbig_endian - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface - [6:6] + sys_iomux_gpo85_doen_cfg + The selected OEN signal for GPIO85. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u1_sdio_m_hbig_endian - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface - [7:7] + sys_iomux_gpo86_doen_cfg + The selected OEN signal for GPIO86. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] read-write - u1_reset_ctrl_clr_reset_status - u1_reset_ctrl_clr_reset_status - [8:8] + sys_iomux_gpo87_doen_cfg + The selected OEN signal for GPIO87. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] read-write + + + + sys_iomux_cfgsaif_syscfg_fmux22 + SYS IOMUX CFG SAIF SYSCFG FMUX 22 + 0x58 + 32 + - u1_reset_ctrl_pll_timecnt_finish - u1_reset_ctrl_pll_timecnt_finish - [9:9] - read-only + sys_iomux_gpo88_doen_cfg + The selected OEN signal for GPIO88. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] + read-write - u1_reset_ctrl_rstn_sw - u1_reset_ctrl_rstn_sw - [10:10] + sys_iomux_gpo89_doen_cfg + The selected OEN signal for GPIO89. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] read-write - u1_reset_ctrl_sys_reset_status - u1_reset_ctrl_sys_reset_status - [14:11] - read-only + sys_iomux_gpo90_doen_cfg + The selected OEN signal for GPIO90. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] + read-write - u2_i2c_ic_en - I2C interface enable. - [15:15] - read-only + sys_iomux_gpo91_doen_cfg + The selected OEN signal for GPIO91. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] + read-write + + + + sys_iomux_cfgsaif_syscfg_fmux23 + SYS IOMUX CFG SAIF SYSCFG FMUX 23 + 0x5c + 32 + - u3_i2c_ic_en - I2C interface enable. - [16:16] - read-only + sys_iomux_gpo92_doen_cfg + The selected OEN signal for GPIO92. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [5:0] + read-write - u4_i2c_ic_en - I2C interface enable. - [17:17] - read-only + sys_iomux_gpo93_doen_cfg + The selected OEN signal for GPIO93. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [13:8] + read-write - u5_i2c_ic_en - I2C interface enable. - [18:18] - read-only + sys_iomux_gpo94_doen_cfg + The selected OEN signal for GPIO94. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [21:16] + read-write - u6_i2c_ic_en - I2C interface enable. - [19:19] - read-only + sys_iomux_gpo95_doen_cfg + The selected OEN signal for GPIO95. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + [29:24] + read-write - - - - syscon_1 - From syscon, peripheral generator - 0x13030000 - - 0 - 0x1000 - registers - - - - simple_mfd_0 - From simple-mfd, peripheral generator - 0x13030000 - - 0 - 0x1000 - registers - - - - starfive_jh7110_sys_pinctrl_0 - From starfive,jh7110-sys-pinctrl, peripheral generator - 0x13040000 - - 0 - 0x10000 - registers - - - sys_iomux_cfgsaif_syscfg_fmux0 - SYS IOMUX CFG SAIF SYSCFG FMUX 0 - 0x0 + sys_iomux_cfgsaif_syscfg_fmux24 + SYS IOMUX CFG SAIF SYSCFG FMUX 24 + 0x60 32 - sys_iomux_gpo0_doen_cfg - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo96_doen_cfg + The selected OEN signal for GPIO96. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo1_doen_cfg - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo97_doen_cfg + The selected OEN signal for GPIO97. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo2_doen_cfg - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo98_doen_cfg + The selected OEN signal for GPIO98. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo3_doen_cfg - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo99_doen_cfg + The selected OEN signal for GPIO99. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux1 - SYS IOMUX CFG SAIF SYSCFG FMUX 1 - 0x4 + sys_iomux_cfgsaif_syscfg_fmux25 + SYS IOMUX CFG SAIF SYSCFG FMUX 25 + 0x64 32 - sys_iomux_gpo4_doen_cfg - The selected OEN signal for GPIO4. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo100_doen_cfg + The selected OEN signal for GPIO100. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo5_doen_cfg - The selected OEN signal for GPIO5. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo101_doen_cfg + The selected OEN signal for GPIO101. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo6_doen_cfg - The selected OEN signal for GPIO6. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo102_doen_cfg + The selected OEN signal for GPIO102. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo7_doen_cfg - The selected OEN signal for GPIO7. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo103_doen_cfg + The selected OEN signal for GPIO103. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux2 - SYS IOMUX CFG SAIF SYSCFG FMUX 2 - 0x8 + sys_iomux_cfgsaif_syscfg_fmux26 + SYS IOMUX CFG SAIF SYSCFG FMUX 26 + 0x68 32 - sys_iomux_gpo8_doen_cfg - The selected OEN signal for GPIO8. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo104_doen_cfg + The selected OEN signal for GPIO104. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo9_doen_cfg - The selected OEN signal for GPIO9. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo105_doen_cfg + The selected OEN signal for GPIO105. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo10_doen_cfg - The selected OEN signal for GPIO10. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo106_doen_cfg + The selected OEN signal for GPIO106. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo11_doen_cfg - The selected OEN signal for GPIO11. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo107_doen_cfg + The selected OEN signal for GPIO107. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux3 - SYS IOMUX CFG SAIF SYSCFG FMUX 3 - 0xc + sys_iomux_cfgsaif_syscfg_fmux27 + SYS IOMUX CFG SAIF SYSCFG FMUX 27 + 0x6c 32 - sys_iomux_gpo12_doen_cfg - The selected OEN signal for GPIO12. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo108_doen_cfg + The selected OEN signal for GPIO108. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo13_doen_cfg - The selected OEN signal for GPIO13. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo109_doen_cfg + The selected OEN signal for GPIO109. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo14_doen_cfg - The selected OEN signal for GPIO14. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo110_doen_cfg + The selected OEN signal for GPIO110. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo15_doen_cfg - The selected OEN signal for GPIO15. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo111_doen_cfg + The selected OEN signal for GPIO111. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux4 - SYS IOMUX CFG SAIF SYSCFG FMUX 4 - 0x10 + sys_iomux_cfgsaif_syscfg_fmux28 + SYS IOMUX CFG SAIF SYSCFG FMUX 28 + 0x70 32 - sys_iomux_gpo16_doen_cfg - The selected OEN signal for GPIO16. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo112_doen_cfg + The selected OEN signal for GPIO112. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo17_doen_cfg - The selected OEN signal for GPIO17. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo113_doen_cfg + The selected OEN signal for GPIO113. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo18_doen_cfg - The selected OEN signal for GPIO18. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo114_doen_cfg + The selected OEN signal for GPIO114. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo19_doen_cfg - The selected OEN signal for GPIO19. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo115_doen_cfg + The selected OEN signal for GPIO115. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux5 - SYS IOMUX CFG SAIF SYSCFG FMUX 5 - 0x14 + sys_iomux_cfgsaif_syscfg_fmux29 + SYS IOMUX CFG SAIF SYSCFG FMUX 29 + 0x74 32 - sys_iomux_gpo20_doen_cfg - The selected OEN signal for GPIO20. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo116_doen_cfg + The selected OEN signal for GPIO116. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo21_doen_cfg - The selected OEN signal for GPIO21. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo117_doen_cfg + The selected OEN signal for GPIO117. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo22_doen_cfg - The selected OEN signal for GPIO22. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo118_doen_cfg + The selected OEN signal for GPIO118. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo23_doen_cfg - The selected OEN signal for GPIO23. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo119_doen_cfg + The selected OEN signal for GPIO119. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux6 - SYS IOMUX CFG SAIF SYSCFG FMUX 6 - 0x18 + sys_iomux_cfgsaif_syscfg_fmux30 + SYS IOMUX CFG SAIF SYSCFG FMUX 30 + 0x78 32 - sys_iomux_gpo24_doen_cfg - The selected OEN signal for GPIO24. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo120_doen_cfg + The selected OEN signal for GPIO120. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo25_doen_cfg - The selected OEN signal for GPIO25. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo121_doen_cfg + The selected OEN signal for GPIO121. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo26_doen_cfg - The selected OEN signal for GPIO26. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo122_doen_cfg + The selected OEN signal for GPIO122. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo27_doen_cfg - The selected OEN signal for GPIO27. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo123_doen_cfg + The selected OEN signal for GPIO123. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux7 - SYS IOMUX CFG SAIF SYSCFG FMUX 7 - 0x1c + sys_iomux_cfgsaif_syscfg_fmux31 + SYS IOMUX CFG SAIF SYSCFG FMUX 31 + 0x7c 32 - sys_iomux_gpo28_doen_cfg - The selected OEN signal for GPIO28. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo124_doen_cfg + The selected OEN signal for GPIO124. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo29_doen_cfg - The selected OEN signal for GPIO29. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo125_doen_cfg + The selected OEN signal for GPIO125. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo30_doen_cfg - The selected OEN signal for GPIO30. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo126_doen_cfg + The selected OEN signal for GPIO126. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo31_doen_cfg - The selected OEN signal for GPIO31. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo127_doen_cfg + The selected OEN signal for GPIO127. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux8 - SYS IOMUX CFG SAIF SYSCFG FMUX 8 - 0x20 + sys_iomux_cfgsaif_syscfg_fmux32 + SYS IOMUX CFG SAIF SYSCFG FMUX 32 + 0x80 32 - sys_iomux_gpo32_doen_cfg - The selected OEN signal for GPIO32. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo128_doen_cfg + The selected OEN signal for GPIO128. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo33_doen_cfg - The selected OEN signal for GPIO33. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo129_doen_cfg + The selected OEN signal for GPIO129. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo34_doen_cfg - The selected OEN signal for GPIO34. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo130_doen_cfg + The selected OEN signal for GPIO130. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo35_doen_cfg - The selected OEN signal for GPIO35. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo131_doen_cfg + The selected OEN signal for GPIO131. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux9 - SYS IOMUX CFG SAIF SYSCFG FMUX 9 - 0x24 + sys_iomux_cfgsaif_syscfg_fmux33 + SYS IOMUX CFG SAIF SYSCFG FMUX 33 + 0x84 32 - sys_iomux_gpo36_doen_cfg - The selected OEN signal for GPIO36. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo132_doen_cfg + The selected OEN signal for GPIO132. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo37_doen_cfg - The selected OEN signal for GPIO37. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo133_doen_cfg + The selected OEN signal for GPIO133. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo38_doen_cfg - The selected OEN signal for GPIO38. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo134_doen_cfg + The selected OEN signal for GPIO134. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo39_doen_cfg - The selected OEN signal for GPIO39. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo135_doen_cfg + The selected OEN signal for GPIO135. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux10 - SYS IOMUX CFG SAIF SYSCFG FMUX 10 - 0x28 + sys_iomux_cfgsaif_syscfg_fmux34 + SYS IOMUX CFG SAIF SYSCFG FMUX 34 + 0x88 32 - sys_iomux_gpo40_doen_cfg - The selected OEN signal for GPIO40. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo136_doen_cfg + The selected OEN signal for GPIO136. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo41_doen_cfg - The selected OEN signal for GPIO41. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo137_doen_cfg + The selected OEN signal for GPIO137. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo42_doen_cfg - The selected OEN signal for GPIO42. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo138_doen_cfg + The selected OEN signal for GPIO138. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo43_doen_cfg - The selected OEN signal for GPIO43. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo139_doen_cfg + The selected OEN signal for GPIO139. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux11 - SYS IOMUX CFG SAIF SYSCFG FMUX 11 - 0x2c + sys_iomux_cfgsaif_syscfg_fmux35 + SYS IOMUX CFG SAIF SYSCFG FMUX 35 + 0x8c 32 - sys_iomux_gpo44_doen_cfg - The selected OEN signal for GPIO44. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo140_doen_cfg + The selected OEN signal for GPIO140. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo45_doen_cfg - The selected OEN signal for GPIO45. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo141_doen_cfg + The selected OEN signal for GPIO141. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo46_doen_cfg - The selected OEN signal for GPIO46. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo142_doen_cfg + The selected OEN signal for GPIO142. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo47_doen_cfg - The selected OEN signal for GPIO47. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo143_doen_cfg + The selected OEN signal for GPIO143. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux12 - SYS IOMUX CFG SAIF SYSCFG FMUX 12 - 0x30 + sys_iomux_cfgsaif_syscfg_fmux36 + SYS IOMUX CFG SAIF SYSCFG FMUX 36 + 0x90 32 - sys_iomux_gpo48_doen_cfg - The selected OEN signal for GPIO48. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo144_doen_cfg + The selected OEN signal for GPIO144. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo49_doen_cfg - The selected OEN signal for GPIO49. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo145_doen_cfg + The selected OEN signal for GPIO145. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo50_doen_cfg - The selected OEN signal for GPIO50. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo146_doen_cfg + The selected OEN signal for GPIO146. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo51_doen_cfg - The selected OEN signal for GPIO51. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo147_doen_cfg + The selected OEN signal for GPIO147. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux13 - SYS IOMUX CFG SAIF SYSCFG FMUX 13 - 0x34 + sys_iomux_cfgsaif_syscfg_fmux37 + SYS IOMUX CFG SAIF SYSCFG FMUX 37 + 0x94 32 - sys_iomux_gpo52_doen_cfg - The selected OEN signal for GPIO52. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo148_doen_cfg + The selected OEN signal for GPIO148. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo53_doen_cfg - The selected OEN signal for GPIO53. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo149_doen_cfg + The selected OEN signal for GPIO149. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo54_doen_cfg - The selected OEN signal for GPIO54. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo150_doen_cfg + The selected OEN signal for GPIO150. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo55_doen_cfg - The selected OEN signal for GPIO55. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo151_doen_cfg + The selected OEN signal for GPIO151. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux14 - SYS IOMUX CFG SAIF SYSCFG FMUX 14 - 0x38 + sys_iomux_cfgsaif_syscfg_fmux38 + SYS IOMUX CFG SAIF SYSCFG FMUX 38 + 0x98 32 - sys_iomux_gpo56_doen_cfg - The selected OEN signal for GPIO56. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo152_doen_cfg + The selected OEN signal for GPIO152. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo57_doen_cfg - The selected OEN signal for GPIO57. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo153_doen_cfg + The selected OEN signal for GPIO153. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo58_doen_cfg - The selected OEN signal for GPIO58. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo154_doen_cfg + The selected OEN signal for GPIO154. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo59_doen_cfg - The selected OEN signal for GPIO59. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo155_doen_cfg + The selected OEN signal for GPIO155. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux15 - SYS IOMUX CFG SAIF SYSCFG FMUX 15 - 0x3c + sys_iomux_cfgsaif_syscfg_fmux39 + SYS IOMUX CFG SAIF SYSCFG FMUX 39 + 0x9c 32 - sys_iomux_gpo60_doen_cfg - The selected OEN signal for GPIO60. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo156_doen_cfg + The selected OEN signal for GPIO156. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo61_doen_cfg - The selected OEN signal for GPIO61. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo157_doen_cfg + The selected OEN signal for GPIO157. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo62_doen_cfg - The selected OEN signal for GPIO62. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo158_doen_cfg + The selected OEN signal for GPIO158. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo63_doen_cfg - The selected OEN signal for GPIO63. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo159_doen_cfg + The selected OEN signal for GPIO159. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux16 - SYS IOMUX CFG SAIF SYSCFG FMUX 16 - 0x40 + sys_iomux_cfgsaif_syscfg_fmux40 + SYS IOMUX CFG SAIF SYSCFG FMUX 40 + 0xa0 32 - sys_iomux_gpo64_doen_cfg - The selected OEN signal for GPIO64. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo160_doen_cfg + The selected OEN signal for GPIO160. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo65_doen_cfg - The selected OEN signal for GPIO65. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo161_doen_cfg + The selected OEN signal for GPIO161. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo66_doen_cfg - The selected OEN signal for GPIO66. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo162_doen_cfg + The selected OEN signal for GPIO162. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo67_doen_cfg - The selected OEN signal for GPIO67. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo163_doen_cfg + The selected OEN signal for GPIO163. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux17 - SYS IOMUX CFG SAIF SYSCFG FMUX 17 - 0x44 + sys_iomux_cfgsaif_syscfg_fmux41 + SYS IOMUX CFG SAIF SYSCFG FMUX 41 + 0xa4 32 - sys_iomux_gpo68_doen_cfg - The selected OEN signal for GPIO68. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo164_doen_cfg + The selected OEN signal for GPIO164. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo69_doen_cfg - The selected OEN signal for GPIO69. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo165_doen_cfg + The selected OEN signal for GPIO165. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo70_doen_cfg - The selected OEN signal for GPIO70. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo166_doen_cfg + The selected OEN signal for GPIO166. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo71_doen_cfg - The selected OEN signal for GPIO71. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo167_doen_cfg + The selected OEN signal for GPIO167. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux18 - SYS IOMUX CFG SAIF SYSCFG FMUX 18 - 0x48 + sys_iomux_cfgsaif_syscfg_fmux42 + SYS IOMUX CFG SAIF SYSCFG FMUX 42 + 0xa8 32 - sys_iomux_gpo72_doen_cfg - The selected OEN signal for GPIO72. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo168_doen_cfg + The selected OEN signal for GPIO168. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo73_doen_cfg - The selected OEN signal for GPIO73. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo169_doen_cfg + The selected OEN signal for GPIO169. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo74_doen_cfg - The selected OEN signal for GPIO74. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo170_doen_cfg + The selected OEN signal for GPIO170. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo75_doen_cfg - The selected OEN signal for GPIO75. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo171_doen_cfg + The selected OEN signal for GPIO171. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux19 - SYS IOMUX CFG SAIF SYSCFG FMUX 19 - 0x4c + sys_iomux_cfgsaif_syscfg_fmux43 + SYS IOMUX CFG SAIF SYSCFG FMUX 43 + 0xac 32 - sys_iomux_gpo76_doen_cfg - The selected OEN signal for GPIO76. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo172_doen_cfg + The selected OEN signal for GPIO172. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo77_doen_cfg - The selected OEN signal for GPIO77. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo173_doen_cfg + The selected OEN signal for GPIO173. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo78_doen_cfg - The selected OEN signal for GPIO78. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo174_doen_cfg + The selected OEN signal for GPIO174. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo79_doen_cfg - The selected OEN signal for GPIO79. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo175_doen_cfg + The selected OEN signal for GPIO175. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux20 - SYS IOMUX CFG SAIF SYSCFG FMUX 20 - 0x50 + sys_iomux_cfgsaif_syscfg_fmux44 + SYS IOMUX CFG SAIF SYSCFG FMUX 44 + 0xb0 32 - sys_iomux_gpo80_doen_cfg - The selected OEN signal for GPIO80. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo176_doen_cfg + The selected OEN signal for GPIO176. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo81_doen_cfg - The selected OEN signal for GPIO81. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo177_doen_cfg + The selected OEN signal for GPIO177. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo82_doen_cfg - The selected OEN signal for GPIO82. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo178_doen_cfg + The selected OEN signal for GPIO178. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo83_doen_cfg - The selected OEN signal for GPIO83. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo179_doen_cfg + The selected OEN signal for GPIO179. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux21 - SYS IOMUX CFG SAIF SYSCFG FMUX 21 - 0x54 + sys_iomux_cfgsaif_syscfg_fmux45 + SYS IOMUX CFG SAIF SYSCFG FMUX 45 + 0xb4 32 - sys_iomux_gpo84_doen_cfg - The selected OEN signal for GPIO84. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo180_doen_cfg + The selected OEN signal for GPIO180. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo85_doen_cfg - The selected OEN signal for GPIO85. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo181_doen_cfg + The selected OEN signal for GPIO181. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo86_doen_cfg - The selected OEN signal for GPIO86. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo182_doen_cfg + The selected OEN signal for GPIO182. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo87_doen_cfg - The selected OEN signal for GPIO87. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo183_doen_cfg + The selected OEN signal for GPIO183. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux22 - SYS IOMUX CFG SAIF SYSCFG FMUX 22 - 0x58 + sys_iomux_cfgsaif_syscfg_fmux46 + SYS IOMUX CFG SAIF SYSCFG FMUX 46 + 0xb8 32 - sys_iomux_gpo88_doen_cfg - The selected OEN signal for GPIO88. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo184_doen_cfg + The selected OEN signal for GPIO184. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo89_doen_cfg - The selected OEN signal for GPIO89. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo185_doen_cfg + The selected OEN signal for GPIO185. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo90_doen_cfg - The selected OEN signal for GPIO90. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo186_doen_cfg + The selected OEN signal for GPIO186. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo91_doen_cfg - The selected OEN signal for GPIO91. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo187_doen_cfg + The selected OEN signal for GPIO187. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux23 - SYS IOMUX CFG SAIF SYSCFG FMUX 23 - 0x5c + sys_iomux_cfgsaif_syscfg_fmux47 + SYS IOMUX CFG SAIF SYSCFG FMUX 47 + 0xbc 32 - sys_iomux_gpo92_doen_cfg - The selected OEN signal for GPIO92. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo188_doen_cfg + The selected OEN signal for GPIO188. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo93_doen_cfg - The selected OEN signal for GPIO93. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo189_doen_cfg + The selected OEN signal for GPIO189. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo94_doen_cfg - The selected OEN signal for GPIO94. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo190_doen_cfg + The selected OEN signal for GPIO190. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo95_doen_cfg - The selected OEN signal for GPIO95. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo191_doen_cfg + The selected OEN signal for GPIO191. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux24 - SYS IOMUX CFG SAIF SYSCFG FMUX 24 - 0x60 + sys_iomux_cfgsaif_syscfg_fmux48 + SYS IOMUX CFG SAIF SYSCFG FMUX 48 + 0xc0 32 - sys_iomux_gpo96_doen_cfg - The selected OEN signal for GPIO96. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo192_doen_cfg + The selected OEN signal for GPIO192. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo97_doen_cfg - The selected OEN signal for GPIO97. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo193_doen_cfg + The selected OEN signal for GPIO193. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo98_doen_cfg - The selected OEN signal for GPIO98. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo194_doen_cfg + The selected OEN signal for GPIO194. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo99_doen_cfg - The selected OEN signal for GPIO99. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo195_doen_cfg + The selected OEN signal for GPIO195. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux25 - SYS IOMUX CFG SAIF SYSCFG FMUX 25 - 0x64 + sys_iomux_cfgsaif_syscfg_fmux49 + SYS IOMUX CFG SAIF SYSCFG FMUX 49 + 0xc4 32 - sys_iomux_gpo100_doen_cfg - The selected OEN signal for GPIO100. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo196_doen_cfg + The selected OEN signal for GPIO196. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo101_doen_cfg - The selected OEN signal for GPIO101. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo197_doen_cfg + The selected OEN signal for GPIO197. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo102_doen_cfg - The selected OEN signal for GPIO102. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo198_doen_cfg + The selected OEN signal for GPIO198. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo103_doen_cfg - The selected OEN signal for GPIO103. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo199_doen_cfg + The selected OEN signal for GPIO199. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux26 - SYS IOMUX CFG SAIF SYSCFG FMUX 26 - 0x68 + sys_iomux_cfgsaif_syscfg_fmux50 + SYS IOMUX CFG SAIF SYSCFG FMUX 50 + 0xc8 32 - sys_iomux_gpo104_doen_cfg - The selected OEN signal for GPIO104. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo200_doen_cfg + The selected OEN signal for GPIO200. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo105_doen_cfg - The selected OEN signal for GPIO105. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo201_doen_cfg + The selected OEN signal for GPIO201. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo106_doen_cfg - The selected OEN signal for GPIO106. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo202_doen_cfg + The selected OEN signal for GPIO202. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo107_doen_cfg - The selected OEN signal for GPIO107. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo203_doen_cfg + The selected OEN signal for GPIO203. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux27 - SYS IOMUX CFG SAIF SYSCFG FMUX 27 - 0x6c + sys_iomux_cfgsaif_syscfg_fmux51 + SYS IOMUX CFG SAIF SYSCFG FMUX 51 + 0xcc 32 - sys_iomux_gpo108_doen_cfg - The selected OEN signal for GPIO108. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo204_doen_cfg + The selected OEN signal for GPIO204. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo109_doen_cfg - The selected OEN signal for GPIO109. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo205_doen_cfg + The selected OEN signal for GPIO205. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo110_doen_cfg - The selected OEN signal for GPIO110. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo206_doen_cfg + The selected OEN signal for GPIO206. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo111_doen_cfg - The selected OEN signal for GPIO111. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo207_doen_cfg + The selected OEN signal for GPIO207. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux28 - SYS IOMUX CFG SAIF SYSCFG FMUX 28 - 0x70 + sys_iomux_cfgsaif_syscfg_fmux52 + SYS IOMUX CFG SAIF SYSCFG FMUX 52 + 0xd0 32 - sys_iomux_gpo112_doen_cfg - The selected OEN signal for GPIO112. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo208_doen_cfg + The selected OEN signal for GPIO208. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo113_doen_cfg - The selected OEN signal for GPIO113. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo209_doen_cfg + The selected OEN signal for GPIO209. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo114_doen_cfg - The selected OEN signal for GPIO114. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo210_doen_cfg + The selected OEN signal for GPIO210. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo115_doen_cfg - The selected OEN signal for GPIO115. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo211_doen_cfg + The selected OEN signal for GPIO211. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux29 - SYS IOMUX CFG SAIF SYSCFG FMUX 29 - 0x74 + sys_iomux_cfgsaif_syscfg_fmux53 + SYS IOMUX CFG SAIF SYSCFG FMUX 53 + 0xd4 32 - sys_iomux_gpo116_doen_cfg - The selected OEN signal for GPIO116. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo212_doen_cfg + The selected OEN signal for GPIO212. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo117_doen_cfg - The selected OEN signal for GPIO117. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo213_doen_cfg + The selected OEN signal for GPIO213. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo118_doen_cfg - The selected OEN signal for GPIO118. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo214_doen_cfg + The selected OEN signal for GPIO214. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo119_doen_cfg - The selected OEN signal for GPIO119. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo215_doen_cfg + The selected OEN signal for GPIO215. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux30 - SYS IOMUX CFG SAIF SYSCFG FMUX 30 - 0x78 + sys_iomux_cfgsaif_syscfg_fmux54 + SYS IOMUX CFG SAIF SYSCFG FMUX 54 + 0xd8 32 - sys_iomux_gpo120_doen_cfg - The selected OEN signal for GPIO120. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo216_doen_cfg + The selected OEN signal for GPIO216. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write - sys_iomux_gpo121_doen_cfg - The selected OEN signal for GPIO121. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo217_doen_cfg + The selected OEN signal for GPIO217. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write - sys_iomux_gpo122_doen_cfg - The selected OEN signal for GPIO122. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo218_doen_cfg + The selected OEN signal for GPIO218. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write - sys_iomux_gpo123_doen_cfg - The selected OEN signal for GPIO123. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. + sys_iomux_gpo219_doen_cfg + The selected OEN signal for GPIO219. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write - sys_iomux_cfgsaif_syscfg_fmux31 - SYS IOMUX CFG SAIF SYSCFG FMUX 31 - 0x7c + sys_iomux_cfgsaif_syscfg_ioirq55 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 55 + 0xdc 32 - sys_iomux_gpo124_doen_cfg - The selected OEN signal for GPIO124. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + sys_gpioen_0_reg + Enable GPIO IRQ function + [0:0] read-write + + + + sys_iomux_cfgsaif_syscfg_ioirq56 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 56 + 0xe0 + 32 + - sys_iomux_gpo125_doen_cfg - The selected OEN signal for GPIO125. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + sys_gpiois_0_reg + 1: Edge trigger, 0: Level trigger + [31:0] read-write + + + + sys_iomux_cfgsaif_syscfg_ioirq57 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 57 + 0xe4 + 32 + - sys_iomux_gpo126_doen_cfg - The selected OEN signal for GPIO126. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + sys_gpiois_1_reg + 1: Edge trigger, 0: Level trigger + [31:0] read-write + + + + sys_iomux_cfgsaif_syscfg_ioirq58 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 58 + 0xe8 + 32 + - sys_iomux_gpo127_doen_cfg - The selected OEN signal for GPIO127. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + sys_gpioic_0_reg + 1: Do not clear the register, 0: Clear the register + [31:0] read-write - sys_iomux_cfgsaif_syscfg_fmux32 - SYS IOMUX CFG SAIF SYSCFG FMUX 32 - 0x80 + sys_iomux_cfgsaif_syscfg_ioirq59 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 59 + 0xec 32 - sys_iomux_gpo128_doen_cfg - The selected OEN signal for GPIO128. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + sys_gpioic_1_reg + 1: Do not clear the register, 0: Clear the register + [31:0] read-write + + + + sys_iomux_cfgsaif_syscfg_ioirq60 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 60 + 0xf0 + 32 + - sys_iomux_gpo129_doen_cfg - The selected OEN signal for GPIO129. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + sys_gpioibe_0_reg + 1: Trigger on both edges, 0: Trigger on a single edge + [31:0] read-write + + + + sys_iomux_cfgsaif_syscfg_ioirq61 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 61 + 0xf4 + 32 + - sys_iomux_gpo130_doen_cfg - The selected OEN signal for GPIO130. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + sys_gpioibe_1_reg + 1: Trigger on both edges, 0: Trigger on a single edge + [31:0] read-write + + + + sys_iomux_cfgsaif_syscfg_ioirq62 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 62 + 0xf8 + 32 + - sys_iomux_gpo131_doen_cfg - The selected OEN signal for GPIO131. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + sys_gpioiev_0_reg + 1: Positive/Low, 0: Negative/High + [31:0] read-write - sys_iomux_cfgsaif_syscfg_fmux33 - SYS IOMUX CFG SAIF SYSCFG FMUX 33 - 0x84 + sys_iomux_cfgsaif_syscfg_ioirq63 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 63 + 0xfc 32 - sys_iomux_gpo132_doen_cfg - The selected OEN signal for GPIO132. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + sys_gpioiev_1_reg + 1: Positive/Low, 0: Negative/High + [31:0] read-write + + + + sys_iomux_cfgsaif_syscfg_ioirq64 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 64 + 0x100 + 32 + - sys_iomux_gpo133_doen_cfg - The selected OEN signal for GPIO133. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + sys_gpioie_0_reg + 1: Unmask, 0: Mask + [31:0] read-write + + + + sys_iomux_cfgsaif_syscfg_ioirq65 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 65 + 0x104 + 32 + - sys_iomux_gpo134_doen_cfg - The selected OEN signal for GPIO134. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + sys_gpioie_1_reg + 1: Unmask, 0: Mask + [31:0] read-write + + + + sys_iomux_cfgsaif_syscfg_ioirq66 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 66 + 0x108 + 32 + - sys_iomux_gpo135_doen_cfg - The selected OEN signal for GPIO135. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] - read-write + sys_gpioris_0_reg + Status of the edge trigger. The register can be cleared by writing gpio ic + [31:0] + read-only - sys_iomux_cfgsaif_syscfg_fmux34 - SYS IOMUX CFG SAIF SYSCFG FMUX 34 - 0x88 + sys_iomux_cfgsaif_syscfg_ioirq67 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 67 + 0x10c 32 - sys_iomux_gpo136_doen_cfg - The selected OEN signal for GPIO136. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] - read-write + sys_gpioris_1_reg + Status of the edge trigger. The register can be cleared by writing gpio ic + [31:0] + read-only + + + + sys_iomux_cfgsaif_syscfg_ioirq68 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 68 + 0x110 + 32 + - sys_iomux_gpo137_doen_cfg - The selected OEN signal for GPIO137. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] - read-write + sys_gpiomis_0_reg + The masked GPIO IRQ status + [31:0] + read-only + + + + sys_iomux_cfgsaif_syscfg_ioirq69 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 69 + 0x114 + 32 + - sys_iomux_gpo138_doen_cfg - The selected OEN signal for GPIO138. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] - read-write + sys_gpiomis_1_reg + The masked GPIO IRQ status + [31:0] + read-only + + + + sys_iomux_cfgsaif_syscfg_ioirq70 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 70 + 0x118 + 32 + - sys_iomux_gpo139_doen_cfg - The selected OEN signal for GPIO139. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] - read-write + sys_gpio_in_sync2_0_reg + Status of the gpio_in after synchronization + [31:0] + read-only - sys_iomux_cfgsaif_syscfg_fmux35 - SYS IOMUX CFG SAIF SYSCFG FMUX 35 - 0x8c + sys_iomux_cfgsaif_syscfg_ioirq71 + SYS IOMUX CFG SAIF SYSCFG IOIRQ 71 + 0x11c 32 - sys_iomux_gpo140_doen_cfg - The selected OEN signal for GPIO140. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] - read-write + sys_gpio_in_sync2_1_reg + Status of the gpio_in after synchronization + [31:0] + read-only + + + + sys_iomux_cfgsaif_syscfg288 + SYS IOMUX CFG SAIF SYSCFG 288 + 0x120 + 32 + - sys_iomux_gpo141_doen_cfg - The selected OEN signal for GPIO141. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio0_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - sys_iomux_gpo142_doen_cfg - The selected OEN signal for GPIO142. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio0_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] read-write - sys_iomux_gpo143_doen_cfg - The selected OEN signal for GPIO143. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio0_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] read-write - - - - sys_iomux_cfgsaif_syscfg_fmux36 - SYS IOMUX CFG SAIF SYSCFG FMUX 36 - 0x90 - 32 - - sys_iomux_gpo144_doen_cfg - The selected OEN signal for GPIO144. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + padcfg_pad_gpio0_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] read-write - sys_iomux_gpo145_doen_cfg - The selected OEN signal for GPIO145. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio0_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] read-write - sys_iomux_gpo146_doen_cfg - The selected OEN signal for GPIO146. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio0_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] read-write - sys_iomux_gpo147_doen_cfg - The selected OEN signal for GPIO147. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio0_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] read-write - sys_iomux_cfgsaif_syscfg_fmux37 - SYS IOMUX CFG SAIF SYSCFG FMUX 37 - 0x94 + sys_iomux_cfgsaif_syscfg292 + SYS IOMUX CFG SAIF SYSCFG 292 + 0x124 32 - sys_iomux_gpo148_doen_cfg - The selected OEN signal for GPIO148. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] - read-write - - - sys_iomux_gpo149_doen_cfg - The selected OEN signal for GPIO149. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio1_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - sys_iomux_gpo150_doen_cfg - The selected OEN signal for GPIO150. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio1_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] read-write - sys_iomux_gpo151_doen_cfg - The selected OEN signal for GPIO151. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio1_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] read-write - - - - sys_iomux_cfgsaif_syscfg_fmux38 - SYS IOMUX CFG SAIF SYSCFG FMUX 38 - 0x98 - 32 - - sys_iomux_gpo152_doen_cfg - The selected OEN signal for GPIO152. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + padcfg_pad_gpio1_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] read-write - sys_iomux_gpo153_doen_cfg - The selected OEN signal for GPIO153. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio1_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] read-write - sys_iomux_gpo154_doen_cfg - The selected OEN signal for GPIO154. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio1_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] read-write - sys_iomux_gpo155_doen_cfg - The selected OEN signal for GPIO155. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio1_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] read-write - sys_iomux_cfgsaif_syscfg_fmux39 - SYS IOMUX CFG SAIF SYSCFG FMUX 39 - 0x9c + sys_iomux_cfgsaif_syscfg296 + SYS IOMUX CFG SAIF SYSCFG 296 + 0x128 32 - sys_iomux_gpo156_doen_cfg - The selected OEN signal for GPIO156. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] - read-write - - - sys_iomux_gpo157_doen_cfg - The selected OEN signal for GPIO157. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio2_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - sys_iomux_gpo158_doen_cfg - The selected OEN signal for GPIO158. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio2_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] read-write - sys_iomux_gpo159_doen_cfg - The selected OEN signal for GPIO159. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio2_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] read-write - - - - sys_iomux_cfgsaif_syscfg_fmux40 - SYS IOMUX CFG SAIF SYSCFG FMUX 40 - 0xa0 - 32 - - sys_iomux_gpo160_doen_cfg - The selected OEN signal for GPIO160. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + padcfg_pad_gpio2_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] read-write - sys_iomux_gpo161_doen_cfg - The selected OEN signal for GPIO161. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio2_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] read-write - sys_iomux_gpo162_doen_cfg - The selected OEN signal for GPIO162. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio2_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] read-write - sys_iomux_gpo163_doen_cfg - The selected OEN signal for GPIO163. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio2_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] read-write - sys_iomux_cfgsaif_syscfg_fmux41 - SYS IOMUX CFG SAIF SYSCFG FMUX 41 - 0xa4 + sys_iomux_cfgsaif_syscfg300 + SYS IOMUX CFG SAIF SYSCFG 300 + 0x12c 32 - sys_iomux_gpo164_doen_cfg - The selected OEN signal for GPIO164. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] - read-write - - - sys_iomux_gpo165_doen_cfg - The selected OEN signal for GPIO165. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio3_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - sys_iomux_gpo166_doen_cfg - The selected OEN signal for GPIO166. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio3_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] read-write - sys_iomux_gpo167_doen_cfg - The selected OEN signal for GPIO167. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio3_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] read-write - - - - sys_iomux_cfgsaif_syscfg_fmux42 - SYS IOMUX CFG SAIF SYSCFG FMUX 42 - 0xa8 - 32 - - sys_iomux_gpo168_doen_cfg - The selected OEN signal for GPIO168. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + padcfg_pad_gpio3_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] read-write - sys_iomux_gpo169_doen_cfg - The selected OEN signal for GPIO169. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio3_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] read-write - sys_iomux_gpo170_doen_cfg - The selected OEN signal for GPIO170. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio3_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] read-write - sys_iomux_gpo171_doen_cfg - The selected OEN signal for GPIO171. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio3_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] read-write - sys_iomux_cfgsaif_syscfg_fmux43 - SYS IOMUX CFG SAIF SYSCFG FMUX 43 - 0xac + sys_iomux_cfgsaif_syscfg304 + SYS IOMUX CFG SAIF SYSCFG 304 + 0x130 32 - sys_iomux_gpo172_doen_cfg - The selected OEN signal for GPIO172. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] - read-write - - - sys_iomux_gpo173_doen_cfg - The selected OEN signal for GPIO173. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio4_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - sys_iomux_gpo174_doen_cfg - The selected OEN signal for GPIO174. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio4_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] read-write - sys_iomux_gpo175_doen_cfg - The selected OEN signal for GPIO175. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio4_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] read-write - - - - sys_iomux_cfgsaif_syscfg_fmux44 - SYS IOMUX CFG SAIF SYSCFG FMUX 44 - 0xb0 - 32 - - sys_iomux_gpo176_doen_cfg - The selected OEN signal for GPIO176. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + padcfg_pad_gpio4_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] read-write - sys_iomux_gpo177_doen_cfg - The selected OEN signal for GPIO177. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio4_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] read-write - sys_iomux_gpo178_doen_cfg - The selected OEN signal for GPIO178. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio4_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] read-write - sys_iomux_gpo179_doen_cfg - The selected OEN signal for GPIO179. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio4_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] read-write - sys_iomux_cfgsaif_syscfg_fmux45 - SYS IOMUX CFG SAIF SYSCFG FMUX 45 - 0xb4 + sys_iomux_cfgsaif_syscfg308 + SYS IOMUX CFG SAIF SYSCFG 308 + 0x134 32 - sys_iomux_gpo180_doen_cfg - The selected OEN signal for GPIO180. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + padcfg_pad_gpio5_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - sys_iomux_gpo181_doen_cfg - The selected OEN signal for GPIO181. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio5_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] read-write - sys_iomux_gpo182_doen_cfg - The selected OEN signal for GPIO182. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio5_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] read-write - sys_iomux_gpo183_doen_cfg - The selected OEN signal for GPIO183. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio5_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] + read-write + + + padcfg_pad_gpio5_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] + read-write + + + padcfg_pad_gpio5_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] + read-write + + + padcfg_pad_gpio5_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] read-write - sys_iomux_cfgsaif_syscfg_fmux46 - SYS IOMUX CFG SAIF SYSCFG FMUX 46 - 0xb8 + sys_iomux_cfgsaif_syscfg312 + SYS IOMUX CFG SAIF SYSCFG 312 + 0x138 32 - sys_iomux_gpo184_doen_cfg - The selected OEN signal for GPIO184. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] - read-write - - - sys_iomux_gpo185_doen_cfg - The selected OEN signal for GPIO185. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio6_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - sys_iomux_gpo186_doen_cfg - The selected OEN signal for GPIO186. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio6_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] read-write - sys_iomux_gpo187_doen_cfg - The selected OEN signal for GPIO187. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio6_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] read-write - - - - sys_iomux_cfgsaif_syscfg_fmux47 - SYS IOMUX CFG SAIF SYSCFG FMUX 47 - 0xbc - 32 - - sys_iomux_gpo188_doen_cfg - The selected OEN signal for GPIO188. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + padcfg_pad_gpio6_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] read-write - sys_iomux_gpo189_doen_cfg - The selected OEN signal for GPIO189. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio6_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] read-write - sys_iomux_gpo190_doen_cfg - The selected OEN signal for GPIO190. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio6_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] read-write - sys_iomux_gpo191_doen_cfg - The selected OEN signal for GPIO191. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio6_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] read-write - sys_iomux_cfgsaif_syscfg_fmux48 - SYS IOMUX CFG SAIF SYSCFG FMUX 48 - 0xc0 + sys_iomux_cfgsaif_syscfg316 + SYS IOMUX CFG SAIF SYSCFG 316 + 0x13c 32 - sys_iomux_gpo192_doen_cfg - The selected OEN signal for GPIO192. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] - read-write - - - sys_iomux_gpo193_doen_cfg - The selected OEN signal for GPIO193. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio7_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - sys_iomux_gpo194_doen_cfg - The selected OEN signal for GPIO194. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio7_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] read-write - sys_iomux_gpo195_doen_cfg - The selected OEN signal for GPIO195. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio7_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] read-write - - - - sys_iomux_cfgsaif_syscfg_fmux49 - SYS IOMUX CFG SAIF SYSCFG FMUX 49 - 0xc4 - 32 - - sys_iomux_gpo196_doen_cfg - The selected OEN signal for GPIO196. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + padcfg_pad_gpio7_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] read-write - sys_iomux_gpo197_doen_cfg - The selected OEN signal for GPIO197. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio7_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] read-write - sys_iomux_gpo198_doen_cfg - The selected OEN signal for GPIO198. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio7_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] read-write - sys_iomux_gpo199_doen_cfg - The selected OEN signal for GPIO199. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio7_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] read-write - sys_iomux_cfgsaif_syscfg_fmux50 - SYS IOMUX CFG SAIF SYSCFG FMUX 50 - 0xc8 + sys_iomux_cfgsaif_syscfg320 + SYS IOMUX CFG SAIF SYSCFG 320 + 0x140 32 - sys_iomux_gpo200_doen_cfg - The selected OEN signal for GPIO200. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] - read-write - - - sys_iomux_gpo201_doen_cfg - The selected OEN signal for GPIO201. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio8_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - sys_iomux_gpo202_doen_cfg - The selected OEN signal for GPIO202. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio8_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] read-write - sys_iomux_gpo203_doen_cfg - The selected OEN signal for GPIO203. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio8_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] read-write - - - - sys_iomux_cfgsaif_syscfg_fmux51 - SYS IOMUX CFG SAIF SYSCFG FMUX 51 - 0xcc - 32 - - sys_iomux_gpo204_doen_cfg - The selected OEN signal for GPIO204. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + padcfg_pad_gpio8_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] read-write - sys_iomux_gpo205_doen_cfg - The selected OEN signal for GPIO205. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio8_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] read-write - sys_iomux_gpo206_doen_cfg - The selected OEN signal for GPIO206. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio8_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] read-write - sys_iomux_gpo207_doen_cfg - The selected OEN signal for GPIO207. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio8_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] read-write - sys_iomux_cfgsaif_syscfg_fmux52 - SYS IOMUX CFG SAIF SYSCFG FMUX 52 - 0xd0 + sys_iomux_cfgsaif_syscfg324 + SYS IOMUX CFG SAIF SYSCFG 324 + 0x144 32 - sys_iomux_gpo208_doen_cfg - The selected OEN signal for GPIO208. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] - read-write - - - sys_iomux_gpo209_doen_cfg - The selected OEN signal for GPIO209. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio9_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - sys_iomux_gpo210_doen_cfg - The selected OEN signal for GPIO210. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio9_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] read-write - sys_iomux_gpo211_doen_cfg - The selected OEN signal for GPIO211. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio9_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] read-write - - - - sys_iomux_cfgsaif_syscfg_fmux53 - SYS IOMUX CFG SAIF SYSCFG FMUX 53 - 0xd4 - 32 - - sys_iomux_gpo212_doen_cfg - The selected OEN signal for GPIO212. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + padcfg_pad_gpio9_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] read-write - sys_iomux_gpo213_doen_cfg - The selected OEN signal for GPIO213. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio9_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] read-write - sys_iomux_gpo214_doen_cfg - The selected OEN signal for GPIO214. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio9_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] read-write - sys_iomux_gpo215_doen_cfg - The selected OEN signal for GPIO215. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio9_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] read-write - sys_iomux_cfgsaif_syscfg_fmux54 - SYS IOMUX CFG SAIF SYSCFG FMUX 54 - 0xd8 + sys_iomux_cfgsaif_syscfg328 + SYS IOMUX CFG SAIF SYSCFG 328 + 0x148 32 - sys_iomux_gpo216_doen_cfg - The selected OEN signal for GPIO216. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [5:0] + padcfg_pad_gpio10_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - sys_iomux_gpo217_doen_cfg - The selected OEN signal for GPIO217. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [13:8] + padcfg_pad_gpio10_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] read-write - sys_iomux_gpo218_doen_cfg - The selected OEN signal for GPIO218. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [21:16] + padcfg_pad_gpio10_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] read-write - sys_iomux_gpo219_doen_cfg - The selected OEN signal for GPIO219. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. - [29:24] + padcfg_pad_gpio10_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq55 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 55 - 0xdc - 32 - - sys_gpioen_0_reg - Enable GPIO IRQ function - [0:0] + padcfg_pad_gpio10_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq56 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 56 - 0xe0 - 32 - - sys_gpiois_0_reg - 1: Edge trigger, 0: Level trigger - [31:0] + padcfg_pad_gpio10_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq57 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 57 - 0xe4 - 32 - - sys_gpiois_1_reg - 1: Edge trigger, 0: Level trigger - [31:0] + padcfg_pad_gpio10_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] read-write - sys_iomux_cfgsaif_syscfg_ioirq58 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 58 - 0xe8 + sys_iomux_cfgsaif_syscfg332 + SYS IOMUX CFG SAIF SYSCFG 332 + 0x14c 32 - sys_gpioic_0_reg - 1: Do not clear the register, 0: Clear the register - [31:0] + padcfg_pad_gpio11_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq59 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 59 - 0xec - 32 - - sys_gpioic_1_reg - 1: Do not clear the register, 0: Clear the register - [31:0] + padcfg_pad_gpio11_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq60 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 60 - 0xf0 - 32 - - sys_gpioibe_0_reg - 1: Trigger on both edges, 0: Trigger on a single edge - [31:0] + padcfg_pad_gpio11_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq61 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 61 - 0xf4 - 32 - - sys_gpioibe_1_reg - 1: Trigger on both edges, 0: Trigger on a single edge - [31:0] + padcfg_pad_gpio11_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq62 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 62 - 0xf8 - 32 - - sys_gpioiev_0_reg - 1: Positive/Low, 0: Negative/High - [31:0] + padcfg_pad_gpio11_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq63 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 63 - 0xfc - 32 - - sys_gpioiev_1_reg - 1: Positive/Low, 0: Negative/High - [31:0] + padcfg_pad_gpio11_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq64 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 64 - 0x100 - 32 - - sys_gpioie_0_reg - 1: Unmask, 0: Mask - [31:0] + padcfg_pad_gpio11_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] read-write - sys_iomux_cfgsaif_syscfg_ioirq65 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 65 - 0x104 + sys_iomux_cfgsaif_syscfg336 + SYS IOMUX CFG SAIF SYSCFG 336 + 0x150 32 - sys_gpioie_1_reg - 1: Unmask, 0: Mask - [31:0] + padcfg_pad_gpio12_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq66 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 66 - 0x108 - 32 - - sys_gpioris_0_reg - Status of the edge trigger. The register can be cleared by writing gpio ic - [31:0] - read-only + padcfg_pad_gpio12_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] + read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq67 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 67 - 0x10c - 32 - - sys_gpioris_1_reg - Status of the edge trigger. The register can be cleared by writing gpio ic - [31:0] - read-only + padcfg_pad_gpio12_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] + read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq68 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 68 - 0x110 - 32 - - sys_gpiomis_0_reg - The masked GPIO IRQ status - [31:0] - read-only + padcfg_pad_gpio12_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] + read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq69 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 69 - 0x114 - 32 - - sys_gpiomis_1_reg - The masked GPIO IRQ status - [31:0] - read-only + padcfg_pad_gpio12_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] + read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq70 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 70 - 0x118 - 32 - - sys_gpio_in_sync2_0_reg - Status of the gpio_in after synchronization - [31:0] - read-only + padcfg_pad_gpio12_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] + read-write - - - - sys_iomux_cfgsaif_syscfg_ioirq71 - SYS IOMUX CFG SAIF SYSCFG IOIRQ 71 - 0x11c - 32 - - sys_gpio_in_sync2_1_reg - Status of the gpio_in after synchronization - [31:0] - read-only + padcfg_pad_gpio12_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] + read-write - - sys_iomux_cfgsaif_syscfg288 - SYS IOMUX CFG SAIF SYSCFG 288 - 0x120 + + sys_iomux_cfgsaif_syscfg340 + SYS IOMUX CFG SAIF SYSCFG 340 + 0x154 32 - padcfg_pad_gpio0_ie + padcfg_pad_gpio13_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio0_ds + padcfg_pad_gpio13_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio0_pu + padcfg_pad_gpio13_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio0_pd + padcfg_pad_gpio13_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio0_slew + padcfg_pad_gpio13_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio0_smt + padcfg_pad_gpio13_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio0_pos + padcfg_pad_gpio13_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -21810,49 +24452,49 @@ - sys_iomux_cfgsaif_syscfg292 - SYS IOMUX CFG SAIF SYSCFG 292 - 0x124 + sys_iomux_cfgsaif_syscfg344 + SYS IOMUX CFG SAIF SYSCFG 344 + 0x158 32 - padcfg_pad_gpio1_ie + padcfg_pad_gpio14_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio1_ds + padcfg_pad_gpio14_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio1_pu + padcfg_pad_gpio14_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio1_pd + padcfg_pad_gpio14_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio1_slew + padcfg_pad_gpio14_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio1_smt + padcfg_pad_gpio14_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio1_pos + padcfg_pad_gpio14_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -21860,49 +24502,49 @@ - sys_iomux_cfgsaif_syscfg296 - SYS IOMUX CFG SAIF SYSCFG 296 - 0x128 + sys_iomux_cfgsaif_syscfg348 + SYS IOMUX CFG SAIF SYSCFG 348 + 0x15c 32 - padcfg_pad_gpio2_ie + padcfg_pad_gpio15_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio2_ds + padcfg_pad_gpio15_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio2_pu + padcfg_pad_gpio15_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio2_pd + padcfg_pad_gpio15_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio2_slew + padcfg_pad_gpio15_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio2_smt + padcfg_pad_gpio15_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio2_pos + padcfg_pad_gpio15_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -21910,49 +24552,49 @@ - sys_iomux_cfgsaif_syscfg300 - SYS IOMUX CFG SAIF SYSCFG 300 - 0x12c + sys_iomux_cfgsaif_syscfg352 + SYS IOMUX CFG SAIF SYSCFG 352 + 0x160 32 - padcfg_pad_gpio3_ie + padcfg_pad_gpio16_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio3_ds + padcfg_pad_gpio16_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio3_pu + padcfg_pad_gpio16_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio3_pd + padcfg_pad_gpio16_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio3_slew + padcfg_pad_gpio16_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio3_smt + padcfg_pad_gpio16_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio3_pos + padcfg_pad_gpio16_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -21960,49 +24602,49 @@ - sys_iomux_cfgsaif_syscfg304 - SYS IOMUX CFG SAIF SYSCFG 304 - 0x130 + sys_iomux_cfgsaif_syscfg356 + SYS IOMUX CFG SAIF SYSCFG 356 + 0x164 32 - padcfg_pad_gpio4_ie + padcfg_pad_gpio17_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio4_ds + padcfg_pad_gpio17_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio4_pu + padcfg_pad_gpio17_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio4_pd + padcfg_pad_gpio17_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio4_slew + padcfg_pad_gpio17_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio4_smt + padcfg_pad_gpio17_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio4_pos + padcfg_pad_gpio17_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22010,49 +24652,49 @@ - sys_iomux_cfgsaif_syscfg308 - SYS IOMUX CFG SAIF SYSCFG 308 - 0x134 + sys_iomux_cfgsaif_syscfg360 + SYS IOMUX CFG SAIF SYSCFG 360 + 0x168 32 - padcfg_pad_gpio5_ie + padcfg_pad_gpio18_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio5_ds + padcfg_pad_gpio18_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio5_pu + padcfg_pad_gpio18_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio5_pd + padcfg_pad_gpio18_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio5_slew + padcfg_pad_gpio18_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio5_smt + padcfg_pad_gpio18_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio5_pos + padcfg_pad_gpio18_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22060,49 +24702,49 @@ - sys_iomux_cfgsaif_syscfg312 - SYS IOMUX CFG SAIF SYSCFG 312 - 0x138 + sys_iomux_cfgsaif_syscfg364 + SYS IOMUX CFG SAIF SYSCFG 364 + 0x16c 32 - padcfg_pad_gpio6_ie + padcfg_pad_gpio19_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio6_ds + padcfg_pad_gpio19_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio6_pu + padcfg_pad_gpio19_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio6_pd + padcfg_pad_gpio19_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio6_slew + padcfg_pad_gpio19_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio6_smt + padcfg_pad_gpio19_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio6_pos + padcfg_pad_gpio19_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22110,49 +24752,49 @@ - sys_iomux_cfgsaif_syscfg316 - SYS IOMUX CFG SAIF SYSCFG 316 - 0x13c + sys_iomux_cfgsaif_syscfg368 + SYS IOMUX CFG SAIF SYSCFG 368 + 0x170 32 - padcfg_pad_gpio7_ie + padcfg_pad_gpio20_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio7_ds + padcfg_pad_gpio20_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio7_pu + padcfg_pad_gpio20_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio7_pd + padcfg_pad_gpio20_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio7_slew + padcfg_pad_gpio20_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio7_smt + padcfg_pad_gpio20_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio7_pos + padcfg_pad_gpio20_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22160,49 +24802,49 @@ - sys_iomux_cfgsaif_syscfg320 - SYS IOMUX CFG SAIF SYSCFG 320 - 0x140 + sys_iomux_cfgsaif_syscfg372 + SYS IOMUX CFG SAIF SYSCFG 372 + 0x174 32 - padcfg_pad_gpio8_ie + padcfg_pad_gpio21_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio8_ds + padcfg_pad_gpio21_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio8_pu + padcfg_pad_gpio21_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio8_pd + padcfg_pad_gpio21_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio8_slew + padcfg_pad_gpio21_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio8_smt + padcfg_pad_gpio21_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio8_pos + padcfg_pad_gpio21_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22210,49 +24852,49 @@ - sys_iomux_cfgsaif_syscfg324 - SYS IOMUX CFG SAIF SYSCFG 324 - 0x144 + sys_iomux_cfgsaif_syscfg376 + SYS IOMUX CFG SAIF SYSCFG 376 + 0x178 32 - padcfg_pad_gpio9_ie + padcfg_pad_gpio22_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio9_ds + padcfg_pad_gpio22_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio9_pu + padcfg_pad_gpio22_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio9_pd + padcfg_pad_gpio22_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio9_slew + padcfg_pad_gpio22_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio9_smt + padcfg_pad_gpio22_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio9_pos + padcfg_pad_gpio22_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22260,49 +24902,49 @@ - sys_iomux_cfgsaif_syscfg328 - SYS IOMUX CFG SAIF SYSCFG 328 - 0x148 + sys_iomux_cfgsaif_syscfg380 + SYS IOMUX CFG SAIF SYSCFG 380 + 0x17c 32 - padcfg_pad_gpio10_ie + padcfg_pad_gpio23_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio10_ds + padcfg_pad_gpio23_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio10_pu + padcfg_pad_gpio23_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio10_pd + padcfg_pad_gpio23_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio10_slew + padcfg_pad_gpio23_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio10_smt + padcfg_pad_gpio23_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio10_pos + padcfg_pad_gpio23_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22310,49 +24952,49 @@ - sys_iomux_cfgsaif_syscfg332 - SYS IOMUX CFG SAIF SYSCFG 332 - 0x14c + sys_iomux_cfgsaif_syscfg384 + SYS IOMUX CFG SAIF SYSCFG 384 + 0x180 32 - padcfg_pad_gpio11_ie + padcfg_pad_gpio24_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio11_ds + padcfg_pad_gpio24_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio11_pu + padcfg_pad_gpio24_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio11_pd + padcfg_pad_gpio24_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio11_slew + padcfg_pad_gpio24_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio11_smt + padcfg_pad_gpio24_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio11_pos + padcfg_pad_gpio24_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22360,49 +25002,49 @@ - sys_iomux_cfgsaif_syscfg336 - SYS IOMUX CFG SAIF SYSCFG 336 - 0x150 + sys_iomux_cfgsaif_syscfg388 + SYS IOMUX CFG SAIF SYSCFG 388 + 0x184 32 - padcfg_pad_gpio12_ie + padcfg_pad_gpio25_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio12_ds + padcfg_pad_gpio25_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio12_pu + padcfg_pad_gpio25_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio12_pd + padcfg_pad_gpio25_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio12_slew + padcfg_pad_gpio25_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio12_smt + padcfg_pad_gpio25_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio12_pos + padcfg_pad_gpio25_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22410,49 +25052,49 @@ - sys_iomux_cfgsaif_syscfg340 - SYS IOMUX CFG SAIF SYSCFG 340 - 0x154 + sys_iomux_cfgsaif_syscfg392 + SYS IOMUX CFG SAIF SYSCFG 392 + 0x188 32 - padcfg_pad_gpio13_ie + padcfg_pad_gpio26_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio13_ds + padcfg_pad_gpio26_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio13_pu + padcfg_pad_gpio26_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio13_pd + padcfg_pad_gpio26_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio13_slew + padcfg_pad_gpio26_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio13_smt + padcfg_pad_gpio26_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio13_pos + padcfg_pad_gpio26_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22460,49 +25102,49 @@ - sys_iomux_cfgsaif_syscfg344 - SYS IOMUX CFG SAIF SYSCFG 344 - 0x158 + sys_iomux_cfgsaif_syscfg396 + SYS IOMUX CFG SAIF SYSCFG 396 + 0x18c 32 - padcfg_pad_gpio14_ie + padcfg_pad_gpio27_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio14_ds + padcfg_pad_gpio27_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio14_pu + padcfg_pad_gpio27_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio14_pd + padcfg_pad_gpio27_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio14_slew + padcfg_pad_gpio27_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio14_smt + padcfg_pad_gpio27_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio14_pos + padcfg_pad_gpio27_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22510,49 +25152,49 @@ - sys_iomux_cfgsaif_syscfg348 - SYS IOMUX CFG SAIF SYSCFG 348 - 0x15c + sys_iomux_cfgsaif_syscfg400 + SYS IOMUX CFG SAIF SYSCFG 400 + 0x190 32 - padcfg_pad_gpio15_ie + padcfg_pad_gpio28_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio15_ds + padcfg_pad_gpio28_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio15_pu + padcfg_pad_gpio28_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio15_pd + padcfg_pad_gpio28_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio15_slew + padcfg_pad_gpio28_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio15_smt + padcfg_pad_gpio28_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio15_pos + padcfg_pad_gpio28_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22560,49 +25202,49 @@ - sys_iomux_cfgsaif_syscfg352 - SYS IOMUX CFG SAIF SYSCFG 352 - 0x160 + sys_iomux_cfgsaif_syscfg404 + SYS IOMUX CFG SAIF SYSCFG 404 + 0x194 32 - padcfg_pad_gpio16_ie + padcfg_pad_gpio29_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio16_ds + padcfg_pad_gpio29_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio16_pu + padcfg_pad_gpio29_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio16_pd + padcfg_pad_gpio29_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio16_slew + padcfg_pad_gpio29_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio16_smt + padcfg_pad_gpio29_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio16_pos + padcfg_pad_gpio29_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22610,49 +25252,49 @@ - sys_iomux_cfgsaif_syscfg356 - SYS IOMUX CFG SAIF SYSCFG 356 - 0x164 + sys_iomux_cfgsaif_syscfg408 + SYS IOMUX CFG SAIF SYSCFG 408 + 0x198 32 - padcfg_pad_gpio17_ie + padcfg_pad_gpio30_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio17_ds + padcfg_pad_gpio30_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio17_pu + padcfg_pad_gpio30_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio17_pd + padcfg_pad_gpio30_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio17_slew + padcfg_pad_gpio30_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio17_smt + padcfg_pad_gpio30_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio17_pos + padcfg_pad_gpio30_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22660,49 +25302,49 @@ - sys_iomux_cfgsaif_syscfg360 - SYS IOMUX CFG SAIF SYSCFG 360 - 0x168 + sys_iomux_cfgsaif_syscfg412 + SYS IOMUX CFG SAIF SYSCFG 412 + 0x19c 32 - padcfg_pad_gpio18_ie + padcfg_pad_gpio31_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio18_ds + padcfg_pad_gpio31_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio18_pu + padcfg_pad_gpio31_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio18_pd + padcfg_pad_gpio31_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio18_slew + padcfg_pad_gpio31_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio18_smt + padcfg_pad_gpio31_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio18_pos + padcfg_pad_gpio31_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22710,49 +25352,49 @@ - sys_iomux_cfgsaif_syscfg364 - SYS IOMUX CFG SAIF SYSCFG 364 - 0x16c + sys_iomux_cfgsaif_syscfg416 + SYS IOMUX CFG SAIF SYSCFG 416 + 0x1a0 32 - padcfg_pad_gpio19_ie + padcfg_pad_gpio32_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio19_ds + padcfg_pad_gpio32_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio19_pu + padcfg_pad_gpio32_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio19_pd + padcfg_pad_gpio32_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio19_slew + padcfg_pad_gpio32_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio19_smt + padcfg_pad_gpio32_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio19_pos + padcfg_pad_gpio32_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22760,49 +25402,49 @@ - sys_iomux_cfgsaif_syscfg368 - SYS IOMUX CFG SAIF SYSCFG 368 - 0x170 + sys_iomux_cfgsaif_syscfg420 + SYS IOMUX CFG SAIF SYSCFG 420 + 0x1a4 32 - padcfg_pad_gpio20_ie + padcfg_pad_gpio33_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio20_ds + padcfg_pad_gpio33_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio20_pu + padcfg_pad_gpio33_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio20_pd + padcfg_pad_gpio33_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio20_slew + padcfg_pad_gpio33_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio20_smt + padcfg_pad_gpio33_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio20_pos + padcfg_pad_gpio33_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22810,49 +25452,49 @@ - sys_iomux_cfgsaif_syscfg372 - SYS IOMUX CFG SAIF SYSCFG 372 - 0x174 + sys_iomux_cfgsaif_syscfg424 + SYS IOMUX CFG SAIF SYSCFG 424 + 0x1a8 32 - padcfg_pad_gpio21_ie + padcfg_pad_gpio34_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio21_ds + padcfg_pad_gpio34_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio21_pu + padcfg_pad_gpio34_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio21_pd + padcfg_pad_gpio34_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio21_slew + padcfg_pad_gpio34_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio21_smt + padcfg_pad_gpio34_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio21_pos + padcfg_pad_gpio34_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22860,49 +25502,49 @@ - sys_iomux_cfgsaif_syscfg376 - SYS IOMUX CFG SAIF SYSCFG 376 - 0x178 + sys_iomux_cfgsaif_syscfg428 + SYS IOMUX CFG SAIF SYSCFG 428 + 0x1ac 32 - padcfg_pad_gpio22_ie + padcfg_pad_gpio35_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio22_ds + padcfg_pad_gpio35_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio22_pu + padcfg_pad_gpio35_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio22_pd + padcfg_pad_gpio35_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio22_slew + padcfg_pad_gpio35_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio22_smt + padcfg_pad_gpio35_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio22_pos + padcfg_pad_gpio35_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22910,49 +25552,49 @@ - sys_iomux_cfgsaif_syscfg380 - SYS IOMUX CFG SAIF SYSCFG 380 - 0x17c + sys_iomux_cfgsaif_syscfg432 + SYS IOMUX CFG SAIF SYSCFG 432 + 0x1b0 32 - padcfg_pad_gpio23_ie + padcfg_pad_gpio36_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio23_ds + padcfg_pad_gpio36_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio23_pu + padcfg_pad_gpio36_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio23_pd + padcfg_pad_gpio36_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio23_slew + padcfg_pad_gpio36_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio23_smt + padcfg_pad_gpio36_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio23_pos + padcfg_pad_gpio36_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -22960,49 +25602,49 @@ - sys_iomux_cfgsaif_syscfg384 - SYS IOMUX CFG SAIF SYSCFG 384 - 0x180 + sys_iomux_cfgsaif_syscfg436 + SYS IOMUX CFG SAIF SYSCFG 436 + 0x1b4 32 - padcfg_pad_gpio24_ie + padcfg_pad_gpio37_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio24_ds + padcfg_pad_gpio37_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio24_pu + padcfg_pad_gpio37_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio24_pd + padcfg_pad_gpio37_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio24_slew + padcfg_pad_gpio37_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio24_smt + padcfg_pad_gpio37_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio24_pos + padcfg_pad_gpio37_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23010,49 +25652,49 @@ - sys_iomux_cfgsaif_syscfg388 - SYS IOMUX CFG SAIF SYSCFG 388 - 0x184 + sys_iomux_cfgsaif_syscfg440 + SYS IOMUX CFG SAIF SYSCFG 440 + 0x1b8 32 - padcfg_pad_gpio25_ie + padcfg_pad_gpio38_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio25_ds + padcfg_pad_gpio38_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio25_pu + padcfg_pad_gpio38_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio25_pd + padcfg_pad_gpio38_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio25_slew + padcfg_pad_gpio38_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio25_smt + padcfg_pad_gpio38_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio25_pos + padcfg_pad_gpio38_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23060,49 +25702,49 @@ - sys_iomux_cfgsaif_syscfg392 - SYS IOMUX CFG SAIF SYSCFG 392 - 0x188 + sys_iomux_cfgsaif_syscfg444 + SYS IOMUX CFG SAIF SYSCFG 444 + 0x1bc 32 - padcfg_pad_gpio26_ie + padcfg_pad_gpio39_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio26_ds + padcfg_pad_gpio39_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio26_pu + padcfg_pad_gpio39_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio26_pd + padcfg_pad_gpio39_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio26_slew + padcfg_pad_gpio39_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio26_smt + padcfg_pad_gpio39_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio26_pos + padcfg_pad_gpio39_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23110,49 +25752,49 @@ - sys_iomux_cfgsaif_syscfg396 - SYS IOMUX CFG SAIF SYSCFG 396 - 0x18c + sys_iomux_cfgsaif_syscfg448 + SYS IOMUX CFG SAIF SYSCFG 448 + 0x1c0 32 - padcfg_pad_gpio27_ie + padcfg_pad_gpio40_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio27_ds + padcfg_pad_gpio40_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio27_pu + padcfg_pad_gpio40_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio27_pd + padcfg_pad_gpio40_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio27_slew + padcfg_pad_gpio40_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio27_smt + padcfg_pad_gpio40_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio27_pos + padcfg_pad_gpio40_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23160,49 +25802,49 @@ - sys_iomux_cfgsaif_syscfg400 - SYS IOMUX CFG SAIF SYSCFG 400 - 0x190 + sys_iomux_cfgsaif_syscfg452 + SYS IOMUX CFG SAIF SYSCFG 452 + 0x1c4 32 - padcfg_pad_gpio28_ie + padcfg_pad_gpio41_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio28_ds + padcfg_pad_gpio41_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio28_pu + padcfg_pad_gpio41_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio28_pd + padcfg_pad_gpio41_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio28_slew + padcfg_pad_gpio41_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio28_smt + padcfg_pad_gpio41_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio28_pos + padcfg_pad_gpio41_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23210,49 +25852,49 @@ - sys_iomux_cfgsaif_syscfg404 - SYS IOMUX CFG SAIF SYSCFG 404 - 0x194 + sys_iomux_cfgsaif_syscfg456 + SYS IOMUX CFG SAIF SYSCFG 456 + 0x1c8 32 - padcfg_pad_gpio29_ie + padcfg_pad_gpio42_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio29_ds + padcfg_pad_gpio42_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio29_pu + padcfg_pad_gpio42_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio29_pd + padcfg_pad_gpio42_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio29_slew + padcfg_pad_gpio42_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio29_smt + padcfg_pad_gpio42_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio29_pos + padcfg_pad_gpio42_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23260,49 +25902,49 @@ - sys_iomux_cfgsaif_syscfg408 - SYS IOMUX CFG SAIF SYSCFG 408 - 0x198 + sys_iomux_cfgsaif_syscfg460 + SYS IOMUX CFG SAIF SYSCFG 460 + 0x1cc 32 - padcfg_pad_gpio30_ie + padcfg_pad_gpio43_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio30_ds + padcfg_pad_gpio43_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio30_pu + padcfg_pad_gpio43_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio30_pd + padcfg_pad_gpio43_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio30_slew + padcfg_pad_gpio43_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio30_smt + padcfg_pad_gpio43_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio30_pos + padcfg_pad_gpio43_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23310,49 +25952,49 @@ - sys_iomux_cfgsaif_syscfg412 - SYS IOMUX CFG SAIF SYSCFG 412 - 0x19c + sys_iomux_cfgsaif_syscfg464 + SYS IOMUX CFG SAIF SYSCFG 464 + 0x1d0 32 - padcfg_pad_gpio31_ie + padcfg_pad_gpio44_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio31_ds + padcfg_pad_gpio44_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio31_pu + padcfg_pad_gpio44_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio31_pd + padcfg_pad_gpio44_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio31_slew + padcfg_pad_gpio44_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio31_smt + padcfg_pad_gpio44_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio31_pos + padcfg_pad_gpio44_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23360,49 +26002,49 @@ - sys_iomux_cfgsaif_syscfg416 - SYS IOMUX CFG SAIF SYSCFG 416 - 0x1a0 + sys_iomux_cfgsaif_syscfg468 + SYS IOMUX CFG SAIF SYSCFG 468 + 0x1d4 32 - padcfg_pad_gpio32_ie + padcfg_pad_gpio45_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio32_ds + padcfg_pad_gpio45_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio32_pu + padcfg_pad_gpio45_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio32_pd + padcfg_pad_gpio45_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio32_slew + padcfg_pad_gpio45_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio32_smt + padcfg_pad_gpio45_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio32_pos + padcfg_pad_gpio45_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23410,49 +26052,49 @@ - sys_iomux_cfgsaif_syscfg420 - SYS IOMUX CFG SAIF SYSCFG 420 - 0x1a4 + sys_iomux_cfgsaif_syscfg472 + SYS IOMUX CFG SAIF SYSCFG 472 + 0x1d8 32 - padcfg_pad_gpio33_ie + padcfg_pad_gpio46_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio33_ds + padcfg_pad_gpio46_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio33_pu + padcfg_pad_gpio46_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio33_pd + padcfg_pad_gpio46_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio33_slew + padcfg_pad_gpio46_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio33_smt + padcfg_pad_gpio46_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio33_pos + padcfg_pad_gpio46_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23460,49 +26102,49 @@ - sys_iomux_cfgsaif_syscfg424 - SYS IOMUX CFG SAIF SYSCFG 424 - 0x1a8 + sys_iomux_cfgsaif_syscfg476 + SYS IOMUX CFG SAIF SYSCFG 476 + 0x1dc 32 - padcfg_pad_gpio34_ie + padcfg_pad_gpio47_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio34_ds + padcfg_pad_gpio47_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio34_pu + padcfg_pad_gpio47_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio34_pd + padcfg_pad_gpio47_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio34_slew + padcfg_pad_gpio47_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio34_smt + padcfg_pad_gpio47_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio34_pos + padcfg_pad_gpio47_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23510,49 +26152,49 @@ - sys_iomux_cfgsaif_syscfg428 - SYS IOMUX CFG SAIF SYSCFG 428 - 0x1ac + sys_iomux_cfgsaif_syscfg480 + SYS IOMUX CFG SAIF SYSCFG 480 + 0x1e0 32 - padcfg_pad_gpio35_ie + padcfg_pad_gpio48_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio35_ds + padcfg_pad_gpio48_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio35_pu + padcfg_pad_gpio48_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio35_pd + padcfg_pad_gpio48_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio35_slew + padcfg_pad_gpio48_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio35_smt + padcfg_pad_gpio48_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio35_pos + padcfg_pad_gpio48_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23560,49 +26202,49 @@ - sys_iomux_cfgsaif_syscfg432 - SYS IOMUX CFG SAIF SYSCFG 432 - 0x1b0 + sys_iomux_cfgsaif_syscfg484 + SYS IOMUX CFG SAIF SYSCFG 484 + 0x1e4 32 - padcfg_pad_gpio36_ie + padcfg_pad_gpio49_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio36_ds + padcfg_pad_gpio49_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio36_pu + padcfg_pad_gpio49_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio36_pd + padcfg_pad_gpio49_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio36_slew + padcfg_pad_gpio49_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio36_smt + padcfg_pad_gpio49_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio36_pos + padcfg_pad_gpio49_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23610,49 +26252,49 @@ - sys_iomux_cfgsaif_syscfg436 - SYS IOMUX CFG SAIF SYSCFG 436 - 0x1b4 + sys_iomux_cfgsaif_syscfg488 + SYS IOMUX CFG SAIF SYSCFG 488 + 0x1e8 32 - padcfg_pad_gpio37_ie + padcfg_pad_gpio50_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio37_ds + padcfg_pad_gpio50_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio37_pu + padcfg_pad_gpio50_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio37_pd + padcfg_pad_gpio50_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio37_slew + padcfg_pad_gpio50_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio37_smt + padcfg_pad_gpio50_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio37_pos + padcfg_pad_gpio50_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23660,49 +26302,49 @@ - sys_iomux_cfgsaif_syscfg440 - SYS IOMUX CFG SAIF SYSCFG 440 - 0x1b8 + sys_iomux_cfgsaif_syscfg492 + SYS IOMUX CFG SAIF SYSCFG 492 + 0x1ec 32 - padcfg_pad_gpio38_ie + padcfg_pad_gpio51_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio38_ds + padcfg_pad_gpio51_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio38_pu + padcfg_pad_gpio51_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio38_pd + padcfg_pad_gpio51_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio38_slew + padcfg_pad_gpio51_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio38_smt + padcfg_pad_gpio51_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio38_pos + padcfg_pad_gpio51_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23710,49 +26352,49 @@ - sys_iomux_cfgsaif_syscfg444 - SYS IOMUX CFG SAIF SYSCFG 444 - 0x1bc + sys_iomux_cfgsaif_syscfg496 + SYS IOMUX CFG SAIF SYSCFG 496 + 0x1f0 32 - padcfg_pad_gpio39_ie + padcfg_pad_gpio52_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio39_ds + padcfg_pad_gpio52_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio39_pu + padcfg_pad_gpio52_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio39_pd + padcfg_pad_gpio52_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio39_slew + padcfg_pad_gpio52_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio39_smt + padcfg_pad_gpio52_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio39_pos + padcfg_pad_gpio52_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23760,49 +26402,49 @@ - sys_iomux_cfgsaif_syscfg448 - SYS IOMUX CFG SAIF SYSCFG 448 - 0x1c0 + sys_iomux_cfgsaif_syscfg500 + SYS IOMUX CFG SAIF SYSCFG 500 + 0x1f4 32 - padcfg_pad_gpio40_ie + padcfg_pad_gpio53_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio40_ds + padcfg_pad_gpio53_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio40_pu + padcfg_pad_gpio53_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio40_pd + padcfg_pad_gpio53_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio40_slew + padcfg_pad_gpio53_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio40_smt + padcfg_pad_gpio53_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio40_pos + padcfg_pad_gpio53_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23810,49 +26452,49 @@ - sys_iomux_cfgsaif_syscfg452 - SYS IOMUX CFG SAIF SYSCFG 452 - 0x1c4 + sys_iomux_cfgsaif_syscfg504 + SYS IOMUX CFG SAIF SYSCFG 504 + 0x1f8 32 - padcfg_pad_gpio41_ie + padcfg_pad_gpio54_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio41_ds + padcfg_pad_gpio54_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio41_pu + padcfg_pad_gpio54_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio41_pd + padcfg_pad_gpio54_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio41_slew + padcfg_pad_gpio54_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio41_smt + padcfg_pad_gpio54_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio41_pos + padcfg_pad_gpio54_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23860,49 +26502,49 @@ - sys_iomux_cfgsaif_syscfg456 - SYS IOMUX CFG SAIF SYSCFG 456 - 0x1c8 + sys_iomux_cfgsaif_syscfg508 + SYS IOMUX CFG SAIF SYSCFG 508 + 0x1fc 32 - padcfg_pad_gpio42_ie + padcfg_pad_gpio55_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio42_ds + padcfg_pad_gpio55_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio42_pu + padcfg_pad_gpio55_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio42_pd + padcfg_pad_gpio55_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio42_slew + padcfg_pad_gpio55_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio42_smt + padcfg_pad_gpio55_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio42_pos + padcfg_pad_gpio55_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23910,49 +26552,49 @@ - sys_iomux_cfgsaif_syscfg460 - SYS IOMUX CFG SAIF SYSCFG 460 - 0x1cc + sys_iomux_cfgsaif_syscfg512 + SYS IOMUX CFG SAIF SYSCFG 512 + 0x200 32 - padcfg_pad_gpio43_ie + padcfg_pad_gpio56_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio43_ds + padcfg_pad_gpio56_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio43_pu + padcfg_pad_gpio56_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio43_pd + padcfg_pad_gpio56_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio43_slew + padcfg_pad_gpio56_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio43_smt + padcfg_pad_gpio56_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio43_pos + padcfg_pad_gpio56_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -23960,49 +26602,49 @@ - sys_iomux_cfgsaif_syscfg464 - SYS IOMUX CFG SAIF SYSCFG 464 - 0x1d0 + sys_iomux_cfgsaif_syscfg516 + SYS IOMUX CFG SAIF SYSCFG 516 + 0x204 32 - padcfg_pad_gpio44_ie + padcfg_pad_gpio57_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio44_ds + padcfg_pad_gpio57_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio44_pu + padcfg_pad_gpio57_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio44_pd + padcfg_pad_gpio57_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio44_slew + padcfg_pad_gpio57_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio44_smt + padcfg_pad_gpio57_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio44_pos + padcfg_pad_gpio57_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24010,49 +26652,49 @@ - sys_iomux_cfgsaif_syscfg468 - SYS IOMUX CFG SAIF SYSCFG 468 - 0x1d4 + sys_iomux_cfgsaif_syscfg520 + SYS IOMUX CFG SAIF SYSCFG 520 + 0x208 32 - padcfg_pad_gpio45_ie + padcfg_pad_gpio58_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio45_ds + padcfg_pad_gpio58_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio45_pu + padcfg_pad_gpio58_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio45_pd + padcfg_pad_gpio58_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio45_slew + padcfg_pad_gpio58_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio45_smt + padcfg_pad_gpio58_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio45_pos + padcfg_pad_gpio58_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24060,49 +26702,49 @@ - sys_iomux_cfgsaif_syscfg472 - SYS IOMUX CFG SAIF SYSCFG 472 - 0x1d8 + sys_iomux_cfgsaif_syscfg524 + SYS IOMUX CFG SAIF SYSCFG 524 + 0x20c 32 - padcfg_pad_gpio46_ie + padcfg_pad_gpio59_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio46_ds + padcfg_pad_gpio59_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio46_pu + padcfg_pad_gpio59_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio46_pd + padcfg_pad_gpio59_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio46_slew + padcfg_pad_gpio59_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio46_smt + padcfg_pad_gpio59_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio46_pos + padcfg_pad_gpio59_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24110,49 +26752,49 @@ - sys_iomux_cfgsaif_syscfg476 - SYS IOMUX CFG SAIF SYSCFG 476 - 0x1dc + sys_iomux_cfgsaif_syscfg528 + SYS IOMUX CFG SAIF SYSCFG 528 + 0x210 32 - padcfg_pad_gpio47_ie + padcfg_pad_gpio60_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio47_ds + padcfg_pad_gpio60_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio47_pu + padcfg_pad_gpio60_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio47_pd + padcfg_pad_gpio60_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio47_slew + padcfg_pad_gpio60_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio47_smt + padcfg_pad_gpio60_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio47_pos + padcfg_pad_gpio60_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24160,49 +26802,49 @@ - sys_iomux_cfgsaif_syscfg480 - SYS IOMUX CFG SAIF SYSCFG 480 - 0x1e0 + sys_iomux_cfgsaif_syscfg532 + SYS IOMUX CFG SAIF SYSCFG 532 + 0x214 32 - padcfg_pad_gpio48_ie + padcfg_pad_gpio61_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio48_ds + padcfg_pad_gpio61_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio48_pu + padcfg_pad_gpio61_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio48_pd + padcfg_pad_gpio61_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio48_slew + padcfg_pad_gpio61_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio48_smt + padcfg_pad_gpio61_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio48_pos + padcfg_pad_gpio61_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24210,49 +26852,49 @@ - sys_iomux_cfgsaif_syscfg484 - SYS IOMUX CFG SAIF SYSCFG 484 - 0x1e4 + sys_iomux_cfgsaif_syscfg536 + SYS IOMUX CFG SAIF SYSCFG 536 + 0x218 32 - padcfg_pad_gpio49_ie + padcfg_pad_gpio62_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio49_ds + padcfg_pad_gpio62_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio49_pu + padcfg_pad_gpio62_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio49_pd + padcfg_pad_gpio62_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio49_slew + padcfg_pad_gpio62_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio49_smt + padcfg_pad_gpio62_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio49_pos + padcfg_pad_gpio62_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24260,49 +26902,49 @@ - sys_iomux_cfgsaif_syscfg488 - SYS IOMUX CFG SAIF SYSCFG 488 - 0x1e8 + sys_iomux_cfgsaif_syscfg540 + SYS IOMUX CFG SAIF SYSCFG 540 + 0x21c 32 - padcfg_pad_gpio50_ie + padcfg_pad_gpio63_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio50_ds + padcfg_pad_gpio63_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio50_pu + padcfg_pad_gpio63_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio50_pd + padcfg_pad_gpio63_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio50_slew + padcfg_pad_gpio63_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio50_smt + padcfg_pad_gpio63_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio50_pos + padcfg_pad_gpio63_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24310,49 +26952,49 @@ - sys_iomux_cfgsaif_syscfg492 - SYS IOMUX CFG SAIF SYSCFG 492 - 0x1ec + sys_iomux_cfgsaif_syscfg544 + SYS IOMUX CFG SAIF SYSCFG 544 + 0x220 32 - padcfg_pad_gpio51_ie + padcfg_pad_sd0_clk_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio51_ds + padcfg_pad_sd0_clk_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio51_pu + padcfg_pad_sd0_clk_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio51_pd + padcfg_pad_sd0_clk_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio51_slew + padcfg_pad_sd0_clk_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio51_smt + padcfg_pad_sd0_clk_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio51_pos + padcfg_pad_sd0_clk_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24360,49 +27002,49 @@ - sys_iomux_cfgsaif_syscfg496 - SYS IOMUX CFG SAIF SYSCFG 496 - 0x1f0 + sys_iomux_cfgsaif_syscfg548 + SYS IOMUX CFG SAIF SYSCFG 548 + 0x224 32 - padcfg_pad_gpio52_ie + padcfg_pad_sd0_cmd_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio52_ds + padcfg_pad_sd0_cmd_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio52_pu + padcfg_pad_sd0_cmd_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio52_pd + padcfg_pad_sd0_cmd_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio52_slew + padcfg_pad_sd0_cmd_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio52_smt + padcfg_pad_sd0_cmd_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio52_pos + padcfg_pad_sd0_cmd_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24410,49 +27052,49 @@ - sys_iomux_cfgsaif_syscfg500 - SYS IOMUX CFG SAIF SYSCFG 500 - 0x1f4 + sys_iomux_cfgsaif_syscfg552 + SYS IOMUX CFG SAIF SYSCFG 552 + 0x228 32 - padcfg_pad_gpio53_ie + padcfg_pad_sd0_data0_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio53_ds + padcfg_pad_sd0_data0_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio53_pu + padcfg_pad_sd0_data0_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio53_pd + padcfg_pad_sd0_data0_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio53_slew + padcfg_pad_sd0_data0_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio53_smt + padcfg_pad_sd0_data0_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio53_pos + padcfg_pad_sd0_data0_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24460,49 +27102,49 @@ - sys_iomux_cfgsaif_syscfg504 - SYS IOMUX CFG SAIF SYSCFG 504 - 0x1f8 + sys_iomux_cfgsaif_syscfg556 + SYS IOMUX CFG SAIF SYSCFG 556 + 0x22c 32 - padcfg_pad_gpio54_ie + padcfg_pad_sd0_data1_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio54_ds + padcfg_pad_sd0_data1_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio54_pu + padcfg_pad_sd0_data1_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio54_pd + padcfg_pad_sd0_data1_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio54_slew + padcfg_pad_sd0_data1_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio54_smt + padcfg_pad_sd0_data1_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio54_pos + padcfg_pad_sd0_data1_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24510,49 +27152,49 @@ - sys_iomux_cfgsaif_syscfg508 - SYS IOMUX CFG SAIF SYSCFG 508 - 0x1fc + sys_iomux_cfgsaif_syscfg560 + SYS IOMUX CFG SAIF SYSCFG 560 + 0x230 32 - padcfg_pad_gpio55_ie + padcfg_pad_sd0_data2_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio55_ds + padcfg_pad_sd0_data2_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio55_pu + padcfg_pad_sd0_data2_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio55_pd + padcfg_pad_sd0_data2_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio55_slew + padcfg_pad_sd0_data2_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio55_smt + padcfg_pad_sd0_data2_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio55_pos + padcfg_pad_sd0_data2_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24560,49 +27202,49 @@ - sys_iomux_cfgsaif_syscfg512 - SYS IOMUX CFG SAIF SYSCFG 512 - 0x200 + sys_iomux_cfgsaif_syscfg564 + SYS IOMUX CFG SAIF SYSCFG 564 + 0x234 32 - padcfg_pad_gpio56_ie + padcfg_pad_sd0_data3_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio56_ds + padcfg_pad_sd0_data3_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio56_pu + padcfg_pad_sd0_data3_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio56_pd + padcfg_pad_sd0_data3_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio56_slew + padcfg_pad_sd0_data3_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio56_smt + padcfg_pad_sd0_data3_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio56_pos + padcfg_pad_sd0_data3_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24610,49 +27252,49 @@ - sys_iomux_cfgsaif_syscfg516 - SYS IOMUX CFG SAIF SYSCFG 516 - 0x204 + sys_iomux_cfgsaif_syscfg568 + SYS IOMUX CFG SAIF SYSCFG 568 + 0x238 32 - padcfg_pad_gpio57_ie + padcfg_pad_sd0_data4_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio57_ds + padcfg_pad_sd0_data4_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio57_pu + padcfg_pad_sd0_data4_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio57_pd + padcfg_pad_sd0_data4_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio57_slew + padcfg_pad_sd0_data4_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio57_smt + padcfg_pad_sd0_data4_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio57_pos + padcfg_pad_sd0_data4_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24660,49 +27302,49 @@ - sys_iomux_cfgsaif_syscfg520 - SYS IOMUX CFG SAIF SYSCFG 520 - 0x208 + sys_iomux_cfgsaif_syscfg572 + SYS IOMUX CFG SAIF SYSCFG 572 + 0x23c 32 - padcfg_pad_gpio58_ie + padcfg_pad_sd0_data5_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio58_ds + padcfg_pad_sd0_data5_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio58_pu + padcfg_pad_sd0_data5_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio58_pd + padcfg_pad_sd0_data5_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio58_slew + padcfg_pad_sd0_data5_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio58_smt + padcfg_pad_sd0_data5_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio58_pos + padcfg_pad_sd0_data5_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24710,49 +27352,49 @@ - sys_iomux_cfgsaif_syscfg524 - SYS IOMUX CFG SAIF SYSCFG 524 - 0x20c + sys_iomux_cfgsaif_syscfg576 + SYS IOMUX CFG SAIF SYSCFG 576 + 0x240 32 - padcfg_pad_gpio59_ie + padcfg_pad_sd0_data6_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio59_ds + padcfg_pad_sd0_data6_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio59_pu + padcfg_pad_sd0_data6_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio59_pd + padcfg_pad_sd0_data6_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio59_slew + padcfg_pad_sd0_data6_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio59_smt + padcfg_pad_sd0_data6_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio59_pos + padcfg_pad_sd0_data6_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24760,49 +27402,49 @@ - sys_iomux_cfgsaif_syscfg528 - SYS IOMUX CFG SAIF SYSCFG 528 - 0x210 + sys_iomux_cfgsaif_syscfg580 + SYS IOMUX CFG SAIF SYSCFG 580 + 0x244 32 - padcfg_pad_gpio60_ie + padcfg_pad_sd0_data7_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio60_ds + padcfg_pad_sd0_data7_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio60_pu + padcfg_pad_sd0_data7_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio60_pd + padcfg_pad_sd0_data7_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio60_slew + padcfg_pad_sd0_data7_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio60_smt + padcfg_pad_sd0_data7_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio60_pos + padcfg_pad_sd0_data7_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24810,49 +27452,49 @@ - sys_iomux_cfgsaif_syscfg532 - SYS IOMUX CFG SAIF SYSCFG 532 - 0x214 + sys_iomux_cfgsaif_syscfg584 + SYS IOMUX CFG SAIF SYSCFG 584 + 0x248 32 - padcfg_pad_gpio61_ie + padcfg_pad_sd0_strb_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_gpio61_ds + padcfg_pad_sd0_strb_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_gpio61_pu + padcfg_pad_sd0_strb_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_gpio61_pd + padcfg_pad_sd0_strb_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_gpio61_slew + padcfg_pad_sd0_strb_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_gpio61_smt + padcfg_pad_sd0_strb_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_gpio61_pos + padcfg_pad_sd0_strb_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -24860,149 +27502,245 @@ - sys_iomux_cfgsaif_syscfg536 - SYS IOMUX CFG SAIF SYSCFG 536 - 0x218 + sys_iomux_cfgsaif_syscfg588 + SYS IOMUX CFG SAIF SYSCFG 588 + 0x24c 32 - padcfg_pad_gpio62_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver - [0:0] + padcfg_pad_gmac1_mdc_syscon + padcfg_pad_gmac1_mdc_syscon + [1:0] read-write + + + + sys_iomux_cfgsaif_syscfg592 + SYS IOMUX CFG SAIF SYSCFG 592 + 0x250 + 32 + - padcfg_pad_gpio62_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + padcfg_pad_gmac1_mdio_syscon + padcfg_pad_gmac1_mdio_syscon + [1:0] read-write + + + + sys_iomux_cfgsaif_syscfg596 + SYS IOMUX CFG SAIF SYSCFG 596 + 0x254 + 32 + - padcfg_pad_gpio62_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] + padcfg_pad_gmac1_rxd0_syscon + padcfg_pad_gmac1_rxd0_syscon + [1:0] read-write + + + + sys_iomux_cfgsaif_syscfg600 + SYS IOMUX CFG SAIF SYSCFG 600 + 0x258 + 32 + - padcfg_pad_gpio62_pd - Pull-Down (PD) settings - 1: Yes, 0: No - [4:4] + padcfg_pad_gmac1_rxd1_syscon + padcfg_pad_gmac1_rxd1_syscon + [1:0] read-write + + + + sys_iomux_cfgsaif_syscfg604 + SYS IOMUX CFG SAIF SYSCFG 604 + 0x25c + 32 + - padcfg_pad_gpio62_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] + padcfg_pad_gmac1_rxd2_syscon + padcfg_pad_gmac1_rxd2_syscon + [1:0] read-write + + + + sys_iomux_cfgsaif_syscfg608 + SYS IOMUX CFG SAIF SYSCFG 608 + 0x260 + 32 + - padcfg_pad_gpio62_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] + padcfg_pad_gmac1_rxd3_syscon + padcfg_pad_gmac1_rxd3_syscon + [1:0] read-write + + + + sys_iomux_cfgsaif_syscfg612 + SYS IOMUX CFG SAIF SYSCFG 612 + 0x264 + 32 + - padcfg_pad_gpio62_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] + padcfg_pad_gmac1_rxdv_syscon + padcfg_pad_gmac1_rxdv_syscon + [1:0] read-write - sys_iomux_cfgsaif_syscfg540 - SYS IOMUX CFG SAIF SYSCFG 540 - 0x21c + sys_iomux_cfgsaif_syscfg616 + SYS IOMUX CFG SAIF SYSCFG 616 + 0x268 32 - padcfg_pad_gpio63_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver - [0:0] + padcfg_pad_gmac1_rxc_syscon + padcfg_pad_gmac1_rxc_syscon + [1:0] read-write + + + + sys_iomux_cfgsaif_syscfg620 + SYS IOMUX CFG SAIF SYSCFG 620 + 0x26c + 32 + - padcfg_pad_gpio63_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + padcfg_pad_gmac1_txd0_syscon + padcfg_pad_gmac1_txd0_syscon + [1:0] read-write + + + + sys_iomux_cfgsaif_syscfg624 + SYS IOMUX CFG SAIF SYSCFG 624 + 0x270 + 32 + - padcfg_pad_gpio63_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] + padcfg_pad_gmac1_txd1_syscon + padcfg_pad_gmac1_txd1_syscon + [1:0] read-write + + + + sys_iomux_cfgsaif_syscfg628 + SYS IOMUX CFG SAIF SYSCFG 628 + 0x274 + 32 + - padcfg_pad_gpio63_pd - Pull-Down (PD) settings - 1: Yes, 0: No - [4:4] + padcfg_pad_gmac1_txd2_syscon + padcfg_pad_gmac1_txd2_syscon + [1:0] read-write + + + + sys_iomux_cfgsaif_syscfg632 + SYS IOMUX CFG SAIF SYSCFG 632 + 0x278 + 32 + - padcfg_pad_gpio63_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] + padcfg_pad_gmac1_txd3_syscon + padcfg_pad_gmac1_txd3_syscon + [1:0] read-write + + + + sys_iomux_cfgsaif_syscfg636 + SYS IOMUX CFG SAIF SYSCFG 636 + 0x27c + 32 + - padcfg_pad_gpio63_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] + padcfg_pad_gmac1_txen_syscon + padcfg_pad_gmac1_txen_syscon + [1:0] read-write + + + + sys_iomux_cfgsaif_syscfg640 + SYS IOMUX CFG SAIF SYSCFG 640 + 0x280 + 32 + - padcfg_pad_gpio63_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] + padcfg_pad_gmac1_txc_syscon + padcfg_pad_gmac1_txc_syscon + [1:0] read-write - sys_iomux_cfgsaif_syscfg544 - SYS IOMUX CFG SAIF SYSCFG 544 - 0x220 + sys_iomux_cfgsaif_syscfg644 + SYS IOMUX CFG SAIF SYSCFG 644 + 0x284 32 - padcfg_pad_sd0_clk_ie + padcfg_pad_qspi_sclk_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_sd0_clk_ds + padcfg_pad_qspi_sclk_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_sd0_clk_pu + padcfg_pad_qspi_sclk_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_sd0_clk_pd + padcfg_pad_qspi_sclk_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_sd0_clk_slew + padcfg_pad_qspi_sclk_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_sd0_clk_smt + padcfg_pad_qspi_sclk_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_sd0_clk_pos + padcfg_pad_qspi_sclk_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -25010,49 +27748,49 @@ - sys_iomux_cfgsaif_syscfg548 - SYS IOMUX CFG SAIF SYSCFG 548 - 0x224 + sys_iomux_cfgsaif_syscfg648 + SYS IOMUX CFG SAIF SYSCFG 648 + 0x288 32 - padcfg_pad_sd0_cmd_ie + padcfg_pad_qspi_csn0_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_sd0_cmd_ds + padcfg_pad_qspi_csn0_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_sd0_cmd_pu + padcfg_pad_qspi_csn0_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_sd0_cmd_pd + padcfg_pad_qspi_csn0_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_sd0_cmd_slew + padcfg_pad_qspi_csn0_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_sd0_cmd_smt + padcfg_pad_qspi_csn0_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_sd0_cmd_pos + padcfg_pad_qspi_csn0_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -25060,49 +27798,49 @@ - sys_iomux_cfgsaif_syscfg552 - SYS IOMUX CFG SAIF SYSCFG 552 - 0x228 + sys_iomux_cfgsaif_syscfg652 + SYS IOMUX CFG SAIF SYSCFG 652 + 0x28c 32 - padcfg_pad_sd0_data0_ie + padcfg_pad_qspi_data0_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_sd0_data0_ds + padcfg_pad_qspi_data0_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_sd0_data0_pu + padcfg_pad_qspi_data0_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_sd0_data0_pd + padcfg_pad_qspi_data0_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_sd0_data0_slew + padcfg_pad_qspi_data0_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_sd0_data0_smt + padcfg_pad_qspi_data0_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_sd0_data0_pos + padcfg_pad_qspi_data0_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -25110,49 +27848,49 @@ - sys_iomux_cfgsaif_syscfg556 - SYS IOMUX CFG SAIF SYSCFG 556 - 0x22c + sys_iomux_cfgsaif_syscfg656 + SYS IOMUX CFG SAIF SYSCFG 656 + 0x290 32 - padcfg_pad_sd0_data1_ie + padcfg_pad_qspi_data1_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_sd0_data1_ds + padcfg_pad_qspi_data1_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_sd0_data1_pu + padcfg_pad_qspi_data1_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_sd0_data1_pd + padcfg_pad_qspi_data1_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_sd0_data1_slew + padcfg_pad_qspi_data1_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_sd0_data1_smt + padcfg_pad_qspi_data1_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_sd0_data1_pos + padcfg_pad_qspi_data1_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -25160,49 +27898,49 @@ - sys_iomux_cfgsaif_syscfg560 - SYS IOMUX CFG SAIF SYSCFG 560 - 0x230 + sys_iomux_cfgsaif_syscfg660 + SYS IOMUX CFG SAIF SYSCFG 660 + 0x294 32 - padcfg_pad_sd0_data2_ie + padcfg_pad_qspi_data2_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_sd0_data2_ds + padcfg_pad_qspi_data2_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_sd0_data2_pu + padcfg_pad_qspi_data2_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_sd0_data2_pd + padcfg_pad_qspi_data2_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_sd0_data2_slew + padcfg_pad_qspi_data2_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_sd0_data2_smt + padcfg_pad_qspi_data2_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_sd0_data2_pos + padcfg_pad_qspi_data2_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -25210,49 +27948,49 @@ - sys_iomux_cfgsaif_syscfg564 - SYS IOMUX CFG SAIF SYSCFG 564 - 0x234 + sys_iomux_cfgsaif_syscfg664 + SYS IOMUX CFG SAIF SYSCFG 664 + 0x298 32 - padcfg_pad_sd0_data3_ie + padcfg_pad_qspi_data3_ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_sd0_data3_ds + padcfg_pad_qspi_data3_ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_sd0_data3_pu + padcfg_pad_qspi_data3_pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_sd0_data3_pd + padcfg_pad_qspi_data3_pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_sd0_data3_slew + padcfg_pad_qspi_data3_slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_sd0_data3_smt + padcfg_pad_qspi_data3_smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_sd0_data3_pos + padcfg_pad_qspi_data3_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -25260,1311 +27998,1593 @@ - sys_iomux_cfgsaif_syscfg568 - SYS IOMUX CFG SAIF SYSCFG 568 - 0x238 + sys_iomux_cfgsaif_syscfg668 + SYS IOMUX CFG SAIF SYSCFG 668 + 0x29c 32 - padcfg_pad_sd0_data4_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver - [0:0] + pad_gmac1_rxc_func_sel + Function selector of GMAC1_RXC: * Function 0: u0_sys_crg.clk_gmac1_rgmii_rx, * Function 1: u0_sys_crg.clk_gmac1_rmii_ref, * Function 2: None, * Function 3: None + [1:0] read-write - padcfg_pad_sd0_data4_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + pad_gpio10_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [4:2] read-write - padcfg_pad_sd0_data4_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] + pad_gpio11_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [7:5] read-write - padcfg_pad_sd0_data4_pd - Pull-Down (PD) settings - 1: Yes, 0: No - [4:4] + pad_gpio12_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [10:8] read-write - padcfg_pad_sd0_data4_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] + pad_gpio13_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [13:11] read-write - padcfg_pad_sd0_data4_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] + pad_gpio14_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [16:14] read-write - padcfg_pad_sd0_data4_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] + pad_gpio15_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [19:17] + read-write + + + pad_gpio16_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [22:20] + read-write + + + pad_gpio17_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [25:23] + read-write + + + pad_gpio18_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [28:26] + read-write + + + pad_gpio19_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [31:29] read-write - sys_iomux_cfgsaif_syscfg572 - SYS IOMUX CFG SAIF SYSCFG 572 - 0x23c + sys_iomux_cfgsaif_syscfg672 + SYS IOMUX CFG SAIF SYSCFG 672 + 0x2a0 32 - padcfg_pad_sd0_data5_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver - [0:0] + pad_gpio20_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [2:0] read-write - padcfg_pad_sd0_data5_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + pad_gpio21_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [5:3] read-write - padcfg_pad_sd0_data5_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] + pad_gpio22_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [8:6] read-write - padcfg_pad_sd0_data5_pd - Pull-Down (PD) settings - 1: Yes, 0: No - [4:4] + pad_gpio23_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [11:9] read-write - padcfg_pad_sd0_data5_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] + pad_gpio24_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [14:12] read-write - padcfg_pad_sd0_data5_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] + pad_gpio25_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [17:15] read-write - padcfg_pad_sd0_data5_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] + pad_gpio26_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [20:18] + read-write + + + pad_gpio27_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [23:21] + read-write + + + pad_gpio28_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [26:24] + read-write + + + pad_gpio29_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [29:27] read-write - sys_iomux_cfgsaif_syscfg576 - SYS IOMUX CFG SAIF SYSCFG 576 - 0x240 + sys_iomux_cfgsaif_syscfg676 + SYS IOMUX CFG SAIF SYSCFG 676 + 0x2a4 32 - padcfg_pad_sd0_data6_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver - [0:0] + pad_gpio30_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [2:0] read-write - padcfg_pad_sd0_data6_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + pad_gpio31_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [5:3] read-write - padcfg_pad_sd0_data6_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] + pad_gpio32_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [8:6] read-write - padcfg_pad_sd0_data6_pd - Pull-Down (PD) settings - 1: Yes, 0: No - [4:4] + pad_gpio33_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [11:9] read-write - padcfg_pad_sd0_data6_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] + pad_gpio34_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [14:12] read-write - padcfg_pad_sd0_data6_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] + pad_gpio35_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [17:15] read-write - padcfg_pad_sd0_data6_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] + pad_gpio36_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [20:18] read-write - - - - sys_iomux_cfgsaif_syscfg580 - SYS IOMUX CFG SAIF SYSCFG 580 - 0x244 - 32 - - padcfg_pad_sd0_data7_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver - [0:0] + pad_gpio37_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [23:21] read-write - padcfg_pad_sd0_data7_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + pad_gpio38_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [26:24] read-write - padcfg_pad_sd0_data7_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] + pad_gpio39_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [29:27] read-write - padcfg_pad_sd0_data7_pd - Pull-Down (PD) settings - 1: Yes, 0: No - [4:4] + pad_gpio40_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [32:30] + read-write + + + + + sys_iomux_cfgsaif_syscfg680 + SYS IOMUX CFG SAIF SYSCFG 680 + 0x2a8 + 32 + + + pad_gpio41_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [2:0] read-write - padcfg_pad_sd0_data7_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] + pad_gpio42_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [5:3] read-write - padcfg_pad_sd0_data7_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] + pad_gpio43_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [8:6] read-write - padcfg_pad_sd0_data7_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] + pad_gpio44_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [11:9] read-write - - - - sys_iomux_cfgsaif_syscfg584 - SYS IOMUX CFG SAIF SYSCFG 584 - 0x248 - 32 - - padcfg_pad_sd0_strb_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver - [0:0] + pad_gpio45_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [14:12] read-write - padcfg_pad_sd0_strb_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + pad_gpio46_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [17:15] read-write - padcfg_pad_sd0_strb_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] + pad_gpio47_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [20:18] read-write - padcfg_pad_sd0_strb_pd - Pull-Down (PD) settings - 1: Yes, 0: No - [4:4] + pad_gpio48_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [23:21] read-write - padcfg_pad_sd0_strb_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] + pad_gpio49_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [26:24] read-write - padcfg_pad_sd0_strb_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] + pad_gpio50_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [29:27] read-write - padcfg_pad_sd0_strb_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] + pad_gpio51_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [32:30] read-write - sys_iomux_cfgsaif_syscfg588 - SYS IOMUX CFG SAIF SYSCFG 588 - 0x24c + sys_iomux_cfgsaif_syscfg684 + SYS IOMUX CFG SAIF SYSCFG 684 + 0x2ac 32 - padcfg_pad_gmac1_mdc_syscon - padcfg_pad_gmac1_mdc_syscon + pad_gpio52_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [1:0] read-write - - - - sys_iomux_cfgsaif_syscfg592 - SYS IOMUX CFG SAIF SYSCFG 592 - 0x250 - 32 - - padcfg_pad_gmac1_mdio_syscon - padcfg_pad_gmac1_mdio_syscon - [1:0] + pad_gpio53_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [3:2] read-write - - - - sys_iomux_cfgsaif_syscfg596 - SYS IOMUX CFG SAIF SYSCFG 596 - 0x254 - 32 - - padcfg_pad_gmac1_rxd0_syscon - padcfg_pad_gmac1_rxd0_syscon - [1:0] + pad_gpio54_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [5:4] read-write - - - - sys_iomux_cfgsaif_syscfg600 - SYS IOMUX CFG SAIF SYSCFG 600 - 0x258 - 32 - - padcfg_pad_gmac1_rxd1_syscon - padcfg_pad_gmac1_rxd1_syscon - [1:0] + pad_gpio56_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [14:12] read-write - - - - sys_iomux_cfgsaif_syscfg604 - SYS IOMUX CFG SAIF SYSCFG 604 - 0x25c - 32 - - padcfg_pad_gmac1_rxd2_syscon - padcfg_pad_gmac1_rxd2_syscon - [1:0] + pad_gpio57_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [17:15] read-write - - - - sys_iomux_cfgsaif_syscfg608 - SYS IOMUX CFG SAIF SYSCFG 608 - 0x260 - 32 - - padcfg_pad_gmac1_rxd3_syscon - padcfg_pad_gmac1_rxd3_syscon - [1:0] + pad_gpio58_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [20:18] read-write - - - - sys_iomux_cfgsaif_syscfg612 - SYS IOMUX CFG SAIF SYSCFG 612 - 0x264 - 32 - - padcfg_pad_gmac1_rxdv_syscon - padcfg_pad_gmac1_rxdv_syscon - [1:0] + pad_gpio59_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [23:21] read-write - - - - sys_iomux_cfgsaif_syscfg616 - SYS IOMUX CFG SAIF SYSCFG 616 - 0x268 - 32 - - padcfg_pad_gmac1_rxc_syscon - padcfg_pad_gmac1_rxc_syscon - [1:0] + pad_gpio60_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [26:24] read-write - - - - sys_iomux_cfgsaif_syscfg620 - SYS IOMUX CFG SAIF SYSCFG 620 - 0x26c - 32 - - padcfg_pad_gmac1_txd0_syscon - padcfg_pad_gmac1_txd0_syscon - [1:0] + pad_gpio61_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [29:27] read-write - - - - sys_iomux_cfgsaif_syscfg624 - SYS IOMUX CFG SAIF SYSCFG 624 - 0x270 - 32 - - padcfg_pad_gmac1_txd1_syscon - padcfg_pad_gmac1_txd1_syscon - [1:0] + pad_gpio62_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [32:30] read-write - - - - sys_iomux_cfgsaif_syscfg628 - SYS IOMUX CFG SAIF SYSCFG 628 - 0x274 - 32 - - padcfg_pad_gmac1_txd2_syscon - padcfg_pad_gmac1_txd2_syscon - [1:0] + pad_gpio63_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [31:30] read-write - sys_iomux_cfgsaif_syscfg632 - SYS IOMUX CFG SAIF SYSCFG 632 - 0x278 + sys_iomux_cfgsaif_syscfg688 + SYS IOMUX CFG SAIF SYSCFG 688 + 0x2b0 32 - padcfg_pad_gmac1_txd3_syscon - padcfg_pad_gmac1_txd3_syscon + pad_gpio6_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [1:0] read-write - - - - sys_iomux_cfgsaif_syscfg636 - SYS IOMUX CFG SAIF SYSCFG 636 - 0x27c - 32 - - padcfg_pad_gmac1_txen_syscon - padcfg_pad_gmac1_txen_syscon - [1:0] + pad_gpio7_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [5:3] read-write - - - - sys_iomux_cfgsaif_syscfg640 - SYS IOMUX CFG SAIF SYSCFG 640 - 0x280 - 32 - - padcfg_pad_gmac1_txc_syscon - padcfg_pad_gmac1_txc_syscon - [1:0] + pad_gpio8_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [8:6] + read-write + + + pad_gpio9_func_sel + GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information + [11:9] read-write - - - - sys_iomux_cfgsaif_syscfg644 - SYS IOMUX CFG SAIF SYSCFG 644 - 0x284 - 32 - - padcfg_pad_qspi_sclk_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver - [0:0] + u0_dom_isp_top_u0_vin_dvp_data_c0_func_sel + Function Selector of DVP_DATA[idx], see Function 2 for more information + [13:11] read-write - padcfg_pad_qspi_sclk_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + u0_dom_isp_top_u0_vin_dvp_data_c10_func_sel + Function Selector of DVP_DATA[idx], see Function 2 for more information + [16:14] read-write - padcfg_pad_qspi_sclk_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] + u0_dom_isp_top_u0_vin_dvp_data_c11_func_sel + Function Selector of DVP_DATA[idx], see Function 2 for more information + [19:17] read-write - padcfg_pad_qspi_sclk_pd - Pull-Down (PD) settings - 1: Yes, 0: No - [4:4] + u0_dom_isp_top_u0_vin_dvp_data_c1_func_sel + Function Selector of DVP_DATA[idx], see Function 2 for more information + [22:20] read-write - padcfg_pad_qspi_sclk_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] + u0_dom_isp_top_u0_vin_dvp_data_c2_func_sel + Function Selector of DVP_DATA[idx], see Function 2 for more information + [25:23] read-write - padcfg_pad_qspi_sclk_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] + u0_dom_isp_top_u0_vin_dvp_data_c3_func_sel + Function Selector of DVP_DATA[idx], see Function 2 for more information + [28:26] read-write - padcfg_pad_qspi_sclk_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] + u0_dom_isp_top_u0_vin_dvp_data_c4_func_sel + Function Selector of DVP_DATA[idx], see Function 2 for more information + [31:29] read-write - sys_iomux_cfgsaif_syscfg648 - SYS IOMUX CFG SAIF SYSCFG 648 - 0x288 + sys_iomux_cfgsaif_syscfg692 + SYS IOMUX CFG SAIF SYSCFG 692 + 0x2b4 32 - padcfg_pad_qspi_csn0_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver - [0:0] + u0_dom_isp_top_u0_vin_dvp_data_c5_func_sel + Function Selector of DVP_DATA[idx], see Function 2 for more information + [2:0] read-write - padcfg_pad_qspi_csn0_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + u0_dom_isp_top_u0_vin_dvp_data_c6_func_sel + Function Selector of DVP_DATA[idx], see Function 2 for more information + [5:3] read-write - padcfg_pad_qspi_csn0_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] + u0_dom_isp_top_u0_vin_dvp_data_c7_func_sel + Function Selector of DVP_DATA[idx], see Function 2 for more information + [8:6] read-write - padcfg_pad_qspi_csn0_pd - Pull-Down (PD) settings - 1: Yes, 0: No - [4:4] + u0_dom_isp_top_u0_vin_dvp_data_c8_func_sel + Function Selector of DVP_DATA[idx], see Function 2 for more information + [11:9] read-write - padcfg_pad_qspi_csn0_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] + u0_dom_isp_top_u0_vin_dvp_data_c9_func_sel + Function Selector of DVP_DATA[idx], see Function 2 for more information + [14:12] read-write - padcfg_pad_qspi_csn0_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] + u0_dom_isp_top_u0_vin_dvp_hvalid_c_func_sel + Function Selector of DVP_HSYNC, see Function 2 for more information + [17:15] read-write - padcfg_pad_qspi_csn0_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] + u0_dom_isp_top_u0_vin_dvp_vvalid_c_func_sel + Function Selector of DVP_VSYNC, see Function 2 for more information + [20:18] + read-write + + + u0_sys_crg_dvp_clk_func_sel + Function Selector of DVP_CLK, see Function 2 for more information + [23:21] read-write + + + + starfive_jh7110_wdt_0 + From starfive,jh7110-wdt, peripheral generator + 0x13070000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_crypto_0 + From starfive,jh7110-crypto, peripheral generator + 0x16000000 + + 0 + 0x4000 + registers + + + + arm_pl080_0 + From arm,pl080, peripheral generator + 0x16008000 + + 0 + 0x4000 + registers + + + + arm_primecell_7 + From arm,primecell, peripheral generator + 0x16008000 + + 0 + 0x4000 + registers + + + + starfive_jh7110_trng_0 + From starfive,jh7110-trng, peripheral generator + 0x1600C000 + + 0 + 0x4000 + registers + + - sys_iomux_cfgsaif_syscfg652 - SYS IOMUX CFG SAIF SYSCFG 652 - 0x28c + ctrl + TRNG CTRL Register + 0x0 32 - padcfg_pad_qspi_data0_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + exec_nop + Execute a NOP instruction [0:0] read-write - padcfg_pad_qspi_data0_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + gene_randnum + Generate a random number + [1:1] read-write - padcfg_pad_qspi_data0_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] + exec_randreseed + Reseed the TRNG from noise sources + [2:2] read-write + + + + stat + TRNG STAT Register + 0x4 + 32 + - padcfg_pad_qspi_data0_pd - Pull-Down (PD) settings - 1: Yes, 0: No - [4:4] - read-write + nonce_mode + TRNG Nonce operating mode + [2:2] + read-only - padcfg_pad_qspi_data0_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] - read-write + r256 + TRNG 256-bit random number operating mode + [3:3] + read-only - padcfg_pad_qspi_data0_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] - read-write + mission_mode + TRNG Mission Mode operating mode + [8:8] + read-only - padcfg_pad_qspi_data0_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] - read-write + seeded + TRNG Seeded operating mode + [9:9] + read-only - - - - sys_iomux_cfgsaif_syscfg656 - SYS IOMUX CFG SAIF SYSCFG 656 - 0x290 - 32 - - padcfg_pad_qspi_data1_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver - [0:0] - read-write + last_reseed0 + TRNG Last Reseed 0 status + [16:16] + read-only - padcfg_pad_qspi_data1_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] - read-write + last_reseed1 + TRNG Last Reseed 1 status + [17:17] + read-only - padcfg_pad_qspi_data1_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] - read-write + last_reseed2 + TRNG Last Reseed 2 status + [18:18] + read-only - padcfg_pad_qspi_data1_pd - Pull-Down (PD) settings - 1: Yes, 0: No - [4:4] - read-write + last_reseed3 + TRNG Last Reseed 3 status + [19:19] + read-only - padcfg_pad_qspi_data1_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] - read-write + last_reseed4 + TRNG Last Reseed 4 status + [20:20] + read-only - padcfg_pad_qspi_data1_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] - read-write + last_reseed5 + TRNG Last Reseed 5 status + [21:21] + read-only - padcfg_pad_qspi_data1_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] + last_reseed6 + TRNG Last Reseed 6 status + [22:22] + read-only + + + last_reseed7 + TRNG Last Reseed 7 status + [23:23] + read-only + + + srvc_rqst + TRNG Service Request + [27:27] + read-only + + + rand_generating + TRNG Random Number Generating Status + [30:30] + read-only + + + rand_seeding + TRNG Random Number Seeding Status + [31:31] + read-only + + + + + mode + TRNG MODE Register + 0x8 + 32 + + + r256 + 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode + [3:3] read-write - sys_iomux_cfgsaif_syscfg660 - SYS IOMUX CFG SAIF SYSCFG 660 - 0x294 + smode + TRNG SMODE Register + 0xc 32 - padcfg_pad_qspi_data2_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver - [0:0] + nonce_mode + Nonce operation mode + [2:2] read-write - padcfg_pad_qspi_data2_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + mission_mode + Mission operation mode + [8:8] read-write - padcfg_pad_qspi_data2_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] + max_rejects + TRNG Maximum Rejects + [31:16] read-write + + + + ie + TRNG Interrupt Enable Register + 0x10 + 32 + - padcfg_pad_qspi_data2_pd - Pull-Down (PD) settings - 1: Yes, 0: No - [4:4] + rand_rdy_en + RAND Ready Enable + [0:0] read-write - padcfg_pad_qspi_data2_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] + seed_done_en + Seed Done Enable + [1:1] read-write - padcfg_pad_qspi_data2_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] + lfsr_lockup_en + LFSR Lockup Enable + [4:4] read-write - padcfg_pad_qspi_data2_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] + glbl_en + Global Enable + [31:31] read-write - sys_iomux_cfgsaif_syscfg664 - SYS IOMUX CFG SAIF SYSCFG 664 - 0x298 + istat + TRNG Interrupt Status Register + 0x14 32 - padcfg_pad_qspi_data3_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + rand_rdy + RAND Ready Enable [0:0] - read-write - - - padcfg_pad_qspi_data3_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] - read-write + read-only - padcfg_pad_qspi_data3_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] - read-write + seed_done + Seed Done Enable + [1:1] + read-only - padcfg_pad_qspi_data3_pd - Pull-Down (PD) settings - 1: Yes, 0: No + lfsr_lockup_en + LFSR Lockup Enable [4:4] - read-write - - - padcfg_pad_qspi_data3_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] - read-write - - - padcfg_pad_qspi_data3_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] - read-write - - - padcfg_pad_qspi_data3_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] - read-write + read-only - sys_iomux_cfgsaif_syscfg668 - SYS IOMUX CFG SAIF SYSCFG 668 - 0x29c + rand0 + TRNG RAND 0 Status Register + 0x20 32 - pad_gmac1_rxc_func_sel - Function selector of GMAC1_RXC: * Function 0: u0_sys_crg.clk_gmac1_rgmii_rx, * Function 1: u0_sys_crg.clk_gmac1_rmii_ref, * Function 2: None, * Function 3: None - [1:0] - read-write + rand + Random number bits + [31:0] + read-only + + + + rand1 + TRNG RAND 1 Status Register + 0x24 + 32 + - pad_gpio10_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [4:2] - read-write + rand + Random number bits + [31:0] + read-only + + + + rand2 + TRNG RAND 2 Status Register + 0x28 + 32 + - pad_gpio11_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [7:5] - read-write + rand + Random number bits + [31:0] + read-only + + + + rand3 + TRNG RAND 3 Status Register + 0x2c + 32 + - pad_gpio12_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [10:8] - read-write + rand + Random number bits + [31:0] + read-only + + + + rand4 + TRNG RAND 4 Status Register + 0x30 + 32 + - pad_gpio13_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [13:11] - read-write + rand + Random number bits + [31:0] + read-only + + + + rand5 + TRNG RAND 5 Status Register + 0x34 + 32 + - pad_gpio14_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [16:14] - read-write + rand + Random number bits + [31:0] + read-only + + + + rand6 + TRNG RAND 6 Status Register + 0x38 + 32 + - pad_gpio15_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [19:17] - read-write + rand + Random number bits + [31:0] + read-only + + + + rand7 + TRNG RAND 7 Status Register + 0x3c + 32 + - pad_gpio16_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [22:20] - read-write + rand + Random number bits + [31:0] + read-only + + + + auto_rqsts + Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter + 0x60 + 32 + - pad_gpio17_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [25:23] + rqsts + Threshold number of reseed requests for auto-reseed counter + [31:0] read-write + + + + auto_age + Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer + 0x64 + 32 + - pad_gpio18_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [28:26] + age + Countdown value for auto-reseed timer + [31:0] read-write + + + + + + starfive_jh7110_mmc_0 + From starfive,jh7110-mmc, peripheral generator + 0x16010000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_mmc_1 + From starfive,jh7110-mmc, peripheral generator + 0x16020000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_dwmac_0 + From starfive,jh7110-dwmac, peripheral generator + 0x16030000 + + 0 + 0x10000 + registers + + + + snps_dwmac_0 + From snps,dwmac, peripheral generator + 0x16030000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_dwmac_1 + From starfive,jh7110-dwmac, peripheral generator + 0x16040000 + + 0 + 0x10000 + registers + + + + snps_dwmac_1 + From snps,dwmac, peripheral generator + 0x16040000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_axi_dma_0 + From starfive,jh7110-axi-dma, peripheral generator + 0x16050000 + + 0 + 0x10000 + registers + + + + starfive_jh7110_aoncrg_0 + From starfive,jh7110-aoncrg, peripheral generator + 0x17000000 + + 0 + 0x10000 + registers + + + + clk_osc + Oscillator Clock + 0x0 + 32 + - pad_gpio19_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [31:29] + clk_divcfg + Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 + [23:0] read-write - sys_iomux_cfgsaif_syscfg672 - SYS IOMUX CFG SAIF SYSCFG 672 - 0x2a0 + clk_aon_apb + AON APB Function Clock + 0x4 32 - pad_gpio20_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [2:0] + clk_mux_sel + Clock multiplexing selector: clk_osc_div4, clk_osc + [29:24] read-write + + + + clk_ahb_gmac5 + AHB GMAC5 Clock + 0x8 + 32 + - pad_gpio21_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [5:3] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_axi_gmac5 + AXI GMAC5 Clock + 0xc + 32 + - pad_gpio22_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [8:6] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_gmac0_rmii_rtx + GMAC0 RMII RTX Clock + 0x10 + 32 + - pad_gpio23_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [11:9] + clk_divcfg + Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2 + [23:0] read-write + + + + clk_gmac5_axi64_tx + GMAC5 AXI64 Clock Transmitter + 0x14 + 32 + - pad_gpio24_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [14:12] + clk_mux_sel + Clock multiplexing selector: u0_sys_crg_clk_gmac0_gtxclk, clk_gmac0_rmii_rtx + [29:24] read-write + + + + clk_gmac5_axi64_txi + GMAC5 AXI64 Clock Transmission Inverter + 0x18 + 32 + - pad_gpio25_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [17:15] + clk_polarity + 1: Clock inverter, 0: Clock buffer + [30:30] read-write + + + + clk_gmac5_axi64_rx + GMAC5 AXI64 Clock Receiver + 0x1c + 32 + - pad_gpio26_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [20:18] + dly_chain_sel + Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. + [23:0] read-write + + + + clk_gmac5_axi64_rxi + GMAC5 AXI64 Clock Receiving Inverter + 0x20 + 32 + - pad_gpio27_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [23:21] + clk_polarity + 1: Clock inverter, 0: Clock buffer + [30:30] read-write + + + + clk_optc_apb + OPTC APB Clock + 0x24 + 32 + - pad_gpio28_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [26:24] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + clk_rtc_hms_apb + RTC HMS APB Clock + 0x28 + 32 + - pad_gpio29_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [29:27] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write - sys_iomux_cfgsaif_syscfg676 - SYS IOMUX CFG SAIF SYSCFG 676 - 0x2a4 + clk_rtc_internal + RTC Internal Clock + 0x2c 32 - pad_gpio30_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [2:0] + clk_divcfg + Clock divider coefficient: Max=1022, Default=750, Min=750, Typical=750 + [23:0] read-write + + + + clk_rtc_hms_osc32k + RTC HMS Clock Oscillator 32K + 0x30 + 32 + - pad_gpio31_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [5:3] + clk_mux_sel + Clock multiplexing selector: clk_rtc, clk_rtc_internal + [29:24] read-write + + + + clk_rtc_hms_cal + RTC HMS Clock Calculator + 0x34 + 32 + - pad_gpio32_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [8:6] + clk_icg + 1: Clock enable, 0: Clock disable + [31:31] read-write + + + + soft_rst_addr_sel + Software RESET Address Selector + 0x38 + 32 + - pad_gpio33_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [11:9] + gmac5_axi64_rstn_axi + 1: Assert reset, 0: De-assert reset + [0:0] read-write - pad_gpio34_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [14:12] + gmac5_axi64_rstn_ahb + 1: Assert reset, 0: De-assert reset + [1:1] read-write - pad_gpio35_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [17:15] + aon_iomux_presetn + 1: Assert reset, 0: De-assert reset + [2:2] read-write - pad_gpio36_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [20:18] + pmu_rstn_apb + 1: Assert reset, 0: De-assert reset + [3:3] read-write - pad_gpio37_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [23:21] + pmu_rstn_wkup + 1: Assert reset, 0: De-assert reset + [4:4] read-write - pad_gpio38_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [26:24] + rtc_hms_rstn_apb + 1: Assert reset, 0: De-assert reset + [5:5] read-write - pad_gpio39_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [29:27] + rtc_hms_rstn_cal + 1: Assert reset, 0: De-assert reset + [6:6] read-write - pad_gpio40_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [32:30] + rtc_hms_rstn_osc32k + 1: Assert reset, 0: De-assert reset + [7:7] read-write - sys_iomux_cfgsaif_syscfg680 - SYS IOMUX CFG SAIF SYSCFG 680 - 0x2a8 + aoncrg_rst_status + AONCRG RESET Status + 0x3c 32 - pad_gpio41_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [2:0] + gmac5_axi64_rstn_axi + 1: Assert reset, 0: De-assert reset + [0:0] read-write - pad_gpio42_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [5:3] + gmac5_axi64_rstn_ahb + 1: Assert reset, 0: De-assert reset + [1:1] read-write - pad_gpio43_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [8:6] + aon_iomux_presetn + 1: Assert reset, 0: De-assert reset + [2:2] read-write - pad_gpio44_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [11:9] + pmu_rstn_apb + 1: Assert reset, 0: De-assert reset + [3:3] read-write - pad_gpio45_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [14:12] + pmu_rstn_wkup + 1: Assert reset, 0: De-assert reset + [4:4] read-write - pad_gpio46_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [17:15] + rtc_hms_rstn_apb + 1: Assert reset, 0: De-assert reset + [5:5] read-write - pad_gpio47_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [20:18] + rtc_hms_rstn_cal + 1: Assert reset, 0: De-assert reset + [6:6] read-write - pad_gpio48_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [23:21] + rtc_hms_rstn_osc32k + 1: Assert reset, 0: De-assert reset + [7:7] read-write + + + + + + starfive_jh7110_aon_syscon_0 + From starfive,jh7110-aon-syscon, peripheral generator + 0x17010000 + + 0 + 0x1000 + registers + + + + aon_sysconsaif_syscfg0 + AON SYSCONSAIF SYSCFG 0 + 0x0 + 32 + - pad_gpio49_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [26:24] + aon_gp_reg + aon_gp_reg + [31:0] read-write + + + + aon_sysconsaif_syscfg4 + AON SYSCONSAIF SYSCFG 4 + 0x4 + 32 + - pad_gpio50_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [29:27] - read-write + u0_boot_ctrl_boot_status + u0_boot_ctrl_boot_status + [3:0] + read-only + + + + aon_sysconsaif_syscfg8 + AON SYSCONSAIF SYSCFG 8 + 0x8 + 32 + - pad_gpio51_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [32:30] - read-write + u0_boot_ctrl_boot_vector_31_0 + u0_boot_ctrl_boot_vector_31_0 + [31:0] + read-only - sys_iomux_cfgsaif_syscfg684 - SYS IOMUX CFG SAIF SYSCFG 684 - 0x2ac + aon_sysconsaif_syscfg12 + AON SYSCONSAIF SYSCFG 12 + 0xc 32 - pad_gpio52_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [1:0] - read-write + u0_boot_ctrl_boot_vector_35_32 + u0_boot_ctrl_boot_vector_35_32 + [3:0] + read-only - pad_gpio53_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [3:2] + gmac5_axi64_scfg_ram_cfg_slp + SRAM/ROM configuration. SLP: sleep enable, high active, default is low. + [4:4] read-write - pad_gpio54_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [5:4] + gmac5_axi64_scfg_ram_cfg_sram_config_sd + SRAM/ROM configuration. SD: shutdown enable, high active, default is low. + [5:5] read-write - pad_gpio56_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [14:12] + gmac5_axi64_scfg_ram_cfg_rtsel + SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. + [7:6] read-write - pad_gpio57_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [17:15] + gmac5_axi64_scfg_ram_cfg_ptsel + SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. + [9:8] read-write - pad_gpio58_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [20:18] + gmac5_axi64_scfg_ram_cfg_trb + SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. + [11:10] read-write - pad_gpio59_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [23:21] + gmac5_axi64_scfg_ram_cfg_wtsel + SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. + [13:12] read-write - pad_gpio60_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [26:24] + gmac5_axi64_scfg_ram_cfg_vs + SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. + [14:14] read-write - pad_gpio61_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [29:27] + gmac5_axi64_scfg_ram_cfg_vg + SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. + [15:15] read-write - pad_gpio62_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [32:30] - read-write + gmac5_axi64_mac_speed_o + gmac5_axi64_mac_speed_o + [17:16] + read-only - pad_gpio63_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [31:30] + gmac5_axi64_phy_intf_sel_i + Active PHY Selected. When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. Values: 0x0 - GMII or MII, 0x1 - RGMII, 0x2 - SGMII, 0x3 - TBI, 0x4 - RMII, 0x5 - RTBI, 0x6 - SMII, 0x7 - REVMII + [20:18] read-write - sys_iomux_cfgsaif_syscfg688 - SYS IOMUX CFG SAIF SYSCFG 688 - 0x2b0 + aon_sysconsaif_syscfg16 + AON SYSCONSAIF SYSCFG 16 + 0x10 32 - pad_gpio6_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [1:0] - read-write - - - pad_gpio7_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [5:3] - read-write - - - pad_gpio8_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [8:6] - read-write - - - pad_gpio9_func_sel - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information - [11:9] - read-write - - - u0_dom_isp_top_u0_vin_dvp_data_c0_func_sel - Function Selector of DVP_DATA[idx], see Function 2 for more information - [13:11] - read-write + gmac5_axi64_ptp_timestamp_o_31_0 + gmac5_axi64_ptp_timestamp_o_31_0 + [31:0] + read-only + + + + aon_sysconsaif_syscfg20 + AON SYSCONSAIF SYSCFG 20 + 0x14 + 32 + - u0_dom_isp_top_u0_vin_dvp_data_c10_func_sel - Function Selector of DVP_DATA[idx], see Function 2 for more information - [16:14] - read-write + gmac5_axi64_ptp_timestamp_o_63_32 + gmac5_axi64_ptp_timestamp_o_63_32 + [31:0] + read-only + + + + aon_sysconsaif_syscfg24 + AON SYSCONSAIF SYSCFG 24 + 0x18 + 32 + - u0_dom_isp_top_u0_vin_dvp_data_c11_func_sel - Function Selector of DVP_DATA[idx], see Function 2 for more information - [19:17] - read-write + u0_otpc_chip_mode + u0_otpc_chip_mode + [0:0] + read-only - u0_dom_isp_top_u0_vin_dvp_data_c1_func_sel - Function Selector of DVP_DATA[idx], see Function 2 for more information - [22:20] - read-write + u0_otpc_crc_pass + u0_otpc_crc_pass + [1:1] + read-only - u0_dom_isp_top_u0_vin_dvp_data_c2_func_sel - Function Selector of DVP_DATA[idx], see Function 2 for more information - [25:23] - read-write + u0_otpc_dbg_enable + u0_otpc_dbg_enable + [2:2] + read-only + + + + aon_sysconsaif_syscfg28 + AON SYSCONSAIF SYSCFG 28 + 0x1c + 32 + - u0_dom_isp_top_u0_vin_dvp_data_c3_func_sel - Function Selector of DVP_DATA[idx], see Function 2 for more information - [28:26] - read-write + u0_otpc_fl_func_lock + u0_otpc_fl_func_lock + [31:0] + read-only + + + + aon_sysconsaif_syscfg32 + AON SYSCONSAIF SYSCFG 32 + 0x20 + 32 + - u0_dom_isp_top_u0_vin_dvp_data_c4_func_sel - Function Selector of DVP_DATA[idx], see Function 2 for more information - [31:29] - read-write + u0_otpc_fl_pll0_lock + u0_otpc_fl_pll0_lock + [31:0] + read-only - sys_iomux_cfgsaif_syscfg692 - SYS IOMUX CFG SAIF SYSCFG 692 - 0x2b4 + aon_sysconsaif_syscfg36 + AON SYSCONSAIF SYSCFG 36 + 0x24 32 - u0_dom_isp_top_u0_vin_dvp_data_c5_func_sel - Function Selector of DVP_DATA[idx], see Function 2 for more information - [2:0] - read-write + u0_otpc_fl_pll1_lock + u0_otpc_fl_pll1_lock + [31:0] + read-only + + + + aon_sysconsaif_syscfg40 + AON SYSCONSAIF SYSCFG 40 + 0x28 + 32 + - u0_dom_isp_top_u0_vin_dvp_data_c6_func_sel - Function Selector of DVP_DATA[idx], see Function 2 for more information - [5:3] - read-write + u0_otpc_fl_sec_boot_lmt + u0_otpc_fl_sec_boot_lmt + [0:0] + read-only - u0_dom_isp_top_u0_vin_dvp_data_c7_func_sel - Function Selector of DVP_DATA[idx], see Function 2 for more information - [8:6] - read-write + u0_otpc_fl_xip + u0_otpc_fl_xip + [1:1] + read-only - u0_dom_isp_top_u0_vin_dvp_data_c8_func_sel - Function Selector of DVP_DATA[idx], see Function 2 for more information - [11:9] - read-write + u0_otpc_load_busy + u0_otpc_load_busy + [2:2] + read-only - u0_dom_isp_top_u0_vin_dvp_data_c9_func_sel - Function Selector of DVP_DATA[idx], see Function 2 for more information - [14:12] + u0_reset_ctrl_clr_reset_status + u0_reset_ctrl_clr_reset_status + [3:3] read-write - u0_dom_isp_top_u0_vin_dvp_hvalid_c_func_sel - Function Selector of DVP_HSYNC, see Function 2 for more information - [17:15] - read-write + u0_reset_ctrl_pll_timecnt_finish + u0_reset_ctrl_pll_timecnt_finish + [4:4] + read-only - u0_dom_isp_top_u0_vin_dvp_vvalid_c_func_sel - Function Selector of DVP_VSYNC, see Function 2 for more information - [20:18] + u0_reset_ctrl_rstn_sw + u0_reset_ctrl_rstn_sw + [5:5] read-write - u0_sys_crg_dvp_clk_func_sel - Function Selector of DVP_CLK, see Function 2 for more information - [23:21] - read-write + u0_reset_ctrl_sys_reset_status + u0_reset_ctrl_sys_reset_status + [9:6] + read-only - snps_dw_mshc_0 - From snps,dw-mshc, peripheral generator - 0x16010000 - - 0 - 0x10000 - registers - - - - snps_dw_mshc_1 - From snps,dw-mshc, peripheral generator - 0x16020000 - - 0 - 0x10000 - registers - - - - starfive_jh7110_dwmac_0 - From starfive,jh7110-dwmac, peripheral generator - 0x16030000 - - 0 - 0x10000 - registers - - - - snps_dwmac_5_20_0 - From snps,dwmac-5_20, peripheral generator - 0x16030000 - - 0 - 0x10000 - registers - - - - starfive_jh7110_dwmac_1 - From starfive,jh7110-dwmac, peripheral generator - 0x16040000 - - 0 - 0x10000 - registers - - - - snps_dwmac_5_20_1 - From snps,dwmac-5_20, peripheral generator - 0x16040000 + syscon_2 + From syscon, peripheral generator + 0x17010000 0 - 0x10000 + 0x1000 registers - starfive_jh7110_aoncrg_0 - From starfive,jh7110-aoncrg, peripheral generator - 0x17000000 + starfive_jh7110_aon_pinctrl_0 + From starfive,jh7110-aon-pinctrl, peripheral generator + 0x17020000 0 0x10000 @@ -26572,1342 +29592,1372 @@ - clk_osc - Oscillator Clock + aon_iomux_cfgsaif_syscfg_fmux0 + AON IOMUX CFG SAIF SYSCFG FMUX 0 0x0 32 - clk_divcfg - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 - [23:0] + aon_iomux_gpo0_doen_cfg + The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. + [2:0] read-write - - - - clk_aon_apb - AON APB Function Clock - 0x4 - 32 - - clk_mux_sel - Clock multiplexing selector: clk_osc_div4, clk_osc - [29:24] + aon_iomux_gpo1_doen_cfg + The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. + [10:8] read-write - - - - clk_ahb_gmac5 - AHB GMAC5 Clock - 0x8 - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + aon_iomux_gpo2_doen_cfg + The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. + [18:16] read-write - - - - clk_axi_gmac5 - AXI GMAC5 Clock - 0xc - 32 - - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + aon_iomux_gpo3_doen_cfg + The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. + [26:24] read-write - clk_gmac0_rmii_rtx - GMAC0 RMII RTX Clock - 0x10 + aon_iomux_cfgsaif_syscfg_fmux1 + AON IOMUX CFG SAIF SYSCFG FMUX 1 + 0x4 32 - clk_divcfg - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2 - [23:0] + aon_iomux_gpo0_dout_cfg + The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. + [3:0] + read-write + + + aon_iomux_gpo1_dout_cfg + The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. + [11:8] + read-write + + + aon_iomux_gpo2_dout_cfg + The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. + [19:16] + read-write + + + aon_iomux_gpo3_dout_cfg + The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. + [27:24] read-write - clk_gmac5_axi64_tx - GMAC5 AXI64 Clock Transmitter - 0x14 + aon_iomux_cfgsaif_syscfg_fmux2 + AON IOMUX CFG SAIF SYSCFG FMUX 2 + 0x8 32 - clk_mux_sel - Clock multiplexing selector: u0_sys_crg_clk_gmac0_gtxclk, clk_gmac0_rmii_rtx - [29:24] + aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg + The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. + [2:0] read-write - - - - clk_gmac5_axi64_txi - GMAC5 AXI64 Clock Transmission Inverter - 0x18 - 32 - - clk_polarity - 1: Clock inverter, 0: Clock buffer - [30:30] + aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg + The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. + [10:8] read-write - - - - clk_gmac5_axi64_rx - GMAC5 AXI64 Clock Receiver - 0x1c - 32 - - dly_chain_sel - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. - [23:0] + aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg + The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. + [18:16] read-write - - - - clk_gmac5_axi64_rxi - GMAC5 AXI64 Clock Receiving Inverter - 0x20 - 32 - - clk_polarity - 1: Clock inverter, 0: Clock buffer - [30:30] + aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg + The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. + [26:24] read-write - clk_optc_apb - OPTC APB Clock - 0x24 + aon_iomux_cfgsaif_syscfg_fmux3 + AON IOMUX CFG SAIF SYSCFG FMUX 3 + 0xc 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + aon_gpioen_0_reg + Enable GPIO IRQ function. + [0:0] read-write - clk_rtc_hms_apb - RTC HMS APB Clock - 0x28 + aon_iomux_cfgsaif_syscfg_ioirq4 + AON IOMUX CFG SAIF SYSCFG IOIRQ 4 + 0x10 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + aon_gpiois_0_reg + 1: Edge trigger, 0: Level trigger + [3:0] read-write - clk_rtc_internal - RTC Internal Clock - 0x2c + aon_iomux_cfgsaif_syscfg_ioirq5 + AON IOMUX CFG SAIF SYSCFG IOIRQ 5 + 0x14 32 - clk_divcfg - Clock divider coefficient: Max=1022, Default=750, Min=750, Typical=750 - [23:0] + aon_gpioic_0_reg + 1: Do not clear the register, 0: Clear the register + [3:0] read-write - clk_rtc_hms_osc32k - RTC HMS Clock Oscillator 32K - 0x30 + aon_iomux_cfgsaif_syscfg_ioirq6 + AON IOMUX CFG SAIF SYSCFG IOIRQ 6 + 0x18 32 - clk_mux_sel - Clock multiplexing selector: clk_rtc, clk_rtc_internal - [29:24] + aon_gpioibe_0_reg + 1: Trigger on both edges, 0: Trigger on a single edge + [3:0] read-write - clk_rtc_hms_cal - RTC HMS Clock Calculator - 0x34 + aon_iomux_cfgsaif_syscfg_ioirq7 + AON IOMUX CFG SAIF SYSCFG IOIRQ 7 + 0x1c 32 - clk_icg - 1: Clock enable, 0: Clock disable - [31:31] + aon_gpioiev_0_reg + 1: Positive/Low, 0: Negative/High + [3:0] read-write - soft_rst_addr_sel - Software RESET Address Selector - 0x38 + aon_iomux_cfgsaif_syscfg_ioirq8 + AON IOMUX CFG SAIF SYSCFG IOIRQ 8 + 0x20 32 - gmac5_axi64_rstn_axi - 1: Assert reset, 0: De-assert reset - [0:0] - read-write - - - gmac5_axi64_rstn_ahb - 1: Assert reset, 0: De-assert reset - [1:1] - read-write - - - aon_iomux_presetn - 1: Assert reset, 0: De-assert reset - [2:2] - read-write - - - pmu_rstn_apb - 1: Assert reset, 0: De-assert reset - [3:3] - read-write - - - pmu_rstn_wkup - 1: Assert reset, 0: De-assert reset - [4:4] - read-write - - - rtc_hms_rstn_apb - 1: Assert reset, 0: De-assert reset - [5:5] - read-write - - - rtc_hms_rstn_cal - 1: Assert reset, 0: De-assert reset - [6:6] - read-write - - - rtc_hms_rstn_osc32k - 1: Assert reset, 0: De-assert reset - [7:7] + aon_gpioie_0_reg + 1: Unmask, 0: Mask + [3:0] read-write - aoncrg_rst_status - AONCRG RESET Status - 0x3c + aon_iomux_cfgsaif_syscfg_ioirq9 + AON IOMUX CFG SAIF SYSCFG IOIRQ 9 + 0x24 32 - gmac5_axi64_rstn_axi - 1: Assert reset, 0: De-assert reset - [0:0] - read-write - - - gmac5_axi64_rstn_ahb - 1: Assert reset, 0: De-assert reset - [1:1] - read-write - - - aon_iomux_presetn - 1: Assert reset, 0: De-assert reset - [2:2] - read-write - - - pmu_rstn_apb - 1: Assert reset, 0: De-assert reset - [3:3] - read-write - - - pmu_rstn_wkup - 1: Assert reset, 0: De-assert reset - [4:4] - read-write - - - rtc_hms_rstn_apb - 1: Assert reset, 0: De-assert reset - [5:5] - read-write - - - rtc_hms_rstn_cal - 1: Assert reset, 0: De-assert reset - [6:6] - read-write - - - rtc_hms_rstn_osc32k - 1: Assert reset, 0: De-assert reset - [7:7] - read-write + aon_gpioris_0_reg + Status of the edge trigger, can be cleared by writing gpioic. + [3:0] + read-only - - - - starfive_jh7110_aon_syscon_0 - From starfive,jh7110-aon-syscon, peripheral generator - 0x17010000 - - 0 - 0x1000 - registers - - - aon_sysconsaif_syscfg0 - AON SYSCONSAIF SYSCFG 0 - 0x0 - 32 - - - aon_gp_reg - aon_gp_reg - [31:0] - read-write + aon_iomux_cfgsaif_syscfg_ioirq10 + AON IOMUX CFG SAIF SYSCFG IOIRQ 10 + 0x28 + 32 + + + aon_gpiomis_0_reg + The masked GPIO IRQ status. + [3:0] + read-only - aon_sysconsaif_syscfg4 - AON SYSCONSAIF SYSCFG 4 - 0x4 + aon_iomux_cfgsaif_syscfg_ioirq11 + AON IOMUX CFG SAIF SYSCFG IOIRQ 11 + 0x2c 32 - u0_boot_ctrl_boot_status - u0_boot_ctrl_boot_status + aon_gpio_in_sync2_0_reg + Status of gpio_in after synchronization. [3:0] read-only - aon_sysconsaif_syscfg8 - AON SYSCONSAIF SYSCFG 8 - 0x8 + aon_iomux_cfgsaif_syscfg48 + AON IOMUX CFG SAIF SYSCFG 48 + 0x30 32 - u0_boot_ctrl_boot_vector_31_0 - u0_boot_ctrl_boot_vector_31_0 - [31:0] - read-only + padcfg_pad_testen_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [0:0] + read-write - aon_sysconsaif_syscfg12 - AON SYSCONSAIF SYSCFG 12 - 0xc + aon_iomux_cfgsaif_syscfg52 + AON IOMUX CFG SAIF SYSCFG 52 + 0x34 32 - u0_boot_ctrl_boot_vector_35_32 - u0_boot_ctrl_boot_vector_35_32 - [3:0] - read-only + padcfg_pad_rgpio0_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] + read-write - gmac5_axi64_scfg_ram_cfg_slp - SRAM/ROM configuration. SLP: sleep enable, high active, default is low. + padcfg_pad_rgpio0_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] + read-write + + + padcfg_pad_rgpio0_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] + read-write + + + padcfg_pad_rgpio0_pd + Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - gmac5_axi64_scfg_ram_cfg_sram_config_sd - SRAM/ROM configuration. SD: shutdown enable, high active, default is low. + padcfg_pad_rgpio0_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - gmac5_axi64_scfg_ram_cfg_rtsel - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. - [7:6] + padcfg_pad_rgpio0_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] read-write - gmac5_axi64_scfg_ram_cfg_ptsel - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. - [9:8] + padcfg_pad_rgpio0_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] read-write + + + + aon_iomux_cfgsaif_syscfg56 + AON IOMUX CFG SAIF SYSCFG 56 + 0x38 + 32 + - gmac5_axi64_scfg_ram_cfg_trb - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. - [11:10] + padcfg_pad_rgpio1_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] read-write - gmac5_axi64_scfg_ram_cfg_wtsel - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. - [13:12] + padcfg_pad_rgpio1_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] read-write - gmac5_axi64_scfg_ram_cfg_vs - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. - [14:14] + padcfg_pad_rgpio1_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] read-write - gmac5_axi64_scfg_ram_cfg_vg - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. - [15:15] + padcfg_pad_rgpio1_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] read-write - gmac5_axi64_mac_speed_o - gmac5_axi64_mac_speed_o - [17:16] - read-only + padcfg_pad_rgpio1_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] + read-write - gmac5_axi64_phy_intf_sel_i - Active PHY Selected. When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. Values: 0x0 - GMII or MII, 0x1 - RGMII, 0x2 - SGMII, 0x3 - TBI, 0x4 - RMII, 0x5 - RTBI, 0x6 - SMII, 0x7 - REVMII - [20:18] + padcfg_pad_rgpio1_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] read-write - - - - aon_sysconsaif_syscfg16 - AON SYSCONSAIF SYSCFG 16 - 0x10 - 32 - - gmac5_axi64_ptp_timestamp_o_31_0 - gmac5_axi64_ptp_timestamp_o_31_0 - [31:0] - read-only + padcfg_pad_rgpio1_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] + read-write - aon_sysconsaif_syscfg20 - AON SYSCONSAIF SYSCFG 20 - 0x14 + aon_iomux_cfgsaif_syscfg60 + AON IOMUX CFG SAIF SYSCFG 60 + 0x3c 32 - gmac5_axi64_ptp_timestamp_o_63_32 - gmac5_axi64_ptp_timestamp_o_63_32 - [31:0] - read-only + padcfg_pad_rgpio2_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + [0:0] + read-write - - - - aon_sysconsaif_syscfg24 - AON SYSCONSAIF SYSCFG 24 - 0x18 - 32 - - u0_otpc_chip_mode - u0_otpc_chip_mode - [0:0] - read-only + padcfg_pad_rgpio2_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] + read-write - u0_otpc_crc_pass - u0_otpc_crc_pass - [1:1] - read-only + padcfg_pad_rgpio2_pu + Pull-Up (PU) settings - 1: Yes, 0: No + [3:3] + read-write - u0_otpc_dbg_enable - u0_otpc_dbg_enable - [2:2] - read-only + padcfg_pad_rgpio2_pd + Pull-Down (PD) settings - 1: Yes, 0: No + [4:4] + read-write - - - - aon_sysconsaif_syscfg28 - AON SYSCONSAIF SYSCFG 28 - 0x1c - 32 - - u0_otpc_fl_func_lock - u0_otpc_fl_func_lock - [31:0] - read-only + padcfg_pad_rgpio2_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast + [5:5] + read-write - - - - aon_sysconsaif_syscfg32 - AON SYSCONSAIF SYSCFG 32 - 0x20 - 32 - - u0_otpc_fl_pll0_lock - u0_otpc_fl_pll0_lock - [31:0] - read-only + padcfg_pad_rgpio2_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] + read-write - - - - aon_sysconsaif_syscfg36 - AON SYSCONSAIF SYSCFG 36 - 0x24 - 32 - - u0_otpc_fl_pll1_lock - u0_otpc_fl_pll1_lock - [31:0] - read-only + padcfg_pad_rgpio2_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] + read-write - aon_sysconsaif_syscfg40 - AON SYSCONSAIF SYSCFG 40 - 0x28 + aon_iomux_cfgsaif_syscfg64 + AON IOMUX CFG SAIF SYSCFG 64 + 0x40 32 - u0_otpc_fl_sec_boot_lmt - u0_otpc_fl_sec_boot_lmt + padcfg_pad_rgpio3_ie + Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] - read-only - - - u0_otpc_fl_xip - u0_otpc_fl_xip - [1:1] - read-only + read-write - - u0_otpc_load_busy - u0_otpc_load_busy - [2:2] - read-only + + padcfg_pad_rgpio3_ds + Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA + [2:1] + read-write - u0_reset_ctrl_clr_reset_status - u0_reset_ctrl_clr_reset_status + padcfg_pad_rgpio3_pu + Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - u0_reset_ctrl_pll_timecnt_finish - u0_reset_ctrl_pll_timecnt_finish + padcfg_pad_rgpio3_pd + Pull-Down (PD) settings - 1: Yes, 0: No [4:4] - read-only + read-write - u0_reset_ctrl_rstn_sw - u0_reset_ctrl_rstn_sw + padcfg_pad_rgpio3_slew + Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - u0_reset_ctrl_sys_reset_status - u0_reset_ctrl_sys_reset_status - [9:6] - read-only + padcfg_pad_rgpio3_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + [6:6] + read-write + + + padcfg_pad_rgpio3_pos + Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + [7:7] + read-write - - - - syscon_2 - From syscon, peripheral generator - 0x17010000 - - 0 - 0x1000 - registers - - - - starfive_jh7110_aon_pinctrl_0 - From starfive,jh7110-aon-pinctrl, peripheral generator - 0x17020000 - - 0 - 0x10000 - registers - - - aon_iomux_cfgsaif_syscfg_fmux0 - AON IOMUX CFG SAIF SYSCFG FMUX 0 - 0x0 + aon_iomux_cfgsaif_syscfg68 + AON IOMUX CFG SAIF SYSCFG 68 + 0x44 32 - aon_iomux_gpo0_doen_cfg - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. - [2:0] - read-write - - - aon_iomux_gpo1_doen_cfg - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. - [10:8] - read-write - - - aon_iomux_gpo2_doen_cfg - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. - [18:16] + padcfg_pad_rstn_smt + Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled + [0:0] read-write - aon_iomux_gpo3_doen_cfg - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. - [26:24] + padcfg_pad_rstn_pos + Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled + [1:1] read-write - aon_iomux_cfgsaif_syscfg_fmux1 - AON IOMUX CFG SAIF SYSCFG FMUX 1 - 0x4 + aon_iomux_cfgsaif_syscfg76 + AON IOMUX CFG SAIF SYSCFG 76 + 0x4c 32 - aon_iomux_gpo0_dout_cfg - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. - [3:0] - read-write - - - aon_iomux_gpo1_dout_cfg - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. - [11:8] + padcfg_pad_rtc_ds + Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA. + [1:0] read-write + + + + aon_iomux_cfgsaif_syscfg84 + AON IOMUX CFG SAIF SYSCFG 84 + 0x54 + 32 + - aon_iomux_gpo2_dout_cfg - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. - [19:16] + padcfg_pad_osc_ds + Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA. + [1:0] read-write + + + + aon_iomux_cfgsaif_syscfg88 + AON IOMUX CFG SAIF SYSCFG 88 + 0x58 + 32 + - aon_iomux_gpo3_dout_cfg - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. - [27:24] + padcfg_pad_gmac0_mdc_syscon + padcfg_pad_gmac0_mdc_syscon + [1:0] read-write - aon_iomux_cfgsaif_syscfg_fmux2 - AON IOMUX CFG SAIF SYSCFG FMUX 2 - 0x8 + aon_iomux_cfgsaif_syscfg92 + AON IOMUX CFG SAIF SYSCFG 92 + 0x5c 32 - aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. - [2:0] + padcfg_pad_gmac0_mdio_syscon + padcfg_pad_gmac0_mdio_syscon + [1:0] read-write + + + + aon_iomux_cfgsaif_syscfg96 + AON IOMUX CFG SAIF SYSCFG 96 + 0x60 + 32 + - aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. - [10:8] + padcfg_pad_gmac0_rxd0_syscon + 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V + [1:0] read-write + + + + aon_iomux_cfgsaif_syscfg100 + AON IOMUX CFG SAIF SYSCFG 100 + 0x64 + 32 + - aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. - [18:16] + padcfg_pad_gmac0_rxd1_syscon + padcfg_pad_gmac0_rxd1_syscon + [1:0] read-write + + + + aon_iomux_cfgsaif_syscfg104 + AON IOMUX CFG SAIF SYSCFG 104 + 0x68 + 32 + - aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. - [26:24] + padcfg_pad_gmac0_rxd2_syscon + padcfg_pad_gmac0_rxd2_syscon + [1:0] read-write - aon_iomux_cfgsaif_syscfg_fmux3 - AON IOMUX CFG SAIF SYSCFG FMUX 3 - 0xc + aon_iomux_cfgsaif_syscfg108 + AON IOMUX CFG SAIF SYSCFG 108 + 0x6c 32 - aon_gpioen_0_reg - Enable GPIO IRQ function. - [0:0] + padcfg_pad_gmac0_rxd3_syscon + padcfg_pad_gmac0_rxd3_syscon + [1:0] read-write - aon_iomux_cfgsaif_syscfg_ioirq4 - AON IOMUX CFG SAIF SYSCFG IOIRQ 4 - 0x10 + aon_iomux_cfgsaif_syscfg112 + AON IOMUX CFG SAIF SYSCFG 112 + 0x70 32 - aon_gpiois_0_reg - 1: Edge trigger, 0: Level trigger - [3:0] + padcfg_pad_gmac0_rxdv_syscon + padcfg_pad_gmac0_rxdv_syscon + [1:0] read-write - aon_iomux_cfgsaif_syscfg_ioirq5 - AON IOMUX CFG SAIF SYSCFG IOIRQ 5 - 0x14 + aon_iomux_cfgsaif_syscfg116 + AON IOMUX CFG SAIF SYSCFG 116 + 0x74 32 - aon_gpioic_0_reg - 1: Do not clear the register, 0: Clear the register - [3:0] + padcfg_pad_gmac0_rxc_syscon + padcfg_pad_gmac0_rxc_syscon + [1:0] read-write - aon_iomux_cfgsaif_syscfg_ioirq6 - AON IOMUX CFG SAIF SYSCFG IOIRQ 6 - 0x18 + aon_iomux_cfgsaif_syscfg120 + AON IOMUX CFG SAIF SYSCFG 120 + 0x78 32 - aon_gpioibe_0_reg - 1: Trigger on both edges, 0: Trigger on a single edge - [3:0] + padcfg_pad_gmac0_txd0_syscon + padcfg_pad_gmac0_txd0_syscon + [1:0] read-write - aon_iomux_cfgsaif_syscfg_ioirq7 - AON IOMUX CFG SAIF SYSCFG IOIRQ 7 - 0x1c + aon_iomux_cfgsaif_syscfg124 + AON IOMUX CFG SAIF SYSCFG 124 + 0x7c 32 - aon_gpioiev_0_reg - 1: Positive/Low, 0: Negative/High - [3:0] + padcfg_pad_gmac0_txd1_syscon + padcfg_pad_gmac0_txd1_syscon + [1:0] read-write - aon_iomux_cfgsaif_syscfg_ioirq8 - AON IOMUX CFG SAIF SYSCFG IOIRQ 8 - 0x20 + aon_iomux_cfgsaif_syscfg128 + AON IOMUX CFG SAIF SYSCFG 128 + 0x80 32 - aon_gpioie_0_reg - 1: Unmask, 0: Mask - [3:0] + padcfg_pad_gmac0_txd2_syscon + padcfg_pad_gmac0_txd2_syscon + [1:0] read-write - aon_iomux_cfgsaif_syscfg_ioirq9 - AON IOMUX CFG SAIF SYSCFG IOIRQ 9 - 0x24 + aon_iomux_cfgsaif_syscfg132 + AON IOMUX CFG SAIF SYSCFG 132 + 0x84 32 - aon_gpioris_0_reg - Status of the edge trigger, can be cleared by writing gpioic. - [3:0] - read-only + padcfg_pad_gmac0_txd3_syscon + padcfg_pad_gmac0_txd3_syscon + [1:0] + read-write - aon_iomux_cfgsaif_syscfg_ioirq10 - AON IOMUX CFG SAIF SYSCFG IOIRQ 10 - 0x28 + aon_iomux_cfgsaif_syscfg136 + AON IOMUX CFG SAIF SYSCFG 136 + 0x88 32 - aon_gpiomis_0_reg - The masked GPIO IRQ status. - [3:0] - read-only + padcfg_pad_gmac0_txen_syscon + padcfg_pad_gmac0_txen_syscon + [1:0] + read-write - aon_iomux_cfgsaif_syscfg_ioirq11 - AON IOMUX CFG SAIF SYSCFG IOIRQ 11 - 0x2c + aon_iomux_cfgsaif_syscfg140 + AON IOMUX CFG SAIF SYSCFG 140 + 0x8c 32 - aon_gpio_in_sync2_0_reg - Status of gpio_in after synchronization. - [3:0] - read-only + padcfg_pad_gmac0_txc_syscon + padcfg_pad_gmac0_txc_syscon + [1:0] + read-write - aon_iomux_cfgsaif_syscfg48 - AON IOMUX CFG SAIF SYSCFG 48 - 0x30 + aon_iomux_cfgsaif_syscfg144 + AON IOMUX CFG SAIF SYSCFG 144 + 0x90 32 - padcfg_pad_testen_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [0:0] + pad_gmac0_rxc_func_sel + Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None + [1:0] read-write + + + + starfive_jh7110_pmu_0 + From starfive,jh7110-pmu, peripheral generator + 0x17030000 + + 0 + 0x10000 + registers + + - aon_iomux_cfgsaif_syscfg52 - AON IOMUX CFG SAIF SYSCFG 52 - 0x34 + hard_event_turn_on_mask + Hardware Event Turn-On Mask + 0x4 32 - padcfg_pad_rgpio0_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + hard_event_0_on_mask + RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event [0:0] read-write - padcfg_pad_rgpio0_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + hard_event_1_on_mask + GMAC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event + [1:1] read-write - padcfg_pad_rgpio0_pu - Pull-Up (PU) settings - 1: Yes, 0: No + hard_event_2_on_mask + RFU, 1: mask hardware event, 0: enable hardware event + [2:2] + read-write + + + hard_event_3_on_mask + RGPIO0 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event [3:3] read-write - padcfg_pad_rgpio0_pd - Pull-Down (PD) settings - 1: Yes, 0: No + hard_event_4_on_mask + RGPIO1 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event [4:4] read-write - padcfg_pad_rgpio0_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast + hard_event_5_on_mask + RGPIO2 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event [5:5] read-write - padcfg_pad_rgpio0_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + hard_event_6_on_mask + RGPIO3 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event [6:6] read-write - padcfg_pad_rgpio0_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled + hard_event_7_on_mask + GPU event, 1: mask hardware event, 0: enable hardware event [7:7] read-write - aon_iomux_cfgsaif_syscfg56 - AON IOMUX CFG SAIF SYSCFG 56 - 0x38 + soft_turn_on_power_mode + Software Turn-On Power Mode + 0xc 32 - padcfg_pad_rgpio1_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + systop_power_mode + SYSTOP turn-on power mode. [0:0] read-write - padcfg_pad_rgpio1_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + cpu_power_mode + CPU turn-on power mode. + [1:1] read-write - padcfg_pad_rgpio1_pu - Pull-Up (PU) settings - 1: Yes, 0: No + gpua_power_mode + GPUA turn-on power mode. + [2:2] + read-write + + + vdec_power_mode + VDEC turn-on power mode. [3:3] read-write - padcfg_pad_rgpio1_pd - Pull-Down (PD) settings - 1: Yes, 0: No + vout_power_mode + VOUT turn-on power mode. [4:4] read-write - padcfg_pad_rgpio1_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast + isp_power_mode + ISP turn-on power mode. [5:5] read-write - padcfg_pad_rgpio1_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + venc_power_mode + VENC turn-on power mode. [6:6] read-write - - padcfg_pad_rgpio1_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] - read-write - - aon_iomux_cfgsaif_syscfg60 - AON IOMUX CFG SAIF SYSCFG 60 - 0x3c + soft_turn_off_power_mode + Software Turn-Off Power Mode + 0x10 32 - padcfg_pad_rgpio2_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver + systop_power_mode + SYSTOP turn-off power mode. [0:0] read-write - padcfg_pad_rgpio2_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + cpu_power_mode + CPU turn-off power mode. + [1:1] read-write - padcfg_pad_rgpio2_pu - Pull-Up (PU) settings - 1: Yes, 0: No + gpua_power_mode + GPUA turn-off power mode. + [2:2] + read-write + + + vdec_power_mode + VDEC turn-off power mode. [3:3] read-write - padcfg_pad_rgpio2_pd - Pull-Down (PD) settings - 1: Yes, 0: No + vout_power_mode + VOUT turn-off power mode. [4:4] read-write - padcfg_pad_rgpio2_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast + isp_power_mode + ISP turn-off power mode. [5:5] read-write - padcfg_pad_rgpio2_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled + venc_power_mode + VENC turn-off power mode. [6:6] read-write + + + + timeout_seq_thd + Threshold Sequence Timeout + 0x14 + 32 + - padcfg_pad_rgpio2_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] + timeout_seq_thd + Threshold Sequence Timeout + [15:0] read-write - aon_iomux_cfgsaif_syscfg64 - AON IOMUX CFG SAIF SYSCFG 64 - 0x40 + pdc0 + Powerdomain Cascade 0 + 0x18 32 - padcfg_pad_rgpio3_ie - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver - [0:0] + pd0_off_cas + Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [4:0] read-write - padcfg_pad_rgpio3_ds - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA - [2:1] + pd0_on_cas + Power domain 0 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [9:5] read-write - padcfg_pad_rgpio3_pu - Pull-Up (PU) settings - 1: Yes, 0: No - [3:3] + pd1_off_cas + Power domain 1 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [14:10] read-write - padcfg_pad_rgpio3_pd - Pull-Down (PD) settings - 1: Yes, 0: No - [4:4] + pd1_on_cas + Power domain 1 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [19:15] read-write - padcfg_pad_rgpio3_slew - Slew Rate Control - 0: Slow (Half frequency), 1: Fast - [5:5] + pd2_off_cas + Power domain 2 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [24:20] + read-write + + + pd2_on_cas + Power domain 2 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [29:25] + read-write + + + + + pdc1 + Powerdomain Cascade 1 + 0x1c + 32 + + + pd3_off_cas + Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [4:0] + read-write + + + pd3_on_cas + Power domain 3 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [9:5] + read-write + + + pd4_off_cas + Power domain 4 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [14:10] + read-write + + + pd4_on_cas + Power domain 4 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [19:15] + read-write + + + pd5_off_cas + Power domain 5 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [24:20] + read-write + + + pd5_on_cas + Power domain 5 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [29:25] + read-write + + + + + pdc2 + Powerdomain Cascade 2 + 0x20 + 32 + + + pd6_off_cas + Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [4:0] + read-write + + + pd6_on_cas + Power domain 6 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [9:5] + read-write + + + pd7_off_cas + Power domain 7 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [14:10] + read-write + + + pd7_on_cas + Power domain 7 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [19:15] + read-write + + + pd8_off_cas + Power domain 8 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [24:20] + read-write + + + pd8_on_cas + Power domain 8 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. + [29:25] + read-write + + + + + sw_encourage + Software Encouragement + 0x44 + 32 + + + sw_encourage + Software Encouragement + [7:0] + read-write + + + + + tim + TIMER Interrupt Mask + 0x48 + 32 + + + seq_done_mask + Mask the sequence complete event. 0: mask, 1: unmask + [0:0] + read-write + + + hw_req_mask + Mask the hardware encouragement request. 0: mask, 1: unmask + [1:1] + read-write + + + sw_fail_mask + Mask the software encouragement failure event. 0: mask, 1: unmask + [3:2] read-write - padcfg_pad_rgpio3_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled - [6:6] + hw_fail_mask + Mask the hardware encouragement failure event. 0: mask, 1: unmask + [5:4] read-write - padcfg_pad_rgpio3_pos - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled - [7:7] + pch_fail_mask + Mask the P-channel encouragement failure event. 0: mask, 1: unmask + [8:6] read-write - aon_iomux_cfgsaif_syscfg68 - AON IOMUX CFG SAIF SYSCFG 68 - 0x44 + pch_bypass + P-channel Bypass + 0x4c 32 - padcfg_pad_rstn_smt - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled + pch_bypass + Bypass P-channel. 0: enable p-channel, 1: bypass p-channel [0:0] read-write - - padcfg_pad_rstn_pos - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled - [1:1] - read-write - - aon_iomux_cfgsaif_syscfg76 - AON IOMUX CFG SAIF SYSCFG 76 - 0x4c + pch_pstate + P-channel PSTATE + 0x50 32 - padcfg_pad_rtc_ds - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA. - [1:0] + pch_pstate + P-channel state set + [4:0] read-write - aon_iomux_cfgsaif_syscfg84 - AON IOMUX CFG SAIF SYSCFG 84 + pch_timeout + P-channel Timeout Threshold 0x54 32 - padcfg_pad_osc_ds - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA. - [1:0] + pch_timeout + P-channel waiting device acknowledge timeout. + [7:0] read-write - aon_iomux_cfgsaif_syscfg88 - AON IOMUX CFG SAIF SYSCFG 88 + lp_timeout + LP Cell Control Timeout Threshold 0x58 32 - padcfg_pad_gmac0_mdc_syscon - padcfg_pad_gmac0_mdc_syscon - [1:0] + lp_timeout + LP Cell Control signal waiting carries acknowledge timeout. + [7:0] read-write - aon_iomux_cfgsaif_syscfg92 - AON IOMUX CFG SAIF SYSCFG 92 + hard_turn_on_power_mode + Hardware Turn-On Power Mode 0x5c 32 - padcfg_pad_gmac0_mdio_syscon - padcfg_pad_gmac0_mdio_syscon - [1:0] + systop_power_mode + SYSTOP turn-on power mode. + [0:0] read-write - - - - aon_iomux_cfgsaif_syscfg96 - AON IOMUX CFG SAIF SYSCFG 96 - 0x60 - 32 - - padcfg_pad_gmac0_rxd0_syscon - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V - [1:0] + cpu_power_mode + CPU turn-on power mode. + [1:1] read-write - - - - aon_iomux_cfgsaif_syscfg100 - AON IOMUX CFG SAIF SYSCFG 100 - 0x64 - 32 - - padcfg_pad_gmac0_rxd1_syscon - padcfg_pad_gmac0_rxd1_syscon - [1:0] + gpua_power_mode + GPUA turn-on power mode. + [2:2] read-write - - - - aon_iomux_cfgsaif_syscfg104 - AON IOMUX CFG SAIF SYSCFG 104 - 0x68 - 32 - - padcfg_pad_gmac0_rxd2_syscon - padcfg_pad_gmac0_rxd2_syscon - [1:0] + vdec_power_mode + VDEC turn-on power mode. + [3:3] read-write - - - - aon_iomux_cfgsaif_syscfg108 - AON IOMUX CFG SAIF SYSCFG 108 - 0x6c - 32 - - padcfg_pad_gmac0_rxd3_syscon - padcfg_pad_gmac0_rxd3_syscon - [1:0] + vout_power_mode + VOUT turn-on power mode. + [4:4] read-write - - - - aon_iomux_cfgsaif_syscfg112 - AON IOMUX CFG SAIF SYSCFG 112 - 0x70 - 32 - - padcfg_pad_gmac0_rxdv_syscon - padcfg_pad_gmac0_rxdv_syscon - [1:0] + isp_power_mode + ISP turn-on power mode. + [5:5] read-write - - - - aon_iomux_cfgsaif_syscfg116 - AON IOMUX CFG SAIF SYSCFG 116 - 0x74 - 32 - - padcfg_pad_gmac0_rxc_syscon - padcfg_pad_gmac0_rxc_syscon - [1:0] + venc_power_mode + VENC turn-on power mode. + [6:6] read-write - aon_iomux_cfgsaif_syscfg120 - AON IOMUX CFG SAIF SYSCFG 120 - 0x78 + current_power_mode + Current Power Mode + 0x80 32 - padcfg_pad_gmac0_txd0_syscon - padcfg_pad_gmac0_txd0_syscon - [1:0] + systop_power_mode + SYSTOP turn-on power mode. + [0:0] + read-write + + + cpu_power_mode + CPU turn-on power mode. + [1:1] + read-write + + + gpua_power_mode + GPUA turn-on power mode. + [2:2] + read-write + + + vdec_power_mode + VDEC turn-on power mode. + [3:3] + read-write + + + vout_power_mode + VOUT turn-on power mode. + [4:4] + read-write + + + isp_power_mode + ISP turn-on power mode. + [5:5] + read-write + + + venc_power_mode + VENC turn-on power mode. + [6:6] read-write - aon_iomux_cfgsaif_syscfg124 - AON IOMUX CFG SAIF SYSCFG 124 - 0x7c + current_seq_state + Current Sequence State + 0x84 32 - padcfg_pad_gmac0_txd1_syscon - padcfg_pad_gmac0_txd1_syscon + power_mode_cur + Current sequence state. [1:0] - read-write + read-only - aon_iomux_cfgsaif_syscfg128 - AON IOMUX CFG SAIF SYSCFG 128 - 0x80 + event_status + PMU Event Status + 0x88 32 - padcfg_pad_gmac0_txd2_syscon - padcfg_pad_gmac0_txd2_syscon - [1:0] - read-write + seq_done_event + Sequence complete. + [0:0] + read-only + + + hw_req_event + Hardware encouragement request. + [1:1] + read-only + + + sw_fail_event + Software encouragement failure. + [3:2] + read-only + + + hw_fail_event + Hardware encouragement failure. + [5:4] + read-only + + + pch_fail_event + P-channel failure. + [8:6] + read-only - aon_iomux_cfgsaif_syscfg132 - AON IOMUX CFG SAIF SYSCFG 132 - 0x84 + int_status + PMU Interrupt Status + 0x8c 32 - padcfg_pad_gmac0_txd3_syscon - padcfg_pad_gmac0_txd3_syscon - [1:0] - read-write + seq_done_event + Sequence complete. + [0:0] + read-only + + + hw_req_event + Hardware encouragement request. + [1:1] + read-only + + + sw_fail_event + Software encouragement failure. + [3:2] + read-only + + + hw_fail_event + Hardware encouragement failure. + [5:4] + read-only + + + pch_fail_event + P-channel failure. + [8:6] + read-only - aon_iomux_cfgsaif_syscfg136 - AON IOMUX CFG SAIF SYSCFG 136 - 0x88 + hw_event_crd + Hardware Event Record + 0x90 32 - padcfg_pad_gmac0_txen_syscon - padcfg_pad_gmac0_txen_syscon - [1:0] - read-write + hw_event_crd + Hardware Event Record. + [7:0] + read-only - aon_iomux_cfgsaif_syscfg140 - AON IOMUX CFG SAIF SYSCFG 140 - 0x8c + encourage_type_crd + Hardware Event Type Record + 0x94 32 - padcfg_pad_gmac0_txc_syscon - padcfg_pad_gmac0_txc_syscon - [1:0] - read-write + encourage_type_crd + Hardware/Software encouragement type record. 0: Software, 1: Hardware. + [0:0] + read-only - aon_iomux_cfgsaif_syscfg144 - AON IOMUX CFG SAIF SYSCFG 144 - 0x90 + pch_active + P-channel PACTIVE Status + 0x98 32 - pad_gmac0_rxc_func_sel - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None - [1:0] - read-write + pch_active + P-channel PACTIVE status. + [10:0] + read-only - starfive_jh7110_pcie_0 - From starfive,jh7110-pcie,reg peripheral generator - 0x2B000000 - - 0 - 0x1000000 - registers - - - - starfive_jh7110_pcie_1 - From starfive,jh7110-pcie,config peripheral generator - 0x940000000 + starfive_jh7110_ispcrg_0 + From starfive,jh7110-ispcrg, peripheral generator + 0x19810000 0 - 0x10000000 - registers - - - - starfive_jh7110_pcie_2 - From starfive,jh7110-pcie,reg peripheral generator - 0x2C000000 - - 0 - 0x1000000 + 0x10000 registers - starfive_jh7110_pcie_3 - From starfive,jh7110-pcie,config peripheral generator - 0x9C0000000 + starfive_jh7110_voutcrg_0 + From starfive,jh7110-voutcrg, peripheral generator + 0x295C0000 0 - 0x10000000 + 0x10000 registers diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_dr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_icr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_mis.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_ris.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_sr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_0/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_dr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_icr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_mis.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_ris.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_sr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_1/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_dr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_icr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_mis.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_ris.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_sr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_2/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_dr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_icr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_mis.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_ris.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_sr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_3/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_dr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_icr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_mis.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_ris.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_sr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_4/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_dr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_icr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_mis.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_ris.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_sr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_5/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6.rs new file mode 100644 index 0000000..7e24761 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + pub ssp_cr0: SSP_CR0, + _reserved1: [u8; 0x02], + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + pub ssp_cr1: SSP_CR1, + _reserved2: [u8; 0x02], + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + pub ssp_dr: SSP_DR, + _reserved3: [u8; 0x02], + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + pub ssp_sr: SSP_SR, + _reserved4: [u8; 0x02], + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + pub ssp_cpsr: SSP_CPSR, + _reserved5: [u8; 0x02], + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + pub ssp_imsc: SSP_IMSC, + _reserved6: [u8; 0x02], + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + pub ssp_ris: SSP_RIS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + pub ssp_mis: SSP_MIS, + _reserved8: [u8; 0x02], + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + pub ssp_icr: SSP_ICR, + _reserved9: [u8; 0x02], + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + pub ssp_dmacr: SSP_DMACR, + _reserved10: [u8; 0x0fba], + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id0: SSP_PERIPH_ID0, + _reserved11: [u8; 0x02], + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id1: SSP_PERIPH_ID1, + _reserved12: [u8; 0x02], + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id2: SSP_PERIPH_ID2, + _reserved13: [u8; 0x02], + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + pub ssp_periph_id3: SSP_PERIPH_ID3, + _reserved14: [u8; 0x02], + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id0: SSP_PCELL_ID0, + _reserved15: [u8; 0x02], + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id1: SSP_PCELL_ID1, + _reserved16: [u8; 0x02], + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id2: SSP_PCELL_ID2, + _reserved17: [u8; 0x02], + #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + pub ssp_pcell_id3: SSP_PCELL_ID3, +} +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +module"] +pub type SSP_CR0 = crate::Reg; +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] +pub mod ssp_cr0; +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +module"] +pub type SSP_CR1 = crate::Reg; +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] +pub mod ssp_cr1; +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +module"] +pub type SSP_DR = crate::Reg; +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] +pub mod ssp_dr; +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +module"] +pub type SSP_SR = crate::Reg; +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] +pub mod ssp_sr; +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +module"] +pub type SSP_CPSR = crate::Reg; +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] +pub mod ssp_cpsr; +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +module"] +pub type SSP_IMSC = crate::Reg; +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] +pub mod ssp_imsc; +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +module"] +pub type SSP_RIS = crate::Reg; +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] +pub mod ssp_ris; +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +module"] +pub type SSP_MIS = crate::Reg; +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] +pub mod ssp_mis; +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +module"] +pub type SSP_ICR = crate::Reg; +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] +pub mod ssp_icr; +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +module"] +pub type SSP_DMACR = crate::Reg; +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] +pub mod ssp_dmacr; +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +module"] +pub type SSP_PERIPH_ID0 = crate::Reg; +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id0; +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +module"] +pub type SSP_PERIPH_ID1 = crate::Reg; +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id1; +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +module"] +pub type SSP_PERIPH_ID2 = crate::Reg; +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id2; +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +module"] +pub type SSP_PERIPH_ID3 = crate::Reg; +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] +pub mod ssp_periph_id3; +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +module"] +pub type SSP_PCELL_ID0 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id0; +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +module"] +pub type SSP_PCELL_ID1 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id1; +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +module"] +pub type SSP_PCELL_ID2 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id2; +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +module"] +pub type SSP_PCELL_ID3 = crate::Reg; +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] +pub mod ssp_pcell_id3; diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_cpsr.rs new file mode 100644 index 0000000..4786592 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_cpsr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_cpsr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cpsr` writer"] +pub type W = crate::W; +#[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CPSR_SPEC; +impl crate::RegisterSpec for SSP_CPSR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cpsr::R`](R) reader structure"] +impl crate::Readable for SSP_CPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cpsr::W`](W) writer structure"] +impl crate::Writable for SSP_CPSR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_cr0.rs new file mode 100644 index 0000000..6dd1733 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_cr0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `ssp_cr0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr0` writer"] +pub type W = crate::W; +#[doc = "Field `scr` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +#[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_R = crate::FieldReader; +#[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self) + } + #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] +/ (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR0_SPEC; +impl crate::RegisterSpec for SSP_CR0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr0::R`](R) reader structure"] +impl crate::Readable for SSP_CR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr0::W`](W) writer structure"] +impl crate::Writable for SSP_CR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_cr1.rs new file mode 100644 index 0000000..0792760 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_cr1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_cr1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_cr1` writer"] +pub type W = crate::W; +#[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_R = crate::BitReader; +#[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_R = crate::BitReader; +#[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_R = crate::BitReader; +#[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_R = crate::BitReader; +#[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self) + } + #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_CR1_SPEC; +impl crate::RegisterSpec for SSP_CR1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_cr1::R`](R) reader structure"] +impl crate::Readable for SSP_CR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_cr1::W`](W) writer structure"] +impl crate::Writable for SSP_CR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_dmacr.rs new file mode 100644 index 0000000..98c9b9b --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_dmacr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_dmacr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dmacr` writer"] +pub type W = crate::W; +#[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DMACR_SPEC; +impl crate::RegisterSpec for SSP_DMACR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dmacr::R`](R) reader structure"] +impl crate::Readable for SSP_DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dmacr::W`](W) writer structure"] +impl crate::Writable for SSP_DMACR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_dr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_dr.rs new file mode 100644 index 0000000..e08e262 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_dr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ssp_dr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_dr` writer"] +pub type W = crate::W; +#[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_DR_SPEC; +impl crate::RegisterSpec for SSP_DR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_dr::R`](R) reader structure"] +impl crate::Readable for SSP_DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_dr::W`](W) writer structure"] +impl crate::Writable for SSP_DR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_icr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_icr.rs new file mode 100644 index 0000000..6764545 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_icr.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ssp_icr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_icr` writer"] +pub type W = crate::W; +#[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_ICR_SPEC; +impl crate::RegisterSpec for SSP_ICR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_icr::R`](R) reader structure"] +impl crate::Readable for SSP_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_icr::W`](W) writer structure"] +impl crate::Writable for SSP_ICR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_imsc.rs new file mode 100644 index 0000000..5cc0e1a --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_imsc.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ssp_imsc` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_imsc` writer"] +pub type W = crate::W; +#[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self) + } + #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_IMSC_SPEC; +impl crate::RegisterSpec for SSP_IMSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"] +impl crate::Readable for SSP_IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"] +impl crate::Writable for SSP_IMSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_mis.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_mis.rs new file mode 100644 index 0000000..e3e4c75 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_mis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_mis` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_mis` writer"] +pub type W = crate::W; +#[doc = "Field `rormis` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `rtmis` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `rxmis` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `txmis` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_MIS_SPEC; +impl crate::RegisterSpec for SSP_MIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_mis::R`](R) reader structure"] +impl crate::Readable for SSP_MIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_mis::W`](W) writer structure"] +impl crate::Writable for SSP_MIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_pcell_id0.rs new file mode 100644 index 0000000..3af6dc3 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_pcell_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id0` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id0` reader - The bits are read as 0xD"] +pub type SSP_PCELL_ID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xD"] + #[inline(always)] + pub fn ssp_pcell_id0(&self) -> SSP_PCELL_ID0_R { + SSP_PCELL_ID0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID0_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_pcell_id1.rs new file mode 100644 index 0000000..eb6fb14 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_pcell_id1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id1` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id1` reader - The bits are read as 0xF0"] +pub type SSP_PCELL_ID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xF0"] + #[inline(always)] + pub fn ssp_pcell_id1(&self) -> SSP_PCELL_ID1_R { + SSP_PCELL_ID1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID1_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_pcell_id2.rs new file mode 100644 index 0000000..2cf6373 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_pcell_id2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id2` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id2` reader - The bits are read as 0x5"] +pub type SSP_PCELL_ID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0x5"] + #[inline(always)] + pub fn ssp_pcell_id2(&self) -> SSP_PCELL_ID2_R { + SSP_PCELL_ID2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID2_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_pcell_id3.rs new file mode 100644 index 0000000..6aeed7d --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_pcell_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_pcell_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_pcell_id3` writer"] +pub type W = crate::W; +#[doc = "Field `ssp_pcell_id3` reader - The bits are read as 0xB1"] +pub type SSP_PCELL_ID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The bits are read as 0xB1"] + #[inline(always)] + pub fn ssp_pcell_id3(&self) -> SSP_PCELL_ID3_R { + SSP_PCELL_ID3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PCELL_ID3_SPEC; +impl crate::RegisterSpec for SSP_PCELL_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_pcell_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PCELL_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_pcell_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PCELL_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_periph_id0.rs new file mode 100644 index 0000000..a136eff --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_periph_id0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id0` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id0` writer"] +pub type W = crate::W; +#[doc = "Field `part_number0` reader - These bits read back as 0x22"] +pub type PART_NUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn part_number0(&self) -> PART_NUMBER0_R { + PART_NUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID0_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id0::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id0::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_periph_id1.rs new file mode 100644 index 0000000..c5c93d0 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_periph_id1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id1` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id1` writer"] +pub type W = crate::W; +#[doc = "Field `part_number1` reader - These bits read back as 0x0"] +pub type PART_NUMBER1_R = crate::FieldReader; +#[doc = "Field `designer0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn part_number1(&self) -> PART_NUMBER1_R { + PART_NUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID1_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id1::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id1::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_periph_id2.rs new file mode 100644 index 0000000..f86b342 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_periph_id2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ssp_periph_id2` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id2` writer"] +pub type W = crate::W; +#[doc = "Field `designer1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `revision` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID2_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id2::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id2::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_periph_id3.rs new file mode 100644 index 0000000..24259b9 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_periph_id3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ssp_periph_id3` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_periph_id3` writer"] +pub type W = crate::W; +#[doc = "Field `configuration` reader - These bits read back as 0x80"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x80"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_PERIPH_ID3_SPEC; +impl crate::RegisterSpec for SSP_PERIPH_ID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_periph_id3::R`](R) reader structure"] +impl crate::Readable for SSP_PERIPH_ID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_periph_id3::W`](W) writer structure"] +impl crate::Writable for SSP_PERIPH_ID3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_ris.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_ris.rs new file mode 100644 index 0000000..25495ca --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_ris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ssp_ris` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_ris` writer"] +pub type W = crate::W; +#[doc = "Field `rorris` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `rtris` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `rxris` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `txris` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_RIS_SPEC; +impl crate::RegisterSpec for SSP_RIS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_ris::R`](R) reader structure"] +impl crate::Readable for SSP_RIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_ris::W`](W) writer structure"] +impl crate::Writable for SSP_RIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_sr.rs b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_sr.rs new file mode 100644 index 0000000..adf4550 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/arm_pl022_6/ssp_sr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ssp_sr` reader"] +pub type R = crate::R; +#[doc = "Register `ssp_sr` writer"] +pub type W = crate::W; +#[doc = "Field `tfe` reader - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `tnf` reader - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `rne` reader - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `rff` reader - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `bsy` reader - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSP_SR_SPEC; +impl crate::RegisterSpec for SSP_SR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`ssp_sr::R`](R) reader structure"] +impl crate::Readable for SSP_SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssp_sr::W`](W) writer structure"] +impl crate::Writable for SSP_SR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/lib.rs b/jh7110-vf2-13b-pac/src/lib.rs index 3468be9..25ea1ea 100644 --- a/jh7110-vf2-13b-pac/src/lib.rs +++ b/jh7110-vf2-13b-pac/src/lib.rs @@ -80,17 +80,17 @@ impl core::fmt::Debug for SIFIVE_CLINT0_0 { } #[doc = "From sifive,clint0, peripheral generator"] pub mod sifive_clint0_0; -#[doc = "From sifive,plic0, peripheral generator"] -pub struct SIFIVE_PLIC0_0 { +#[doc = "From snps,designware-i2c, peripheral generator"] +pub struct SNPS_DESIGNWARE_I2C_0 { _marker: PhantomData<*const ()>, } -unsafe impl Send for SIFIVE_PLIC0_0 {} -impl SIFIVE_PLIC0_0 { +unsafe impl Send for SNPS_DESIGNWARE_I2C_0 {} +impl SNPS_DESIGNWARE_I2C_0 { #[doc = r"Pointer to the register block"] - pub const PTR: *const sifive_plic0_0::RegisterBlock = 0x0c00_0000 as *const _; + pub const PTR: *const snps_designware_i2c_0::RegisterBlock = 0x1003_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const sifive_plic0_0::RegisterBlock { + pub const fn ptr() -> *const snps_designware_i2c_0::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -112,31 +112,31 @@ impl SIFIVE_PLIC0_0 { } } } -impl Deref for SIFIVE_PLIC0_0 { - type Target = sifive_plic0_0::RegisterBlock; +impl Deref for SNPS_DESIGNWARE_I2C_0 { + type Target = snps_designware_i2c_0::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for SIFIVE_PLIC0_0 { +impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SIFIVE_PLIC0_0").finish() + f.debug_struct("SNPS_DESIGNWARE_I2C_0").finish() } } -#[doc = "From sifive,plic0, peripheral generator"] -pub mod sifive_plic0_0; #[doc = "From snps,designware-i2c, peripheral generator"] -pub struct SNPS_DESIGNWARE_I2C_0 { +pub mod snps_designware_i2c_0; +#[doc = "From snps,designware-i2c, peripheral generator"] +pub struct SNPS_DESIGNWARE_I2C_1 { _marker: PhantomData<*const ()>, } -unsafe impl Send for SNPS_DESIGNWARE_I2C_0 {} -impl SNPS_DESIGNWARE_I2C_0 { +unsafe impl Send for SNPS_DESIGNWARE_I2C_1 {} +impl SNPS_DESIGNWARE_I2C_1 { #[doc = r"Pointer to the register block"] - pub const PTR: *const snps_designware_i2c_0::RegisterBlock = 0x1003_0000 as *const _; + pub const PTR: *const snps_designware_i2c_1::RegisterBlock = 0x1004_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const snps_designware_i2c_0::RegisterBlock { + pub const fn ptr() -> *const snps_designware_i2c_1::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -158,31 +158,31 @@ impl SNPS_DESIGNWARE_I2C_0 { } } } -impl Deref for SNPS_DESIGNWARE_I2C_0 { - type Target = snps_designware_i2c_0::RegisterBlock; +impl Deref for SNPS_DESIGNWARE_I2C_1 { + type Target = snps_designware_i2c_1::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_0 { +impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SNPS_DESIGNWARE_I2C_0").finish() + f.debug_struct("SNPS_DESIGNWARE_I2C_1").finish() } } #[doc = "From snps,designware-i2c, peripheral generator"] -pub mod snps_designware_i2c_0; +pub mod snps_designware_i2c_1; #[doc = "From snps,designware-i2c, peripheral generator"] -pub struct SNPS_DESIGNWARE_I2C_1 { +pub struct SNPS_DESIGNWARE_I2C_2 { _marker: PhantomData<*const ()>, } -unsafe impl Send for SNPS_DESIGNWARE_I2C_1 {} -impl SNPS_DESIGNWARE_I2C_1 { +unsafe impl Send for SNPS_DESIGNWARE_I2C_2 {} +impl SNPS_DESIGNWARE_I2C_2 { #[doc = r"Pointer to the register block"] - pub const PTR: *const snps_designware_i2c_1::RegisterBlock = 0x1004_0000 as *const _; + pub const PTR: *const snps_designware_i2c_2::RegisterBlock = 0x1005_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const snps_designware_i2c_1::RegisterBlock { + pub const fn ptr() -> *const snps_designware_i2c_2::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -204,31 +204,31 @@ impl SNPS_DESIGNWARE_I2C_1 { } } } -impl Deref for SNPS_DESIGNWARE_I2C_1 { - type Target = snps_designware_i2c_1::RegisterBlock; +impl Deref for SNPS_DESIGNWARE_I2C_2 { + type Target = snps_designware_i2c_2::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_1 { +impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SNPS_DESIGNWARE_I2C_1").finish() + f.debug_struct("SNPS_DESIGNWARE_I2C_2").finish() } } #[doc = "From snps,designware-i2c, peripheral generator"] -pub mod snps_designware_i2c_1; -#[doc = "From snps,designware-i2c, peripheral generator"] -pub struct SNPS_DESIGNWARE_I2C_2 { +pub mod snps_designware_i2c_2; +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_0 { _marker: PhantomData<*const ()>, } -unsafe impl Send for SNPS_DESIGNWARE_I2C_2 {} -impl SNPS_DESIGNWARE_I2C_2 { +unsafe impl Send for ARM_PL022_0 {} +impl ARM_PL022_0 { #[doc = r"Pointer to the register block"] - pub const PTR: *const snps_designware_i2c_2::RegisterBlock = 0x1005_0000 as *const _; + pub const PTR: *const arm_pl022_0::RegisterBlock = 0x1006_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const snps_designware_i2c_2::RegisterBlock { + pub const fn ptr() -> *const arm_pl022_0::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -250,20 +250,112 @@ impl SNPS_DESIGNWARE_I2C_2 { } } } -impl Deref for SNPS_DESIGNWARE_I2C_2 { - type Target = snps_designware_i2c_2::RegisterBlock; +impl Deref for ARM_PL022_0 { + type Target = arm_pl022_0::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_2 { +impl core::fmt::Debug for ARM_PL022_0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SNPS_DESIGNWARE_I2C_2").finish() + f.debug_struct("ARM_PL022_0").finish() } } -#[doc = "From snps,designware-i2c, peripheral generator"] -pub mod snps_designware_i2c_2; +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_0; +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ARM_PL022_1 {} +impl ARM_PL022_1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const arm_pl022_1::RegisterBlock = 0x1007_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const arm_pl022_1::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ARM_PL022_1 { + type Target = arm_pl022_1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ARM_PL022_1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARM_PL022_1").finish() + } +} +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_1; +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ARM_PL022_2 {} +impl ARM_PL022_2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const arm_pl022_2::RegisterBlock = 0x1008_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const arm_pl022_2::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ARM_PL022_2 { + type Target = arm_pl022_2::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ARM_PL022_2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARM_PL022_2").finish() + } +} +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_2; #[doc = "From starfive,jh7110-stgcrg, peripheral generator"] pub struct STARFIVE_JH7110_STGCRG_0 { _marker: PhantomData<*const ()>, @@ -540,17 +632,109 @@ impl core::fmt::Debug for SNPS_DESIGNWARE_I2C_6 { } #[doc = "From snps,designware-i2c, peripheral generator"] pub mod snps_designware_i2c_6; -#[doc = "From starfive,jh7110-pwm, peripheral generator"] -pub struct STARFIVE_JH7110_PWM_0 { +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ARM_PL022_3 {} +impl ARM_PL022_3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const arm_pl022_3::RegisterBlock = 0x1207_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const arm_pl022_3::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ARM_PL022_3 { + type Target = arm_pl022_3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ARM_PL022_3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARM_PL022_3").finish() + } +} +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_3; +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ARM_PL022_4 {} +impl ARM_PL022_4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const arm_pl022_4::RegisterBlock = 0x1208_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const arm_pl022_4::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ARM_PL022_4 { + type Target = arm_pl022_4::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ARM_PL022_4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARM_PL022_4").finish() + } +} +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_4; +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_5 { _marker: PhantomData<*const ()>, } -unsafe impl Send for STARFIVE_JH7110_PWM_0 {} -impl STARFIVE_JH7110_PWM_0 { +unsafe impl Send for ARM_PL022_5 {} +impl ARM_PL022_5 { #[doc = r"Pointer to the register block"] - pub const PTR: *const starfive_jh7110_pwm_0::RegisterBlock = 0x120d_0000 as *const _; + pub const PTR: *const arm_pl022_5::RegisterBlock = 0x1209_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const starfive_jh7110_pwm_0::RegisterBlock { + pub const fn ptr() -> *const arm_pl022_5::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -572,20 +756,66 @@ impl STARFIVE_JH7110_PWM_0 { } } } -impl Deref for STARFIVE_JH7110_PWM_0 { - type Target = starfive_jh7110_pwm_0::RegisterBlock; +impl Deref for ARM_PL022_5 { + type Target = arm_pl022_5::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for STARFIVE_JH7110_PWM_0 { +impl core::fmt::Debug for ARM_PL022_5 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("STARFIVE_JH7110_PWM_0").finish() + f.debug_struct("ARM_PL022_5").finish() } } -#[doc = "From starfive,jh7110-pwm, peripheral generator"] -pub mod starfive_jh7110_pwm_0; +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_5; +#[doc = "From arm,pl022, peripheral generator"] +pub struct ARM_PL022_6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ARM_PL022_6 {} +impl ARM_PL022_6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const arm_pl022_6::RegisterBlock = 0x120a_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const arm_pl022_6::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ARM_PL022_6 { + type Target = arm_pl022_6::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ARM_PL022_6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARM_PL022_6").finish() + } +} +#[doc = "From arm,pl022, peripheral generator"] +pub mod arm_pl022_6; #[doc = "From starfive,jh7110-syscrg, peripheral generator"] pub struct STARFIVE_JH7110_SYSCRG_0 { _marker: PhantomData<*const ()>, @@ -724,6 +954,52 @@ impl core::fmt::Debug for STARFIVE_JH7110_SYS_PINCTRL_0 { } #[doc = "From starfive,jh7110-sys-pinctrl, peripheral generator"] pub mod starfive_jh7110_sys_pinctrl_0; +#[doc = "From starfive,jh7110-trng, peripheral generator"] +pub struct STARFIVE_JH7110_TRNG_0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for STARFIVE_JH7110_TRNG_0 {} +impl STARFIVE_JH7110_TRNG_0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const starfive_jh7110_trng_0::RegisterBlock = 0x1600_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const starfive_jh7110_trng_0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for STARFIVE_JH7110_TRNG_0 { + type Target = starfive_jh7110_trng_0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for STARFIVE_JH7110_TRNG_0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STARFIVE_JH7110_TRNG_0").finish() + } +} +#[doc = "From starfive,jh7110-trng, peripheral generator"] +pub mod starfive_jh7110_trng_0; #[doc = "From starfive,jh7110-aoncrg, peripheral generator"] pub struct STARFIVE_JH7110_AONCRG_0 { _marker: PhantomData<*const ()>, @@ -862,6 +1138,52 @@ impl core::fmt::Debug for STARFIVE_JH7110_AON_PINCTRL_0 { } #[doc = "From starfive,jh7110-aon-pinctrl, peripheral generator"] pub mod starfive_jh7110_aon_pinctrl_0; +#[doc = "From starfive,jh7110-pmu, peripheral generator"] +pub struct STARFIVE_JH7110_PMU_0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for STARFIVE_JH7110_PMU_0 {} +impl STARFIVE_JH7110_PMU_0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const starfive_jh7110_pmu_0::RegisterBlock = 0x1703_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const starfive_jh7110_pmu_0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for STARFIVE_JH7110_PMU_0 { + type Target = starfive_jh7110_pmu_0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for STARFIVE_JH7110_PMU_0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STARFIVE_JH7110_PMU_0").finish() + } +} +#[doc = "From starfive,jh7110-pmu, peripheral generator"] +pub mod starfive_jh7110_pmu_0; #[no_mangle] static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] @@ -869,14 +1191,18 @@ static mut DEVICE_PERIPHERALS: bool = false; pub struct Peripherals { #[doc = "SIFIVE_CLINT0_0"] pub SIFIVE_CLINT0_0: SIFIVE_CLINT0_0, - #[doc = "SIFIVE_PLIC0_0"] - pub SIFIVE_PLIC0_0: SIFIVE_PLIC0_0, #[doc = "SNPS_DESIGNWARE_I2C_0"] pub SNPS_DESIGNWARE_I2C_0: SNPS_DESIGNWARE_I2C_0, #[doc = "SNPS_DESIGNWARE_I2C_1"] pub SNPS_DESIGNWARE_I2C_1: SNPS_DESIGNWARE_I2C_1, #[doc = "SNPS_DESIGNWARE_I2C_2"] pub SNPS_DESIGNWARE_I2C_2: SNPS_DESIGNWARE_I2C_2, + #[doc = "ARM_PL022_0"] + pub ARM_PL022_0: ARM_PL022_0, + #[doc = "ARM_PL022_1"] + pub ARM_PL022_1: ARM_PL022_1, + #[doc = "ARM_PL022_2"] + pub ARM_PL022_2: ARM_PL022_2, #[doc = "STARFIVE_JH7110_STGCRG_0"] pub STARFIVE_JH7110_STGCRG_0: STARFIVE_JH7110_STGCRG_0, #[doc = "STARFIVE_JH7110_STG_SYSCON_0"] @@ -889,20 +1215,30 @@ pub struct Peripherals { pub SNPS_DESIGNWARE_I2C_5: SNPS_DESIGNWARE_I2C_5, #[doc = "SNPS_DESIGNWARE_I2C_6"] pub SNPS_DESIGNWARE_I2C_6: SNPS_DESIGNWARE_I2C_6, - #[doc = "STARFIVE_JH7110_PWM_0"] - pub STARFIVE_JH7110_PWM_0: STARFIVE_JH7110_PWM_0, + #[doc = "ARM_PL022_3"] + pub ARM_PL022_3: ARM_PL022_3, + #[doc = "ARM_PL022_4"] + pub ARM_PL022_4: ARM_PL022_4, + #[doc = "ARM_PL022_5"] + pub ARM_PL022_5: ARM_PL022_5, + #[doc = "ARM_PL022_6"] + pub ARM_PL022_6: ARM_PL022_6, #[doc = "STARFIVE_JH7110_SYSCRG_0"] pub STARFIVE_JH7110_SYSCRG_0: STARFIVE_JH7110_SYSCRG_0, #[doc = "STARFIVE_JH7110_SYS_SYSCON_0"] pub STARFIVE_JH7110_SYS_SYSCON_0: STARFIVE_JH7110_SYS_SYSCON_0, #[doc = "STARFIVE_JH7110_SYS_PINCTRL_0"] pub STARFIVE_JH7110_SYS_PINCTRL_0: STARFIVE_JH7110_SYS_PINCTRL_0, + #[doc = "STARFIVE_JH7110_TRNG_0"] + pub STARFIVE_JH7110_TRNG_0: STARFIVE_JH7110_TRNG_0, #[doc = "STARFIVE_JH7110_AONCRG_0"] pub STARFIVE_JH7110_AONCRG_0: STARFIVE_JH7110_AONCRG_0, #[doc = "STARFIVE_JH7110_AON_SYSCON_0"] pub STARFIVE_JH7110_AON_SYSCON_0: STARFIVE_JH7110_AON_SYSCON_0, #[doc = "STARFIVE_JH7110_AON_PINCTRL_0"] pub STARFIVE_JH7110_AON_PINCTRL_0: STARFIVE_JH7110_AON_PINCTRL_0, + #[doc = "STARFIVE_JH7110_PMU_0"] + pub STARFIVE_JH7110_PMU_0: STARFIVE_JH7110_PMU_0, } impl Peripherals { #[doc = r" Returns all the peripherals *once*."] @@ -928,9 +1264,6 @@ impl Peripherals { SIFIVE_CLINT0_0: SIFIVE_CLINT0_0 { _marker: PhantomData, }, - SIFIVE_PLIC0_0: SIFIVE_PLIC0_0 { - _marker: PhantomData, - }, SNPS_DESIGNWARE_I2C_0: SNPS_DESIGNWARE_I2C_0 { _marker: PhantomData, }, @@ -940,6 +1273,15 @@ impl Peripherals { SNPS_DESIGNWARE_I2C_2: SNPS_DESIGNWARE_I2C_2 { _marker: PhantomData, }, + ARM_PL022_0: ARM_PL022_0 { + _marker: PhantomData, + }, + ARM_PL022_1: ARM_PL022_1 { + _marker: PhantomData, + }, + ARM_PL022_2: ARM_PL022_2 { + _marker: PhantomData, + }, STARFIVE_JH7110_STGCRG_0: STARFIVE_JH7110_STGCRG_0 { _marker: PhantomData, }, @@ -958,7 +1300,16 @@ impl Peripherals { SNPS_DESIGNWARE_I2C_6: SNPS_DESIGNWARE_I2C_6 { _marker: PhantomData, }, - STARFIVE_JH7110_PWM_0: STARFIVE_JH7110_PWM_0 { + ARM_PL022_3: ARM_PL022_3 { + _marker: PhantomData, + }, + ARM_PL022_4: ARM_PL022_4 { + _marker: PhantomData, + }, + ARM_PL022_5: ARM_PL022_5 { + _marker: PhantomData, + }, + ARM_PL022_6: ARM_PL022_6 { _marker: PhantomData, }, STARFIVE_JH7110_SYSCRG_0: STARFIVE_JH7110_SYSCRG_0 { @@ -970,6 +1321,9 @@ impl Peripherals { STARFIVE_JH7110_SYS_PINCTRL_0: STARFIVE_JH7110_SYS_PINCTRL_0 { _marker: PhantomData, }, + STARFIVE_JH7110_TRNG_0: STARFIVE_JH7110_TRNG_0 { + _marker: PhantomData, + }, STARFIVE_JH7110_AONCRG_0: STARFIVE_JH7110_AONCRG_0 { _marker: PhantomData, }, @@ -979,6 +1333,9 @@ impl Peripherals { STARFIVE_JH7110_AON_PINCTRL_0: STARFIVE_JH7110_AON_PINCTRL_0 { _marker: PhantomData, }, + STARFIVE_JH7110_PMU_0: STARFIVE_JH7110_PMU_0 { + _marker: PhantomData, + }, } } } diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0.rs new file mode 100644 index 0000000..8ab98ca --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0.rs @@ -0,0 +1,159 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x04], + #[doc = "0x04 - Hardware Event Turn-On Mask"] + pub hard_event_turn_on_mask: HARD_EVENT_TURN_ON_MASK, + _reserved1: [u8; 0x04], + #[doc = "0x0c - Software Turn-On Power Mode"] + pub soft_turn_on_power_mode: SOFT_TURN_ON_POWER_MODE, + #[doc = "0x10 - Software Turn-Off Power Mode"] + pub soft_turn_off_power_mode: SOFT_TURN_OFF_POWER_MODE, + #[doc = "0x14 - Threshold Sequence Timeout"] + pub timeout_seq_thd: TIMEOUT_SEQ_THD, + #[doc = "0x18 - Powerdomain Cascade 0"] + pub pdc0: PDC0, + #[doc = "0x1c - Powerdomain Cascade 1"] + pub pdc1: PDC1, + #[doc = "0x20 - Powerdomain Cascade 2"] + pub pdc2: PDC2, + _reserved7: [u8; 0x20], + #[doc = "0x44 - Software Encouragement"] + pub sw_encourage: SW_ENCOURAGE, + #[doc = "0x48 - TIMER Interrupt Mask"] + pub tim: TIM, + #[doc = "0x4c - P-channel Bypass"] + pub pch_bypass: PCH_BYPASS, + #[doc = "0x50 - P-channel PSTATE"] + pub pch_pstate: PCH_PSTATE, + #[doc = "0x54 - P-channel Timeout Threshold"] + pub pch_timeout: PCH_TIMEOUT, + #[doc = "0x58 - LP Cell Control Timeout Threshold"] + pub lp_timeout: LP_TIMEOUT, + #[doc = "0x5c - Hardware Turn-On Power Mode"] + pub hard_turn_on_power_mode: HARD_TURN_ON_POWER_MODE, + _reserved14: [u8; 0x20], + #[doc = "0x80 - Current Power Mode"] + pub current_power_mode: CURRENT_POWER_MODE, + #[doc = "0x84 - Current Sequence State"] + pub current_seq_state: CURRENT_SEQ_STATE, + #[doc = "0x88 - PMU Event Status"] + pub event_status: EVENT_STATUS, + #[doc = "0x8c - PMU Interrupt Status"] + pub int_status: INT_STATUS, + #[doc = "0x90 - Hardware Event Record"] + pub hw_event_crd: HW_EVENT_CRD, + #[doc = "0x94 - Hardware Event Type Record"] + pub encourage_type_crd: ENCOURAGE_TYPE_CRD, + #[doc = "0x98 - P-channel PACTIVE Status"] + pub pch_active: PCH_ACTIVE, +} +#[doc = "hard_event_turn_on_mask (rw) register accessor: Hardware Event Turn-On Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hard_event_turn_on_mask::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hard_event_turn_on_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hard_event_turn_on_mask`] +module"] +pub type HARD_EVENT_TURN_ON_MASK = + crate::Reg; +#[doc = "Hardware Event Turn-On Mask"] +pub mod hard_event_turn_on_mask; +#[doc = "soft_turn_on_power_mode (rw) register accessor: Software Turn-On Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_turn_on_power_mode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_turn_on_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_turn_on_power_mode`] +module"] +pub type SOFT_TURN_ON_POWER_MODE = + crate::Reg; +#[doc = "Software Turn-On Power Mode"] +pub mod soft_turn_on_power_mode; +#[doc = "soft_turn_off_power_mode (rw) register accessor: Software Turn-Off Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_turn_off_power_mode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_turn_off_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_turn_off_power_mode`] +module"] +pub type SOFT_TURN_OFF_POWER_MODE = + crate::Reg; +#[doc = "Software Turn-Off Power Mode"] +pub mod soft_turn_off_power_mode; +#[doc = "timeout_seq_thd (rw) register accessor: Threshold Sequence Timeout\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_seq_thd::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_seq_thd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`timeout_seq_thd`] +module"] +pub type TIMEOUT_SEQ_THD = crate::Reg; +#[doc = "Threshold Sequence Timeout"] +pub mod timeout_seq_thd; +#[doc = "pdc0 (rw) register accessor: Powerdomain Cascade 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pdc0`] +module"] +pub type PDC0 = crate::Reg; +#[doc = "Powerdomain Cascade 0"] +pub mod pdc0; +#[doc = "pdc1 (rw) register accessor: Powerdomain Cascade 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pdc1`] +module"] +pub type PDC1 = crate::Reg; +#[doc = "Powerdomain Cascade 1"] +pub mod pdc1; +#[doc = "pdc2 (rw) register accessor: Powerdomain Cascade 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pdc2`] +module"] +pub type PDC2 = crate::Reg; +#[doc = "Powerdomain Cascade 2"] +pub mod pdc2; +#[doc = "sw_encourage (rw) register accessor: Software Encouragement\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_encourage::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_encourage::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sw_encourage`] +module"] +pub type SW_ENCOURAGE = crate::Reg; +#[doc = "Software Encouragement"] +pub mod sw_encourage; +#[doc = "tim (rw) register accessor: TIMER Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tim`] +module"] +pub type TIM = crate::Reg; +#[doc = "TIMER Interrupt Mask"] +pub mod tim; +#[doc = "pch_bypass (rw) register accessor: P-channel Bypass\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_bypass::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pch_bypass`] +module"] +pub type PCH_BYPASS = crate::Reg; +#[doc = "P-channel Bypass"] +pub mod pch_bypass; +#[doc = "pch_pstate (rw) register accessor: P-channel PSTATE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_pstate::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_pstate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pch_pstate`] +module"] +pub type PCH_PSTATE = crate::Reg; +#[doc = "P-channel PSTATE"] +pub mod pch_pstate; +#[doc = "pch_timeout (rw) register accessor: P-channel Timeout Threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_timeout::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pch_timeout`] +module"] +pub type PCH_TIMEOUT = crate::Reg; +#[doc = "P-channel Timeout Threshold"] +pub mod pch_timeout; +#[doc = "lp_timeout (rw) register accessor: LP Cell Control Timeout Threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timeout::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lp_timeout`] +module"] +pub type LP_TIMEOUT = crate::Reg; +#[doc = "LP Cell Control Timeout Threshold"] +pub mod lp_timeout; +#[doc = "hard_turn_on_power_mode (rw) register accessor: Hardware Turn-On Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hard_turn_on_power_mode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hard_turn_on_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hard_turn_on_power_mode`] +module"] +pub type HARD_TURN_ON_POWER_MODE = + crate::Reg; +#[doc = "Hardware Turn-On Power Mode"] +pub mod hard_turn_on_power_mode; +#[doc = "current_power_mode (rw) register accessor: Current Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current_power_mode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`current_power_mode`] +module"] +pub type CURRENT_POWER_MODE = crate::Reg; +#[doc = "Current Power Mode"] +pub mod current_power_mode; +#[doc = "current_seq_state (rw) register accessor: Current Sequence State\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current_seq_state::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current_seq_state::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`current_seq_state`] +module"] +pub type CURRENT_SEQ_STATE = crate::Reg; +#[doc = "Current Sequence State"] +pub mod current_seq_state; +#[doc = "event_status (rw) register accessor: PMU Event Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`event_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`event_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`event_status`] +module"] +pub type EVENT_STATUS = crate::Reg; +#[doc = "PMU Event Status"] +pub mod event_status; +#[doc = "int_status (rw) register accessor: PMU Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`int_status`] +module"] +pub type INT_STATUS = crate::Reg; +#[doc = "PMU Interrupt Status"] +pub mod int_status; +#[doc = "hw_event_crd (rw) register accessor: Hardware Event Record\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_event_crd::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hw_event_crd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hw_event_crd`] +module"] +pub type HW_EVENT_CRD = crate::Reg; +#[doc = "Hardware Event Record"] +pub mod hw_event_crd; +#[doc = "encourage_type_crd (rw) register accessor: Hardware Event Type Record\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`encourage_type_crd::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`encourage_type_crd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`encourage_type_crd`] +module"] +pub type ENCOURAGE_TYPE_CRD = crate::Reg; +#[doc = "Hardware Event Type Record"] +pub mod encourage_type_crd; +#[doc = "pch_active (rw) register accessor: P-channel PACTIVE Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_active::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_active::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pch_active`] +module"] +pub type PCH_ACTIVE = crate::Reg; +#[doc = "P-channel PACTIVE Status"] +pub mod pch_active; diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/current_power_mode.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/current_power_mode.rs new file mode 100644 index 0000000..e8445e3 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/current_power_mode.rs @@ -0,0 +1,131 @@ +#[doc = "Register `current_power_mode` reader"] +pub type R = crate::R; +#[doc = "Register `current_power_mode` writer"] +pub type W = crate::W; +#[doc = "Field `systop_power_mode` reader - SYSTOP turn-on power mode."] +pub type SYSTOP_POWER_MODE_R = crate::BitReader; +#[doc = "Field `systop_power_mode` writer - SYSTOP turn-on power mode."] +pub type SYSTOP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `cpu_power_mode` reader - CPU turn-on power mode."] +pub type CPU_POWER_MODE_R = crate::BitReader; +#[doc = "Field `cpu_power_mode` writer - CPU turn-on power mode."] +pub type CPU_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `gpua_power_mode` reader - GPUA turn-on power mode."] +pub type GPUA_POWER_MODE_R = crate::BitReader; +#[doc = "Field `gpua_power_mode` writer - GPUA turn-on power mode."] +pub type GPUA_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `vdec_power_mode` reader - VDEC turn-on power mode."] +pub type VDEC_POWER_MODE_R = crate::BitReader; +#[doc = "Field `vdec_power_mode` writer - VDEC turn-on power mode."] +pub type VDEC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `vout_power_mode` reader - VOUT turn-on power mode."] +pub type VOUT_POWER_MODE_R = crate::BitReader; +#[doc = "Field `vout_power_mode` writer - VOUT turn-on power mode."] +pub type VOUT_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `isp_power_mode` reader - ISP turn-on power mode."] +pub type ISP_POWER_MODE_R = crate::BitReader; +#[doc = "Field `isp_power_mode` writer - ISP turn-on power mode."] +pub type ISP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `venc_power_mode` reader - VENC turn-on power mode."] +pub type VENC_POWER_MODE_R = crate::BitReader; +#[doc = "Field `venc_power_mode` writer - VENC turn-on power mode."] +pub type VENC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - SYSTOP turn-on power mode."] + #[inline(always)] + pub fn systop_power_mode(&self) -> SYSTOP_POWER_MODE_R { + SYSTOP_POWER_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CPU turn-on power mode."] + #[inline(always)] + pub fn cpu_power_mode(&self) -> CPU_POWER_MODE_R { + CPU_POWER_MODE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - GPUA turn-on power mode."] + #[inline(always)] + pub fn gpua_power_mode(&self) -> GPUA_POWER_MODE_R { + GPUA_POWER_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - VDEC turn-on power mode."] + #[inline(always)] + pub fn vdec_power_mode(&self) -> VDEC_POWER_MODE_R { + VDEC_POWER_MODE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VOUT turn-on power mode."] + #[inline(always)] + pub fn vout_power_mode(&self) -> VOUT_POWER_MODE_R { + VOUT_POWER_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - ISP turn-on power mode."] + #[inline(always)] + pub fn isp_power_mode(&self) -> ISP_POWER_MODE_R { + ISP_POWER_MODE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - VENC turn-on power mode."] + #[inline(always)] + pub fn venc_power_mode(&self) -> VENC_POWER_MODE_R { + VENC_POWER_MODE_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - SYSTOP turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { + SYSTOP_POWER_MODE_W::new(self) + } + #[doc = "Bit 1 - CPU turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { + CPU_POWER_MODE_W::new(self) + } + #[doc = "Bit 2 - GPUA turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { + GPUA_POWER_MODE_W::new(self) + } + #[doc = "Bit 3 - VDEC turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { + VDEC_POWER_MODE_W::new(self) + } + #[doc = "Bit 4 - VOUT turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { + VOUT_POWER_MODE_W::new(self) + } + #[doc = "Bit 5 - ISP turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { + ISP_POWER_MODE_W::new(self) + } + #[doc = "Bit 6 - VENC turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { + VENC_POWER_MODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Current Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current_power_mode::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current_power_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CURRENT_POWER_MODE_SPEC; +impl crate::RegisterSpec for CURRENT_POWER_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`current_power_mode::R`](R) reader structure"] +impl crate::Readable for CURRENT_POWER_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`current_power_mode::W`](W) writer structure"] +impl crate::Writable for CURRENT_POWER_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/current_seq_state.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/current_seq_state.rs new file mode 100644 index 0000000..6b37031 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/current_seq_state.rs @@ -0,0 +1,33 @@ +#[doc = "Register `current_seq_state` reader"] +pub type R = crate::R; +#[doc = "Register `current_seq_state` writer"] +pub type W = crate::W; +#[doc = "Field `power_mode_cur` reader - Current sequence state."] +pub type POWER_MODE_CUR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Current sequence state."] + #[inline(always)] + pub fn power_mode_cur(&self) -> POWER_MODE_CUR_R { + POWER_MODE_CUR_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Current Sequence State\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current_seq_state::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current_seq_state::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CURRENT_SEQ_STATE_SPEC; +impl crate::RegisterSpec for CURRENT_SEQ_STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`current_seq_state::R`](R) reader structure"] +impl crate::Readable for CURRENT_SEQ_STATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`current_seq_state::W`](W) writer structure"] +impl crate::Writable for CURRENT_SEQ_STATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/encourage_type_crd.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/encourage_type_crd.rs new file mode 100644 index 0000000..b272139 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/encourage_type_crd.rs @@ -0,0 +1,33 @@ +#[doc = "Register `encourage_type_crd` reader"] +pub type R = crate::R; +#[doc = "Register `encourage_type_crd` writer"] +pub type W = crate::W; +#[doc = "Field `encourage_type_crd` reader - Hardware/Software encouragement type record. 0: Software, 1: Hardware."] +pub type ENCOURAGE_TYPE_CRD_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Hardware/Software encouragement type record. 0: Software, 1: Hardware."] + #[inline(always)] + pub fn encourage_type_crd(&self) -> ENCOURAGE_TYPE_CRD_R { + ENCOURAGE_TYPE_CRD_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Hardware Event Type Record\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`encourage_type_crd::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`encourage_type_crd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENCOURAGE_TYPE_CRD_SPEC; +impl crate::RegisterSpec for ENCOURAGE_TYPE_CRD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`encourage_type_crd::R`](R) reader structure"] +impl crate::Readable for ENCOURAGE_TYPE_CRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`encourage_type_crd::W`](W) writer structure"] +impl crate::Writable for ENCOURAGE_TYPE_CRD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/event_status.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/event_status.rs new file mode 100644 index 0000000..9cf0a76 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/event_status.rs @@ -0,0 +1,61 @@ +#[doc = "Register `event_status` reader"] +pub type R = crate::R; +#[doc = "Register `event_status` writer"] +pub type W = crate::W; +#[doc = "Field `seq_done_event` reader - Sequence complete."] +pub type SEQ_DONE_EVENT_R = crate::BitReader; +#[doc = "Field `hw_req_event` reader - Hardware encouragement request."] +pub type HW_REQ_EVENT_R = crate::BitReader; +#[doc = "Field `sw_fail_event` reader - Software encouragement failure."] +pub type SW_FAIL_EVENT_R = crate::FieldReader; +#[doc = "Field `hw_fail_event` reader - Hardware encouragement failure."] +pub type HW_FAIL_EVENT_R = crate::FieldReader; +#[doc = "Field `pch_fail_event` reader - P-channel failure."] +pub type PCH_FAIL_EVENT_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Sequence complete."] + #[inline(always)] + pub fn seq_done_event(&self) -> SEQ_DONE_EVENT_R { + SEQ_DONE_EVENT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Hardware encouragement request."] + #[inline(always)] + pub fn hw_req_event(&self) -> HW_REQ_EVENT_R { + HW_REQ_EVENT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Software encouragement failure."] + #[inline(always)] + pub fn sw_fail_event(&self) -> SW_FAIL_EVENT_R { + SW_FAIL_EVENT_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Hardware encouragement failure."] + #[inline(always)] + pub fn hw_fail_event(&self) -> HW_FAIL_EVENT_R { + HW_FAIL_EVENT_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:8 - P-channel failure."] + #[inline(always)] + pub fn pch_fail_event(&self) -> PCH_FAIL_EVENT_R { + PCH_FAIL_EVENT_R::new(((self.bits >> 6) & 7) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PMU Event Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`event_status::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`event_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVENT_STATUS_SPEC; +impl crate::RegisterSpec for EVENT_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`event_status::R`](R) reader structure"] +impl crate::Readable for EVENT_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`event_status::W`](W) writer structure"] +impl crate::Writable for EVENT_STATUS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/hard_event_turn_on_mask.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/hard_event_turn_on_mask.rs new file mode 100644 index 0000000..240a821 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/hard_event_turn_on_mask.rs @@ -0,0 +1,162 @@ +#[doc = "Register `hard_event_turn_on_mask` reader"] +pub type R = crate::R; +#[doc = "Register `hard_event_turn_on_mask` writer"] +pub type W = crate::W; +#[doc = "Field `hard_event_0_on_mask` reader - RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_0_ON_MASK_R = crate::BitReader; +#[doc = "Field `hard_event_0_on_mask` writer - RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_0_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `hard_event_1_on_mask` reader - GMAC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_1_ON_MASK_R = crate::BitReader; +#[doc = "Field `hard_event_1_on_mask` writer - GMAC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_1_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `hard_event_2_on_mask` reader - RFU, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_2_ON_MASK_R = crate::BitReader; +#[doc = "Field `hard_event_2_on_mask` writer - RFU, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_2_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `hard_event_3_on_mask` reader - RGPIO0 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_3_ON_MASK_R = crate::BitReader; +#[doc = "Field `hard_event_3_on_mask` writer - RGPIO0 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_3_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `hard_event_4_on_mask` reader - RGPIO1 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_4_ON_MASK_R = crate::BitReader; +#[doc = "Field `hard_event_4_on_mask` writer - RGPIO1 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_4_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `hard_event_5_on_mask` reader - RGPIO2 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_5_ON_MASK_R = crate::BitReader; +#[doc = "Field `hard_event_5_on_mask` writer - RGPIO2 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_5_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `hard_event_6_on_mask` reader - RGPIO3 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_6_ON_MASK_R = crate::BitReader; +#[doc = "Field `hard_event_6_on_mask` writer - RGPIO3 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_6_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `hard_event_7_on_mask` reader - GPU event, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_7_ON_MASK_R = crate::BitReader; +#[doc = "Field `hard_event_7_on_mask` writer - GPU event, 1: mask hardware event, 0: enable hardware event"] +pub type HARD_EVENT_7_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + pub fn hard_event_0_on_mask(&self) -> HARD_EVENT_0_ON_MASK_R { + HARD_EVENT_0_ON_MASK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - GMAC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + pub fn hard_event_1_on_mask(&self) -> HARD_EVENT_1_ON_MASK_R { + HARD_EVENT_1_ON_MASK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RFU, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + pub fn hard_event_2_on_mask(&self) -> HARD_EVENT_2_ON_MASK_R { + HARD_EVENT_2_ON_MASK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RGPIO0 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + pub fn hard_event_3_on_mask(&self) -> HARD_EVENT_3_ON_MASK_R { + HARD_EVENT_3_ON_MASK_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RGPIO1 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + pub fn hard_event_4_on_mask(&self) -> HARD_EVENT_4_ON_MASK_R { + HARD_EVENT_4_ON_MASK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - RGPIO2 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + pub fn hard_event_5_on_mask(&self) -> HARD_EVENT_5_ON_MASK_R { + HARD_EVENT_5_ON_MASK_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RGPIO3 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + pub fn hard_event_6_on_mask(&self) -> HARD_EVENT_6_ON_MASK_R { + HARD_EVENT_6_ON_MASK_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - GPU event, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + pub fn hard_event_7_on_mask(&self) -> HARD_EVENT_7_ON_MASK_R { + HARD_EVENT_7_ON_MASK_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + #[must_use] + pub fn hard_event_0_on_mask( + &mut self, + ) -> HARD_EVENT_0_ON_MASK_W { + HARD_EVENT_0_ON_MASK_W::new(self) + } + #[doc = "Bit 1 - GMAC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + #[must_use] + pub fn hard_event_1_on_mask( + &mut self, + ) -> HARD_EVENT_1_ON_MASK_W { + HARD_EVENT_1_ON_MASK_W::new(self) + } + #[doc = "Bit 2 - RFU, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + #[must_use] + pub fn hard_event_2_on_mask( + &mut self, + ) -> HARD_EVENT_2_ON_MASK_W { + HARD_EVENT_2_ON_MASK_W::new(self) + } + #[doc = "Bit 3 - RGPIO0 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + #[must_use] + pub fn hard_event_3_on_mask( + &mut self, + ) -> HARD_EVENT_3_ON_MASK_W { + HARD_EVENT_3_ON_MASK_W::new(self) + } + #[doc = "Bit 4 - RGPIO1 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + #[must_use] + pub fn hard_event_4_on_mask( + &mut self, + ) -> HARD_EVENT_4_ON_MASK_W { + HARD_EVENT_4_ON_MASK_W::new(self) + } + #[doc = "Bit 5 - RGPIO2 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + #[must_use] + pub fn hard_event_5_on_mask( + &mut self, + ) -> HARD_EVENT_5_ON_MASK_W { + HARD_EVENT_5_ON_MASK_W::new(self) + } + #[doc = "Bit 6 - RGPIO3 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + #[must_use] + pub fn hard_event_6_on_mask( + &mut self, + ) -> HARD_EVENT_6_ON_MASK_W { + HARD_EVENT_6_ON_MASK_W::new(self) + } + #[doc = "Bit 7 - GPU event, 1: mask hardware event, 0: enable hardware event"] + #[inline(always)] + #[must_use] + pub fn hard_event_7_on_mask( + &mut self, + ) -> HARD_EVENT_7_ON_MASK_W { + HARD_EVENT_7_ON_MASK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Hardware Event Turn-On Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hard_event_turn_on_mask::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hard_event_turn_on_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HARD_EVENT_TURN_ON_MASK_SPEC; +impl crate::RegisterSpec for HARD_EVENT_TURN_ON_MASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hard_event_turn_on_mask::R`](R) reader structure"] +impl crate::Readable for HARD_EVENT_TURN_ON_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hard_event_turn_on_mask::W`](W) writer structure"] +impl crate::Writable for HARD_EVENT_TURN_ON_MASK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/hard_turn_on_power_mode.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/hard_turn_on_power_mode.rs new file mode 100644 index 0000000..f2807e3 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/hard_turn_on_power_mode.rs @@ -0,0 +1,131 @@ +#[doc = "Register `hard_turn_on_power_mode` reader"] +pub type R = crate::R; +#[doc = "Register `hard_turn_on_power_mode` writer"] +pub type W = crate::W; +#[doc = "Field `systop_power_mode` reader - SYSTOP turn-on power mode."] +pub type SYSTOP_POWER_MODE_R = crate::BitReader; +#[doc = "Field `systop_power_mode` writer - SYSTOP turn-on power mode."] +pub type SYSTOP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `cpu_power_mode` reader - CPU turn-on power mode."] +pub type CPU_POWER_MODE_R = crate::BitReader; +#[doc = "Field `cpu_power_mode` writer - CPU turn-on power mode."] +pub type CPU_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `gpua_power_mode` reader - GPUA turn-on power mode."] +pub type GPUA_POWER_MODE_R = crate::BitReader; +#[doc = "Field `gpua_power_mode` writer - GPUA turn-on power mode."] +pub type GPUA_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `vdec_power_mode` reader - VDEC turn-on power mode."] +pub type VDEC_POWER_MODE_R = crate::BitReader; +#[doc = "Field `vdec_power_mode` writer - VDEC turn-on power mode."] +pub type VDEC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `vout_power_mode` reader - VOUT turn-on power mode."] +pub type VOUT_POWER_MODE_R = crate::BitReader; +#[doc = "Field `vout_power_mode` writer - VOUT turn-on power mode."] +pub type VOUT_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `isp_power_mode` reader - ISP turn-on power mode."] +pub type ISP_POWER_MODE_R = crate::BitReader; +#[doc = "Field `isp_power_mode` writer - ISP turn-on power mode."] +pub type ISP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `venc_power_mode` reader - VENC turn-on power mode."] +pub type VENC_POWER_MODE_R = crate::BitReader; +#[doc = "Field `venc_power_mode` writer - VENC turn-on power mode."] +pub type VENC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - SYSTOP turn-on power mode."] + #[inline(always)] + pub fn systop_power_mode(&self) -> SYSTOP_POWER_MODE_R { + SYSTOP_POWER_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CPU turn-on power mode."] + #[inline(always)] + pub fn cpu_power_mode(&self) -> CPU_POWER_MODE_R { + CPU_POWER_MODE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - GPUA turn-on power mode."] + #[inline(always)] + pub fn gpua_power_mode(&self) -> GPUA_POWER_MODE_R { + GPUA_POWER_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - VDEC turn-on power mode."] + #[inline(always)] + pub fn vdec_power_mode(&self) -> VDEC_POWER_MODE_R { + VDEC_POWER_MODE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VOUT turn-on power mode."] + #[inline(always)] + pub fn vout_power_mode(&self) -> VOUT_POWER_MODE_R { + VOUT_POWER_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - ISP turn-on power mode."] + #[inline(always)] + pub fn isp_power_mode(&self) -> ISP_POWER_MODE_R { + ISP_POWER_MODE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - VENC turn-on power mode."] + #[inline(always)] + pub fn venc_power_mode(&self) -> VENC_POWER_MODE_R { + VENC_POWER_MODE_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - SYSTOP turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { + SYSTOP_POWER_MODE_W::new(self) + } + #[doc = "Bit 1 - CPU turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { + CPU_POWER_MODE_W::new(self) + } + #[doc = "Bit 2 - GPUA turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { + GPUA_POWER_MODE_W::new(self) + } + #[doc = "Bit 3 - VDEC turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { + VDEC_POWER_MODE_W::new(self) + } + #[doc = "Bit 4 - VOUT turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { + VOUT_POWER_MODE_W::new(self) + } + #[doc = "Bit 5 - ISP turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { + ISP_POWER_MODE_W::new(self) + } + #[doc = "Bit 6 - VENC turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { + VENC_POWER_MODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Hardware Turn-On Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hard_turn_on_power_mode::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hard_turn_on_power_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HARD_TURN_ON_POWER_MODE_SPEC; +impl crate::RegisterSpec for HARD_TURN_ON_POWER_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hard_turn_on_power_mode::R`](R) reader structure"] +impl crate::Readable for HARD_TURN_ON_POWER_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hard_turn_on_power_mode::W`](W) writer structure"] +impl crate::Writable for HARD_TURN_ON_POWER_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/hw_event_crd.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/hw_event_crd.rs new file mode 100644 index 0000000..c0ddedd --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/hw_event_crd.rs @@ -0,0 +1,33 @@ +#[doc = "Register `hw_event_crd` reader"] +pub type R = crate::R; +#[doc = "Register `hw_event_crd` writer"] +pub type W = crate::W; +#[doc = "Field `hw_event_crd` reader - Hardware Event Record."] +pub type HW_EVENT_CRD_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Hardware Event Record."] + #[inline(always)] + pub fn hw_event_crd(&self) -> HW_EVENT_CRD_R { + HW_EVENT_CRD_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Hardware Event Record\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_event_crd::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hw_event_crd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HW_EVENT_CRD_SPEC; +impl crate::RegisterSpec for HW_EVENT_CRD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hw_event_crd::R`](R) reader structure"] +impl crate::Readable for HW_EVENT_CRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hw_event_crd::W`](W) writer structure"] +impl crate::Writable for HW_EVENT_CRD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/int_status.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/int_status.rs new file mode 100644 index 0000000..b68bfaa --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/int_status.rs @@ -0,0 +1,61 @@ +#[doc = "Register `int_status` reader"] +pub type R = crate::R; +#[doc = "Register `int_status` writer"] +pub type W = crate::W; +#[doc = "Field `seq_done_event` reader - Sequence complete."] +pub type SEQ_DONE_EVENT_R = crate::BitReader; +#[doc = "Field `hw_req_event` reader - Hardware encouragement request."] +pub type HW_REQ_EVENT_R = crate::BitReader; +#[doc = "Field `sw_fail_event` reader - Software encouragement failure."] +pub type SW_FAIL_EVENT_R = crate::FieldReader; +#[doc = "Field `hw_fail_event` reader - Hardware encouragement failure."] +pub type HW_FAIL_EVENT_R = crate::FieldReader; +#[doc = "Field `pch_fail_event` reader - P-channel failure."] +pub type PCH_FAIL_EVENT_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Sequence complete."] + #[inline(always)] + pub fn seq_done_event(&self) -> SEQ_DONE_EVENT_R { + SEQ_DONE_EVENT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Hardware encouragement request."] + #[inline(always)] + pub fn hw_req_event(&self) -> HW_REQ_EVENT_R { + HW_REQ_EVENT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Software encouragement failure."] + #[inline(always)] + pub fn sw_fail_event(&self) -> SW_FAIL_EVENT_R { + SW_FAIL_EVENT_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Hardware encouragement failure."] + #[inline(always)] + pub fn hw_fail_event(&self) -> HW_FAIL_EVENT_R { + HW_FAIL_EVENT_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:8 - P-channel failure."] + #[inline(always)] + pub fn pch_fail_event(&self) -> PCH_FAIL_EVENT_R { + PCH_FAIL_EVENT_R::new(((self.bits >> 6) & 7) as u8) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PMU Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_STATUS_SPEC; +impl crate::RegisterSpec for INT_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_status::R`](R) reader structure"] +impl crate::Readable for INT_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_status::W`](W) writer structure"] +impl crate::Writable for INT_STATUS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/lp_timeout.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/lp_timeout.rs new file mode 100644 index 0000000..90478a6 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/lp_timeout.rs @@ -0,0 +1,41 @@ +#[doc = "Register `lp_timeout` reader"] +pub type R = crate::R; +#[doc = "Register `lp_timeout` writer"] +pub type W = crate::W; +#[doc = "Field `lp_timeout` reader - LP Cell Control signal waiting carries acknowledge timeout."] +pub type LP_TIMEOUT_R = crate::FieldReader; +#[doc = "Field `lp_timeout` writer - LP Cell Control signal waiting carries acknowledge timeout."] +pub type LP_TIMEOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - LP Cell Control signal waiting carries acknowledge timeout."] + #[inline(always)] + pub fn lp_timeout(&self) -> LP_TIMEOUT_R { + LP_TIMEOUT_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - LP Cell Control signal waiting carries acknowledge timeout."] + #[inline(always)] + #[must_use] + pub fn lp_timeout(&mut self) -> LP_TIMEOUT_W { + LP_TIMEOUT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LP Cell Control Timeout Threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timeout::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TIMEOUT_SPEC; +impl crate::RegisterSpec for LP_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_timeout::R`](R) reader structure"] +impl crate::Readable for LP_TIMEOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_timeout::W`](W) writer structure"] +impl crate::Writable for LP_TIMEOUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pch_active.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pch_active.rs new file mode 100644 index 0000000..91760cc --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pch_active.rs @@ -0,0 +1,33 @@ +#[doc = "Register `pch_active` reader"] +pub type R = crate::R; +#[doc = "Register `pch_active` writer"] +pub type W = crate::W; +#[doc = "Field `pch_active` reader - P-channel PACTIVE status."] +pub type PCH_ACTIVE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:10 - P-channel PACTIVE status."] + #[inline(always)] + pub fn pch_active(&self) -> PCH_ACTIVE_R { + PCH_ACTIVE_R::new((self.bits & 0x07ff) as u16) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "P-channel PACTIVE Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_active::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_active::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PCH_ACTIVE_SPEC; +impl crate::RegisterSpec for PCH_ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pch_active::R`](R) reader structure"] +impl crate::Readable for PCH_ACTIVE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pch_active::W`](W) writer structure"] +impl crate::Writable for PCH_ACTIVE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pch_bypass.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pch_bypass.rs new file mode 100644 index 0000000..bfcffc7 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pch_bypass.rs @@ -0,0 +1,41 @@ +#[doc = "Register `pch_bypass` reader"] +pub type R = crate::R; +#[doc = "Register `pch_bypass` writer"] +pub type W = crate::W; +#[doc = "Field `pch_bypass` reader - Bypass P-channel. 0: enable p-channel, 1: bypass p-channel"] +pub type PCH_BYPASS_R = crate::BitReader; +#[doc = "Field `pch_bypass` writer - Bypass P-channel. 0: enable p-channel, 1: bypass p-channel"] +pub type PCH_BYPASS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Bypass P-channel. 0: enable p-channel, 1: bypass p-channel"] + #[inline(always)] + pub fn pch_bypass(&self) -> PCH_BYPASS_R { + PCH_BYPASS_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bypass P-channel. 0: enable p-channel, 1: bypass p-channel"] + #[inline(always)] + #[must_use] + pub fn pch_bypass(&mut self) -> PCH_BYPASS_W { + PCH_BYPASS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "P-channel Bypass\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_bypass::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PCH_BYPASS_SPEC; +impl crate::RegisterSpec for PCH_BYPASS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pch_bypass::R`](R) reader structure"] +impl crate::Readable for PCH_BYPASS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pch_bypass::W`](W) writer structure"] +impl crate::Writable for PCH_BYPASS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pch_pstate.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pch_pstate.rs new file mode 100644 index 0000000..7f85a83 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pch_pstate.rs @@ -0,0 +1,41 @@ +#[doc = "Register `pch_pstate` reader"] +pub type R = crate::R; +#[doc = "Register `pch_pstate` writer"] +pub type W = crate::W; +#[doc = "Field `pch_pstate` reader - P-channel state set"] +pub type PCH_PSTATE_R = crate::FieldReader; +#[doc = "Field `pch_pstate` writer - P-channel state set"] +pub type PCH_PSTATE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +impl R { + #[doc = "Bits 0:4 - P-channel state set"] + #[inline(always)] + pub fn pch_pstate(&self) -> PCH_PSTATE_R { + PCH_PSTATE_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - P-channel state set"] + #[inline(always)] + #[must_use] + pub fn pch_pstate(&mut self) -> PCH_PSTATE_W { + PCH_PSTATE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "P-channel PSTATE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_pstate::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_pstate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PCH_PSTATE_SPEC; +impl crate::RegisterSpec for PCH_PSTATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pch_pstate::R`](R) reader structure"] +impl crate::Readable for PCH_PSTATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pch_pstate::W`](W) writer structure"] +impl crate::Writable for PCH_PSTATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pch_timeout.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pch_timeout.rs new file mode 100644 index 0000000..5de8125 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pch_timeout.rs @@ -0,0 +1,41 @@ +#[doc = "Register `pch_timeout` reader"] +pub type R = crate::R; +#[doc = "Register `pch_timeout` writer"] +pub type W = crate::W; +#[doc = "Field `pch_timeout` reader - P-channel waiting device acknowledge timeout."] +pub type PCH_TIMEOUT_R = crate::FieldReader; +#[doc = "Field `pch_timeout` writer - P-channel waiting device acknowledge timeout."] +pub type PCH_TIMEOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - P-channel waiting device acknowledge timeout."] + #[inline(always)] + pub fn pch_timeout(&self) -> PCH_TIMEOUT_R { + PCH_TIMEOUT_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - P-channel waiting device acknowledge timeout."] + #[inline(always)] + #[must_use] + pub fn pch_timeout(&mut self) -> PCH_TIMEOUT_W { + PCH_TIMEOUT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "P-channel Timeout Threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_timeout::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PCH_TIMEOUT_SPEC; +impl crate::RegisterSpec for PCH_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pch_timeout::R`](R) reader structure"] +impl crate::Readable for PCH_TIMEOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pch_timeout::W`](W) writer structure"] +impl crate::Writable for PCH_TIMEOUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pdc0.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pdc0.rs new file mode 100644 index 0000000..745fcde --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pdc0.rs @@ -0,0 +1,116 @@ +#[doc = "Register `pdc0` reader"] +pub type R = crate::R; +#[doc = "Register `pdc0` writer"] +pub type W = crate::W; +#[doc = "Field `pd0_off_cas` reader - Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD0_OFF_CAS_R = crate::FieldReader; +#[doc = "Field `pd0_off_cas` writer - Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD0_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd0_on_cas` reader - Power domain 0 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD0_ON_CAS_R = crate::FieldReader; +#[doc = "Field `pd0_on_cas` writer - Power domain 0 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD0_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd1_off_cas` reader - Power domain 1 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD1_OFF_CAS_R = crate::FieldReader; +#[doc = "Field `pd1_off_cas` writer - Power domain 1 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD1_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd1_on_cas` reader - Power domain 1 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD1_ON_CAS_R = crate::FieldReader; +#[doc = "Field `pd1_on_cas` writer - Power domain 1 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD1_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd2_off_cas` reader - Power domain 2 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD2_OFF_CAS_R = crate::FieldReader; +#[doc = "Field `pd2_off_cas` writer - Power domain 2 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD2_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd2_on_cas` reader - Power domain 2 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD2_ON_CAS_R = crate::FieldReader; +#[doc = "Field `pd2_on_cas` writer - Power domain 2 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD2_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +impl R { + #[doc = "Bits 0:4 - Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd0_off_cas(&self) -> PD0_OFF_CAS_R { + PD0_OFF_CAS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - Power domain 0 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd0_on_cas(&self) -> PD0_ON_CAS_R { + PD0_ON_CAS_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:14 - Power domain 1 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd1_off_cas(&self) -> PD1_OFF_CAS_R { + PD1_OFF_CAS_R::new(((self.bits >> 10) & 0x1f) as u8) + } + #[doc = "Bits 15:19 - Power domain 1 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd1_on_cas(&self) -> PD1_ON_CAS_R { + PD1_ON_CAS_R::new(((self.bits >> 15) & 0x1f) as u8) + } + #[doc = "Bits 20:24 - Power domain 2 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd2_off_cas(&self) -> PD2_OFF_CAS_R { + PD2_OFF_CAS_R::new(((self.bits >> 20) & 0x1f) as u8) + } + #[doc = "Bits 25:29 - Power domain 2 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd2_on_cas(&self) -> PD2_ON_CAS_R { + PD2_ON_CAS_R::new(((self.bits >> 25) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd0_off_cas(&mut self) -> PD0_OFF_CAS_W { + PD0_OFF_CAS_W::new(self) + } + #[doc = "Bits 5:9 - Power domain 0 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd0_on_cas(&mut self) -> PD0_ON_CAS_W { + PD0_ON_CAS_W::new(self) + } + #[doc = "Bits 10:14 - Power domain 1 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd1_off_cas(&mut self) -> PD1_OFF_CAS_W { + PD1_OFF_CAS_W::new(self) + } + #[doc = "Bits 15:19 - Power domain 1 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd1_on_cas(&mut self) -> PD1_ON_CAS_W { + PD1_ON_CAS_W::new(self) + } + #[doc = "Bits 20:24 - Power domain 2 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd2_off_cas(&mut self) -> PD2_OFF_CAS_W { + PD2_OFF_CAS_W::new(self) + } + #[doc = "Bits 25:29 - Power domain 2 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd2_on_cas(&mut self) -> PD2_ON_CAS_W { + PD2_ON_CAS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Powerdomain Cascade 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PDC0_SPEC; +impl crate::RegisterSpec for PDC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pdc0::R`](R) reader structure"] +impl crate::Readable for PDC0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pdc0::W`](W) writer structure"] +impl crate::Writable for PDC0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pdc1.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pdc1.rs new file mode 100644 index 0000000..ff7da40 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pdc1.rs @@ -0,0 +1,116 @@ +#[doc = "Register `pdc1` reader"] +pub type R = crate::R; +#[doc = "Register `pdc1` writer"] +pub type W = crate::W; +#[doc = "Field `pd3_off_cas` reader - Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD3_OFF_CAS_R = crate::FieldReader; +#[doc = "Field `pd3_off_cas` writer - Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD3_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd3_on_cas` reader - Power domain 3 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD3_ON_CAS_R = crate::FieldReader; +#[doc = "Field `pd3_on_cas` writer - Power domain 3 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD3_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd4_off_cas` reader - Power domain 4 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD4_OFF_CAS_R = crate::FieldReader; +#[doc = "Field `pd4_off_cas` writer - Power domain 4 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD4_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd4_on_cas` reader - Power domain 4 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD4_ON_CAS_R = crate::FieldReader; +#[doc = "Field `pd4_on_cas` writer - Power domain 4 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD4_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd5_off_cas` reader - Power domain 5 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD5_OFF_CAS_R = crate::FieldReader; +#[doc = "Field `pd5_off_cas` writer - Power domain 5 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD5_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd5_on_cas` reader - Power domain 5 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD5_ON_CAS_R = crate::FieldReader; +#[doc = "Field `pd5_on_cas` writer - Power domain 5 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD5_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +impl R { + #[doc = "Bits 0:4 - Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd3_off_cas(&self) -> PD3_OFF_CAS_R { + PD3_OFF_CAS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - Power domain 3 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd3_on_cas(&self) -> PD3_ON_CAS_R { + PD3_ON_CAS_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:14 - Power domain 4 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd4_off_cas(&self) -> PD4_OFF_CAS_R { + PD4_OFF_CAS_R::new(((self.bits >> 10) & 0x1f) as u8) + } + #[doc = "Bits 15:19 - Power domain 4 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd4_on_cas(&self) -> PD4_ON_CAS_R { + PD4_ON_CAS_R::new(((self.bits >> 15) & 0x1f) as u8) + } + #[doc = "Bits 20:24 - Power domain 5 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd5_off_cas(&self) -> PD5_OFF_CAS_R { + PD5_OFF_CAS_R::new(((self.bits >> 20) & 0x1f) as u8) + } + #[doc = "Bits 25:29 - Power domain 5 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd5_on_cas(&self) -> PD5_ON_CAS_R { + PD5_ON_CAS_R::new(((self.bits >> 25) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd3_off_cas(&mut self) -> PD3_OFF_CAS_W { + PD3_OFF_CAS_W::new(self) + } + #[doc = "Bits 5:9 - Power domain 3 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd3_on_cas(&mut self) -> PD3_ON_CAS_W { + PD3_ON_CAS_W::new(self) + } + #[doc = "Bits 10:14 - Power domain 4 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd4_off_cas(&mut self) -> PD4_OFF_CAS_W { + PD4_OFF_CAS_W::new(self) + } + #[doc = "Bits 15:19 - Power domain 4 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd4_on_cas(&mut self) -> PD4_ON_CAS_W { + PD4_ON_CAS_W::new(self) + } + #[doc = "Bits 20:24 - Power domain 5 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd5_off_cas(&mut self) -> PD5_OFF_CAS_W { + PD5_OFF_CAS_W::new(self) + } + #[doc = "Bits 25:29 - Power domain 5 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd5_on_cas(&mut self) -> PD5_ON_CAS_W { + PD5_ON_CAS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Powerdomain Cascade 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PDC1_SPEC; +impl crate::RegisterSpec for PDC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pdc1::R`](R) reader structure"] +impl crate::Readable for PDC1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pdc1::W`](W) writer structure"] +impl crate::Writable for PDC1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pdc2.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pdc2.rs new file mode 100644 index 0000000..7a79307 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/pdc2.rs @@ -0,0 +1,116 @@ +#[doc = "Register `pdc2` reader"] +pub type R = crate::R; +#[doc = "Register `pdc2` writer"] +pub type W = crate::W; +#[doc = "Field `pd6_off_cas` reader - Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD6_OFF_CAS_R = crate::FieldReader; +#[doc = "Field `pd6_off_cas` writer - Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD6_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd6_on_cas` reader - Power domain 6 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD6_ON_CAS_R = crate::FieldReader; +#[doc = "Field `pd6_on_cas` writer - Power domain 6 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD6_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd7_off_cas` reader - Power domain 7 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD7_OFF_CAS_R = crate::FieldReader; +#[doc = "Field `pd7_off_cas` writer - Power domain 7 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD7_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd7_on_cas` reader - Power domain 7 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD7_ON_CAS_R = crate::FieldReader; +#[doc = "Field `pd7_on_cas` writer - Power domain 7 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD7_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd8_off_cas` reader - Power domain 8 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD8_OFF_CAS_R = crate::FieldReader; +#[doc = "Field `pd8_off_cas` writer - Power domain 8 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD8_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `pd8_on_cas` reader - Power domain 8 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD8_ON_CAS_R = crate::FieldReader; +#[doc = "Field `pd8_on_cas` writer - Power domain 8 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] +pub type PD8_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +impl R { + #[doc = "Bits 0:4 - Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd6_off_cas(&self) -> PD6_OFF_CAS_R { + PD6_OFF_CAS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - Power domain 6 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd6_on_cas(&self) -> PD6_ON_CAS_R { + PD6_ON_CAS_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:14 - Power domain 7 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd7_off_cas(&self) -> PD7_OFF_CAS_R { + PD7_OFF_CAS_R::new(((self.bits >> 10) & 0x1f) as u8) + } + #[doc = "Bits 15:19 - Power domain 7 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd7_on_cas(&self) -> PD7_ON_CAS_R { + PD7_ON_CAS_R::new(((self.bits >> 15) & 0x1f) as u8) + } + #[doc = "Bits 20:24 - Power domain 8 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd8_off_cas(&self) -> PD8_OFF_CAS_R { + PD8_OFF_CAS_R::new(((self.bits >> 20) & 0x1f) as u8) + } + #[doc = "Bits 25:29 - Power domain 8 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + pub fn pd8_on_cas(&self) -> PD8_ON_CAS_R { + PD8_ON_CAS_R::new(((self.bits >> 25) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd6_off_cas(&mut self) -> PD6_OFF_CAS_W { + PD6_OFF_CAS_W::new(self) + } + #[doc = "Bits 5:9 - Power domain 6 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd6_on_cas(&mut self) -> PD6_ON_CAS_W { + PD6_ON_CAS_W::new(self) + } + #[doc = "Bits 10:14 - Power domain 7 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd7_off_cas(&mut self) -> PD7_OFF_CAS_W { + PD7_OFF_CAS_W::new(self) + } + #[doc = "Bits 15:19 - Power domain 7 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd7_on_cas(&mut self) -> PD7_ON_CAS_W { + PD7_ON_CAS_W::new(self) + } + #[doc = "Bits 20:24 - Power domain 8 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd8_off_cas(&mut self) -> PD8_OFF_CAS_W { + PD8_OFF_CAS_W::new(self) + } + #[doc = "Bits 25:29 - Power domain 8 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] + #[inline(always)] + #[must_use] + pub fn pd8_on_cas(&mut self) -> PD8_ON_CAS_W { + PD8_ON_CAS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Powerdomain Cascade 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PDC2_SPEC; +impl crate::RegisterSpec for PDC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pdc2::R`](R) reader structure"] +impl crate::Readable for PDC2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pdc2::W`](W) writer structure"] +impl crate::Writable for PDC2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/soft_turn_off_power_mode.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/soft_turn_off_power_mode.rs new file mode 100644 index 0000000..c9baeeb --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/soft_turn_off_power_mode.rs @@ -0,0 +1,131 @@ +#[doc = "Register `soft_turn_off_power_mode` reader"] +pub type R = crate::R; +#[doc = "Register `soft_turn_off_power_mode` writer"] +pub type W = crate::W; +#[doc = "Field `systop_power_mode` reader - SYSTOP turn-off power mode."] +pub type SYSTOP_POWER_MODE_R = crate::BitReader; +#[doc = "Field `systop_power_mode` writer - SYSTOP turn-off power mode."] +pub type SYSTOP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `cpu_power_mode` reader - CPU turn-off power mode."] +pub type CPU_POWER_MODE_R = crate::BitReader; +#[doc = "Field `cpu_power_mode` writer - CPU turn-off power mode."] +pub type CPU_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `gpua_power_mode` reader - GPUA turn-off power mode."] +pub type GPUA_POWER_MODE_R = crate::BitReader; +#[doc = "Field `gpua_power_mode` writer - GPUA turn-off power mode."] +pub type GPUA_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `vdec_power_mode` reader - VDEC turn-off power mode."] +pub type VDEC_POWER_MODE_R = crate::BitReader; +#[doc = "Field `vdec_power_mode` writer - VDEC turn-off power mode."] +pub type VDEC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `vout_power_mode` reader - VOUT turn-off power mode."] +pub type VOUT_POWER_MODE_R = crate::BitReader; +#[doc = "Field `vout_power_mode` writer - VOUT turn-off power mode."] +pub type VOUT_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `isp_power_mode` reader - ISP turn-off power mode."] +pub type ISP_POWER_MODE_R = crate::BitReader; +#[doc = "Field `isp_power_mode` writer - ISP turn-off power mode."] +pub type ISP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `venc_power_mode` reader - VENC turn-off power mode."] +pub type VENC_POWER_MODE_R = crate::BitReader; +#[doc = "Field `venc_power_mode` writer - VENC turn-off power mode."] +pub type VENC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - SYSTOP turn-off power mode."] + #[inline(always)] + pub fn systop_power_mode(&self) -> SYSTOP_POWER_MODE_R { + SYSTOP_POWER_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CPU turn-off power mode."] + #[inline(always)] + pub fn cpu_power_mode(&self) -> CPU_POWER_MODE_R { + CPU_POWER_MODE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - GPUA turn-off power mode."] + #[inline(always)] + pub fn gpua_power_mode(&self) -> GPUA_POWER_MODE_R { + GPUA_POWER_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - VDEC turn-off power mode."] + #[inline(always)] + pub fn vdec_power_mode(&self) -> VDEC_POWER_MODE_R { + VDEC_POWER_MODE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VOUT turn-off power mode."] + #[inline(always)] + pub fn vout_power_mode(&self) -> VOUT_POWER_MODE_R { + VOUT_POWER_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - ISP turn-off power mode."] + #[inline(always)] + pub fn isp_power_mode(&self) -> ISP_POWER_MODE_R { + ISP_POWER_MODE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - VENC turn-off power mode."] + #[inline(always)] + pub fn venc_power_mode(&self) -> VENC_POWER_MODE_R { + VENC_POWER_MODE_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - SYSTOP turn-off power mode."] + #[inline(always)] + #[must_use] + pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { + SYSTOP_POWER_MODE_W::new(self) + } + #[doc = "Bit 1 - CPU turn-off power mode."] + #[inline(always)] + #[must_use] + pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { + CPU_POWER_MODE_W::new(self) + } + #[doc = "Bit 2 - GPUA turn-off power mode."] + #[inline(always)] + #[must_use] + pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { + GPUA_POWER_MODE_W::new(self) + } + #[doc = "Bit 3 - VDEC turn-off power mode."] + #[inline(always)] + #[must_use] + pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { + VDEC_POWER_MODE_W::new(self) + } + #[doc = "Bit 4 - VOUT turn-off power mode."] + #[inline(always)] + #[must_use] + pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { + VOUT_POWER_MODE_W::new(self) + } + #[doc = "Bit 5 - ISP turn-off power mode."] + #[inline(always)] + #[must_use] + pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { + ISP_POWER_MODE_W::new(self) + } + #[doc = "Bit 6 - VENC turn-off power mode."] + #[inline(always)] + #[must_use] + pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { + VENC_POWER_MODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Software Turn-Off Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_turn_off_power_mode::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_turn_off_power_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SOFT_TURN_OFF_POWER_MODE_SPEC; +impl crate::RegisterSpec for SOFT_TURN_OFF_POWER_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`soft_turn_off_power_mode::R`](R) reader structure"] +impl crate::Readable for SOFT_TURN_OFF_POWER_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`soft_turn_off_power_mode::W`](W) writer structure"] +impl crate::Writable for SOFT_TURN_OFF_POWER_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/soft_turn_on_power_mode.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/soft_turn_on_power_mode.rs new file mode 100644 index 0000000..7d40be3 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/soft_turn_on_power_mode.rs @@ -0,0 +1,131 @@ +#[doc = "Register `soft_turn_on_power_mode` reader"] +pub type R = crate::R; +#[doc = "Register `soft_turn_on_power_mode` writer"] +pub type W = crate::W; +#[doc = "Field `systop_power_mode` reader - SYSTOP turn-on power mode."] +pub type SYSTOP_POWER_MODE_R = crate::BitReader; +#[doc = "Field `systop_power_mode` writer - SYSTOP turn-on power mode."] +pub type SYSTOP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `cpu_power_mode` reader - CPU turn-on power mode."] +pub type CPU_POWER_MODE_R = crate::BitReader; +#[doc = "Field `cpu_power_mode` writer - CPU turn-on power mode."] +pub type CPU_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `gpua_power_mode` reader - GPUA turn-on power mode."] +pub type GPUA_POWER_MODE_R = crate::BitReader; +#[doc = "Field `gpua_power_mode` writer - GPUA turn-on power mode."] +pub type GPUA_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `vdec_power_mode` reader - VDEC turn-on power mode."] +pub type VDEC_POWER_MODE_R = crate::BitReader; +#[doc = "Field `vdec_power_mode` writer - VDEC turn-on power mode."] +pub type VDEC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `vout_power_mode` reader - VOUT turn-on power mode."] +pub type VOUT_POWER_MODE_R = crate::BitReader; +#[doc = "Field `vout_power_mode` writer - VOUT turn-on power mode."] +pub type VOUT_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `isp_power_mode` reader - ISP turn-on power mode."] +pub type ISP_POWER_MODE_R = crate::BitReader; +#[doc = "Field `isp_power_mode` writer - ISP turn-on power mode."] +pub type ISP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `venc_power_mode` reader - VENC turn-on power mode."] +pub type VENC_POWER_MODE_R = crate::BitReader; +#[doc = "Field `venc_power_mode` writer - VENC turn-on power mode."] +pub type VENC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - SYSTOP turn-on power mode."] + #[inline(always)] + pub fn systop_power_mode(&self) -> SYSTOP_POWER_MODE_R { + SYSTOP_POWER_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CPU turn-on power mode."] + #[inline(always)] + pub fn cpu_power_mode(&self) -> CPU_POWER_MODE_R { + CPU_POWER_MODE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - GPUA turn-on power mode."] + #[inline(always)] + pub fn gpua_power_mode(&self) -> GPUA_POWER_MODE_R { + GPUA_POWER_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - VDEC turn-on power mode."] + #[inline(always)] + pub fn vdec_power_mode(&self) -> VDEC_POWER_MODE_R { + VDEC_POWER_MODE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VOUT turn-on power mode."] + #[inline(always)] + pub fn vout_power_mode(&self) -> VOUT_POWER_MODE_R { + VOUT_POWER_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - ISP turn-on power mode."] + #[inline(always)] + pub fn isp_power_mode(&self) -> ISP_POWER_MODE_R { + ISP_POWER_MODE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - VENC turn-on power mode."] + #[inline(always)] + pub fn venc_power_mode(&self) -> VENC_POWER_MODE_R { + VENC_POWER_MODE_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - SYSTOP turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { + SYSTOP_POWER_MODE_W::new(self) + } + #[doc = "Bit 1 - CPU turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { + CPU_POWER_MODE_W::new(self) + } + #[doc = "Bit 2 - GPUA turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { + GPUA_POWER_MODE_W::new(self) + } + #[doc = "Bit 3 - VDEC turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { + VDEC_POWER_MODE_W::new(self) + } + #[doc = "Bit 4 - VOUT turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { + VOUT_POWER_MODE_W::new(self) + } + #[doc = "Bit 5 - ISP turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { + ISP_POWER_MODE_W::new(self) + } + #[doc = "Bit 6 - VENC turn-on power mode."] + #[inline(always)] + #[must_use] + pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { + VENC_POWER_MODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Software Turn-On Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_turn_on_power_mode::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_turn_on_power_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SOFT_TURN_ON_POWER_MODE_SPEC; +impl crate::RegisterSpec for SOFT_TURN_ON_POWER_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`soft_turn_on_power_mode::R`](R) reader structure"] +impl crate::Readable for SOFT_TURN_ON_POWER_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`soft_turn_on_power_mode::W`](W) writer structure"] +impl crate::Writable for SOFT_TURN_ON_POWER_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/sw_encourage.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/sw_encourage.rs new file mode 100644 index 0000000..f52bbbc --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/sw_encourage.rs @@ -0,0 +1,41 @@ +#[doc = "Register `sw_encourage` reader"] +pub type R = crate::R; +#[doc = "Register `sw_encourage` writer"] +pub type W = crate::W; +#[doc = "Field `sw_encourage` reader - Software Encouragement"] +pub type SW_ENCOURAGE_R = crate::FieldReader; +#[doc = "Field `sw_encourage` writer - Software Encouragement"] +pub type SW_ENCOURAGE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - Software Encouragement"] + #[inline(always)] + pub fn sw_encourage(&self) -> SW_ENCOURAGE_R { + SW_ENCOURAGE_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Software Encouragement"] + #[inline(always)] + #[must_use] + pub fn sw_encourage(&mut self) -> SW_ENCOURAGE_W { + SW_ENCOURAGE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Software Encouragement\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_encourage::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_encourage::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_ENCOURAGE_SPEC; +impl crate::RegisterSpec for SW_ENCOURAGE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_encourage::R`](R) reader structure"] +impl crate::Readable for SW_ENCOURAGE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_encourage::W`](W) writer structure"] +impl crate::Writable for SW_ENCOURAGE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/tim.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/tim.rs new file mode 100644 index 0000000..2bc8b62 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/tim.rs @@ -0,0 +1,101 @@ +#[doc = "Register `tim` reader"] +pub type R = crate::R; +#[doc = "Register `tim` writer"] +pub type W = crate::W; +#[doc = "Field `seq_done_mask` reader - Mask the sequence complete event. 0: mask, 1: unmask"] +pub type SEQ_DONE_MASK_R = crate::BitReader; +#[doc = "Field `seq_done_mask` writer - Mask the sequence complete event. 0: mask, 1: unmask"] +pub type SEQ_DONE_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `hw_req_mask` reader - Mask the hardware encouragement request. 0: mask, 1: unmask"] +pub type HW_REQ_MASK_R = crate::BitReader; +#[doc = "Field `hw_req_mask` writer - Mask the hardware encouragement request. 0: mask, 1: unmask"] +pub type HW_REQ_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `sw_fail_mask` reader - Mask the software encouragement failure event. 0: mask, 1: unmask"] +pub type SW_FAIL_MASK_R = crate::FieldReader; +#[doc = "Field `sw_fail_mask` writer - Mask the software encouragement failure event. 0: mask, 1: unmask"] +pub type SW_FAIL_MASK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `hw_fail_mask` reader - Mask the hardware encouragement failure event. 0: mask, 1: unmask"] +pub type HW_FAIL_MASK_R = crate::FieldReader; +#[doc = "Field `hw_fail_mask` writer - Mask the hardware encouragement failure event. 0: mask, 1: unmask"] +pub type HW_FAIL_MASK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +#[doc = "Field `pch_fail_mask` reader - Mask the P-channel encouragement failure event. 0: mask, 1: unmask"] +pub type PCH_FAIL_MASK_R = crate::FieldReader; +#[doc = "Field `pch_fail_mask` writer - Mask the P-channel encouragement failure event. 0: mask, 1: unmask"] +pub type PCH_FAIL_MASK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +impl R { + #[doc = "Bit 0 - Mask the sequence complete event. 0: mask, 1: unmask"] + #[inline(always)] + pub fn seq_done_mask(&self) -> SEQ_DONE_MASK_R { + SEQ_DONE_MASK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mask the hardware encouragement request. 0: mask, 1: unmask"] + #[inline(always)] + pub fn hw_req_mask(&self) -> HW_REQ_MASK_R { + HW_REQ_MASK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Mask the software encouragement failure event. 0: mask, 1: unmask"] + #[inline(always)] + pub fn sw_fail_mask(&self) -> SW_FAIL_MASK_R { + SW_FAIL_MASK_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Mask the hardware encouragement failure event. 0: mask, 1: unmask"] + #[inline(always)] + pub fn hw_fail_mask(&self) -> HW_FAIL_MASK_R { + HW_FAIL_MASK_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:8 - Mask the P-channel encouragement failure event. 0: mask, 1: unmask"] + #[inline(always)] + pub fn pch_fail_mask(&self) -> PCH_FAIL_MASK_R { + PCH_FAIL_MASK_R::new(((self.bits >> 6) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - Mask the sequence complete event. 0: mask, 1: unmask"] + #[inline(always)] + #[must_use] + pub fn seq_done_mask(&mut self) -> SEQ_DONE_MASK_W { + SEQ_DONE_MASK_W::new(self) + } + #[doc = "Bit 1 - Mask the hardware encouragement request. 0: mask, 1: unmask"] + #[inline(always)] + #[must_use] + pub fn hw_req_mask(&mut self) -> HW_REQ_MASK_W { + HW_REQ_MASK_W::new(self) + } + #[doc = "Bits 2:3 - Mask the software encouragement failure event. 0: mask, 1: unmask"] + #[inline(always)] + #[must_use] + pub fn sw_fail_mask(&mut self) -> SW_FAIL_MASK_W { + SW_FAIL_MASK_W::new(self) + } + #[doc = "Bits 4:5 - Mask the hardware encouragement failure event. 0: mask, 1: unmask"] + #[inline(always)] + #[must_use] + pub fn hw_fail_mask(&mut self) -> HW_FAIL_MASK_W { + HW_FAIL_MASK_W::new(self) + } + #[doc = "Bits 6:8 - Mask the P-channel encouragement failure event. 0: mask, 1: unmask"] + #[inline(always)] + #[must_use] + pub fn pch_fail_mask(&mut self) -> PCH_FAIL_MASK_W { + PCH_FAIL_MASK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TIMER Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIM_SPEC; +impl crate::RegisterSpec for TIM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tim::R`](R) reader structure"] +impl crate::Readable for TIM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tim::W`](W) writer structure"] +impl crate::Writable for TIM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/timeout_seq_thd.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/timeout_seq_thd.rs new file mode 100644 index 0000000..e076c6c --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_pmu_0/timeout_seq_thd.rs @@ -0,0 +1,41 @@ +#[doc = "Register `timeout_seq_thd` reader"] +pub type R = crate::R; +#[doc = "Register `timeout_seq_thd` writer"] +pub type W = crate::W; +#[doc = "Field `timeout_seq_thd` reader - Threshold Sequence Timeout"] +pub type TIMEOUT_SEQ_THD_R = crate::FieldReader; +#[doc = "Field `timeout_seq_thd` writer - Threshold Sequence Timeout"] +pub type TIMEOUT_SEQ_THD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bits 0:15 - Threshold Sequence Timeout"] + #[inline(always)] + pub fn timeout_seq_thd(&self) -> TIMEOUT_SEQ_THD_R { + TIMEOUT_SEQ_THD_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Threshold Sequence Timeout"] + #[inline(always)] + #[must_use] + pub fn timeout_seq_thd(&mut self) -> TIMEOUT_SEQ_THD_W { + TIMEOUT_SEQ_THD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Threshold Sequence Timeout\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_seq_thd::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_seq_thd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMEOUT_SEQ_THD_SPEC; +impl crate::RegisterSpec for TIMEOUT_SEQ_THD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timeout_seq_thd::R`](R) reader structure"] +impl crate::Readable for TIMEOUT_SEQ_THD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timeout_seq_thd::W`](W) writer structure"] +impl crate::Writable for TIMEOUT_SEQ_THD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0.rs new file mode 100644 index 0000000..c4fa9aa --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0.rs @@ -0,0 +1,118 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - TRNG CTRL Register"] + pub ctrl: CTRL, + #[doc = "0x04 - TRNG STAT Register"] + pub stat: STAT, + #[doc = "0x08 - TRNG MODE Register"] + pub mode: MODE, + #[doc = "0x0c - TRNG SMODE Register"] + pub smode: SMODE, + #[doc = "0x10 - TRNG Interrupt Enable Register"] + pub ie: IE, + #[doc = "0x14 - TRNG Interrupt Status Register"] + pub istat: ISTAT, + _reserved6: [u8; 0x08], + #[doc = "0x20 - TRNG RAND 0 Status Register"] + pub rand0: RAND0, + #[doc = "0x24 - TRNG RAND 1 Status Register"] + pub rand1: RAND1, + #[doc = "0x28 - TRNG RAND 2 Status Register"] + pub rand2: RAND2, + #[doc = "0x2c - TRNG RAND 3 Status Register"] + pub rand3: RAND3, + #[doc = "0x30 - TRNG RAND 4 Status Register"] + pub rand4: RAND4, + #[doc = "0x34 - TRNG RAND 5 Status Register"] + pub rand5: RAND5, + #[doc = "0x38 - TRNG RAND 6 Status Register"] + pub rand6: RAND6, + #[doc = "0x3c - TRNG RAND 7 Status Register"] + pub rand7: RAND7, + _reserved14: [u8; 0x20], + #[doc = "0x60 - Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter"] + pub auto_rqsts: AUTO_RQSTS, + #[doc = "0x64 - Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer"] + pub auto_age: AUTO_AGE, +} +#[doc = "ctrl (rw) register accessor: TRNG CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctrl`] +module"] +pub type CTRL = crate::Reg; +#[doc = "TRNG CTRL Register"] +pub mod ctrl; +#[doc = "stat (rw) register accessor: TRNG STAT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stat`] +module"] +pub type STAT = crate::Reg; +#[doc = "TRNG STAT Register"] +pub mod stat; +#[doc = "mode (rw) register accessor: TRNG MODE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mode`] +module"] +pub type MODE = crate::Reg; +#[doc = "TRNG MODE Register"] +pub mod mode; +#[doc = "smode (rw) register accessor: TRNG SMODE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`smode`] +module"] +pub type SMODE = crate::Reg; +#[doc = "TRNG SMODE Register"] +pub mod smode; +#[doc = "ie (rw) register accessor: TRNG Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ie`] +module"] +pub type IE = crate::Reg; +#[doc = "TRNG Interrupt Enable Register"] +pub mod ie; +#[doc = "istat (rw) register accessor: TRNG Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`istat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`istat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`istat`] +module"] +pub type ISTAT = crate::Reg; +#[doc = "TRNG Interrupt Status Register"] +pub mod istat; +#[doc = "rand0 (rw) register accessor: TRNG RAND 0 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand0`] +module"] +pub type RAND0 = crate::Reg; +#[doc = "TRNG RAND 0 Status Register"] +pub mod rand0; +#[doc = "rand1 (rw) register accessor: TRNG RAND 1 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand1`] +module"] +pub type RAND1 = crate::Reg; +#[doc = "TRNG RAND 1 Status Register"] +pub mod rand1; +#[doc = "rand2 (rw) register accessor: TRNG RAND 2 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand2`] +module"] +pub type RAND2 = crate::Reg; +#[doc = "TRNG RAND 2 Status Register"] +pub mod rand2; +#[doc = "rand3 (rw) register accessor: TRNG RAND 3 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand3`] +module"] +pub type RAND3 = crate::Reg; +#[doc = "TRNG RAND 3 Status Register"] +pub mod rand3; +#[doc = "rand4 (rw) register accessor: TRNG RAND 4 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand4`] +module"] +pub type RAND4 = crate::Reg; +#[doc = "TRNG RAND 4 Status Register"] +pub mod rand4; +#[doc = "rand5 (rw) register accessor: TRNG RAND 5 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand5`] +module"] +pub type RAND5 = crate::Reg; +#[doc = "TRNG RAND 5 Status Register"] +pub mod rand5; +#[doc = "rand6 (rw) register accessor: TRNG RAND 6 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand6`] +module"] +pub type RAND6 = crate::Reg; +#[doc = "TRNG RAND 6 Status Register"] +pub mod rand6; +#[doc = "rand7 (rw) register accessor: TRNG RAND 7 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand7`] +module"] +pub type RAND7 = crate::Reg; +#[doc = "TRNG RAND 7 Status Register"] +pub mod rand7; +#[doc = "auto_rqsts (rw) register accessor: Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`auto_rqsts::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`auto_rqsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`auto_rqsts`] +module"] +pub type AUTO_RQSTS = crate::Reg; +#[doc = "Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter"] +pub mod auto_rqsts; +#[doc = "auto_age (rw) register accessor: Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`auto_age::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`auto_age::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`auto_age`] +module"] +pub type AUTO_AGE = crate::Reg; +#[doc = "Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer"] +pub mod auto_age; diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/auto_age.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/auto_age.rs new file mode 100644 index 0000000..a711c39 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/auto_age.rs @@ -0,0 +1,41 @@ +#[doc = "Register `auto_age` reader"] +pub type R = crate::R; +#[doc = "Register `auto_age` writer"] +pub type W = crate::W; +#[doc = "Field `age` reader - Countdown value for auto-reseed timer"] +pub type AGE_R = crate::FieldReader; +#[doc = "Field `age` writer - Countdown value for auto-reseed timer"] +pub type AGE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +impl R { + #[doc = "Bits 0:31 - Countdown value for auto-reseed timer"] + #[inline(always)] + pub fn age(&self) -> AGE_R { + AGE_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Countdown value for auto-reseed timer"] + #[inline(always)] + #[must_use] + pub fn age(&mut self) -> AGE_W { + AGE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`auto_age::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`auto_age::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AUTO_AGE_SPEC; +impl crate::RegisterSpec for AUTO_AGE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`auto_age::R`](R) reader structure"] +impl crate::Readable for AUTO_AGE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`auto_age::W`](W) writer structure"] +impl crate::Writable for AUTO_AGE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/auto_rqsts.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/auto_rqsts.rs new file mode 100644 index 0000000..d6bb092 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/auto_rqsts.rs @@ -0,0 +1,41 @@ +#[doc = "Register `auto_rqsts` reader"] +pub type R = crate::R; +#[doc = "Register `auto_rqsts` writer"] +pub type W = crate::W; +#[doc = "Field `rqsts` reader - Threshold number of reseed requests for auto-reseed counter"] +pub type RQSTS_R = crate::FieldReader; +#[doc = "Field `rqsts` writer - Threshold number of reseed requests for auto-reseed counter"] +pub type RQSTS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +impl R { + #[doc = "Bits 0:31 - Threshold number of reseed requests for auto-reseed counter"] + #[inline(always)] + pub fn rqsts(&self) -> RQSTS_R { + RQSTS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Threshold number of reseed requests for auto-reseed counter"] + #[inline(always)] + #[must_use] + pub fn rqsts(&mut self) -> RQSTS_W { + RQSTS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`auto_rqsts::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`auto_rqsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AUTO_RQSTS_SPEC; +impl crate::RegisterSpec for AUTO_RQSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`auto_rqsts::R`](R) reader structure"] +impl crate::Readable for AUTO_RQSTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`auto_rqsts::W`](W) writer structure"] +impl crate::Writable for AUTO_RQSTS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/ctrl.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/ctrl.rs new file mode 100644 index 0000000..17511a1 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/ctrl.rs @@ -0,0 +1,71 @@ +#[doc = "Register `ctrl` reader"] +pub type R = crate::R; +#[doc = "Register `ctrl` writer"] +pub type W = crate::W; +#[doc = "Field `exec_nop` reader - Execute a NOP instruction"] +pub type EXEC_NOP_R = crate::BitReader; +#[doc = "Field `exec_nop` writer - Execute a NOP instruction"] +pub type EXEC_NOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `gene_randnum` reader - Generate a random number"] +pub type GENE_RANDNUM_R = crate::BitReader; +#[doc = "Field `gene_randnum` writer - Generate a random number"] +pub type GENE_RANDNUM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `exec_randreseed` reader - Reseed the TRNG from noise sources"] +pub type EXEC_RANDRESEED_R = crate::BitReader; +#[doc = "Field `exec_randreseed` writer - Reseed the TRNG from noise sources"] +pub type EXEC_RANDRESEED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Execute a NOP instruction"] + #[inline(always)] + pub fn exec_nop(&self) -> EXEC_NOP_R { + EXEC_NOP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Generate a random number"] + #[inline(always)] + pub fn gene_randnum(&self) -> GENE_RANDNUM_R { + GENE_RANDNUM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reseed the TRNG from noise sources"] + #[inline(always)] + pub fn exec_randreseed(&self) -> EXEC_RANDRESEED_R { + EXEC_RANDRESEED_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Execute a NOP instruction"] + #[inline(always)] + #[must_use] + pub fn exec_nop(&mut self) -> EXEC_NOP_W { + EXEC_NOP_W::new(self) + } + #[doc = "Bit 1 - Generate a random number"] + #[inline(always)] + #[must_use] + pub fn gene_randnum(&mut self) -> GENE_RANDNUM_W { + GENE_RANDNUM_W::new(self) + } + #[doc = "Bit 2 - Reseed the TRNG from noise sources"] + #[inline(always)] + #[must_use] + pub fn exec_randreseed(&mut self) -> EXEC_RANDRESEED_W { + EXEC_RANDRESEED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/ie.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/ie.rs new file mode 100644 index 0000000..dee70fe --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/ie.rs @@ -0,0 +1,86 @@ +#[doc = "Register `ie` reader"] +pub type R = crate::R; +#[doc = "Register `ie` writer"] +pub type W = crate::W; +#[doc = "Field `rand_rdy_en` reader - RAND Ready Enable"] +pub type RAND_RDY_EN_R = crate::BitReader; +#[doc = "Field `rand_rdy_en` writer - RAND Ready Enable"] +pub type RAND_RDY_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `seed_done_en` reader - Seed Done Enable"] +pub type SEED_DONE_EN_R = crate::BitReader; +#[doc = "Field `seed_done_en` writer - Seed Done Enable"] +pub type SEED_DONE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `lfsr_lockup_en` reader - LFSR Lockup Enable"] +pub type LFSR_LOCKUP_EN_R = crate::BitReader; +#[doc = "Field `lfsr_lockup_en` writer - LFSR Lockup Enable"] +pub type LFSR_LOCKUP_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `glbl_en` reader - Global Enable"] +pub type GLBL_EN_R = crate::BitReader; +#[doc = "Field `glbl_en` writer - Global Enable"] +pub type GLBL_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - RAND Ready Enable"] + #[inline(always)] + pub fn rand_rdy_en(&self) -> RAND_RDY_EN_R { + RAND_RDY_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Seed Done Enable"] + #[inline(always)] + pub fn seed_done_en(&self) -> SEED_DONE_EN_R { + SEED_DONE_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - LFSR Lockup Enable"] + #[inline(always)] + pub fn lfsr_lockup_en(&self) -> LFSR_LOCKUP_EN_R { + LFSR_LOCKUP_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 31 - Global Enable"] + #[inline(always)] + pub fn glbl_en(&self) -> GLBL_EN_R { + GLBL_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RAND Ready Enable"] + #[inline(always)] + #[must_use] + pub fn rand_rdy_en(&mut self) -> RAND_RDY_EN_W { + RAND_RDY_EN_W::new(self) + } + #[doc = "Bit 1 - Seed Done Enable"] + #[inline(always)] + #[must_use] + pub fn seed_done_en(&mut self) -> SEED_DONE_EN_W { + SEED_DONE_EN_W::new(self) + } + #[doc = "Bit 4 - LFSR Lockup Enable"] + #[inline(always)] + #[must_use] + pub fn lfsr_lockup_en(&mut self) -> LFSR_LOCKUP_EN_W { + LFSR_LOCKUP_EN_W::new(self) + } + #[doc = "Bit 31 - Global Enable"] + #[inline(always)] + #[must_use] + pub fn glbl_en(&mut self) -> GLBL_EN_W { + GLBL_EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IE_SPEC; +impl crate::RegisterSpec for IE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ie::R`](R) reader structure"] +impl crate::Readable for IE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ie::W`](W) writer structure"] +impl crate::Writable for IE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/istat.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/istat.rs new file mode 100644 index 0000000..d17bc57 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/istat.rs @@ -0,0 +1,47 @@ +#[doc = "Register `istat` reader"] +pub type R = crate::R; +#[doc = "Register `istat` writer"] +pub type W = crate::W; +#[doc = "Field `rand_rdy` reader - RAND Ready Enable"] +pub type RAND_RDY_R = crate::BitReader; +#[doc = "Field `seed_done` reader - Seed Done Enable"] +pub type SEED_DONE_R = crate::BitReader; +#[doc = "Field `lfsr_lockup_en` reader - LFSR Lockup Enable"] +pub type LFSR_LOCKUP_EN_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - RAND Ready Enable"] + #[inline(always)] + pub fn rand_rdy(&self) -> RAND_RDY_R { + RAND_RDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Seed Done Enable"] + #[inline(always)] + pub fn seed_done(&self) -> SEED_DONE_R { + SEED_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - LFSR Lockup Enable"] + #[inline(always)] + pub fn lfsr_lockup_en(&self) -> LFSR_LOCKUP_EN_R { + LFSR_LOCKUP_EN_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`istat::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`istat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ISTAT_SPEC; +impl crate::RegisterSpec for ISTAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`istat::R`](R) reader structure"] +impl crate::Readable for ISTAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`istat::W`](W) writer structure"] +impl crate::Writable for ISTAT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/mode.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/mode.rs new file mode 100644 index 0000000..0483fcb --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/mode.rs @@ -0,0 +1,41 @@ +#[doc = "Register `mode` reader"] +pub type R = crate::R; +#[doc = "Register `mode` writer"] +pub type W = crate::W; +#[doc = "Field `r256` reader - 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode"] +pub type R256_R = crate::BitReader; +#[doc = "Field `r256` writer - 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode"] +pub type R256_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 3 - 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode"] + #[inline(always)] + pub fn r256(&self) -> R256_R { + R256_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 3 - 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode"] + #[inline(always)] + #[must_use] + pub fn r256(&mut self) -> R256_W { + R256_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG MODE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MODE_SPEC; +impl crate::RegisterSpec for MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mode::R`](R) reader structure"] +impl crate::Readable for MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"] +impl crate::Writable for MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand0.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand0.rs new file mode 100644 index 0000000..8d640b8 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `rand0` reader"] +pub type R = crate::R; +#[doc = "Register `rand0` writer"] +pub type W = crate::W; +#[doc = "Field `rand` reader - Random number bits"] +pub type RAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Random number bits"] + #[inline(always)] + pub fn rand(&self) -> RAND_R { + RAND_R::new(self.bits) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG RAND 0 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RAND0_SPEC; +impl crate::RegisterSpec for RAND0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rand0::R`](R) reader structure"] +impl crate::Readable for RAND0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rand0::W`](W) writer structure"] +impl crate::Writable for RAND0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand1.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand1.rs new file mode 100644 index 0000000..02759fc --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `rand1` reader"] +pub type R = crate::R; +#[doc = "Register `rand1` writer"] +pub type W = crate::W; +#[doc = "Field `rand` reader - Random number bits"] +pub type RAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Random number bits"] + #[inline(always)] + pub fn rand(&self) -> RAND_R { + RAND_R::new(self.bits) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG RAND 1 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RAND1_SPEC; +impl crate::RegisterSpec for RAND1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rand1::R`](R) reader structure"] +impl crate::Readable for RAND1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rand1::W`](W) writer structure"] +impl crate::Writable for RAND1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand2.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand2.rs new file mode 100644 index 0000000..9c12892 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `rand2` reader"] +pub type R = crate::R; +#[doc = "Register `rand2` writer"] +pub type W = crate::W; +#[doc = "Field `rand` reader - Random number bits"] +pub type RAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Random number bits"] + #[inline(always)] + pub fn rand(&self) -> RAND_R { + RAND_R::new(self.bits) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG RAND 2 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RAND2_SPEC; +impl crate::RegisterSpec for RAND2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rand2::R`](R) reader structure"] +impl crate::Readable for RAND2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rand2::W`](W) writer structure"] +impl crate::Writable for RAND2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand3.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand3.rs new file mode 100644 index 0000000..3cf673c --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `rand3` reader"] +pub type R = crate::R; +#[doc = "Register `rand3` writer"] +pub type W = crate::W; +#[doc = "Field `rand` reader - Random number bits"] +pub type RAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Random number bits"] + #[inline(always)] + pub fn rand(&self) -> RAND_R { + RAND_R::new(self.bits) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG RAND 3 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RAND3_SPEC; +impl crate::RegisterSpec for RAND3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rand3::R`](R) reader structure"] +impl crate::Readable for RAND3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rand3::W`](W) writer structure"] +impl crate::Writable for RAND3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand4.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand4.rs new file mode 100644 index 0000000..053c800 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `rand4` reader"] +pub type R = crate::R; +#[doc = "Register `rand4` writer"] +pub type W = crate::W; +#[doc = "Field `rand` reader - Random number bits"] +pub type RAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Random number bits"] + #[inline(always)] + pub fn rand(&self) -> RAND_R { + RAND_R::new(self.bits) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG RAND 4 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand4::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RAND4_SPEC; +impl crate::RegisterSpec for RAND4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rand4::R`](R) reader structure"] +impl crate::Readable for RAND4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rand4::W`](W) writer structure"] +impl crate::Writable for RAND4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand5.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand5.rs new file mode 100644 index 0000000..2c3614a --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `rand5` reader"] +pub type R = crate::R; +#[doc = "Register `rand5` writer"] +pub type W = crate::W; +#[doc = "Field `rand` reader - Random number bits"] +pub type RAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Random number bits"] + #[inline(always)] + pub fn rand(&self) -> RAND_R { + RAND_R::new(self.bits) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG RAND 5 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand5::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RAND5_SPEC; +impl crate::RegisterSpec for RAND5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rand5::R`](R) reader structure"] +impl crate::Readable for RAND5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rand5::W`](W) writer structure"] +impl crate::Writable for RAND5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand6.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand6.rs new file mode 100644 index 0000000..62ff145 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `rand6` reader"] +pub type R = crate::R; +#[doc = "Register `rand6` writer"] +pub type W = crate::W; +#[doc = "Field `rand` reader - Random number bits"] +pub type RAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Random number bits"] + #[inline(always)] + pub fn rand(&self) -> RAND_R { + RAND_R::new(self.bits) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG RAND 6 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand6::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RAND6_SPEC; +impl crate::RegisterSpec for RAND6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rand6::R`](R) reader structure"] +impl crate::Readable for RAND6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rand6::W`](W) writer structure"] +impl crate::Writable for RAND6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand7.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand7.rs new file mode 100644 index 0000000..ae12b01 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/rand7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `rand7` reader"] +pub type R = crate::R; +#[doc = "Register `rand7` writer"] +pub type W = crate::W; +#[doc = "Field `rand` reader - Random number bits"] +pub type RAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Random number bits"] + #[inline(always)] + pub fn rand(&self) -> RAND_R { + RAND_R::new(self.bits) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG RAND 7 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand7::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RAND7_SPEC; +impl crate::RegisterSpec for RAND7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rand7::R`](R) reader structure"] +impl crate::Readable for RAND7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rand7::W`](W) writer structure"] +impl crate::Writable for RAND7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/smode.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/smode.rs new file mode 100644 index 0000000..23f0a12 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/smode.rs @@ -0,0 +1,71 @@ +#[doc = "Register `smode` reader"] +pub type R = crate::R; +#[doc = "Register `smode` writer"] +pub type W = crate::W; +#[doc = "Field `nonce_mode` reader - Nonce operation mode"] +pub type NONCE_MODE_R = crate::BitReader; +#[doc = "Field `nonce_mode` writer - Nonce operation mode"] +pub type NONCE_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `mission_mode` reader - Mission operation mode"] +pub type MISSION_MODE_R = crate::BitReader; +#[doc = "Field `mission_mode` writer - Mission operation mode"] +pub type MISSION_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `max_rejects` reader - TRNG Maximum Rejects"] +pub type MAX_REJECTS_R = crate::FieldReader; +#[doc = "Field `max_rejects` writer - TRNG Maximum Rejects"] +pub type MAX_REJECTS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +impl R { + #[doc = "Bit 2 - Nonce operation mode"] + #[inline(always)] + pub fn nonce_mode(&self) -> NONCE_MODE_R { + NONCE_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - Mission operation mode"] + #[inline(always)] + pub fn mission_mode(&self) -> MISSION_MODE_R { + MISSION_MODE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 16:31 - TRNG Maximum Rejects"] + #[inline(always)] + pub fn max_rejects(&self) -> MAX_REJECTS_R { + MAX_REJECTS_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 2 - Nonce operation mode"] + #[inline(always)] + #[must_use] + pub fn nonce_mode(&mut self) -> NONCE_MODE_W { + NONCE_MODE_W::new(self) + } + #[doc = "Bit 8 - Mission operation mode"] + #[inline(always)] + #[must_use] + pub fn mission_mode(&mut self) -> MISSION_MODE_W { + MISSION_MODE_W::new(self) + } + #[doc = "Bits 16:31 - TRNG Maximum Rejects"] + #[inline(always)] + #[must_use] + pub fn max_rejects(&mut self) -> MAX_REJECTS_W { + MAX_REJECTS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG SMODE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smode::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SMODE_SPEC; +impl crate::RegisterSpec for SMODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`smode::R`](R) reader structure"] +impl crate::Readable for SMODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`smode::W`](W) writer structure"] +impl crate::Writable for SMODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/stat.rs b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/stat.rs new file mode 100644 index 0000000..afc22a4 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/starfive_jh7110_trng_0/stat.rs @@ -0,0 +1,131 @@ +#[doc = "Register `stat` reader"] +pub type R = crate::R; +#[doc = "Register `stat` writer"] +pub type W = crate::W; +#[doc = "Field `nonce_mode` reader - TRNG Nonce operating mode"] +pub type NONCE_MODE_R = crate::BitReader; +#[doc = "Field `r256` reader - TRNG 256-bit random number operating mode"] +pub type R256_R = crate::BitReader; +#[doc = "Field `mission_mode` reader - TRNG Mission Mode operating mode"] +pub type MISSION_MODE_R = crate::BitReader; +#[doc = "Field `seeded` reader - TRNG Seeded operating mode"] +pub type SEEDED_R = crate::BitReader; +#[doc = "Field `last_reseed0` reader - TRNG Last Reseed 0 status"] +pub type LAST_RESEED0_R = crate::BitReader; +#[doc = "Field `last_reseed1` reader - TRNG Last Reseed 1 status"] +pub type LAST_RESEED1_R = crate::BitReader; +#[doc = "Field `last_reseed2` reader - TRNG Last Reseed 2 status"] +pub type LAST_RESEED2_R = crate::BitReader; +#[doc = "Field `last_reseed3` reader - TRNG Last Reseed 3 status"] +pub type LAST_RESEED3_R = crate::BitReader; +#[doc = "Field `last_reseed4` reader - TRNG Last Reseed 4 status"] +pub type LAST_RESEED4_R = crate::BitReader; +#[doc = "Field `last_reseed5` reader - TRNG Last Reseed 5 status"] +pub type LAST_RESEED5_R = crate::BitReader; +#[doc = "Field `last_reseed6` reader - TRNG Last Reseed 6 status"] +pub type LAST_RESEED6_R = crate::BitReader; +#[doc = "Field `last_reseed7` reader - TRNG Last Reseed 7 status"] +pub type LAST_RESEED7_R = crate::BitReader; +#[doc = "Field `srvc_rqst` reader - TRNG Service Request"] +pub type SRVC_RQST_R = crate::BitReader; +#[doc = "Field `rand_generating` reader - TRNG Random Number Generating Status"] +pub type RAND_GENERATING_R = crate::BitReader; +#[doc = "Field `rand_seeding` reader - TRNG Random Number Seeding Status"] +pub type RAND_SEEDING_R = crate::BitReader; +impl R { + #[doc = "Bit 2 - TRNG Nonce operating mode"] + #[inline(always)] + pub fn nonce_mode(&self) -> NONCE_MODE_R { + NONCE_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TRNG 256-bit random number operating mode"] + #[inline(always)] + pub fn r256(&self) -> R256_R { + R256_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - TRNG Mission Mode operating mode"] + #[inline(always)] + pub fn mission_mode(&self) -> MISSION_MODE_R { + MISSION_MODE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - TRNG Seeded operating mode"] + #[inline(always)] + pub fn seeded(&self) -> SEEDED_R { + SEEDED_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 16 - TRNG Last Reseed 0 status"] + #[inline(always)] + pub fn last_reseed0(&self) -> LAST_RESEED0_R { + LAST_RESEED0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - TRNG Last Reseed 1 status"] + #[inline(always)] + pub fn last_reseed1(&self) -> LAST_RESEED1_R { + LAST_RESEED1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - TRNG Last Reseed 2 status"] + #[inline(always)] + pub fn last_reseed2(&self) -> LAST_RESEED2_R { + LAST_RESEED2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - TRNG Last Reseed 3 status"] + #[inline(always)] + pub fn last_reseed3(&self) -> LAST_RESEED3_R { + LAST_RESEED3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - TRNG Last Reseed 4 status"] + #[inline(always)] + pub fn last_reseed4(&self) -> LAST_RESEED4_R { + LAST_RESEED4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - TRNG Last Reseed 5 status"] + #[inline(always)] + pub fn last_reseed5(&self) -> LAST_RESEED5_R { + LAST_RESEED5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - TRNG Last Reseed 6 status"] + #[inline(always)] + pub fn last_reseed6(&self) -> LAST_RESEED6_R { + LAST_RESEED6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - TRNG Last Reseed 7 status"] + #[inline(always)] + pub fn last_reseed7(&self) -> LAST_RESEED7_R { + LAST_RESEED7_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 27 - TRNG Service Request"] + #[inline(always)] + pub fn srvc_rqst(&self) -> SRVC_RQST_R { + SRVC_RQST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 30 - TRNG Random Number Generating Status"] + #[inline(always)] + pub fn rand_generating(&self) -> RAND_GENERATING_R { + RAND_GENERATING_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - TRNG Random Number Seeding Status"] + #[inline(always)] + pub fn rand_seeding(&self) -> RAND_SEEDING_R { + RAND_SEEDING_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TRNG STAT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STAT_SPEC; +impl crate::RegisterSpec for STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] +impl crate::Writable for STAT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +}