From fc3c968a08dd6cd9a034c2ee1d1cba42fe3b8edf Mon Sep 17 00:00:00 2001 From: rmsyn Date: Sun, 10 Dec 2023 02:57:53 +0000 Subject: [PATCH] fixup: aon_pinctrl: simplify register names Simplifies register names from the ones supplied in the JH7110 Technical Reference Manual. Uses the `generate_register` helper function to increase code re-use, and add resettable implementations in generated code. --- cmsis-svd-generator | 2 +- .../jh7110-starfive-visionfive-2-v1.2a.svd | 291 +++++----- jh7110-vf2-12a-pac/src/aon_pinctrl.rs | 523 ++++++++---------- .../aon_iomux_cfgsaif_syscfg100.rs | 47 -- .../aon_iomux_cfgsaif_syscfg104.rs | 47 -- .../aon_iomux_cfgsaif_syscfg108.rs | 47 -- .../aon_iomux_cfgsaif_syscfg112.rs | 47 -- .../aon_iomux_cfgsaif_syscfg116.rs | 47 -- .../aon_iomux_cfgsaif_syscfg120.rs | 47 -- .../aon_iomux_cfgsaif_syscfg124.rs | 47 -- .../aon_iomux_cfgsaif_syscfg128.rs | 47 -- .../aon_iomux_cfgsaif_syscfg132.rs | 47 -- .../aon_iomux_cfgsaif_syscfg136.rs | 47 -- .../aon_iomux_cfgsaif_syscfg140.rs | 47 -- .../aon_iomux_cfgsaif_syscfg144.rs | 47 -- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs | 47 -- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs | 149 ----- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs | 149 ----- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs | 149 ----- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs | 149 ----- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs | 64 --- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs | 45 -- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs | 45 -- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs | 47 -- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs | 47 -- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs | 47 -- .../aon_iomux_cfgsaif_syscfg_fmux0.rs | 98 ---- .../aon_iomux_cfgsaif_syscfg_fmux1.rs | 98 ---- .../aon_iomux_cfgsaif_syscfg_fmux2.rs | 114 ---- .../aon_iomux_cfgsaif_syscfg_fmux3.rs | 45 -- .../aon_iomux_cfgsaif_syscfg_ioirq10.rs | 37 -- .../aon_iomux_cfgsaif_syscfg_ioirq11.rs | 37 -- .../aon_iomux_cfgsaif_syscfg_ioirq4.rs | 45 -- .../aon_iomux_cfgsaif_syscfg_ioirq5.rs | 45 -- .../aon_iomux_cfgsaif_syscfg_ioirq6.rs | 47 -- .../aon_iomux_cfgsaif_syscfg_ioirq7.rs | 47 -- .../aon_iomux_cfgsaif_syscfg_ioirq8.rs | 45 -- .../aon_iomux_cfgsaif_syscfg_ioirq9.rs | 37 -- jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_0.rs | 94 ++++ jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_1.rs | 94 ++++ jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_2.rs | 94 ++++ jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_3.rs | 49 ++ .../src/aon_pinctrl/gmac0_mdc.rs | 49 ++ .../src/aon_pinctrl/gmac0_mdio.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxc.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxc_func_sel.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxd0.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxd1.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxd2.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxd3.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxdv.rs | 49 ++ .../src/aon_pinctrl/gmac0_txc.rs | 49 ++ .../src/aon_pinctrl/gmac0_txd0.rs | 49 ++ .../src/aon_pinctrl/gmac0_txd1.rs | 49 ++ .../src/aon_pinctrl/gmac0_txd2.rs | 49 ++ .../src/aon_pinctrl/gmac0_txd3.rs | 49 ++ .../src/aon_pinctrl/gmac0_txen.rs | 49 ++ jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_0.rs | 49 ++ jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_1.rs | 49 ++ jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_2.rs | 49 ++ jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_3.rs | 49 ++ jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_4.rs | 49 ++ jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_5.rs | 41 ++ jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_6.rs | 41 ++ jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_7.rs | 41 ++ jh7110-vf2-12a-pac/src/aon_pinctrl/osc.rs | 49 ++ jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_0.rs | 139 +++++ jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_1.rs | 139 +++++ jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_2.rs | 139 +++++ jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_3.rs | 139 +++++ jh7110-vf2-12a-pac/src/aon_pinctrl/rstn.rs | 64 +++ jh7110-vf2-12a-pac/src/aon_pinctrl/rtc.rs | 49 ++ jh7110-vf2-12a-pac/src/aon_pinctrl/testen.rs | 49 ++ .../jh7110-starfive-visionfive-2-v1.3b.svd | 291 +++++----- jh7110-vf2-13b-pac/src/aon_pinctrl.rs | 523 ++++++++---------- .../aon_iomux_cfgsaif_syscfg100.rs | 47 -- .../aon_iomux_cfgsaif_syscfg104.rs | 47 -- .../aon_iomux_cfgsaif_syscfg108.rs | 47 -- .../aon_iomux_cfgsaif_syscfg112.rs | 47 -- .../aon_iomux_cfgsaif_syscfg116.rs | 47 -- .../aon_iomux_cfgsaif_syscfg120.rs | 47 -- .../aon_iomux_cfgsaif_syscfg124.rs | 47 -- .../aon_iomux_cfgsaif_syscfg128.rs | 47 -- .../aon_iomux_cfgsaif_syscfg132.rs | 47 -- .../aon_iomux_cfgsaif_syscfg136.rs | 47 -- .../aon_iomux_cfgsaif_syscfg140.rs | 47 -- .../aon_iomux_cfgsaif_syscfg144.rs | 47 -- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs | 47 -- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs | 149 ----- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs | 149 ----- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs | 149 ----- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs | 149 ----- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs | 64 --- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs | 45 -- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs | 45 -- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs | 47 -- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs | 47 -- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs | 47 -- .../aon_iomux_cfgsaif_syscfg_fmux0.rs | 98 ---- .../aon_iomux_cfgsaif_syscfg_fmux1.rs | 98 ---- .../aon_iomux_cfgsaif_syscfg_fmux2.rs | 114 ---- .../aon_iomux_cfgsaif_syscfg_fmux3.rs | 45 -- .../aon_iomux_cfgsaif_syscfg_ioirq10.rs | 37 -- .../aon_iomux_cfgsaif_syscfg_ioirq11.rs | 37 -- .../aon_iomux_cfgsaif_syscfg_ioirq4.rs | 45 -- .../aon_iomux_cfgsaif_syscfg_ioirq5.rs | 45 -- .../aon_iomux_cfgsaif_syscfg_ioirq6.rs | 47 -- .../aon_iomux_cfgsaif_syscfg_ioirq7.rs | 47 -- .../aon_iomux_cfgsaif_syscfg_ioirq8.rs | 45 -- .../aon_iomux_cfgsaif_syscfg_ioirq9.rs | 37 -- jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_0.rs | 94 ++++ jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_1.rs | 94 ++++ jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_2.rs | 94 ++++ jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_3.rs | 49 ++ .../src/aon_pinctrl/gmac0_mdc.rs | 49 ++ .../src/aon_pinctrl/gmac0_mdio.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxc.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxc_func_sel.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxd0.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxd1.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxd2.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxd3.rs | 49 ++ .../src/aon_pinctrl/gmac0_rxdv.rs | 49 ++ .../src/aon_pinctrl/gmac0_txc.rs | 49 ++ .../src/aon_pinctrl/gmac0_txd0.rs | 49 ++ .../src/aon_pinctrl/gmac0_txd1.rs | 49 ++ .../src/aon_pinctrl/gmac0_txd2.rs | 49 ++ .../src/aon_pinctrl/gmac0_txd3.rs | 49 ++ .../src/aon_pinctrl/gmac0_txen.rs | 49 ++ jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_0.rs | 49 ++ jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_1.rs | 49 ++ jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_2.rs | 49 ++ jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_3.rs | 49 ++ jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_4.rs | 49 ++ jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_5.rs | 41 ++ jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_6.rs | 41 ++ jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_7.rs | 41 ++ jh7110-vf2-13b-pac/src/aon_pinctrl/osc.rs | 49 ++ jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_0.rs | 139 +++++ jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_1.rs | 139 +++++ jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_2.rs | 139 +++++ jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_3.rs | 139 +++++ jh7110-vf2-13b-pac/src/aon_pinctrl/rstn.rs | 64 +++ jh7110-vf2-13b-pac/src/aon_pinctrl/rtc.rs | 49 ++ jh7110-vf2-13b-pac/src/aon_pinctrl/testen.rs | 49 ++ 145 files changed, 5217 insertions(+), 5209 deletions(-) delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs delete mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_0.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_1.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_2.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_3.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_mdc.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_mdio.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxc.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxc_func_sel.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd0.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd1.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd2.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd3.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxdv.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txc.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd0.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd1.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd2.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd3.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txen.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_0.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_1.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_2.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_3.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_4.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_5.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_6.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_7.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/osc.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_0.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_1.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_2.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_3.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/rstn.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/rtc.rs create mode 100644 jh7110-vf2-12a-pac/src/aon_pinctrl/testen.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs delete mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_0.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_1.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_2.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_3.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_mdc.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_mdio.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxc.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxc_func_sel.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd0.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd1.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd2.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd3.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxdv.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txc.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd0.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd1.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd2.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd3.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txen.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_0.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_1.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_2.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_3.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_4.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_5.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_6.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_7.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/osc.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_0.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_1.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_2.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_3.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/rstn.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/rtc.rs create mode 100644 jh7110-vf2-13b-pac/src/aon_pinctrl/testen.rs diff --git a/cmsis-svd-generator b/cmsis-svd-generator index 65216a6..abd71f4 160000 --- a/cmsis-svd-generator +++ b/cmsis-svd-generator @@ -1 +1 @@ -Subproject commit 65216a6443f9409fec097eeecee62e988957f3bb +Subproject commit abd71f444d53e7824f0cb8f308be1cc54f5a922b diff --git a/jh7110-vf2-12a-pac/jh7110-starfive-visionfive-2-v1.2a.svd b/jh7110-vf2-12a-pac/jh7110-starfive-visionfive-2-v1.2a.svd index 21f2453..b2dbcc4 100644 --- a/jh7110-vf2-12a-pac/jh7110-starfive-visionfive-2-v1.2a.svd +++ b/jh7110-vf2-12a-pac/jh7110-starfive-visionfive-2-v1.2a.svd @@ -43145,31 +43145,32 @@ - aon_iomux_cfgsaif_syscfg_fmux0 + fmux_0 AON IOMUX CFG SAIF SYSCFG FMUX 0 0x0 32 + 0 - aon_iomux_gpo0_doen_cfg + gpo_doen_0 The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [2:0] read-write - aon_iomux_gpo1_doen_cfg + gpo_doen_1 The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [10:8] read-write - aon_iomux_gpo2_doen_cfg + gpo_doen_2 The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [18:16] read-write - aon_iomux_gpo3_doen_cfg + gpo_doen_3 The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [26:24] read-write @@ -43177,31 +43178,32 @@ - aon_iomux_cfgsaif_syscfg_fmux1 - AON IOMUX CFG SAIF SYSCFG FMUX 1 + fmux_1 + AON IOMUX CFG SAIF SYSCFG FMUX 4 0x4 32 + 0 - aon_iomux_gpo0_dout_cfg + gpo_dout_0 The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [3:0] read-write - aon_iomux_gpo1_dout_cfg + gpo_dout_1 The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [11:8] read-write - aon_iomux_gpo2_dout_cfg + gpo_dout_2 The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [19:16] read-write - aon_iomux_gpo3_dout_cfg + gpo_dout_3 The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [27:24] read-write @@ -43209,31 +43211,32 @@ - aon_iomux_cfgsaif_syscfg_fmux2 - AON IOMUX CFG SAIF SYSCFG FMUX 2 + fmux_2 + AON IOMUX CFG SAIF SYSCFG FMUX 8 0x8 32 + 0 - aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg + gpi_pmu_wakeup_0 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [2:0] read-write - aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg + gpi_pmu_wakeup_1 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [10:8] read-write - aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg + gpi_pmu_wakeup_2 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [18:16] read-write - aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg + gpi_pmu_wakeup_3 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [26:24] read-write @@ -43241,13 +43244,14 @@ - aon_iomux_cfgsaif_syscfg_fmux3 - AON IOMUX CFG SAIF SYSCFG FMUX 3 + fmux_3 + AON IOMUX CFG SAIF SYSCFG FMUX 12 0xc 32 + 0 - aon_gpioen_0_reg + gpen_0 Enable GPIO IRQ function. [0:0] read-write @@ -43255,13 +43259,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq4 - AON IOMUX CFG SAIF SYSCFG IOIRQ 4 + ioirq_0 + AON IOMUX CFG SAIF SYSCFG IOIRQ 16 0x10 32 + 0 - aon_gpiois_0_reg + is 1: Edge trigger, 0: Level trigger [3:0] read-write @@ -43269,13 +43274,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq5 - AON IOMUX CFG SAIF SYSCFG IOIRQ 5 + ioirq_1 + AON IOMUX CFG SAIF SYSCFG IOIRQ 20 0x14 32 + 0 - aon_gpioic_0_reg + ic 1: Do not clear the register, 0: Clear the register [3:0] read-write @@ -43283,13 +43289,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq6 - AON IOMUX CFG SAIF SYSCFG IOIRQ 6 + ioirq_2 + AON IOMUX CFG SAIF SYSCFG IOIRQ 24 0x18 32 + 0 - aon_gpioibe_0_reg + ibe 1: Trigger on both edges, 0: Trigger on a single edge [3:0] read-write @@ -43297,13 +43304,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq7 - AON IOMUX CFG SAIF SYSCFG IOIRQ 7 + ioirq_3 + AON IOMUX CFG SAIF SYSCFG IOIRQ 28 0x1c 32 + 0 - aon_gpioiev_0_reg + iev 1: Positive/Low, 0: Negative/High [3:0] read-write @@ -43311,13 +43319,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq8 - AON IOMUX CFG SAIF SYSCFG IOIRQ 8 + ioirq_4 + AON IOMUX CFG SAIF SYSCFG IOIRQ 32 0x20 32 + 0 - aon_gpioie_0_reg + ie 1: Unmask, 0: Mask [3:0] read-write @@ -43325,13 +43334,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq9 - AON IOMUX CFG SAIF SYSCFG IOIRQ 9 + ioirq_5 + AON IOMUX CFG SAIF SYSCFG IOIRQ 36 0x24 32 + 0 - aon_gpioris_0_reg + ris Status of the edge trigger, can be cleared by writing gpioic. [3:0] read-only @@ -43339,13 +43349,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq10 - AON IOMUX CFG SAIF SYSCFG IOIRQ 10 + ioirq_6 + AON IOMUX CFG SAIF SYSCFG IOIRQ 40 0x28 32 + 0 - aon_gpiomis_0_reg + mis The masked GPIO IRQ status. [3:0] read-only @@ -43353,13 +43364,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq11 - AON IOMUX CFG SAIF SYSCFG IOIRQ 11 + ioirq_7 + AON IOMUX CFG SAIF SYSCFG IOIRQ 44 0x2c 32 + 0 - aon_gpio_in_sync2_0_reg + in_sync2 Status of gpio_in after synchronization. [3:0] read-only @@ -43367,13 +43379,14 @@ - aon_iomux_cfgsaif_syscfg48 + testen AON IOMUX CFG SAIF SYSCFG 48 0x30 32 + 0 - padcfg_pad_testen_pos + testen_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [0:0] read-write @@ -43381,49 +43394,50 @@ - aon_iomux_cfgsaif_syscfg52 + rgpio_0 AON IOMUX CFG SAIF SYSCFG 52 0x34 32 + 0 - padcfg_pad_rgpio0_ie + ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_rgpio0_ds + ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_rgpio0_pu + pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_rgpio0_pd + pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_rgpio0_slew + slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_rgpio0_smt + smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_rgpio0_pos + pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -43431,49 +43445,50 @@ - aon_iomux_cfgsaif_syscfg56 + rgpio_1 AON IOMUX CFG SAIF SYSCFG 56 0x38 32 + 0 - padcfg_pad_rgpio1_ie + ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_rgpio1_ds + ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_rgpio1_pu + pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_rgpio1_pd + pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_rgpio1_slew + slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_rgpio1_smt + smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_rgpio1_pos + pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -43481,49 +43496,50 @@ - aon_iomux_cfgsaif_syscfg60 + rgpio_2 AON IOMUX CFG SAIF SYSCFG 60 0x3c 32 + 0 - padcfg_pad_rgpio2_ie + ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_rgpio2_ds + ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_rgpio2_pu + pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_rgpio2_pd + pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_rgpio2_slew + slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_rgpio2_smt + smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_rgpio2_pos + pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -43531,49 +43547,50 @@ - aon_iomux_cfgsaif_syscfg64 + rgpio_3 AON IOMUX CFG SAIF SYSCFG 64 0x40 32 + 0 - padcfg_pad_rgpio3_ie + ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_rgpio3_ds + ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_rgpio3_pu + pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_rgpio3_pd + pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_rgpio3_slew + slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_rgpio3_smt + smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_rgpio3_pos + pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -43581,19 +43598,20 @@ - aon_iomux_cfgsaif_syscfg68 + rstn AON IOMUX CFG SAIF SYSCFG 68 0x44 32 + 0 - padcfg_pad_rstn_smt + smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled [0:0] read-write - padcfg_pad_rstn_pos + pos Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled [1:1] read-write @@ -43601,13 +43619,14 @@ - aon_iomux_cfgsaif_syscfg76 + rtc AON IOMUX CFG SAIF SYSCFG 76 0x4c 32 + 0 - padcfg_pad_rtc_ds + ds Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA. [1:0] read-write @@ -43615,13 +43634,14 @@ - aon_iomux_cfgsaif_syscfg84 + osc AON IOMUX CFG SAIF SYSCFG 84 0x54 32 + 0 - padcfg_pad_osc_ds + ds Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA. [1:0] read-write @@ -43629,41 +43649,44 @@ - aon_iomux_cfgsaif_syscfg88 + gmac0_mdc AON IOMUX CFG SAIF SYSCFG 88 0x58 32 + 0 - padcfg_pad_gmac0_mdc_syscon - padcfg_pad_gmac0_mdc_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg92 + gmac0_mdio AON IOMUX CFG SAIF SYSCFG 92 0x5c 32 + 0 - padcfg_pad_gmac0_mdio_syscon - padcfg_pad_gmac0_mdio_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg96 + gmac0_rxd0 AON IOMUX CFG SAIF SYSCFG 96 0x60 32 + 0 - padcfg_pad_gmac0_rxd0_syscon + value 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V [1:0] read-write @@ -43671,167 +43694,179 @@ - aon_iomux_cfgsaif_syscfg100 + gmac0_rxd1 AON IOMUX CFG SAIF SYSCFG 100 0x64 32 + 0 - padcfg_pad_gmac0_rxd1_syscon - padcfg_pad_gmac0_rxd1_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg104 + gmac0_rxd2 AON IOMUX CFG SAIF SYSCFG 104 0x68 32 + 0 - padcfg_pad_gmac0_rxd2_syscon - padcfg_pad_gmac0_rxd2_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg108 + gmac0_rxd3 AON IOMUX CFG SAIF SYSCFG 108 0x6c 32 + 0 - padcfg_pad_gmac0_rxd3_syscon - padcfg_pad_gmac0_rxd3_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg112 + gmac0_rxdv AON IOMUX CFG SAIF SYSCFG 112 0x70 32 + 0 - padcfg_pad_gmac0_rxdv_syscon - padcfg_pad_gmac0_rxdv_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg116 + gmac0_rxc AON IOMUX CFG SAIF SYSCFG 116 0x74 32 + 0 - padcfg_pad_gmac0_rxc_syscon - padcfg_pad_gmac0_rxc_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg120 + gmac0_txd0 AON IOMUX CFG SAIF SYSCFG 120 0x78 32 + 0 - padcfg_pad_gmac0_txd0_syscon - padcfg_pad_gmac0_txd0_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg124 + gmac0_txd1 AON IOMUX CFG SAIF SYSCFG 124 0x7c 32 + 0 - padcfg_pad_gmac0_txd1_syscon - padcfg_pad_gmac0_txd1_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg128 + gmac0_txd2 AON IOMUX CFG SAIF SYSCFG 128 0x80 32 + 0 - padcfg_pad_gmac0_txd2_syscon - padcfg_pad_gmac0_txd2_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg132 + gmac0_txd3 AON IOMUX CFG SAIF SYSCFG 132 0x84 32 + 0 - padcfg_pad_gmac0_txd3_syscon - padcfg_pad_gmac0_txd3_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg136 + gmac0_txen AON IOMUX CFG SAIF SYSCFG 136 0x88 32 + 0 - padcfg_pad_gmac0_txen_syscon - padcfg_pad_gmac0_txen_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg140 + gmac0_txc AON IOMUX CFG SAIF SYSCFG 140 0x8c 32 + 0 - padcfg_pad_gmac0_txc_syscon - padcfg_pad_gmac0_txc_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg144 + gmac0_rxc_func_sel AON IOMUX CFG SAIF SYSCFG 144 0x90 32 + 0 - pad_gmac0_rxc_func_sel + value Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None [1:0] read-write diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl.rs index 665a4ad..1a9cf4d 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl.rs @@ -1,428 +1,393 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - aon_iomux_cfgsaif_syscfg_fmux0: AON_IOMUX_CFGSAIF_SYSCFG_FMUX0, - aon_iomux_cfgsaif_syscfg_fmux1: AON_IOMUX_CFGSAIF_SYSCFG_FMUX1, - aon_iomux_cfgsaif_syscfg_fmux2: AON_IOMUX_CFGSAIF_SYSCFG_FMUX2, - aon_iomux_cfgsaif_syscfg_fmux3: AON_IOMUX_CFGSAIF_SYSCFG_FMUX3, - aon_iomux_cfgsaif_syscfg_ioirq4: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4, - aon_iomux_cfgsaif_syscfg_ioirq5: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5, - aon_iomux_cfgsaif_syscfg_ioirq6: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6, - aon_iomux_cfgsaif_syscfg_ioirq7: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7, - aon_iomux_cfgsaif_syscfg_ioirq8: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8, - aon_iomux_cfgsaif_syscfg_ioirq9: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9, - aon_iomux_cfgsaif_syscfg_ioirq10: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10, - aon_iomux_cfgsaif_syscfg_ioirq11: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11, - aon_iomux_cfgsaif_syscfg48: AON_IOMUX_CFGSAIF_SYSCFG48, - aon_iomux_cfgsaif_syscfg52: AON_IOMUX_CFGSAIF_SYSCFG52, - aon_iomux_cfgsaif_syscfg56: AON_IOMUX_CFGSAIF_SYSCFG56, - aon_iomux_cfgsaif_syscfg60: AON_IOMUX_CFGSAIF_SYSCFG60, - aon_iomux_cfgsaif_syscfg64: AON_IOMUX_CFGSAIF_SYSCFG64, - aon_iomux_cfgsaif_syscfg68: AON_IOMUX_CFGSAIF_SYSCFG68, + fmux_0: FMUX_0, + fmux_1: FMUX_1, + fmux_2: FMUX_2, + fmux_3: FMUX_3, + ioirq_0: IOIRQ_0, + ioirq_1: IOIRQ_1, + ioirq_2: IOIRQ_2, + ioirq_3: IOIRQ_3, + ioirq_4: IOIRQ_4, + ioirq_5: IOIRQ_5, + ioirq_6: IOIRQ_6, + ioirq_7: IOIRQ_7, + testen: TESTEN, + rgpio_0: RGPIO_0, + rgpio_1: RGPIO_1, + rgpio_2: RGPIO_2, + rgpio_3: RGPIO_3, + rstn: RSTN, _reserved18: [u8; 0x04], - aon_iomux_cfgsaif_syscfg76: AON_IOMUX_CFGSAIF_SYSCFG76, + rtc: RTC, _reserved19: [u8; 0x04], - aon_iomux_cfgsaif_syscfg84: AON_IOMUX_CFGSAIF_SYSCFG84, - aon_iomux_cfgsaif_syscfg88: AON_IOMUX_CFGSAIF_SYSCFG88, - aon_iomux_cfgsaif_syscfg92: AON_IOMUX_CFGSAIF_SYSCFG92, - aon_iomux_cfgsaif_syscfg96: AON_IOMUX_CFGSAIF_SYSCFG96, - aon_iomux_cfgsaif_syscfg100: AON_IOMUX_CFGSAIF_SYSCFG100, - aon_iomux_cfgsaif_syscfg104: AON_IOMUX_CFGSAIF_SYSCFG104, - aon_iomux_cfgsaif_syscfg108: AON_IOMUX_CFGSAIF_SYSCFG108, - aon_iomux_cfgsaif_syscfg112: AON_IOMUX_CFGSAIF_SYSCFG112, - aon_iomux_cfgsaif_syscfg116: AON_IOMUX_CFGSAIF_SYSCFG116, - aon_iomux_cfgsaif_syscfg120: AON_IOMUX_CFGSAIF_SYSCFG120, - aon_iomux_cfgsaif_syscfg124: AON_IOMUX_CFGSAIF_SYSCFG124, - aon_iomux_cfgsaif_syscfg128: AON_IOMUX_CFGSAIF_SYSCFG128, - aon_iomux_cfgsaif_syscfg132: AON_IOMUX_CFGSAIF_SYSCFG132, - aon_iomux_cfgsaif_syscfg136: AON_IOMUX_CFGSAIF_SYSCFG136, - aon_iomux_cfgsaif_syscfg140: AON_IOMUX_CFGSAIF_SYSCFG140, - aon_iomux_cfgsaif_syscfg144: AON_IOMUX_CFGSAIF_SYSCFG144, + osc: OSC, + gmac0_mdc: GMAC0_MDC, + gmac0_mdio: GMAC0_MDIO, + gmac0_rxd0: GMAC0_RXD0, + gmac0_rxd1: GMAC0_RXD1, + gmac0_rxd2: GMAC0_RXD2, + gmac0_rxd3: GMAC0_RXD3, + gmac0_rxdv: GMAC0_RXDV, + gmac0_rxc: GMAC0_RXC, + gmac0_txd0: GMAC0_TXD0, + gmac0_txd1: GMAC0_TXD1, + gmac0_txd2: GMAC0_TXD2, + gmac0_txd3: GMAC0_TXD3, + gmac0_txen: GMAC0_TXEN, + gmac0_txc: GMAC0_TXC, + gmac0_rxc_func_sel: GMAC0_RXC_FUNC_SEL, } impl RegisterBlock { #[doc = "0x00 - AON IOMUX CFG SAIF SYSCFG FMUX 0"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_fmux0(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX0 { - &self.aon_iomux_cfgsaif_syscfg_fmux0 + pub const fn fmux_0(&self) -> &FMUX_0 { + &self.fmux_0 } - #[doc = "0x04 - AON IOMUX CFG SAIF SYSCFG FMUX 1"] + #[doc = "0x04 - AON IOMUX CFG SAIF SYSCFG FMUX 4"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_fmux1(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX1 { - &self.aon_iomux_cfgsaif_syscfg_fmux1 + pub const fn fmux_1(&self) -> &FMUX_1 { + &self.fmux_1 } - #[doc = "0x08 - AON IOMUX CFG SAIF SYSCFG FMUX 2"] + #[doc = "0x08 - AON IOMUX CFG SAIF SYSCFG FMUX 8"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_fmux2(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX2 { - &self.aon_iomux_cfgsaif_syscfg_fmux2 + pub const fn fmux_2(&self) -> &FMUX_2 { + &self.fmux_2 } - #[doc = "0x0c - AON IOMUX CFG SAIF SYSCFG FMUX 3"] + #[doc = "0x0c - AON IOMUX CFG SAIF SYSCFG FMUX 12"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_fmux3(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX3 { - &self.aon_iomux_cfgsaif_syscfg_fmux3 + pub const fn fmux_3(&self) -> &FMUX_3 { + &self.fmux_3 } - #[doc = "0x10 - AON IOMUX CFG SAIF SYSCFG IOIRQ 4"] + #[doc = "0x10 - AON IOMUX CFG SAIF SYSCFG IOIRQ 16"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq4(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4 { - &self.aon_iomux_cfgsaif_syscfg_ioirq4 + pub const fn ioirq_0(&self) -> &IOIRQ_0 { + &self.ioirq_0 } - #[doc = "0x14 - AON IOMUX CFG SAIF SYSCFG IOIRQ 5"] + #[doc = "0x14 - AON IOMUX CFG SAIF SYSCFG IOIRQ 20"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq5(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5 { - &self.aon_iomux_cfgsaif_syscfg_ioirq5 + pub const fn ioirq_1(&self) -> &IOIRQ_1 { + &self.ioirq_1 } - #[doc = "0x18 - AON IOMUX CFG SAIF SYSCFG IOIRQ 6"] + #[doc = "0x18 - AON IOMUX CFG SAIF SYSCFG IOIRQ 24"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq6(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6 { - &self.aon_iomux_cfgsaif_syscfg_ioirq6 + pub const fn ioirq_2(&self) -> &IOIRQ_2 { + &self.ioirq_2 } - #[doc = "0x1c - AON IOMUX CFG SAIF SYSCFG IOIRQ 7"] + #[doc = "0x1c - AON IOMUX CFG SAIF SYSCFG IOIRQ 28"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq7(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7 { - &self.aon_iomux_cfgsaif_syscfg_ioirq7 + pub const fn ioirq_3(&self) -> &IOIRQ_3 { + &self.ioirq_3 } - #[doc = "0x20 - AON IOMUX CFG SAIF SYSCFG IOIRQ 8"] + #[doc = "0x20 - AON IOMUX CFG SAIF SYSCFG IOIRQ 32"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq8(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8 { - &self.aon_iomux_cfgsaif_syscfg_ioirq8 + pub const fn ioirq_4(&self) -> &IOIRQ_4 { + &self.ioirq_4 } - #[doc = "0x24 - AON IOMUX CFG SAIF SYSCFG IOIRQ 9"] + #[doc = "0x24 - AON IOMUX CFG SAIF SYSCFG IOIRQ 36"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq9(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9 { - &self.aon_iomux_cfgsaif_syscfg_ioirq9 + pub const fn ioirq_5(&self) -> &IOIRQ_5 { + &self.ioirq_5 } - #[doc = "0x28 - AON IOMUX CFG SAIF SYSCFG IOIRQ 10"] + #[doc = "0x28 - AON IOMUX CFG SAIF SYSCFG IOIRQ 40"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq10(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10 { - &self.aon_iomux_cfgsaif_syscfg_ioirq10 + pub const fn ioirq_6(&self) -> &IOIRQ_6 { + &self.ioirq_6 } - #[doc = "0x2c - AON IOMUX CFG SAIF SYSCFG IOIRQ 11"] + #[doc = "0x2c - AON IOMUX CFG SAIF SYSCFG IOIRQ 44"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq11(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11 { - &self.aon_iomux_cfgsaif_syscfg_ioirq11 + pub const fn ioirq_7(&self) -> &IOIRQ_7 { + &self.ioirq_7 } #[doc = "0x30 - AON IOMUX CFG SAIF SYSCFG 48"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg48(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG48 { - &self.aon_iomux_cfgsaif_syscfg48 + pub const fn testen(&self) -> &TESTEN { + &self.testen } #[doc = "0x34 - AON IOMUX CFG SAIF SYSCFG 52"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg52(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG52 { - &self.aon_iomux_cfgsaif_syscfg52 + pub const fn rgpio_0(&self) -> &RGPIO_0 { + &self.rgpio_0 } #[doc = "0x38 - AON IOMUX CFG SAIF SYSCFG 56"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg56(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG56 { - &self.aon_iomux_cfgsaif_syscfg56 + pub const fn rgpio_1(&self) -> &RGPIO_1 { + &self.rgpio_1 } #[doc = "0x3c - AON IOMUX CFG SAIF SYSCFG 60"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg60(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG60 { - &self.aon_iomux_cfgsaif_syscfg60 + pub const fn rgpio_2(&self) -> &RGPIO_2 { + &self.rgpio_2 } #[doc = "0x40 - AON IOMUX CFG SAIF SYSCFG 64"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg64(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG64 { - &self.aon_iomux_cfgsaif_syscfg64 + pub const fn rgpio_3(&self) -> &RGPIO_3 { + &self.rgpio_3 } #[doc = "0x44 - AON IOMUX CFG SAIF SYSCFG 68"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg68(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG68 { - &self.aon_iomux_cfgsaif_syscfg68 + pub const fn rstn(&self) -> &RSTN { + &self.rstn } #[doc = "0x4c - AON IOMUX CFG SAIF SYSCFG 76"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg76(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG76 { - &self.aon_iomux_cfgsaif_syscfg76 + pub const fn rtc(&self) -> &RTC { + &self.rtc } #[doc = "0x54 - AON IOMUX CFG SAIF SYSCFG 84"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg84(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG84 { - &self.aon_iomux_cfgsaif_syscfg84 + pub const fn osc(&self) -> &OSC { + &self.osc } #[doc = "0x58 - AON IOMUX CFG SAIF SYSCFG 88"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg88(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG88 { - &self.aon_iomux_cfgsaif_syscfg88 + pub const fn gmac0_mdc(&self) -> &GMAC0_MDC { + &self.gmac0_mdc } #[doc = "0x5c - AON IOMUX CFG SAIF SYSCFG 92"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg92(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG92 { - &self.aon_iomux_cfgsaif_syscfg92 + pub const fn gmac0_mdio(&self) -> &GMAC0_MDIO { + &self.gmac0_mdio } #[doc = "0x60 - AON IOMUX CFG SAIF SYSCFG 96"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg96(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG96 { - &self.aon_iomux_cfgsaif_syscfg96 + pub const fn gmac0_rxd0(&self) -> &GMAC0_RXD0 { + &self.gmac0_rxd0 } #[doc = "0x64 - AON IOMUX CFG SAIF SYSCFG 100"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg100(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG100 { - &self.aon_iomux_cfgsaif_syscfg100 + pub const fn gmac0_rxd1(&self) -> &GMAC0_RXD1 { + &self.gmac0_rxd1 } #[doc = "0x68 - AON IOMUX CFG SAIF SYSCFG 104"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg104(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG104 { - &self.aon_iomux_cfgsaif_syscfg104 + pub const fn gmac0_rxd2(&self) -> &GMAC0_RXD2 { + &self.gmac0_rxd2 } #[doc = "0x6c - AON IOMUX CFG SAIF SYSCFG 108"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg108(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG108 { - &self.aon_iomux_cfgsaif_syscfg108 + pub const fn gmac0_rxd3(&self) -> &GMAC0_RXD3 { + &self.gmac0_rxd3 } #[doc = "0x70 - AON IOMUX CFG SAIF SYSCFG 112"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg112(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG112 { - &self.aon_iomux_cfgsaif_syscfg112 + pub const fn gmac0_rxdv(&self) -> &GMAC0_RXDV { + &self.gmac0_rxdv } #[doc = "0x74 - AON IOMUX CFG SAIF SYSCFG 116"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg116(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG116 { - &self.aon_iomux_cfgsaif_syscfg116 + pub const fn gmac0_rxc(&self) -> &GMAC0_RXC { + &self.gmac0_rxc } #[doc = "0x78 - AON IOMUX CFG SAIF SYSCFG 120"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg120(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG120 { - &self.aon_iomux_cfgsaif_syscfg120 + pub const fn gmac0_txd0(&self) -> &GMAC0_TXD0 { + &self.gmac0_txd0 } #[doc = "0x7c - AON IOMUX CFG SAIF SYSCFG 124"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg124(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG124 { - &self.aon_iomux_cfgsaif_syscfg124 + pub const fn gmac0_txd1(&self) -> &GMAC0_TXD1 { + &self.gmac0_txd1 } #[doc = "0x80 - AON IOMUX CFG SAIF SYSCFG 128"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg128(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG128 { - &self.aon_iomux_cfgsaif_syscfg128 + pub const fn gmac0_txd2(&self) -> &GMAC0_TXD2 { + &self.gmac0_txd2 } #[doc = "0x84 - AON IOMUX CFG SAIF SYSCFG 132"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg132(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG132 { - &self.aon_iomux_cfgsaif_syscfg132 + pub const fn gmac0_txd3(&self) -> &GMAC0_TXD3 { + &self.gmac0_txd3 } #[doc = "0x88 - AON IOMUX CFG SAIF SYSCFG 136"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg136(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG136 { - &self.aon_iomux_cfgsaif_syscfg136 + pub const fn gmac0_txen(&self) -> &GMAC0_TXEN { + &self.gmac0_txen } #[doc = "0x8c - AON IOMUX CFG SAIF SYSCFG 140"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg140(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG140 { - &self.aon_iomux_cfgsaif_syscfg140 + pub const fn gmac0_txc(&self) -> &GMAC0_TXC { + &self.gmac0_txc } #[doc = "0x90 - AON IOMUX CFG SAIF SYSCFG 144"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg144(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG144 { - &self.aon_iomux_cfgsaif_syscfg144 + pub const fn gmac0_rxc_func_sel(&self) -> &GMAC0_RXC_FUNC_SEL { + &self.gmac0_rxc_func_sel } } -#[doc = "aon_iomux_cfgsaif_syscfg_fmux0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux0`] +#[doc = "fmux_0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmux_0`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX0 = - crate::Reg; +pub type FMUX_0 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 0"] -pub mod aon_iomux_cfgsaif_syscfg_fmux0; -#[doc = "aon_iomux_cfgsaif_syscfg_fmux1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux1`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX1 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 1"] -pub mod aon_iomux_cfgsaif_syscfg_fmux1; -#[doc = "aon_iomux_cfgsaif_syscfg_fmux2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux2`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX2 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 2"] -pub mod aon_iomux_cfgsaif_syscfg_fmux2; -#[doc = "aon_iomux_cfgsaif_syscfg_fmux3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux3`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX3 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 3"] -pub mod aon_iomux_cfgsaif_syscfg_fmux3; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq4 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq4`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 4"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq4; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq5 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq5`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 5"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq5; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq6 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq6`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 6"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq6; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq7 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq7`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 7"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq7; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq8 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq8`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 8"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq8; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq9 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq9::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq9`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 9"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq9; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq10 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq10::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq10`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 10"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq10; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq11 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq11::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq11`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 11"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq11; -#[doc = "aon_iomux_cfgsaif_syscfg48 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg48`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG48 = - crate::Reg; +pub mod fmux_0; +#[doc = "fmux_1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmux_1`] +module"] +pub type FMUX_1 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 4"] +pub mod fmux_1; +#[doc = "fmux_2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmux_2`] +module"] +pub type FMUX_2 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 8"] +pub mod fmux_2; +#[doc = "fmux_3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmux_3`] +module"] +pub type FMUX_3 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 12"] +pub mod fmux_3; +#[doc = "ioirq_0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_0`] +module"] +pub type IOIRQ_0 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 16"] +pub mod ioirq_0; +#[doc = "ioirq_1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_1`] +module"] +pub type IOIRQ_1 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 20"] +pub mod ioirq_1; +#[doc = "ioirq_2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_2`] +module"] +pub type IOIRQ_2 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 24"] +pub mod ioirq_2; +#[doc = "ioirq_3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_3`] +module"] +pub type IOIRQ_3 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 28"] +pub mod ioirq_3; +#[doc = "ioirq_4 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_4`] +module"] +pub type IOIRQ_4 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 32"] +pub mod ioirq_4; +#[doc = "ioirq_5 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_5`] +module"] +pub type IOIRQ_5 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 36"] +pub mod ioirq_5; +#[doc = "ioirq_6 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_6`] +module"] +pub type IOIRQ_6 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 40"] +pub mod ioirq_6; +#[doc = "ioirq_7 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_7`] +module"] +pub type IOIRQ_7 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 44"] +pub mod ioirq_7; +#[doc = "testen (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`testen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`testen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@testen`] +module"] +pub type TESTEN = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 48"] -pub mod aon_iomux_cfgsaif_syscfg48; -#[doc = "aon_iomux_cfgsaif_syscfg52 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg52`] +pub mod testen; +#[doc = "rgpio_0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rgpio_0`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG52 = - crate::Reg; +pub type RGPIO_0 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 52"] -pub mod aon_iomux_cfgsaif_syscfg52; -#[doc = "aon_iomux_cfgsaif_syscfg56 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg56`] +pub mod rgpio_0; +#[doc = "rgpio_1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rgpio_1`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG56 = - crate::Reg; +pub type RGPIO_1 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 56"] -pub mod aon_iomux_cfgsaif_syscfg56; -#[doc = "aon_iomux_cfgsaif_syscfg60 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg60`] +pub mod rgpio_1; +#[doc = "rgpio_2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rgpio_2`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG60 = - crate::Reg; +pub type RGPIO_2 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 60"] -pub mod aon_iomux_cfgsaif_syscfg60; -#[doc = "aon_iomux_cfgsaif_syscfg64 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg64`] +pub mod rgpio_2; +#[doc = "rgpio_3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rgpio_3`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG64 = - crate::Reg; +pub type RGPIO_3 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 64"] -pub mod aon_iomux_cfgsaif_syscfg64; -#[doc = "aon_iomux_cfgsaif_syscfg68 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg68`] +pub mod rgpio_3; +#[doc = "rstn (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstn::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstn::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstn`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG68 = - crate::Reg; +pub type RSTN = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 68"] -pub mod aon_iomux_cfgsaif_syscfg68; -#[doc = "aon_iomux_cfgsaif_syscfg76 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg76`] +pub mod rstn; +#[doc = "rtc (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG76 = - crate::Reg; +pub type RTC = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 76"] -pub mod aon_iomux_cfgsaif_syscfg76; -#[doc = "aon_iomux_cfgsaif_syscfg84 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg84`] +pub mod rtc; +#[doc = "osc (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`osc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`osc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@osc`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG84 = - crate::Reg; +pub type OSC = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 84"] -pub mod aon_iomux_cfgsaif_syscfg84; -#[doc = "aon_iomux_cfgsaif_syscfg88 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg88`] +pub mod osc; +#[doc = "gmac0_mdc (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_mdc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_mdc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_mdc`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG88 = - crate::Reg; +pub type GMAC0_MDC = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 88"] -pub mod aon_iomux_cfgsaif_syscfg88; -#[doc = "aon_iomux_cfgsaif_syscfg92 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg92`] +pub mod gmac0_mdc; +#[doc = "gmac0_mdio (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_mdio::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_mdio::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_mdio`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG92 = - crate::Reg; +pub type GMAC0_MDIO = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 92"] -pub mod aon_iomux_cfgsaif_syscfg92; -#[doc = "aon_iomux_cfgsaif_syscfg96 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg96`] +pub mod gmac0_mdio; +#[doc = "gmac0_rxd0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxd0`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG96 = - crate::Reg; +pub type GMAC0_RXD0 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 96"] -pub mod aon_iomux_cfgsaif_syscfg96; -#[doc = "aon_iomux_cfgsaif_syscfg100 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg100`] +pub mod gmac0_rxd0; +#[doc = "gmac0_rxd1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxd1`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG100 = - crate::Reg; +pub type GMAC0_RXD1 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 100"] -pub mod aon_iomux_cfgsaif_syscfg100; -#[doc = "aon_iomux_cfgsaif_syscfg104 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg104`] +pub mod gmac0_rxd1; +#[doc = "gmac0_rxd2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxd2`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG104 = - crate::Reg; +pub type GMAC0_RXD2 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 104"] -pub mod aon_iomux_cfgsaif_syscfg104; -#[doc = "aon_iomux_cfgsaif_syscfg108 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg108`] +pub mod gmac0_rxd2; +#[doc = "gmac0_rxd3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxd3`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG108 = - crate::Reg; +pub type GMAC0_RXD3 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 108"] -pub mod aon_iomux_cfgsaif_syscfg108; -#[doc = "aon_iomux_cfgsaif_syscfg112 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg112`] +pub mod gmac0_rxd3; +#[doc = "gmac0_rxdv (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxdv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxdv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxdv`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG112 = - crate::Reg; +pub type GMAC0_RXDV = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 112"] -pub mod aon_iomux_cfgsaif_syscfg112; -#[doc = "aon_iomux_cfgsaif_syscfg116 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg116`] +pub mod gmac0_rxdv; +#[doc = "gmac0_rxc (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxc`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG116 = - crate::Reg; +pub type GMAC0_RXC = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 116"] -pub mod aon_iomux_cfgsaif_syscfg116; -#[doc = "aon_iomux_cfgsaif_syscfg120 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg120`] +pub mod gmac0_rxc; +#[doc = "gmac0_txd0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_txd0`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG120 = - crate::Reg; +pub type GMAC0_TXD0 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 120"] -pub mod aon_iomux_cfgsaif_syscfg120; -#[doc = "aon_iomux_cfgsaif_syscfg124 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg124`] +pub mod gmac0_txd0; +#[doc = "gmac0_txd1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_txd1`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG124 = - crate::Reg; +pub type GMAC0_TXD1 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 124"] -pub mod aon_iomux_cfgsaif_syscfg124; -#[doc = "aon_iomux_cfgsaif_syscfg128 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg128`] +pub mod gmac0_txd1; +#[doc = "gmac0_txd2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_txd2`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG128 = - crate::Reg; +pub type GMAC0_TXD2 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 128"] -pub mod aon_iomux_cfgsaif_syscfg128; -#[doc = "aon_iomux_cfgsaif_syscfg132 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg132`] +pub mod gmac0_txd2; +#[doc = "gmac0_txd3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_txd3`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG132 = - crate::Reg; +pub type GMAC0_TXD3 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 132"] -pub mod aon_iomux_cfgsaif_syscfg132; -#[doc = "aon_iomux_cfgsaif_syscfg136 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg136`] +pub mod gmac0_txd3; +#[doc = "gmac0_txen (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_txen`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG136 = - crate::Reg; +pub type GMAC0_TXEN = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 136"] -pub mod aon_iomux_cfgsaif_syscfg136; -#[doc = "aon_iomux_cfgsaif_syscfg140 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg140`] +pub mod gmac0_txen; +#[doc = "gmac0_txc (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_txc`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG140 = - crate::Reg; +pub type GMAC0_TXC = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 140"] -pub mod aon_iomux_cfgsaif_syscfg140; -#[doc = "aon_iomux_cfgsaif_syscfg144 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg144`] +pub mod gmac0_txc; +#[doc = "gmac0_rxc_func_sel (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxc_func_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxc_func_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxc_func_sel`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG144 = - crate::Reg; +pub type GMAC0_RXC_FUNC_SEL = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 144"] -pub mod aon_iomux_cfgsaif_syscfg144; +pub mod gmac0_rxc_func_sel; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs deleted file mode 100644 index 7a6eb49..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg100` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg100` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_rxd1_syscon` reader - padcfg_pad_gmac0_rxd1_syscon"] -pub type PADCFG_PAD_GMAC0_RXD1_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_rxd1_syscon` writer - padcfg_pad_gmac0_rxd1_syscon"] -pub type PADCFG_PAD_GMAC0_RXD1_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd1_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_rxd1_syscon(&self) -> PADCFG_PAD_GMAC0_RXD1_SYSCON_R { - PADCFG_PAD_GMAC0_RXD1_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd1_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_rxd1_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_RXD1_SYSCON_W { - PADCFG_PAD_GMAC0_RXD1_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg100::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg100::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG100_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG100_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg100::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG100_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg100::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG100_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs deleted file mode 100644 index c7f5618..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg104` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg104` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_rxd2_syscon` reader - padcfg_pad_gmac0_rxd2_syscon"] -pub type PADCFG_PAD_GMAC0_RXD2_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_rxd2_syscon` writer - padcfg_pad_gmac0_rxd2_syscon"] -pub type PADCFG_PAD_GMAC0_RXD2_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd2_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_rxd2_syscon(&self) -> PADCFG_PAD_GMAC0_RXD2_SYSCON_R { - PADCFG_PAD_GMAC0_RXD2_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd2_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_rxd2_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_RXD2_SYSCON_W { - PADCFG_PAD_GMAC0_RXD2_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg104::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg104::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG104_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG104_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg104::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG104_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg104::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG104_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs deleted file mode 100644 index 31aaf9e..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg108` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg108` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_rxd3_syscon` reader - padcfg_pad_gmac0_rxd3_syscon"] -pub type PADCFG_PAD_GMAC0_RXD3_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_rxd3_syscon` writer - padcfg_pad_gmac0_rxd3_syscon"] -pub type PADCFG_PAD_GMAC0_RXD3_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd3_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_rxd3_syscon(&self) -> PADCFG_PAD_GMAC0_RXD3_SYSCON_R { - PADCFG_PAD_GMAC0_RXD3_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd3_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_rxd3_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_RXD3_SYSCON_W { - PADCFG_PAD_GMAC0_RXD3_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg108::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg108::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG108_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG108_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg108::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG108_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg108::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG108_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs deleted file mode 100644 index 7b68d46..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg112` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg112` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_rxdv_syscon` reader - padcfg_pad_gmac0_rxdv_syscon"] -pub type PADCFG_PAD_GMAC0_RXDV_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_rxdv_syscon` writer - padcfg_pad_gmac0_rxdv_syscon"] -pub type PADCFG_PAD_GMAC0_RXDV_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxdv_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_rxdv_syscon(&self) -> PADCFG_PAD_GMAC0_RXDV_SYSCON_R { - PADCFG_PAD_GMAC0_RXDV_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxdv_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_rxdv_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_RXDV_SYSCON_W { - PADCFG_PAD_GMAC0_RXDV_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg112::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg112::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG112_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG112_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg112::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG112_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg112::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG112_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs deleted file mode 100644 index 5a9c872..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg116` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg116` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_rxc_syscon` reader - padcfg_pad_gmac0_rxc_syscon"] -pub type PADCFG_PAD_GMAC0_RXC_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_rxc_syscon` writer - padcfg_pad_gmac0_rxc_syscon"] -pub type PADCFG_PAD_GMAC0_RXC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxc_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_rxc_syscon(&self) -> PADCFG_PAD_GMAC0_RXC_SYSCON_R { - PADCFG_PAD_GMAC0_RXC_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxc_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_rxc_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_RXC_SYSCON_W { - PADCFG_PAD_GMAC0_RXC_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg116::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg116::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG116_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG116_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg116::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG116_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg116::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG116_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs deleted file mode 100644 index 71a2e97..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg120` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg120` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_txd0_syscon` reader - padcfg_pad_gmac0_txd0_syscon"] -pub type PADCFG_PAD_GMAC0_TXD0_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_txd0_syscon` writer - padcfg_pad_gmac0_txd0_syscon"] -pub type PADCFG_PAD_GMAC0_TXD0_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd0_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_txd0_syscon(&self) -> PADCFG_PAD_GMAC0_TXD0_SYSCON_R { - PADCFG_PAD_GMAC0_TXD0_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd0_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_txd0_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_TXD0_SYSCON_W { - PADCFG_PAD_GMAC0_TXD0_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg120::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg120::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG120_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG120_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg120::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG120_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg120::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG120_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs deleted file mode 100644 index dda00ba..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg124` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg124` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_txd1_syscon` reader - padcfg_pad_gmac0_txd1_syscon"] -pub type PADCFG_PAD_GMAC0_TXD1_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_txd1_syscon` writer - padcfg_pad_gmac0_txd1_syscon"] -pub type PADCFG_PAD_GMAC0_TXD1_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd1_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_txd1_syscon(&self) -> PADCFG_PAD_GMAC0_TXD1_SYSCON_R { - PADCFG_PAD_GMAC0_TXD1_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd1_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_txd1_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_TXD1_SYSCON_W { - PADCFG_PAD_GMAC0_TXD1_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg124::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg124::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG124_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG124_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg124::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG124_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg124::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG124_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs deleted file mode 100644 index 18bc4c0..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg128` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg128` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_txd2_syscon` reader - padcfg_pad_gmac0_txd2_syscon"] -pub type PADCFG_PAD_GMAC0_TXD2_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_txd2_syscon` writer - padcfg_pad_gmac0_txd2_syscon"] -pub type PADCFG_PAD_GMAC0_TXD2_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd2_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_txd2_syscon(&self) -> PADCFG_PAD_GMAC0_TXD2_SYSCON_R { - PADCFG_PAD_GMAC0_TXD2_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd2_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_txd2_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_TXD2_SYSCON_W { - PADCFG_PAD_GMAC0_TXD2_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg128::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg128::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG128_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG128_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg128::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG128_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg128::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG128_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs deleted file mode 100644 index b8888c2..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg132` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg132` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_txd3_syscon` reader - padcfg_pad_gmac0_txd3_syscon"] -pub type PADCFG_PAD_GMAC0_TXD3_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_txd3_syscon` writer - padcfg_pad_gmac0_txd3_syscon"] -pub type PADCFG_PAD_GMAC0_TXD3_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd3_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_txd3_syscon(&self) -> PADCFG_PAD_GMAC0_TXD3_SYSCON_R { - PADCFG_PAD_GMAC0_TXD3_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd3_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_txd3_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_TXD3_SYSCON_W { - PADCFG_PAD_GMAC0_TXD3_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg132::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg132::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG132_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG132_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg132::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG132_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg132::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG132_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs deleted file mode 100644 index 1423c0e..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg136` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg136` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_txen_syscon` reader - padcfg_pad_gmac0_txen_syscon"] -pub type PADCFG_PAD_GMAC0_TXEN_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_txen_syscon` writer - padcfg_pad_gmac0_txen_syscon"] -pub type PADCFG_PAD_GMAC0_TXEN_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txen_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_txen_syscon(&self) -> PADCFG_PAD_GMAC0_TXEN_SYSCON_R { - PADCFG_PAD_GMAC0_TXEN_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txen_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_txen_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_TXEN_SYSCON_W { - PADCFG_PAD_GMAC0_TXEN_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg136::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg136::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG136_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG136_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg136::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG136_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg136::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG136_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs deleted file mode 100644 index 3328694..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg140` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg140` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_txc_syscon` reader - padcfg_pad_gmac0_txc_syscon"] -pub type PADCFG_PAD_GMAC0_TXC_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_txc_syscon` writer - padcfg_pad_gmac0_txc_syscon"] -pub type PADCFG_PAD_GMAC0_TXC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txc_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_txc_syscon(&self) -> PADCFG_PAD_GMAC0_TXC_SYSCON_R { - PADCFG_PAD_GMAC0_TXC_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txc_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_txc_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_TXC_SYSCON_W { - PADCFG_PAD_GMAC0_TXC_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg140::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg140::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG140_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG140_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg140::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG140_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg140::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG140_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs deleted file mode 100644 index 4e9cfe6..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg144` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg144` writer"] -pub type W = crate::W; -#[doc = "Field `pad_gmac0_rxc_func_sel` reader - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] -pub type PAD_GMAC0_RXC_FUNC_SEL_R = crate::FieldReader; -#[doc = "Field `pad_gmac0_rxc_func_sel` writer - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] -pub type PAD_GMAC0_RXC_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] - #[inline(always)] - pub fn pad_gmac0_rxc_func_sel(&self) -> PAD_GMAC0_RXC_FUNC_SEL_R { - PAD_GMAC0_RXC_FUNC_SEL_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] - #[inline(always)] - #[must_use] - pub fn pad_gmac0_rxc_func_sel( - &mut self, - ) -> PAD_GMAC0_RXC_FUNC_SEL_W { - PAD_GMAC0_RXC_FUNC_SEL_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg144::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg144::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG144_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG144_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg144::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG144_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg144::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG144_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs deleted file mode 100644 index 6e37db2..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg48` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg48` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_testen_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_TESTEN_POS_R = crate::BitReader; -#[doc = "Field `padcfg_pad_testen_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_TESTEN_POS_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - pub fn padcfg_pad_testen_pos(&self) -> PADCFG_PAD_TESTEN_POS_R { - PADCFG_PAD_TESTEN_POS_R::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_testen_pos( - &mut self, - ) -> PADCFG_PAD_TESTEN_POS_W { - PADCFG_PAD_TESTEN_POS_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg48::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg48::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG48_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG48_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg48::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG48_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg48::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG48_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs deleted file mode 100644 index e6eee84..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs +++ /dev/null @@ -1,149 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg52` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg52` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_rgpio0_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO0_IE_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio0_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO0_IE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio0_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO0_DS_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_rgpio0_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO0_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `padcfg_pad_rgpio0_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO0_PU_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio0_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO0_PU_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio0_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO0_PD_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio0_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO0_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio0_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO0_SLEW_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio0_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO0_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio0_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO0_SMT_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio0_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO0_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio0_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO0_POS_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio0_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO0_POS_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_ie(&self) -> PADCFG_PAD_RGPIO0_IE_R { - PADCFG_PAD_RGPIO0_IE_R::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_ds(&self) -> PADCFG_PAD_RGPIO0_DS_R { - PADCFG_PAD_RGPIO0_DS_R::new(((self.bits >> 1) & 3) as u8) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_pu(&self) -> PADCFG_PAD_RGPIO0_PU_R { - PADCFG_PAD_RGPIO0_PU_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_pd(&self) -> PADCFG_PAD_RGPIO0_PD_R { - PADCFG_PAD_RGPIO0_PD_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_slew(&self) -> PADCFG_PAD_RGPIO0_SLEW_R { - PADCFG_PAD_RGPIO0_SLEW_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_smt(&self) -> PADCFG_PAD_RGPIO0_SMT_R { - PADCFG_PAD_RGPIO0_SMT_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_pos(&self) -> PADCFG_PAD_RGPIO0_POS_R { - PADCFG_PAD_RGPIO0_POS_R::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_ie( - &mut self, - ) -> PADCFG_PAD_RGPIO0_IE_W { - PADCFG_PAD_RGPIO0_IE_W::new(self, 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_ds( - &mut self, - ) -> PADCFG_PAD_RGPIO0_DS_W { - PADCFG_PAD_RGPIO0_DS_W::new(self, 1) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_pu( - &mut self, - ) -> PADCFG_PAD_RGPIO0_PU_W { - PADCFG_PAD_RGPIO0_PU_W::new(self, 3) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_pd( - &mut self, - ) -> PADCFG_PAD_RGPIO0_PD_W { - PADCFG_PAD_RGPIO0_PD_W::new(self, 4) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_slew( - &mut self, - ) -> PADCFG_PAD_RGPIO0_SLEW_W { - PADCFG_PAD_RGPIO0_SLEW_W::new(self, 5) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_smt( - &mut self, - ) -> PADCFG_PAD_RGPIO0_SMT_W { - PADCFG_PAD_RGPIO0_SMT_W::new(self, 6) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_pos( - &mut self, - ) -> PADCFG_PAD_RGPIO0_POS_W { - PADCFG_PAD_RGPIO0_POS_W::new(self, 7) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg52::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg52::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG52_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG52_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg52::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG52_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg52::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG52_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs deleted file mode 100644 index e4df2d1..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs +++ /dev/null @@ -1,149 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg56` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg56` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_rgpio1_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO1_IE_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio1_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO1_IE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio1_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO1_DS_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_rgpio1_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO1_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `padcfg_pad_rgpio1_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO1_PU_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio1_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO1_PU_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio1_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO1_PD_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio1_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO1_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio1_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO1_SLEW_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio1_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO1_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio1_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO1_SMT_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio1_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO1_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio1_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO1_POS_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio1_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO1_POS_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_ie(&self) -> PADCFG_PAD_RGPIO1_IE_R { - PADCFG_PAD_RGPIO1_IE_R::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_ds(&self) -> PADCFG_PAD_RGPIO1_DS_R { - PADCFG_PAD_RGPIO1_DS_R::new(((self.bits >> 1) & 3) as u8) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_pu(&self) -> PADCFG_PAD_RGPIO1_PU_R { - PADCFG_PAD_RGPIO1_PU_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_pd(&self) -> PADCFG_PAD_RGPIO1_PD_R { - PADCFG_PAD_RGPIO1_PD_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_slew(&self) -> PADCFG_PAD_RGPIO1_SLEW_R { - PADCFG_PAD_RGPIO1_SLEW_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_smt(&self) -> PADCFG_PAD_RGPIO1_SMT_R { - PADCFG_PAD_RGPIO1_SMT_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_pos(&self) -> PADCFG_PAD_RGPIO1_POS_R { - PADCFG_PAD_RGPIO1_POS_R::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_ie( - &mut self, - ) -> PADCFG_PAD_RGPIO1_IE_W { - PADCFG_PAD_RGPIO1_IE_W::new(self, 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_ds( - &mut self, - ) -> PADCFG_PAD_RGPIO1_DS_W { - PADCFG_PAD_RGPIO1_DS_W::new(self, 1) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_pu( - &mut self, - ) -> PADCFG_PAD_RGPIO1_PU_W { - PADCFG_PAD_RGPIO1_PU_W::new(self, 3) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_pd( - &mut self, - ) -> PADCFG_PAD_RGPIO1_PD_W { - PADCFG_PAD_RGPIO1_PD_W::new(self, 4) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_slew( - &mut self, - ) -> PADCFG_PAD_RGPIO1_SLEW_W { - PADCFG_PAD_RGPIO1_SLEW_W::new(self, 5) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_smt( - &mut self, - ) -> PADCFG_PAD_RGPIO1_SMT_W { - PADCFG_PAD_RGPIO1_SMT_W::new(self, 6) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_pos( - &mut self, - ) -> PADCFG_PAD_RGPIO1_POS_W { - PADCFG_PAD_RGPIO1_POS_W::new(self, 7) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg56::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg56::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG56_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG56_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg56::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG56_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg56::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG56_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs deleted file mode 100644 index 5a6586e..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs +++ /dev/null @@ -1,149 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg60` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg60` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_rgpio2_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO2_IE_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio2_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO2_IE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio2_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO2_DS_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_rgpio2_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO2_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `padcfg_pad_rgpio2_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO2_PU_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio2_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO2_PU_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio2_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO2_PD_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio2_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO2_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio2_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO2_SLEW_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio2_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO2_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio2_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO2_SMT_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio2_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO2_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio2_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO2_POS_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio2_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO2_POS_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_ie(&self) -> PADCFG_PAD_RGPIO2_IE_R { - PADCFG_PAD_RGPIO2_IE_R::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_ds(&self) -> PADCFG_PAD_RGPIO2_DS_R { - PADCFG_PAD_RGPIO2_DS_R::new(((self.bits >> 1) & 3) as u8) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_pu(&self) -> PADCFG_PAD_RGPIO2_PU_R { - PADCFG_PAD_RGPIO2_PU_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_pd(&self) -> PADCFG_PAD_RGPIO2_PD_R { - PADCFG_PAD_RGPIO2_PD_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_slew(&self) -> PADCFG_PAD_RGPIO2_SLEW_R { - PADCFG_PAD_RGPIO2_SLEW_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_smt(&self) -> PADCFG_PAD_RGPIO2_SMT_R { - PADCFG_PAD_RGPIO2_SMT_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_pos(&self) -> PADCFG_PAD_RGPIO2_POS_R { - PADCFG_PAD_RGPIO2_POS_R::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_ie( - &mut self, - ) -> PADCFG_PAD_RGPIO2_IE_W { - PADCFG_PAD_RGPIO2_IE_W::new(self, 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_ds( - &mut self, - ) -> PADCFG_PAD_RGPIO2_DS_W { - PADCFG_PAD_RGPIO2_DS_W::new(self, 1) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_pu( - &mut self, - ) -> PADCFG_PAD_RGPIO2_PU_W { - PADCFG_PAD_RGPIO2_PU_W::new(self, 3) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_pd( - &mut self, - ) -> PADCFG_PAD_RGPIO2_PD_W { - PADCFG_PAD_RGPIO2_PD_W::new(self, 4) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_slew( - &mut self, - ) -> PADCFG_PAD_RGPIO2_SLEW_W { - PADCFG_PAD_RGPIO2_SLEW_W::new(self, 5) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_smt( - &mut self, - ) -> PADCFG_PAD_RGPIO2_SMT_W { - PADCFG_PAD_RGPIO2_SMT_W::new(self, 6) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_pos( - &mut self, - ) -> PADCFG_PAD_RGPIO2_POS_W { - PADCFG_PAD_RGPIO2_POS_W::new(self, 7) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg60::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg60::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG60_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG60_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg60::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG60_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg60::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG60_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs deleted file mode 100644 index 8dfbee5..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs +++ /dev/null @@ -1,149 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg64` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg64` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_rgpio3_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO3_IE_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio3_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO3_IE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio3_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO3_DS_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_rgpio3_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO3_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `padcfg_pad_rgpio3_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO3_PU_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio3_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO3_PU_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio3_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO3_PD_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio3_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO3_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio3_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO3_SLEW_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio3_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO3_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio3_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO3_SMT_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio3_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO3_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio3_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO3_POS_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio3_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO3_POS_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_ie(&self) -> PADCFG_PAD_RGPIO3_IE_R { - PADCFG_PAD_RGPIO3_IE_R::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_ds(&self) -> PADCFG_PAD_RGPIO3_DS_R { - PADCFG_PAD_RGPIO3_DS_R::new(((self.bits >> 1) & 3) as u8) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_pu(&self) -> PADCFG_PAD_RGPIO3_PU_R { - PADCFG_PAD_RGPIO3_PU_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_pd(&self) -> PADCFG_PAD_RGPIO3_PD_R { - PADCFG_PAD_RGPIO3_PD_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_slew(&self) -> PADCFG_PAD_RGPIO3_SLEW_R { - PADCFG_PAD_RGPIO3_SLEW_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_smt(&self) -> PADCFG_PAD_RGPIO3_SMT_R { - PADCFG_PAD_RGPIO3_SMT_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_pos(&self) -> PADCFG_PAD_RGPIO3_POS_R { - PADCFG_PAD_RGPIO3_POS_R::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_ie( - &mut self, - ) -> PADCFG_PAD_RGPIO3_IE_W { - PADCFG_PAD_RGPIO3_IE_W::new(self, 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_ds( - &mut self, - ) -> PADCFG_PAD_RGPIO3_DS_W { - PADCFG_PAD_RGPIO3_DS_W::new(self, 1) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_pu( - &mut self, - ) -> PADCFG_PAD_RGPIO3_PU_W { - PADCFG_PAD_RGPIO3_PU_W::new(self, 3) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_pd( - &mut self, - ) -> PADCFG_PAD_RGPIO3_PD_W { - PADCFG_PAD_RGPIO3_PD_W::new(self, 4) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_slew( - &mut self, - ) -> PADCFG_PAD_RGPIO3_SLEW_W { - PADCFG_PAD_RGPIO3_SLEW_W::new(self, 5) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_smt( - &mut self, - ) -> PADCFG_PAD_RGPIO3_SMT_W { - PADCFG_PAD_RGPIO3_SMT_W::new(self, 6) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_pos( - &mut self, - ) -> PADCFG_PAD_RGPIO3_POS_W { - PADCFG_PAD_RGPIO3_POS_W::new(self, 7) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg64::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg64::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG64_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG64_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg64::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG64_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg64::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG64_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs deleted file mode 100644 index 6c5a65b..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs +++ /dev/null @@ -1,64 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg68` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg68` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_rstn_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] -pub type PADCFG_PAD_RSTN_SMT_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rstn_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] -pub type PADCFG_PAD_RSTN_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rstn_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RSTN_POS_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rstn_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RSTN_POS_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] - #[inline(always)] - pub fn padcfg_pad_rstn_smt(&self) -> PADCFG_PAD_RSTN_SMT_R { - PADCFG_PAD_RSTN_SMT_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - pub fn padcfg_pad_rstn_pos(&self) -> PADCFG_PAD_RSTN_POS_R { - PADCFG_PAD_RSTN_POS_R::new(((self.bits >> 1) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rstn_smt( - &mut self, - ) -> PADCFG_PAD_RSTN_SMT_W { - PADCFG_PAD_RSTN_SMT_W::new(self, 0) - } - #[doc = "Bit 1 - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rstn_pos( - &mut self, - ) -> PADCFG_PAD_RSTN_POS_W { - PADCFG_PAD_RSTN_POS_W::new(self, 1) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg68::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg68::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG68_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG68_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg68::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG68_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg68::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG68_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs deleted file mode 100644 index 452613c..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs +++ /dev/null @@ -1,45 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg76` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg76` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_rtc_ds` reader - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] -pub type PADCFG_PAD_RTC_DS_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_rtc_ds` writer - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] -pub type PADCFG_PAD_RTC_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] - #[inline(always)] - pub fn padcfg_pad_rtc_ds(&self) -> PADCFG_PAD_RTC_DS_R { - PADCFG_PAD_RTC_DS_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rtc_ds(&mut self) -> PADCFG_PAD_RTC_DS_W { - PADCFG_PAD_RTC_DS_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg76::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg76::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG76_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG76_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg76::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG76_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg76::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG76_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs deleted file mode 100644 index 067aebb..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs +++ /dev/null @@ -1,45 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg84` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg84` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_osc_ds` reader - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] -pub type PADCFG_PAD_OSC_DS_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_osc_ds` writer - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] -pub type PADCFG_PAD_OSC_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] - #[inline(always)] - pub fn padcfg_pad_osc_ds(&self) -> PADCFG_PAD_OSC_DS_R { - PADCFG_PAD_OSC_DS_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_osc_ds(&mut self) -> PADCFG_PAD_OSC_DS_W { - PADCFG_PAD_OSC_DS_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg84::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg84::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG84_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG84_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg84::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG84_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg84::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG84_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs deleted file mode 100644 index f744712..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg88` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg88` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_mdc_syscon` reader - padcfg_pad_gmac0_mdc_syscon"] -pub type PADCFG_PAD_GMAC0_MDC_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_mdc_syscon` writer - padcfg_pad_gmac0_mdc_syscon"] -pub type PADCFG_PAD_GMAC0_MDC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_mdc_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_mdc_syscon(&self) -> PADCFG_PAD_GMAC0_MDC_SYSCON_R { - PADCFG_PAD_GMAC0_MDC_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_mdc_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_mdc_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_MDC_SYSCON_W { - PADCFG_PAD_GMAC0_MDC_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg88::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg88::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG88_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG88_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg88::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG88_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg88::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG88_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs deleted file mode 100644 index fd12b7e..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg92` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg92` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_mdio_syscon` reader - padcfg_pad_gmac0_mdio_syscon"] -pub type PADCFG_PAD_GMAC0_MDIO_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_mdio_syscon` writer - padcfg_pad_gmac0_mdio_syscon"] -pub type PADCFG_PAD_GMAC0_MDIO_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_mdio_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_mdio_syscon(&self) -> PADCFG_PAD_GMAC0_MDIO_SYSCON_R { - PADCFG_PAD_GMAC0_MDIO_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_mdio_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_mdio_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_MDIO_SYSCON_W { - PADCFG_PAD_GMAC0_MDIO_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg92::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg92::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG92_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG92_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg92::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG92_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg92::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG92_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs deleted file mode 100644 index 3f8dabd..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg96` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg96` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_rxd0_syscon` reader - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] -pub type PADCFG_PAD_GMAC0_RXD0_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_rxd0_syscon` writer - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] -pub type PADCFG_PAD_GMAC0_RXD0_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] - #[inline(always)] - pub fn padcfg_pad_gmac0_rxd0_syscon(&self) -> PADCFG_PAD_GMAC0_RXD0_SYSCON_R { - PADCFG_PAD_GMAC0_RXD0_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_rxd0_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_RXD0_SYSCON_W { - PADCFG_PAD_GMAC0_RXD0_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg96::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg96::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG96_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG96_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg96::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG96_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg96::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG96_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs deleted file mode 100644 index 1bb9c0c..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux0` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux0` writer"] -pub type W = crate::W; -#[doc = "Field `aon_iomux_gpo0_doen_cfg` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO0_DOEN_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo0_doen_cfg` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO0_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `aon_iomux_gpo1_doen_cfg` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO1_DOEN_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo1_doen_cfg` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO1_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `aon_iomux_gpo2_doen_cfg` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO2_DOEN_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo2_doen_cfg` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO2_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `aon_iomux_gpo3_doen_cfg` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO3_DOEN_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo3_doen_cfg` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO3_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:2 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo0_doen_cfg(&self) -> AON_IOMUX_GPO0_DOEN_CFG_R { - AON_IOMUX_GPO0_DOEN_CFG_R::new((self.bits & 7) as u8) - } - #[doc = "Bits 8:10 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo1_doen_cfg(&self) -> AON_IOMUX_GPO1_DOEN_CFG_R { - AON_IOMUX_GPO1_DOEN_CFG_R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 16:18 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo2_doen_cfg(&self) -> AON_IOMUX_GPO2_DOEN_CFG_R { - AON_IOMUX_GPO2_DOEN_CFG_R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bits 24:26 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo3_doen_cfg(&self) -> AON_IOMUX_GPO3_DOEN_CFG_R { - AON_IOMUX_GPO3_DOEN_CFG_R::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo0_doen_cfg( - &mut self, - ) -> AON_IOMUX_GPO0_DOEN_CFG_W { - AON_IOMUX_GPO0_DOEN_CFG_W::new(self, 0) - } - #[doc = "Bits 8:10 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo1_doen_cfg( - &mut self, - ) -> AON_IOMUX_GPO1_DOEN_CFG_W { - AON_IOMUX_GPO1_DOEN_CFG_W::new(self, 8) - } - #[doc = "Bits 16:18 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo2_doen_cfg( - &mut self, - ) -> AON_IOMUX_GPO2_DOEN_CFG_W { - AON_IOMUX_GPO2_DOEN_CFG_W::new(self, 16) - } - #[doc = "Bits 24:26 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo3_doen_cfg( - &mut self, - ) -> AON_IOMUX_GPO3_DOEN_CFG_W { - AON_IOMUX_GPO3_DOEN_CFG_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_FMUX0_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_FMUX0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_fmux0::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_fmux0::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs deleted file mode 100644 index 045b180..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux1` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux1` writer"] -pub type W = crate::W; -#[doc = "Field `aon_iomux_gpo0_dout_cfg` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO0_DOUT_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo0_dout_cfg` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO0_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `aon_iomux_gpo1_dout_cfg` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO1_DOUT_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo1_dout_cfg` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO1_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `aon_iomux_gpo2_dout_cfg` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO2_DOUT_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo2_dout_cfg` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO2_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `aon_iomux_gpo3_dout_cfg` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO3_DOUT_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo3_dout_cfg` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO3_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo0_dout_cfg(&self) -> AON_IOMUX_GPO0_DOUT_CFG_R { - AON_IOMUX_GPO0_DOUT_CFG_R::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 8:11 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo1_dout_cfg(&self) -> AON_IOMUX_GPO1_DOUT_CFG_R { - AON_IOMUX_GPO1_DOUT_CFG_R::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 16:19 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo2_dout_cfg(&self) -> AON_IOMUX_GPO2_DOUT_CFG_R { - AON_IOMUX_GPO2_DOUT_CFG_R::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 24:27 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo3_dout_cfg(&self) -> AON_IOMUX_GPO3_DOUT_CFG_R { - AON_IOMUX_GPO3_DOUT_CFG_R::new(((self.bits >> 24) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo0_dout_cfg( - &mut self, - ) -> AON_IOMUX_GPO0_DOUT_CFG_W { - AON_IOMUX_GPO0_DOUT_CFG_W::new(self, 0) - } - #[doc = "Bits 8:11 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo1_dout_cfg( - &mut self, - ) -> AON_IOMUX_GPO1_DOUT_CFG_W { - AON_IOMUX_GPO1_DOUT_CFG_W::new(self, 8) - } - #[doc = "Bits 16:19 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo2_dout_cfg( - &mut self, - ) -> AON_IOMUX_GPO2_DOUT_CFG_W { - AON_IOMUX_GPO2_DOUT_CFG_W::new(self, 16) - } - #[doc = "Bits 24:27 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo3_dout_cfg( - &mut self, - ) -> AON_IOMUX_GPO3_DOUT_CFG_W { - AON_IOMUX_GPO3_DOUT_CFG_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_FMUX1_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_FMUX1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_fmux1::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_fmux1::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs deleted file mode 100644 index a8f9ba4..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs +++ /dev/null @@ -1,114 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux2` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux2` writer"] -pub type W = crate::W; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W<'a, REG> = - crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W<'a, REG> = - crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W<'a, REG> = - crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W<'a, REG> = - crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:2 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg( - &self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_R { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_R::new((self.bits & 7) as u8) - } - #[doc = "Bits 8:10 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg( - &self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_R { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 16:18 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg( - &self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_R { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bits 24:26 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg( - &self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_R { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_R::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg( - &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W - { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W::new(self, 0) - } - #[doc = "Bits 8:10 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg( - &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W - { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W::new(self, 8) - } - #[doc = "Bits 16:18 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg( - &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W - { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W::new(self, 16) - } - #[doc = "Bits 24:26 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg( - &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W - { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_fmux2::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_fmux2::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs deleted file mode 100644 index 94cc018..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs +++ /dev/null @@ -1,45 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux3` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux3` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpioen_0_reg` reader - Enable GPIO IRQ function."] -pub type AON_GPIOEN_0_REG_R = crate::BitReader; -#[doc = "Field `aon_gpioen_0_reg` writer - Enable GPIO IRQ function."] -pub type AON_GPIOEN_0_REG_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Enable GPIO IRQ function."] - #[inline(always)] - pub fn aon_gpioen_0_reg(&self) -> AON_GPIOEN_0_REG_R { - AON_GPIOEN_0_REG_R::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Enable GPIO IRQ function."] - #[inline(always)] - #[must_use] - pub fn aon_gpioen_0_reg(&mut self) -> AON_GPIOEN_0_REG_W { - AON_GPIOEN_0_REG_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_FMUX3_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_FMUX3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_fmux3::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_fmux3::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX3_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs deleted file mode 100644 index 71d7011..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq10` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq10` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpiomis_0_reg` reader - The masked GPIO IRQ status."] -pub type AON_GPIOMIS_0_REG_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - The masked GPIO IRQ status."] - #[inline(always)] - pub fn aon_gpiomis_0_reg(&self) -> AON_GPIOMIS_0_REG_R { - AON_GPIOMIS_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq10::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq10::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq10::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs deleted file mode 100644 index 6e7f217..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq11` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq11` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpio_in_sync2_0_reg` reader - Status of gpio_in after synchronization."] -pub type AON_GPIO_IN_SYNC2_0_REG_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Status of gpio_in after synchronization."] - #[inline(always)] - pub fn aon_gpio_in_sync2_0_reg(&self) -> AON_GPIO_IN_SYNC2_0_REG_R { - AON_GPIO_IN_SYNC2_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq11::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq11::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq11::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs deleted file mode 100644 index f984d07..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs +++ /dev/null @@ -1,45 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq4` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq4` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpiois_0_reg` reader - 1: Edge trigger, 0: Level trigger"] -pub type AON_GPIOIS_0_REG_R = crate::FieldReader; -#[doc = "Field `aon_gpiois_0_reg` writer - 1: Edge trigger, 0: Level trigger"] -pub type AON_GPIOIS_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - 1: Edge trigger, 0: Level trigger"] - #[inline(always)] - pub fn aon_gpiois_0_reg(&self) -> AON_GPIOIS_0_REG_R { - AON_GPIOIS_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - 1: Edge trigger, 0: Level trigger"] - #[inline(always)] - #[must_use] - pub fn aon_gpiois_0_reg(&mut self) -> AON_GPIOIS_0_REG_W { - AON_GPIOIS_0_REG_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq4::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq4::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq4::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs deleted file mode 100644 index 91bc1c3..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs +++ /dev/null @@ -1,45 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq5` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq5` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpioic_0_reg` reader - 1: Do not clear the register, 0: Clear the register"] -pub type AON_GPIOIC_0_REG_R = crate::FieldReader; -#[doc = "Field `aon_gpioic_0_reg` writer - 1: Do not clear the register, 0: Clear the register"] -pub type AON_GPIOIC_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - 1: Do not clear the register, 0: Clear the register"] - #[inline(always)] - pub fn aon_gpioic_0_reg(&self) -> AON_GPIOIC_0_REG_R { - AON_GPIOIC_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - 1: Do not clear the register, 0: Clear the register"] - #[inline(always)] - #[must_use] - pub fn aon_gpioic_0_reg(&mut self) -> AON_GPIOIC_0_REG_W { - AON_GPIOIC_0_REG_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq5::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq5::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq5::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs deleted file mode 100644 index 925eb89..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq6` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq6` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpioibe_0_reg` reader - 1: Trigger on both edges, 0: Trigger on a single edge"] -pub type AON_GPIOIBE_0_REG_R = crate::FieldReader; -#[doc = "Field `aon_gpioibe_0_reg` writer - 1: Trigger on both edges, 0: Trigger on a single edge"] -pub type AON_GPIOIBE_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - 1: Trigger on both edges, 0: Trigger on a single edge"] - #[inline(always)] - pub fn aon_gpioibe_0_reg(&self) -> AON_GPIOIBE_0_REG_R { - AON_GPIOIBE_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - 1: Trigger on both edges, 0: Trigger on a single edge"] - #[inline(always)] - #[must_use] - pub fn aon_gpioibe_0_reg( - &mut self, - ) -> AON_GPIOIBE_0_REG_W { - AON_GPIOIBE_0_REG_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq6::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq6::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq6::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs deleted file mode 100644 index 353765a..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq7` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq7` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpioiev_0_reg` reader - 1: Positive/Low, 0: Negative/High"] -pub type AON_GPIOIEV_0_REG_R = crate::FieldReader; -#[doc = "Field `aon_gpioiev_0_reg` writer - 1: Positive/Low, 0: Negative/High"] -pub type AON_GPIOIEV_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - 1: Positive/Low, 0: Negative/High"] - #[inline(always)] - pub fn aon_gpioiev_0_reg(&self) -> AON_GPIOIEV_0_REG_R { - AON_GPIOIEV_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - 1: Positive/Low, 0: Negative/High"] - #[inline(always)] - #[must_use] - pub fn aon_gpioiev_0_reg( - &mut self, - ) -> AON_GPIOIEV_0_REG_W { - AON_GPIOIEV_0_REG_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq7::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq7::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq7::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs deleted file mode 100644 index cd46c19..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs +++ /dev/null @@ -1,45 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq8` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq8` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpioie_0_reg` reader - 1: Unmask, 0: Mask"] -pub type AON_GPIOIE_0_REG_R = crate::FieldReader; -#[doc = "Field `aon_gpioie_0_reg` writer - 1: Unmask, 0: Mask"] -pub type AON_GPIOIE_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - 1: Unmask, 0: Mask"] - #[inline(always)] - pub fn aon_gpioie_0_reg(&self) -> AON_GPIOIE_0_REG_R { - AON_GPIOIE_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - 1: Unmask, 0: Mask"] - #[inline(always)] - #[must_use] - pub fn aon_gpioie_0_reg(&mut self) -> AON_GPIOIE_0_REG_W { - AON_GPIOIE_0_REG_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq8::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq8::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq8::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs deleted file mode 100644 index 72caae7..0000000 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq9` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq9` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpioris_0_reg` reader - Status of the edge trigger, can be cleared by writing gpioic."] -pub type AON_GPIORIS_0_REG_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Status of the edge trigger, can be cleared by writing gpioic."] - #[inline(always)] - pub fn aon_gpioris_0_reg(&self) -> AON_GPIORIS_0_REG_R { - AON_GPIORIS_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq9::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq9::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq9::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_0.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_0.rs new file mode 100644 index 0000000..2d9da31 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_0.rs @@ -0,0 +1,94 @@ +#[doc = "Register `fmux_0` reader"] +pub type R = crate::R; +#[doc = "Register `fmux_0` writer"] +pub type W = crate::W; +#[doc = "Field `gpo_doen_0` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_0_R = crate::FieldReader; +#[doc = "Field `gpo_doen_0` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `gpo_doen_1` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_1_R = crate::FieldReader; +#[doc = "Field `gpo_doen_1` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `gpo_doen_2` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_2_R = crate::FieldReader; +#[doc = "Field `gpo_doen_2` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `gpo_doen_3` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_3_R = crate::FieldReader; +#[doc = "Field `gpo_doen_3` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_doen_0(&self) -> GPO_DOEN_0_R { + GPO_DOEN_0_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 8:10 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_doen_1(&self) -> GPO_DOEN_1_R { + GPO_DOEN_1_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 16:18 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_doen_2(&self) -> GPO_DOEN_2_R { + GPO_DOEN_2_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 24:26 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_doen_3(&self) -> GPO_DOEN_3_R { + GPO_DOEN_3_R::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_doen_0(&mut self) -> GPO_DOEN_0_W { + GPO_DOEN_0_W::new(self, 0) + } + #[doc = "Bits 8:10 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_doen_1(&mut self) -> GPO_DOEN_1_W { + GPO_DOEN_1_W::new(self, 8) + } + #[doc = "Bits 16:18 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_doen_2(&mut self) -> GPO_DOEN_2_W { + GPO_DOEN_2_W::new(self, 16) + } + #[doc = "Bits 24:26 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_doen_3(&mut self) -> GPO_DOEN_3_W { + GPO_DOEN_3_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FMUX_0_SPEC; +impl crate::RegisterSpec for FMUX_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmux_0::R`](R) reader structure"] +impl crate::Readable for FMUX_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fmux_0::W`](W) writer structure"] +impl crate::Writable for FMUX_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets fmux_0 to value 0"] +impl crate::Resettable for FMUX_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_1.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_1.rs new file mode 100644 index 0000000..df4e9b5 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_1.rs @@ -0,0 +1,94 @@ +#[doc = "Register `fmux_1` reader"] +pub type R = crate::R; +#[doc = "Register `fmux_1` writer"] +pub type W = crate::W; +#[doc = "Field `gpo_dout_0` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_0_R = crate::FieldReader; +#[doc = "Field `gpo_dout_0` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `gpo_dout_1` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_1_R = crate::FieldReader; +#[doc = "Field `gpo_dout_1` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `gpo_dout_2` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_2_R = crate::FieldReader; +#[doc = "Field `gpo_dout_2` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `gpo_dout_3` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_3_R = crate::FieldReader; +#[doc = "Field `gpo_dout_3` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_dout_0(&self) -> GPO_DOUT_0_R { + GPO_DOUT_0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:11 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_dout_1(&self) -> GPO_DOUT_1_R { + GPO_DOUT_1_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_dout_2(&self) -> GPO_DOUT_2_R { + GPO_DOUT_2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_dout_3(&self) -> GPO_DOUT_3_R { + GPO_DOUT_3_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_dout_0(&mut self) -> GPO_DOUT_0_W { + GPO_DOUT_0_W::new(self, 0) + } + #[doc = "Bits 8:11 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_dout_1(&mut self) -> GPO_DOUT_1_W { + GPO_DOUT_1_W::new(self, 8) + } + #[doc = "Bits 16:19 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_dout_2(&mut self) -> GPO_DOUT_2_W { + GPO_DOUT_2_W::new(self, 16) + } + #[doc = "Bits 24:27 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_dout_3(&mut self) -> GPO_DOUT_3_W { + GPO_DOUT_3_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FMUX_1_SPEC; +impl crate::RegisterSpec for FMUX_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmux_1::R`](R) reader structure"] +impl crate::Readable for FMUX_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fmux_1::W`](W) writer structure"] +impl crate::Writable for FMUX_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets fmux_1 to value 0"] +impl crate::Resettable for FMUX_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_2.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_2.rs new file mode 100644 index 0000000..d43da5a --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_2.rs @@ -0,0 +1,94 @@ +#[doc = "Register `fmux_2` reader"] +pub type R = crate::R; +#[doc = "Register `fmux_2` writer"] +pub type W = crate::W; +#[doc = "Field `gpi_pmu_wakeup_0` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_0_R = crate::FieldReader; +#[doc = "Field `gpi_pmu_wakeup_0` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `gpi_pmu_wakeup_1` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_1_R = crate::FieldReader; +#[doc = "Field `gpi_pmu_wakeup_1` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `gpi_pmu_wakeup_2` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_2_R = crate::FieldReader; +#[doc = "Field `gpi_pmu_wakeup_2` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `gpi_pmu_wakeup_3` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_3_R = crate::FieldReader; +#[doc = "Field `gpi_pmu_wakeup_3` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + pub fn gpi_pmu_wakeup_0(&self) -> GPI_PMU_WAKEUP_0_R { + GPI_PMU_WAKEUP_0_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 8:10 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + pub fn gpi_pmu_wakeup_1(&self) -> GPI_PMU_WAKEUP_1_R { + GPI_PMU_WAKEUP_1_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 16:18 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + pub fn gpi_pmu_wakeup_2(&self) -> GPI_PMU_WAKEUP_2_R { + GPI_PMU_WAKEUP_2_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 24:26 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + pub fn gpi_pmu_wakeup_3(&self) -> GPI_PMU_WAKEUP_3_R { + GPI_PMU_WAKEUP_3_R::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + #[must_use] + pub fn gpi_pmu_wakeup_0(&mut self) -> GPI_PMU_WAKEUP_0_W { + GPI_PMU_WAKEUP_0_W::new(self, 0) + } + #[doc = "Bits 8:10 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + #[must_use] + pub fn gpi_pmu_wakeup_1(&mut self) -> GPI_PMU_WAKEUP_1_W { + GPI_PMU_WAKEUP_1_W::new(self, 8) + } + #[doc = "Bits 16:18 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + #[must_use] + pub fn gpi_pmu_wakeup_2(&mut self) -> GPI_PMU_WAKEUP_2_W { + GPI_PMU_WAKEUP_2_W::new(self, 16) + } + #[doc = "Bits 24:26 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + #[must_use] + pub fn gpi_pmu_wakeup_3(&mut self) -> GPI_PMU_WAKEUP_3_W { + GPI_PMU_WAKEUP_3_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FMUX_2_SPEC; +impl crate::RegisterSpec for FMUX_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmux_2::R`](R) reader structure"] +impl crate::Readable for FMUX_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fmux_2::W`](W) writer structure"] +impl crate::Writable for FMUX_2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets fmux_2 to value 0"] +impl crate::Resettable for FMUX_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_3.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_3.rs new file mode 100644 index 0000000..5cfcc65 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/fmux_3.rs @@ -0,0 +1,49 @@ +#[doc = "Register `fmux_3` reader"] +pub type R = crate::R; +#[doc = "Register `fmux_3` writer"] +pub type W = crate::W; +#[doc = "Field `gpen_0` reader - Enable GPIO IRQ function."] +pub type GPEN_0_R = crate::BitReader; +#[doc = "Field `gpen_0` writer - Enable GPIO IRQ function."] +pub type GPEN_0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable GPIO IRQ function."] + #[inline(always)] + pub fn gpen_0(&self) -> GPEN_0_R { + GPEN_0_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable GPIO IRQ function."] + #[inline(always)] + #[must_use] + pub fn gpen_0(&mut self) -> GPEN_0_W { + GPEN_0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FMUX_3_SPEC; +impl crate::RegisterSpec for FMUX_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmux_3::R`](R) reader structure"] +impl crate::Readable for FMUX_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fmux_3::W`](W) writer structure"] +impl crate::Writable for FMUX_3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets fmux_3 to value 0"] +impl crate::Resettable for FMUX_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_mdc.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_mdc.rs new file mode 100644 index 0000000..5e2cf8b --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_mdc.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_mdc` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_mdc` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_mdc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_mdc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_MDC_SPEC; +impl crate::RegisterSpec for GMAC0_MDC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_mdc::R`](R) reader structure"] +impl crate::Readable for GMAC0_MDC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_mdc::W`](W) writer structure"] +impl crate::Writable for GMAC0_MDC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_mdc to value 0"] +impl crate::Resettable for GMAC0_MDC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_mdio.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_mdio.rs new file mode 100644 index 0000000..b24ded7 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_mdio.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_mdio` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_mdio` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_mdio::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_mdio::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_MDIO_SPEC; +impl crate::RegisterSpec for GMAC0_MDIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_mdio::R`](R) reader structure"] +impl crate::Readable for GMAC0_MDIO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_mdio::W`](W) writer structure"] +impl crate::Writable for GMAC0_MDIO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_mdio to value 0"] +impl crate::Resettable for GMAC0_MDIO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxc.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxc.rs new file mode 100644 index 0000000..8afdb42 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxc.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxc` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxc` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXC_SPEC; +impl crate::RegisterSpec for GMAC0_RXC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxc::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxc::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxc to value 0"] +impl crate::Resettable for GMAC0_RXC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxc_func_sel.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxc_func_sel.rs new file mode 100644 index 0000000..b80809d --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxc_func_sel.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxc_func_sel` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxc_func_sel` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxc_func_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxc_func_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXC_FUNC_SEL_SPEC; +impl crate::RegisterSpec for GMAC0_RXC_FUNC_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxc_func_sel::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXC_FUNC_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxc_func_sel::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXC_FUNC_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxc_func_sel to value 0"] +impl crate::Resettable for GMAC0_RXC_FUNC_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd0.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd0.rs new file mode 100644 index 0000000..c4e8839 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxd0` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxd0` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXD0_SPEC; +impl crate::RegisterSpec for GMAC0_RXD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxd0::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxd0::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxd0 to value 0"] +impl crate::Resettable for GMAC0_RXD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd1.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd1.rs new file mode 100644 index 0000000..6109d76 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxd1` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxd1` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXD1_SPEC; +impl crate::RegisterSpec for GMAC0_RXD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxd1::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxd1::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxd1 to value 0"] +impl crate::Resettable for GMAC0_RXD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd2.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd2.rs new file mode 100644 index 0000000..0686f72 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd2.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxd2` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxd2` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXD2_SPEC; +impl crate::RegisterSpec for GMAC0_RXD2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxd2::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXD2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxd2::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXD2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxd2 to value 0"] +impl crate::Resettable for GMAC0_RXD2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd3.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd3.rs new file mode 100644 index 0000000..097dfe4 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxd3.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxd3` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxd3` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXD3_SPEC; +impl crate::RegisterSpec for GMAC0_RXD3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxd3::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXD3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxd3::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXD3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxd3 to value 0"] +impl crate::Resettable for GMAC0_RXD3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxdv.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxdv.rs new file mode 100644 index 0000000..7b3062b --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_rxdv.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxdv` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxdv` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxdv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxdv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXDV_SPEC; +impl crate::RegisterSpec for GMAC0_RXDV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxdv::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXDV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxdv::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXDV_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxdv to value 0"] +impl crate::Resettable for GMAC0_RXDV_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txc.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txc.rs new file mode 100644 index 0000000..8c7bb7b --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txc.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_txc` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_txc` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_TXC_SPEC; +impl crate::RegisterSpec for GMAC0_TXC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_txc::R`](R) reader structure"] +impl crate::Readable for GMAC0_TXC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_txc::W`](W) writer structure"] +impl crate::Writable for GMAC0_TXC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_txc to value 0"] +impl crate::Resettable for GMAC0_TXC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd0.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd0.rs new file mode 100644 index 0000000..01ac307 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_txd0` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_txd0` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_TXD0_SPEC; +impl crate::RegisterSpec for GMAC0_TXD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_txd0::R`](R) reader structure"] +impl crate::Readable for GMAC0_TXD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_txd0::W`](W) writer structure"] +impl crate::Writable for GMAC0_TXD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_txd0 to value 0"] +impl crate::Resettable for GMAC0_TXD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd1.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd1.rs new file mode 100644 index 0000000..9d0651d --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_txd1` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_txd1` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_TXD1_SPEC; +impl crate::RegisterSpec for GMAC0_TXD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_txd1::R`](R) reader structure"] +impl crate::Readable for GMAC0_TXD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_txd1::W`](W) writer structure"] +impl crate::Writable for GMAC0_TXD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_txd1 to value 0"] +impl crate::Resettable for GMAC0_TXD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd2.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd2.rs new file mode 100644 index 0000000..f0823f4 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd2.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_txd2` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_txd2` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_TXD2_SPEC; +impl crate::RegisterSpec for GMAC0_TXD2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_txd2::R`](R) reader structure"] +impl crate::Readable for GMAC0_TXD2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_txd2::W`](W) writer structure"] +impl crate::Writable for GMAC0_TXD2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_txd2 to value 0"] +impl crate::Resettable for GMAC0_TXD2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd3.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd3.rs new file mode 100644 index 0000000..ce629d9 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txd3.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_txd3` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_txd3` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_TXD3_SPEC; +impl crate::RegisterSpec for GMAC0_TXD3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_txd3::R`](R) reader structure"] +impl crate::Readable for GMAC0_TXD3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_txd3::W`](W) writer structure"] +impl crate::Writable for GMAC0_TXD3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_txd3 to value 0"] +impl crate::Resettable for GMAC0_TXD3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txen.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txen.rs new file mode 100644 index 0000000..5f87204 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/gmac0_txen.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_txen` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_txen` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_TXEN_SPEC; +impl crate::RegisterSpec for GMAC0_TXEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_txen::R`](R) reader structure"] +impl crate::Readable for GMAC0_TXEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_txen::W`](W) writer structure"] +impl crate::Writable for GMAC0_TXEN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_txen to value 0"] +impl crate::Resettable for GMAC0_TXEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_0.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_0.rs new file mode 100644 index 0000000..95929fe --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ioirq_0` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_0` writer"] +pub type W = crate::W; +#[doc = "Field `is` reader - 1: Edge trigger, 0: Level trigger"] +pub type IS_R = crate::FieldReader; +#[doc = "Field `is` writer - 1: Edge trigger, 0: Level trigger"] +pub type IS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - 1: Edge trigger, 0: Level trigger"] + #[inline(always)] + pub fn is(&self) -> IS_R { + IS_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - 1: Edge trigger, 0: Level trigger"] + #[inline(always)] + #[must_use] + pub fn is(&mut self) -> IS_W { + IS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_0_SPEC; +impl crate::RegisterSpec for IOIRQ_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_0::R`](R) reader structure"] +impl crate::Readable for IOIRQ_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_0::W`](W) writer structure"] +impl crate::Writable for IOIRQ_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_0 to value 0"] +impl crate::Resettable for IOIRQ_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_1.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_1.rs new file mode 100644 index 0000000..bf8010c --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ioirq_1` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_1` writer"] +pub type W = crate::W; +#[doc = "Field `ic` reader - 1: Do not clear the register, 0: Clear the register"] +pub type IC_R = crate::FieldReader; +#[doc = "Field `ic` writer - 1: Do not clear the register, 0: Clear the register"] +pub type IC_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - 1: Do not clear the register, 0: Clear the register"] + #[inline(always)] + pub fn ic(&self) -> IC_R { + IC_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - 1: Do not clear the register, 0: Clear the register"] + #[inline(always)] + #[must_use] + pub fn ic(&mut self) -> IC_W { + IC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_1_SPEC; +impl crate::RegisterSpec for IOIRQ_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_1::R`](R) reader structure"] +impl crate::Readable for IOIRQ_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_1::W`](W) writer structure"] +impl crate::Writable for IOIRQ_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_1 to value 0"] +impl crate::Resettable for IOIRQ_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_2.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_2.rs new file mode 100644 index 0000000..0a22287 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_2.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ioirq_2` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_2` writer"] +pub type W = crate::W; +#[doc = "Field `ibe` reader - 1: Trigger on both edges, 0: Trigger on a single edge"] +pub type IBE_R = crate::FieldReader; +#[doc = "Field `ibe` writer - 1: Trigger on both edges, 0: Trigger on a single edge"] +pub type IBE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - 1: Trigger on both edges, 0: Trigger on a single edge"] + #[inline(always)] + pub fn ibe(&self) -> IBE_R { + IBE_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - 1: Trigger on both edges, 0: Trigger on a single edge"] + #[inline(always)] + #[must_use] + pub fn ibe(&mut self) -> IBE_W { + IBE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_2_SPEC; +impl crate::RegisterSpec for IOIRQ_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_2::R`](R) reader structure"] +impl crate::Readable for IOIRQ_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_2::W`](W) writer structure"] +impl crate::Writable for IOIRQ_2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_2 to value 0"] +impl crate::Resettable for IOIRQ_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_3.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_3.rs new file mode 100644 index 0000000..0711733 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_3.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ioirq_3` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_3` writer"] +pub type W = crate::W; +#[doc = "Field `iev` reader - 1: Positive/Low, 0: Negative/High"] +pub type IEV_R = crate::FieldReader; +#[doc = "Field `iev` writer - 1: Positive/Low, 0: Negative/High"] +pub type IEV_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - 1: Positive/Low, 0: Negative/High"] + #[inline(always)] + pub fn iev(&self) -> IEV_R { + IEV_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - 1: Positive/Low, 0: Negative/High"] + #[inline(always)] + #[must_use] + pub fn iev(&mut self) -> IEV_W { + IEV_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_3_SPEC; +impl crate::RegisterSpec for IOIRQ_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_3::R`](R) reader structure"] +impl crate::Readable for IOIRQ_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_3::W`](W) writer structure"] +impl crate::Writable for IOIRQ_3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_3 to value 0"] +impl crate::Resettable for IOIRQ_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_4.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_4.rs new file mode 100644 index 0000000..689d0f1 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_4.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ioirq_4` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_4` writer"] +pub type W = crate::W; +#[doc = "Field `ie` reader - 1: Unmask, 0: Mask"] +pub type IE_R = crate::FieldReader; +#[doc = "Field `ie` writer - 1: Unmask, 0: Mask"] +pub type IE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - 1: Unmask, 0: Mask"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - 1: Unmask, 0: Mask"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_4_SPEC; +impl crate::RegisterSpec for IOIRQ_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_4::R`](R) reader structure"] +impl crate::Readable for IOIRQ_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_4::W`](W) writer structure"] +impl crate::Writable for IOIRQ_4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_4 to value 0"] +impl crate::Resettable for IOIRQ_4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_5.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_5.rs new file mode 100644 index 0000000..2da2125 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_5.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ioirq_5` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_5` writer"] +pub type W = crate::W; +#[doc = "Field `ris` reader - Status of the edge trigger, can be cleared by writing gpioic."] +pub type RIS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Status of the edge trigger, can be cleared by writing gpioic."] + #[inline(always)] + pub fn ris(&self) -> RIS_R { + RIS_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_5_SPEC; +impl crate::RegisterSpec for IOIRQ_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_5::R`](R) reader structure"] +impl crate::Readable for IOIRQ_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_5::W`](W) writer structure"] +impl crate::Writable for IOIRQ_5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_5 to value 0"] +impl crate::Resettable for IOIRQ_5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_6.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_6.rs new file mode 100644 index 0000000..8bbd513 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_6.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ioirq_6` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_6` writer"] +pub type W = crate::W; +#[doc = "Field `mis` reader - The masked GPIO IRQ status."] +pub type MIS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - The masked GPIO IRQ status."] + #[inline(always)] + pub fn mis(&self) -> MIS_R { + MIS_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_6_SPEC; +impl crate::RegisterSpec for IOIRQ_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_6::R`](R) reader structure"] +impl crate::Readable for IOIRQ_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_6::W`](W) writer structure"] +impl crate::Writable for IOIRQ_6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_6 to value 0"] +impl crate::Resettable for IOIRQ_6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_7.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_7.rs new file mode 100644 index 0000000..2f5aded --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/ioirq_7.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ioirq_7` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_7` writer"] +pub type W = crate::W; +#[doc = "Field `in_sync2` reader - Status of gpio_in after synchronization."] +pub type IN_SYNC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Status of gpio_in after synchronization."] + #[inline(always)] + pub fn in_sync2(&self) -> IN_SYNC2_R { + IN_SYNC2_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_7_SPEC; +impl crate::RegisterSpec for IOIRQ_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_7::R`](R) reader structure"] +impl crate::Readable for IOIRQ_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_7::W`](W) writer structure"] +impl crate::Writable for IOIRQ_7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_7 to value 0"] +impl crate::Resettable for IOIRQ_7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/osc.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/osc.rs new file mode 100644 index 0000000..c224162 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/osc.rs @@ -0,0 +1,49 @@ +#[doc = "Register `osc` reader"] +pub type R = crate::R; +#[doc = "Register `osc` writer"] +pub type W = crate::W; +#[doc = "Field `ds` reader - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] +pub type DS_R = crate::FieldReader; +#[doc = "Field `ds` writer - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] + #[inline(always)] + #[must_use] + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`osc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`osc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OSC_SPEC; +impl crate::RegisterSpec for OSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`osc::R`](R) reader structure"] +impl crate::Readable for OSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`osc::W`](W) writer structure"] +impl crate::Writable for OSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets osc to value 0"] +impl crate::Resettable for OSC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_0.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_0.rs new file mode 100644 index 0000000..9eb524e --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_0.rs @@ -0,0 +1,139 @@ +#[doc = "Register `rgpio_0` reader"] +pub type R = crate::R; +#[doc = "Register `rgpio_0` writer"] +pub type W = crate::W; +#[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_R = crate::BitReader; +#[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_R = crate::FieldReader; +#[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_R = crate::BitReader; +#[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_R = crate::BitReader; +#[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_R = crate::BitReader; +#[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_R = crate::BitReader; +#[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_R = crate::BitReader; +#[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pu(&self) -> PU_R { + PU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pd(&self) -> PD_R { + PD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + pub fn slew(&self) -> SLEW_R { + SLEW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + pub fn smt(&self) -> SMT_R { + SMT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + pub fn pos(&self) -> POS_R { + POS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + #[must_use] + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + #[must_use] + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + #[must_use] + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + #[must_use] + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RGPIO_0_SPEC; +impl crate::RegisterSpec for RGPIO_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rgpio_0::R`](R) reader structure"] +impl crate::Readable for RGPIO_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rgpio_0::W`](W) writer structure"] +impl crate::Writable for RGPIO_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets rgpio_0 to value 0"] +impl crate::Resettable for RGPIO_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_1.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_1.rs new file mode 100644 index 0000000..4232f2d --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_1.rs @@ -0,0 +1,139 @@ +#[doc = "Register `rgpio_1` reader"] +pub type R = crate::R; +#[doc = "Register `rgpio_1` writer"] +pub type W = crate::W; +#[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_R = crate::BitReader; +#[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_R = crate::FieldReader; +#[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_R = crate::BitReader; +#[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_R = crate::BitReader; +#[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_R = crate::BitReader; +#[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_R = crate::BitReader; +#[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_R = crate::BitReader; +#[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pu(&self) -> PU_R { + PU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pd(&self) -> PD_R { + PD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + pub fn slew(&self) -> SLEW_R { + SLEW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + pub fn smt(&self) -> SMT_R { + SMT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + pub fn pos(&self) -> POS_R { + POS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + #[must_use] + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + #[must_use] + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + #[must_use] + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + #[must_use] + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RGPIO_1_SPEC; +impl crate::RegisterSpec for RGPIO_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rgpio_1::R`](R) reader structure"] +impl crate::Readable for RGPIO_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rgpio_1::W`](W) writer structure"] +impl crate::Writable for RGPIO_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets rgpio_1 to value 0"] +impl crate::Resettable for RGPIO_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_2.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_2.rs new file mode 100644 index 0000000..fa5bca7 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_2.rs @@ -0,0 +1,139 @@ +#[doc = "Register `rgpio_2` reader"] +pub type R = crate::R; +#[doc = "Register `rgpio_2` writer"] +pub type W = crate::W; +#[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_R = crate::BitReader; +#[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_R = crate::FieldReader; +#[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_R = crate::BitReader; +#[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_R = crate::BitReader; +#[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_R = crate::BitReader; +#[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_R = crate::BitReader; +#[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_R = crate::BitReader; +#[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pu(&self) -> PU_R { + PU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pd(&self) -> PD_R { + PD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + pub fn slew(&self) -> SLEW_R { + SLEW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + pub fn smt(&self) -> SMT_R { + SMT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + pub fn pos(&self) -> POS_R { + POS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + #[must_use] + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + #[must_use] + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + #[must_use] + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + #[must_use] + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RGPIO_2_SPEC; +impl crate::RegisterSpec for RGPIO_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rgpio_2::R`](R) reader structure"] +impl crate::Readable for RGPIO_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rgpio_2::W`](W) writer structure"] +impl crate::Writable for RGPIO_2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets rgpio_2 to value 0"] +impl crate::Resettable for RGPIO_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_3.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_3.rs new file mode 100644 index 0000000..ca90310 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/rgpio_3.rs @@ -0,0 +1,139 @@ +#[doc = "Register `rgpio_3` reader"] +pub type R = crate::R; +#[doc = "Register `rgpio_3` writer"] +pub type W = crate::W; +#[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_R = crate::BitReader; +#[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_R = crate::FieldReader; +#[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_R = crate::BitReader; +#[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_R = crate::BitReader; +#[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_R = crate::BitReader; +#[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_R = crate::BitReader; +#[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_R = crate::BitReader; +#[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pu(&self) -> PU_R { + PU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pd(&self) -> PD_R { + PD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + pub fn slew(&self) -> SLEW_R { + SLEW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + pub fn smt(&self) -> SMT_R { + SMT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + pub fn pos(&self) -> POS_R { + POS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + #[must_use] + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + #[must_use] + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + #[must_use] + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + #[must_use] + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RGPIO_3_SPEC; +impl crate::RegisterSpec for RGPIO_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rgpio_3::R`](R) reader structure"] +impl crate::Readable for RGPIO_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rgpio_3::W`](W) writer structure"] +impl crate::Writable for RGPIO_3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets rgpio_3 to value 0"] +impl crate::Resettable for RGPIO_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/rstn.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/rstn.rs new file mode 100644 index 0000000..726d5e6 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/rstn.rs @@ -0,0 +1,64 @@ +#[doc = "Register `rstn` reader"] +pub type R = crate::R; +#[doc = "Register `rstn` writer"] +pub type W = crate::W; +#[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] +pub type SMT_R = crate::BitReader; +#[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_R = crate::BitReader; +#[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] + #[inline(always)] + pub fn smt(&self) -> SMT_R { + SMT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + pub fn pos(&self) -> POS_R { + POS_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] + #[inline(always)] + #[must_use] + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 0) + } + #[doc = "Bit 1 - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + #[must_use] + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstn::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstn::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RSTN_SPEC; +impl crate::RegisterSpec for RSTN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rstn::R`](R) reader structure"] +impl crate::Readable for RSTN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rstn::W`](W) writer structure"] +impl crate::Writable for RSTN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets rstn to value 0"] +impl crate::Resettable for RSTN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/rtc.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/rtc.rs new file mode 100644 index 0000000..04570ba --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/rtc.rs @@ -0,0 +1,49 @@ +#[doc = "Register `rtc` reader"] +pub type R = crate::R; +#[doc = "Register `rtc` writer"] +pub type W = crate::W; +#[doc = "Field `ds` reader - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] +pub type DS_R = crate::FieldReader; +#[doc = "Field `ds` writer - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] + #[inline(always)] + #[must_use] + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RTC_SPEC; +impl crate::RegisterSpec for RTC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rtc::R`](R) reader structure"] +impl crate::Readable for RTC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rtc::W`](W) writer structure"] +impl crate::Writable for RTC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets rtc to value 0"] +impl crate::Resettable for RTC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/testen.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/testen.rs new file mode 100644 index 0000000..7bfe248 --- /dev/null +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/testen.rs @@ -0,0 +1,49 @@ +#[doc = "Register `testen` reader"] +pub type R = crate::R; +#[doc = "Register `testen` writer"] +pub type W = crate::W; +#[doc = "Field `testen_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type TESTEN_POS_R = crate::BitReader; +#[doc = "Field `testen_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type TESTEN_POS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + pub fn testen_pos(&self) -> TESTEN_POS_R { + TESTEN_POS_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + #[must_use] + pub fn testen_pos(&mut self) -> TESTEN_POS_W { + TESTEN_POS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`testen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`testen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TESTEN_SPEC; +impl crate::RegisterSpec for TESTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`testen::R`](R) reader structure"] +impl crate::Readable for TESTEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`testen::W`](W) writer structure"] +impl crate::Writable for TESTEN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets testen to value 0"] +impl crate::Resettable for TESTEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/jh7110-starfive-visionfive-2-v1.3b.svd b/jh7110-vf2-13b-pac/jh7110-starfive-visionfive-2-v1.3b.svd index af86a6c..17b4848 100644 --- a/jh7110-vf2-13b-pac/jh7110-starfive-visionfive-2-v1.3b.svd +++ b/jh7110-vf2-13b-pac/jh7110-starfive-visionfive-2-v1.3b.svd @@ -43043,31 +43043,32 @@ - aon_iomux_cfgsaif_syscfg_fmux0 + fmux_0 AON IOMUX CFG SAIF SYSCFG FMUX 0 0x0 32 + 0 - aon_iomux_gpo0_doen_cfg + gpo_doen_0 The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [2:0] read-write - aon_iomux_gpo1_doen_cfg + gpo_doen_1 The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [10:8] read-write - aon_iomux_gpo2_doen_cfg + gpo_doen_2 The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [18:16] read-write - aon_iomux_gpo3_doen_cfg + gpo_doen_3 The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [26:24] read-write @@ -43075,31 +43076,32 @@ - aon_iomux_cfgsaif_syscfg_fmux1 - AON IOMUX CFG SAIF SYSCFG FMUX 1 + fmux_1 + AON IOMUX CFG SAIF SYSCFG FMUX 4 0x4 32 + 0 - aon_iomux_gpo0_dout_cfg + gpo_dout_0 The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [3:0] read-write - aon_iomux_gpo1_dout_cfg + gpo_dout_1 The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [11:8] read-write - aon_iomux_gpo2_dout_cfg + gpo_dout_2 The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [19:16] read-write - aon_iomux_gpo3_dout_cfg + gpo_dout_3 The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [27:24] read-write @@ -43107,31 +43109,32 @@ - aon_iomux_cfgsaif_syscfg_fmux2 - AON IOMUX CFG SAIF SYSCFG FMUX 2 + fmux_2 + AON IOMUX CFG SAIF SYSCFG FMUX 8 0x8 32 + 0 - aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg + gpi_pmu_wakeup_0 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [2:0] read-write - aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg + gpi_pmu_wakeup_1 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [10:8] read-write - aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg + gpi_pmu_wakeup_2 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [18:16] read-write - aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg + gpi_pmu_wakeup_3 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [26:24] read-write @@ -43139,13 +43142,14 @@ - aon_iomux_cfgsaif_syscfg_fmux3 - AON IOMUX CFG SAIF SYSCFG FMUX 3 + fmux_3 + AON IOMUX CFG SAIF SYSCFG FMUX 12 0xc 32 + 0 - aon_gpioen_0_reg + gpen_0 Enable GPIO IRQ function. [0:0] read-write @@ -43153,13 +43157,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq4 - AON IOMUX CFG SAIF SYSCFG IOIRQ 4 + ioirq_0 + AON IOMUX CFG SAIF SYSCFG IOIRQ 16 0x10 32 + 0 - aon_gpiois_0_reg + is 1: Edge trigger, 0: Level trigger [3:0] read-write @@ -43167,13 +43172,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq5 - AON IOMUX CFG SAIF SYSCFG IOIRQ 5 + ioirq_1 + AON IOMUX CFG SAIF SYSCFG IOIRQ 20 0x14 32 + 0 - aon_gpioic_0_reg + ic 1: Do not clear the register, 0: Clear the register [3:0] read-write @@ -43181,13 +43187,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq6 - AON IOMUX CFG SAIF SYSCFG IOIRQ 6 + ioirq_2 + AON IOMUX CFG SAIF SYSCFG IOIRQ 24 0x18 32 + 0 - aon_gpioibe_0_reg + ibe 1: Trigger on both edges, 0: Trigger on a single edge [3:0] read-write @@ -43195,13 +43202,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq7 - AON IOMUX CFG SAIF SYSCFG IOIRQ 7 + ioirq_3 + AON IOMUX CFG SAIF SYSCFG IOIRQ 28 0x1c 32 + 0 - aon_gpioiev_0_reg + iev 1: Positive/Low, 0: Negative/High [3:0] read-write @@ -43209,13 +43217,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq8 - AON IOMUX CFG SAIF SYSCFG IOIRQ 8 + ioirq_4 + AON IOMUX CFG SAIF SYSCFG IOIRQ 32 0x20 32 + 0 - aon_gpioie_0_reg + ie 1: Unmask, 0: Mask [3:0] read-write @@ -43223,13 +43232,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq9 - AON IOMUX CFG SAIF SYSCFG IOIRQ 9 + ioirq_5 + AON IOMUX CFG SAIF SYSCFG IOIRQ 36 0x24 32 + 0 - aon_gpioris_0_reg + ris Status of the edge trigger, can be cleared by writing gpioic. [3:0] read-only @@ -43237,13 +43247,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq10 - AON IOMUX CFG SAIF SYSCFG IOIRQ 10 + ioirq_6 + AON IOMUX CFG SAIF SYSCFG IOIRQ 40 0x28 32 + 0 - aon_gpiomis_0_reg + mis The masked GPIO IRQ status. [3:0] read-only @@ -43251,13 +43262,14 @@ - aon_iomux_cfgsaif_syscfg_ioirq11 - AON IOMUX CFG SAIF SYSCFG IOIRQ 11 + ioirq_7 + AON IOMUX CFG SAIF SYSCFG IOIRQ 44 0x2c 32 + 0 - aon_gpio_in_sync2_0_reg + in_sync2 Status of gpio_in after synchronization. [3:0] read-only @@ -43265,13 +43277,14 @@ - aon_iomux_cfgsaif_syscfg48 + testen AON IOMUX CFG SAIF SYSCFG 48 0x30 32 + 0 - padcfg_pad_testen_pos + testen_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [0:0] read-write @@ -43279,49 +43292,50 @@ - aon_iomux_cfgsaif_syscfg52 + rgpio_0 AON IOMUX CFG SAIF SYSCFG 52 0x34 32 + 0 - padcfg_pad_rgpio0_ie + ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_rgpio0_ds + ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_rgpio0_pu + pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_rgpio0_pd + pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_rgpio0_slew + slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_rgpio0_smt + smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_rgpio0_pos + pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -43329,49 +43343,50 @@ - aon_iomux_cfgsaif_syscfg56 + rgpio_1 AON IOMUX CFG SAIF SYSCFG 56 0x38 32 + 0 - padcfg_pad_rgpio1_ie + ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_rgpio1_ds + ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_rgpio1_pu + pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_rgpio1_pd + pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_rgpio1_slew + slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_rgpio1_smt + smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_rgpio1_pos + pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -43379,49 +43394,50 @@ - aon_iomux_cfgsaif_syscfg60 + rgpio_2 AON IOMUX CFG SAIF SYSCFG 60 0x3c 32 + 0 - padcfg_pad_rgpio2_ie + ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_rgpio2_ds + ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_rgpio2_pu + pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_rgpio2_pd + pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_rgpio2_slew + slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_rgpio2_smt + smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_rgpio2_pos + pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -43429,49 +43445,50 @@ - aon_iomux_cfgsaif_syscfg64 + rgpio_3 AON IOMUX CFG SAIF SYSCFG 64 0x40 32 + 0 - padcfg_pad_rgpio3_ie + ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write - padcfg_pad_rgpio3_ds + ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write - padcfg_pad_rgpio3_pu + pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write - padcfg_pad_rgpio3_pd + pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write - padcfg_pad_rgpio3_slew + slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write - padcfg_pad_rgpio3_smt + smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write - padcfg_pad_rgpio3_pos + pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write @@ -43479,19 +43496,20 @@ - aon_iomux_cfgsaif_syscfg68 + rstn AON IOMUX CFG SAIF SYSCFG 68 0x44 32 + 0 - padcfg_pad_rstn_smt + smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled [0:0] read-write - padcfg_pad_rstn_pos + pos Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled [1:1] read-write @@ -43499,13 +43517,14 @@ - aon_iomux_cfgsaif_syscfg76 + rtc AON IOMUX CFG SAIF SYSCFG 76 0x4c 32 + 0 - padcfg_pad_rtc_ds + ds Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA. [1:0] read-write @@ -43513,13 +43532,14 @@ - aon_iomux_cfgsaif_syscfg84 + osc AON IOMUX CFG SAIF SYSCFG 84 0x54 32 + 0 - padcfg_pad_osc_ds + ds Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA. [1:0] read-write @@ -43527,41 +43547,44 @@ - aon_iomux_cfgsaif_syscfg88 + gmac0_mdc AON IOMUX CFG SAIF SYSCFG 88 0x58 32 + 0 - padcfg_pad_gmac0_mdc_syscon - padcfg_pad_gmac0_mdc_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg92 + gmac0_mdio AON IOMUX CFG SAIF SYSCFG 92 0x5c 32 + 0 - padcfg_pad_gmac0_mdio_syscon - padcfg_pad_gmac0_mdio_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg96 + gmac0_rxd0 AON IOMUX CFG SAIF SYSCFG 96 0x60 32 + 0 - padcfg_pad_gmac0_rxd0_syscon + value 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V [1:0] read-write @@ -43569,167 +43592,179 @@ - aon_iomux_cfgsaif_syscfg100 + gmac0_rxd1 AON IOMUX CFG SAIF SYSCFG 100 0x64 32 + 0 - padcfg_pad_gmac0_rxd1_syscon - padcfg_pad_gmac0_rxd1_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg104 + gmac0_rxd2 AON IOMUX CFG SAIF SYSCFG 104 0x68 32 + 0 - padcfg_pad_gmac0_rxd2_syscon - padcfg_pad_gmac0_rxd2_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg108 + gmac0_rxd3 AON IOMUX CFG SAIF SYSCFG 108 0x6c 32 + 0 - padcfg_pad_gmac0_rxd3_syscon - padcfg_pad_gmac0_rxd3_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg112 + gmac0_rxdv AON IOMUX CFG SAIF SYSCFG 112 0x70 32 + 0 - padcfg_pad_gmac0_rxdv_syscon - padcfg_pad_gmac0_rxdv_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg116 + gmac0_rxc AON IOMUX CFG SAIF SYSCFG 116 0x74 32 + 0 - padcfg_pad_gmac0_rxc_syscon - padcfg_pad_gmac0_rxc_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg120 + gmac0_txd0 AON IOMUX CFG SAIF SYSCFG 120 0x78 32 + 0 - padcfg_pad_gmac0_txd0_syscon - padcfg_pad_gmac0_txd0_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg124 + gmac0_txd1 AON IOMUX CFG SAIF SYSCFG 124 0x7c 32 + 0 - padcfg_pad_gmac0_txd1_syscon - padcfg_pad_gmac0_txd1_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg128 + gmac0_txd2 AON IOMUX CFG SAIF SYSCFG 128 0x80 32 + 0 - padcfg_pad_gmac0_txd2_syscon - padcfg_pad_gmac0_txd2_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg132 + gmac0_txd3 AON IOMUX CFG SAIF SYSCFG 132 0x84 32 + 0 - padcfg_pad_gmac0_txd3_syscon - padcfg_pad_gmac0_txd3_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg136 + gmac0_txen AON IOMUX CFG SAIF SYSCFG 136 0x88 32 + 0 - padcfg_pad_gmac0_txen_syscon - padcfg_pad_gmac0_txen_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg140 + gmac0_txc AON IOMUX CFG SAIF SYSCFG 140 0x8c 32 + 0 - padcfg_pad_gmac0_txc_syscon - padcfg_pad_gmac0_txc_syscon + value + value [1:0] read-write - aon_iomux_cfgsaif_syscfg144 + gmac0_rxc_func_sel AON IOMUX CFG SAIF SYSCFG 144 0x90 32 + 0 - pad_gmac0_rxc_func_sel + value Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None [1:0] read-write diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl.rs index 665a4ad..1a9cf4d 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl.rs @@ -1,428 +1,393 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - aon_iomux_cfgsaif_syscfg_fmux0: AON_IOMUX_CFGSAIF_SYSCFG_FMUX0, - aon_iomux_cfgsaif_syscfg_fmux1: AON_IOMUX_CFGSAIF_SYSCFG_FMUX1, - aon_iomux_cfgsaif_syscfg_fmux2: AON_IOMUX_CFGSAIF_SYSCFG_FMUX2, - aon_iomux_cfgsaif_syscfg_fmux3: AON_IOMUX_CFGSAIF_SYSCFG_FMUX3, - aon_iomux_cfgsaif_syscfg_ioirq4: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4, - aon_iomux_cfgsaif_syscfg_ioirq5: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5, - aon_iomux_cfgsaif_syscfg_ioirq6: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6, - aon_iomux_cfgsaif_syscfg_ioirq7: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7, - aon_iomux_cfgsaif_syscfg_ioirq8: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8, - aon_iomux_cfgsaif_syscfg_ioirq9: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9, - aon_iomux_cfgsaif_syscfg_ioirq10: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10, - aon_iomux_cfgsaif_syscfg_ioirq11: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11, - aon_iomux_cfgsaif_syscfg48: AON_IOMUX_CFGSAIF_SYSCFG48, - aon_iomux_cfgsaif_syscfg52: AON_IOMUX_CFGSAIF_SYSCFG52, - aon_iomux_cfgsaif_syscfg56: AON_IOMUX_CFGSAIF_SYSCFG56, - aon_iomux_cfgsaif_syscfg60: AON_IOMUX_CFGSAIF_SYSCFG60, - aon_iomux_cfgsaif_syscfg64: AON_IOMUX_CFGSAIF_SYSCFG64, - aon_iomux_cfgsaif_syscfg68: AON_IOMUX_CFGSAIF_SYSCFG68, + fmux_0: FMUX_0, + fmux_1: FMUX_1, + fmux_2: FMUX_2, + fmux_3: FMUX_3, + ioirq_0: IOIRQ_0, + ioirq_1: IOIRQ_1, + ioirq_2: IOIRQ_2, + ioirq_3: IOIRQ_3, + ioirq_4: IOIRQ_4, + ioirq_5: IOIRQ_5, + ioirq_6: IOIRQ_6, + ioirq_7: IOIRQ_7, + testen: TESTEN, + rgpio_0: RGPIO_0, + rgpio_1: RGPIO_1, + rgpio_2: RGPIO_2, + rgpio_3: RGPIO_3, + rstn: RSTN, _reserved18: [u8; 0x04], - aon_iomux_cfgsaif_syscfg76: AON_IOMUX_CFGSAIF_SYSCFG76, + rtc: RTC, _reserved19: [u8; 0x04], - aon_iomux_cfgsaif_syscfg84: AON_IOMUX_CFGSAIF_SYSCFG84, - aon_iomux_cfgsaif_syscfg88: AON_IOMUX_CFGSAIF_SYSCFG88, - aon_iomux_cfgsaif_syscfg92: AON_IOMUX_CFGSAIF_SYSCFG92, - aon_iomux_cfgsaif_syscfg96: AON_IOMUX_CFGSAIF_SYSCFG96, - aon_iomux_cfgsaif_syscfg100: AON_IOMUX_CFGSAIF_SYSCFG100, - aon_iomux_cfgsaif_syscfg104: AON_IOMUX_CFGSAIF_SYSCFG104, - aon_iomux_cfgsaif_syscfg108: AON_IOMUX_CFGSAIF_SYSCFG108, - aon_iomux_cfgsaif_syscfg112: AON_IOMUX_CFGSAIF_SYSCFG112, - aon_iomux_cfgsaif_syscfg116: AON_IOMUX_CFGSAIF_SYSCFG116, - aon_iomux_cfgsaif_syscfg120: AON_IOMUX_CFGSAIF_SYSCFG120, - aon_iomux_cfgsaif_syscfg124: AON_IOMUX_CFGSAIF_SYSCFG124, - aon_iomux_cfgsaif_syscfg128: AON_IOMUX_CFGSAIF_SYSCFG128, - aon_iomux_cfgsaif_syscfg132: AON_IOMUX_CFGSAIF_SYSCFG132, - aon_iomux_cfgsaif_syscfg136: AON_IOMUX_CFGSAIF_SYSCFG136, - aon_iomux_cfgsaif_syscfg140: AON_IOMUX_CFGSAIF_SYSCFG140, - aon_iomux_cfgsaif_syscfg144: AON_IOMUX_CFGSAIF_SYSCFG144, + osc: OSC, + gmac0_mdc: GMAC0_MDC, + gmac0_mdio: GMAC0_MDIO, + gmac0_rxd0: GMAC0_RXD0, + gmac0_rxd1: GMAC0_RXD1, + gmac0_rxd2: GMAC0_RXD2, + gmac0_rxd3: GMAC0_RXD3, + gmac0_rxdv: GMAC0_RXDV, + gmac0_rxc: GMAC0_RXC, + gmac0_txd0: GMAC0_TXD0, + gmac0_txd1: GMAC0_TXD1, + gmac0_txd2: GMAC0_TXD2, + gmac0_txd3: GMAC0_TXD3, + gmac0_txen: GMAC0_TXEN, + gmac0_txc: GMAC0_TXC, + gmac0_rxc_func_sel: GMAC0_RXC_FUNC_SEL, } impl RegisterBlock { #[doc = "0x00 - AON IOMUX CFG SAIF SYSCFG FMUX 0"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_fmux0(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX0 { - &self.aon_iomux_cfgsaif_syscfg_fmux0 + pub const fn fmux_0(&self) -> &FMUX_0 { + &self.fmux_0 } - #[doc = "0x04 - AON IOMUX CFG SAIF SYSCFG FMUX 1"] + #[doc = "0x04 - AON IOMUX CFG SAIF SYSCFG FMUX 4"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_fmux1(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX1 { - &self.aon_iomux_cfgsaif_syscfg_fmux1 + pub const fn fmux_1(&self) -> &FMUX_1 { + &self.fmux_1 } - #[doc = "0x08 - AON IOMUX CFG SAIF SYSCFG FMUX 2"] + #[doc = "0x08 - AON IOMUX CFG SAIF SYSCFG FMUX 8"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_fmux2(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX2 { - &self.aon_iomux_cfgsaif_syscfg_fmux2 + pub const fn fmux_2(&self) -> &FMUX_2 { + &self.fmux_2 } - #[doc = "0x0c - AON IOMUX CFG SAIF SYSCFG FMUX 3"] + #[doc = "0x0c - AON IOMUX CFG SAIF SYSCFG FMUX 12"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_fmux3(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX3 { - &self.aon_iomux_cfgsaif_syscfg_fmux3 + pub const fn fmux_3(&self) -> &FMUX_3 { + &self.fmux_3 } - #[doc = "0x10 - AON IOMUX CFG SAIF SYSCFG IOIRQ 4"] + #[doc = "0x10 - AON IOMUX CFG SAIF SYSCFG IOIRQ 16"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq4(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4 { - &self.aon_iomux_cfgsaif_syscfg_ioirq4 + pub const fn ioirq_0(&self) -> &IOIRQ_0 { + &self.ioirq_0 } - #[doc = "0x14 - AON IOMUX CFG SAIF SYSCFG IOIRQ 5"] + #[doc = "0x14 - AON IOMUX CFG SAIF SYSCFG IOIRQ 20"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq5(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5 { - &self.aon_iomux_cfgsaif_syscfg_ioirq5 + pub const fn ioirq_1(&self) -> &IOIRQ_1 { + &self.ioirq_1 } - #[doc = "0x18 - AON IOMUX CFG SAIF SYSCFG IOIRQ 6"] + #[doc = "0x18 - AON IOMUX CFG SAIF SYSCFG IOIRQ 24"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq6(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6 { - &self.aon_iomux_cfgsaif_syscfg_ioirq6 + pub const fn ioirq_2(&self) -> &IOIRQ_2 { + &self.ioirq_2 } - #[doc = "0x1c - AON IOMUX CFG SAIF SYSCFG IOIRQ 7"] + #[doc = "0x1c - AON IOMUX CFG SAIF SYSCFG IOIRQ 28"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq7(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7 { - &self.aon_iomux_cfgsaif_syscfg_ioirq7 + pub const fn ioirq_3(&self) -> &IOIRQ_3 { + &self.ioirq_3 } - #[doc = "0x20 - AON IOMUX CFG SAIF SYSCFG IOIRQ 8"] + #[doc = "0x20 - AON IOMUX CFG SAIF SYSCFG IOIRQ 32"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq8(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8 { - &self.aon_iomux_cfgsaif_syscfg_ioirq8 + pub const fn ioirq_4(&self) -> &IOIRQ_4 { + &self.ioirq_4 } - #[doc = "0x24 - AON IOMUX CFG SAIF SYSCFG IOIRQ 9"] + #[doc = "0x24 - AON IOMUX CFG SAIF SYSCFG IOIRQ 36"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq9(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9 { - &self.aon_iomux_cfgsaif_syscfg_ioirq9 + pub const fn ioirq_5(&self) -> &IOIRQ_5 { + &self.ioirq_5 } - #[doc = "0x28 - AON IOMUX CFG SAIF SYSCFG IOIRQ 10"] + #[doc = "0x28 - AON IOMUX CFG SAIF SYSCFG IOIRQ 40"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq10(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10 { - &self.aon_iomux_cfgsaif_syscfg_ioirq10 + pub const fn ioirq_6(&self) -> &IOIRQ_6 { + &self.ioirq_6 } - #[doc = "0x2c - AON IOMUX CFG SAIF SYSCFG IOIRQ 11"] + #[doc = "0x2c - AON IOMUX CFG SAIF SYSCFG IOIRQ 44"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg_ioirq11(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11 { - &self.aon_iomux_cfgsaif_syscfg_ioirq11 + pub const fn ioirq_7(&self) -> &IOIRQ_7 { + &self.ioirq_7 } #[doc = "0x30 - AON IOMUX CFG SAIF SYSCFG 48"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg48(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG48 { - &self.aon_iomux_cfgsaif_syscfg48 + pub const fn testen(&self) -> &TESTEN { + &self.testen } #[doc = "0x34 - AON IOMUX CFG SAIF SYSCFG 52"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg52(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG52 { - &self.aon_iomux_cfgsaif_syscfg52 + pub const fn rgpio_0(&self) -> &RGPIO_0 { + &self.rgpio_0 } #[doc = "0x38 - AON IOMUX CFG SAIF SYSCFG 56"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg56(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG56 { - &self.aon_iomux_cfgsaif_syscfg56 + pub const fn rgpio_1(&self) -> &RGPIO_1 { + &self.rgpio_1 } #[doc = "0x3c - AON IOMUX CFG SAIF SYSCFG 60"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg60(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG60 { - &self.aon_iomux_cfgsaif_syscfg60 + pub const fn rgpio_2(&self) -> &RGPIO_2 { + &self.rgpio_2 } #[doc = "0x40 - AON IOMUX CFG SAIF SYSCFG 64"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg64(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG64 { - &self.aon_iomux_cfgsaif_syscfg64 + pub const fn rgpio_3(&self) -> &RGPIO_3 { + &self.rgpio_3 } #[doc = "0x44 - AON IOMUX CFG SAIF SYSCFG 68"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg68(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG68 { - &self.aon_iomux_cfgsaif_syscfg68 + pub const fn rstn(&self) -> &RSTN { + &self.rstn } #[doc = "0x4c - AON IOMUX CFG SAIF SYSCFG 76"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg76(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG76 { - &self.aon_iomux_cfgsaif_syscfg76 + pub const fn rtc(&self) -> &RTC { + &self.rtc } #[doc = "0x54 - AON IOMUX CFG SAIF SYSCFG 84"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg84(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG84 { - &self.aon_iomux_cfgsaif_syscfg84 + pub const fn osc(&self) -> &OSC { + &self.osc } #[doc = "0x58 - AON IOMUX CFG SAIF SYSCFG 88"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg88(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG88 { - &self.aon_iomux_cfgsaif_syscfg88 + pub const fn gmac0_mdc(&self) -> &GMAC0_MDC { + &self.gmac0_mdc } #[doc = "0x5c - AON IOMUX CFG SAIF SYSCFG 92"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg92(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG92 { - &self.aon_iomux_cfgsaif_syscfg92 + pub const fn gmac0_mdio(&self) -> &GMAC0_MDIO { + &self.gmac0_mdio } #[doc = "0x60 - AON IOMUX CFG SAIF SYSCFG 96"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg96(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG96 { - &self.aon_iomux_cfgsaif_syscfg96 + pub const fn gmac0_rxd0(&self) -> &GMAC0_RXD0 { + &self.gmac0_rxd0 } #[doc = "0x64 - AON IOMUX CFG SAIF SYSCFG 100"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg100(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG100 { - &self.aon_iomux_cfgsaif_syscfg100 + pub const fn gmac0_rxd1(&self) -> &GMAC0_RXD1 { + &self.gmac0_rxd1 } #[doc = "0x68 - AON IOMUX CFG SAIF SYSCFG 104"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg104(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG104 { - &self.aon_iomux_cfgsaif_syscfg104 + pub const fn gmac0_rxd2(&self) -> &GMAC0_RXD2 { + &self.gmac0_rxd2 } #[doc = "0x6c - AON IOMUX CFG SAIF SYSCFG 108"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg108(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG108 { - &self.aon_iomux_cfgsaif_syscfg108 + pub const fn gmac0_rxd3(&self) -> &GMAC0_RXD3 { + &self.gmac0_rxd3 } #[doc = "0x70 - AON IOMUX CFG SAIF SYSCFG 112"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg112(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG112 { - &self.aon_iomux_cfgsaif_syscfg112 + pub const fn gmac0_rxdv(&self) -> &GMAC0_RXDV { + &self.gmac0_rxdv } #[doc = "0x74 - AON IOMUX CFG SAIF SYSCFG 116"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg116(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG116 { - &self.aon_iomux_cfgsaif_syscfg116 + pub const fn gmac0_rxc(&self) -> &GMAC0_RXC { + &self.gmac0_rxc } #[doc = "0x78 - AON IOMUX CFG SAIF SYSCFG 120"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg120(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG120 { - &self.aon_iomux_cfgsaif_syscfg120 + pub const fn gmac0_txd0(&self) -> &GMAC0_TXD0 { + &self.gmac0_txd0 } #[doc = "0x7c - AON IOMUX CFG SAIF SYSCFG 124"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg124(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG124 { - &self.aon_iomux_cfgsaif_syscfg124 + pub const fn gmac0_txd1(&self) -> &GMAC0_TXD1 { + &self.gmac0_txd1 } #[doc = "0x80 - AON IOMUX CFG SAIF SYSCFG 128"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg128(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG128 { - &self.aon_iomux_cfgsaif_syscfg128 + pub const fn gmac0_txd2(&self) -> &GMAC0_TXD2 { + &self.gmac0_txd2 } #[doc = "0x84 - AON IOMUX CFG SAIF SYSCFG 132"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg132(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG132 { - &self.aon_iomux_cfgsaif_syscfg132 + pub const fn gmac0_txd3(&self) -> &GMAC0_TXD3 { + &self.gmac0_txd3 } #[doc = "0x88 - AON IOMUX CFG SAIF SYSCFG 136"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg136(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG136 { - &self.aon_iomux_cfgsaif_syscfg136 + pub const fn gmac0_txen(&self) -> &GMAC0_TXEN { + &self.gmac0_txen } #[doc = "0x8c - AON IOMUX CFG SAIF SYSCFG 140"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg140(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG140 { - &self.aon_iomux_cfgsaif_syscfg140 + pub const fn gmac0_txc(&self) -> &GMAC0_TXC { + &self.gmac0_txc } #[doc = "0x90 - AON IOMUX CFG SAIF SYSCFG 144"] #[inline(always)] - pub const fn aon_iomux_cfgsaif_syscfg144(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG144 { - &self.aon_iomux_cfgsaif_syscfg144 + pub const fn gmac0_rxc_func_sel(&self) -> &GMAC0_RXC_FUNC_SEL { + &self.gmac0_rxc_func_sel } } -#[doc = "aon_iomux_cfgsaif_syscfg_fmux0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux0`] +#[doc = "fmux_0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmux_0`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX0 = - crate::Reg; +pub type FMUX_0 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 0"] -pub mod aon_iomux_cfgsaif_syscfg_fmux0; -#[doc = "aon_iomux_cfgsaif_syscfg_fmux1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux1`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX1 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 1"] -pub mod aon_iomux_cfgsaif_syscfg_fmux1; -#[doc = "aon_iomux_cfgsaif_syscfg_fmux2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux2`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX2 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 2"] -pub mod aon_iomux_cfgsaif_syscfg_fmux2; -#[doc = "aon_iomux_cfgsaif_syscfg_fmux3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux3`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX3 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 3"] -pub mod aon_iomux_cfgsaif_syscfg_fmux3; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq4 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq4`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 4"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq4; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq5 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq5`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 5"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq5; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq6 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq6`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 6"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq6; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq7 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq7`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 7"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq7; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq8 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq8`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 8"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq8; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq9 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq9::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq9`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 9"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq9; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq10 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq10::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq10`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 10"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq10; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq11 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq11::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq11`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11 = - crate::Reg; -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 11"] -pub mod aon_iomux_cfgsaif_syscfg_ioirq11; -#[doc = "aon_iomux_cfgsaif_syscfg48 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg48`] -module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG48 = - crate::Reg; +pub mod fmux_0; +#[doc = "fmux_1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmux_1`] +module"] +pub type FMUX_1 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 4"] +pub mod fmux_1; +#[doc = "fmux_2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmux_2`] +module"] +pub type FMUX_2 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 8"] +pub mod fmux_2; +#[doc = "fmux_3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmux_3`] +module"] +pub type FMUX_3 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 12"] +pub mod fmux_3; +#[doc = "ioirq_0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_0`] +module"] +pub type IOIRQ_0 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 16"] +pub mod ioirq_0; +#[doc = "ioirq_1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_1`] +module"] +pub type IOIRQ_1 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 20"] +pub mod ioirq_1; +#[doc = "ioirq_2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_2`] +module"] +pub type IOIRQ_2 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 24"] +pub mod ioirq_2; +#[doc = "ioirq_3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_3`] +module"] +pub type IOIRQ_3 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 28"] +pub mod ioirq_3; +#[doc = "ioirq_4 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_4`] +module"] +pub type IOIRQ_4 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 32"] +pub mod ioirq_4; +#[doc = "ioirq_5 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_5`] +module"] +pub type IOIRQ_5 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 36"] +pub mod ioirq_5; +#[doc = "ioirq_6 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_6`] +module"] +pub type IOIRQ_6 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 40"] +pub mod ioirq_6; +#[doc = "ioirq_7 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq_7`] +module"] +pub type IOIRQ_7 = crate::Reg; +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 44"] +pub mod ioirq_7; +#[doc = "testen (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`testen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`testen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@testen`] +module"] +pub type TESTEN = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 48"] -pub mod aon_iomux_cfgsaif_syscfg48; -#[doc = "aon_iomux_cfgsaif_syscfg52 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg52`] +pub mod testen; +#[doc = "rgpio_0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rgpio_0`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG52 = - crate::Reg; +pub type RGPIO_0 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 52"] -pub mod aon_iomux_cfgsaif_syscfg52; -#[doc = "aon_iomux_cfgsaif_syscfg56 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg56`] +pub mod rgpio_0; +#[doc = "rgpio_1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rgpio_1`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG56 = - crate::Reg; +pub type RGPIO_1 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 56"] -pub mod aon_iomux_cfgsaif_syscfg56; -#[doc = "aon_iomux_cfgsaif_syscfg60 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg60`] +pub mod rgpio_1; +#[doc = "rgpio_2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rgpio_2`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG60 = - crate::Reg; +pub type RGPIO_2 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 60"] -pub mod aon_iomux_cfgsaif_syscfg60; -#[doc = "aon_iomux_cfgsaif_syscfg64 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg64`] +pub mod rgpio_2; +#[doc = "rgpio_3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rgpio_3`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG64 = - crate::Reg; +pub type RGPIO_3 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 64"] -pub mod aon_iomux_cfgsaif_syscfg64; -#[doc = "aon_iomux_cfgsaif_syscfg68 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg68`] +pub mod rgpio_3; +#[doc = "rstn (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstn::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstn::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstn`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG68 = - crate::Reg; +pub type RSTN = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 68"] -pub mod aon_iomux_cfgsaif_syscfg68; -#[doc = "aon_iomux_cfgsaif_syscfg76 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg76`] +pub mod rstn; +#[doc = "rtc (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG76 = - crate::Reg; +pub type RTC = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 76"] -pub mod aon_iomux_cfgsaif_syscfg76; -#[doc = "aon_iomux_cfgsaif_syscfg84 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg84`] +pub mod rtc; +#[doc = "osc (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`osc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`osc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@osc`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG84 = - crate::Reg; +pub type OSC = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 84"] -pub mod aon_iomux_cfgsaif_syscfg84; -#[doc = "aon_iomux_cfgsaif_syscfg88 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg88`] +pub mod osc; +#[doc = "gmac0_mdc (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_mdc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_mdc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_mdc`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG88 = - crate::Reg; +pub type GMAC0_MDC = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 88"] -pub mod aon_iomux_cfgsaif_syscfg88; -#[doc = "aon_iomux_cfgsaif_syscfg92 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg92`] +pub mod gmac0_mdc; +#[doc = "gmac0_mdio (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_mdio::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_mdio::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_mdio`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG92 = - crate::Reg; +pub type GMAC0_MDIO = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 92"] -pub mod aon_iomux_cfgsaif_syscfg92; -#[doc = "aon_iomux_cfgsaif_syscfg96 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg96`] +pub mod gmac0_mdio; +#[doc = "gmac0_rxd0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxd0`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG96 = - crate::Reg; +pub type GMAC0_RXD0 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 96"] -pub mod aon_iomux_cfgsaif_syscfg96; -#[doc = "aon_iomux_cfgsaif_syscfg100 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg100`] +pub mod gmac0_rxd0; +#[doc = "gmac0_rxd1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxd1`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG100 = - crate::Reg; +pub type GMAC0_RXD1 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 100"] -pub mod aon_iomux_cfgsaif_syscfg100; -#[doc = "aon_iomux_cfgsaif_syscfg104 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg104`] +pub mod gmac0_rxd1; +#[doc = "gmac0_rxd2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxd2`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG104 = - crate::Reg; +pub type GMAC0_RXD2 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 104"] -pub mod aon_iomux_cfgsaif_syscfg104; -#[doc = "aon_iomux_cfgsaif_syscfg108 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg108`] +pub mod gmac0_rxd2; +#[doc = "gmac0_rxd3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxd3`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG108 = - crate::Reg; +pub type GMAC0_RXD3 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 108"] -pub mod aon_iomux_cfgsaif_syscfg108; -#[doc = "aon_iomux_cfgsaif_syscfg112 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg112`] +pub mod gmac0_rxd3; +#[doc = "gmac0_rxdv (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxdv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxdv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxdv`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG112 = - crate::Reg; +pub type GMAC0_RXDV = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 112"] -pub mod aon_iomux_cfgsaif_syscfg112; -#[doc = "aon_iomux_cfgsaif_syscfg116 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg116`] +pub mod gmac0_rxdv; +#[doc = "gmac0_rxc (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxc`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG116 = - crate::Reg; +pub type GMAC0_RXC = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 116"] -pub mod aon_iomux_cfgsaif_syscfg116; -#[doc = "aon_iomux_cfgsaif_syscfg120 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg120`] +pub mod gmac0_rxc; +#[doc = "gmac0_txd0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_txd0`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG120 = - crate::Reg; +pub type GMAC0_TXD0 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 120"] -pub mod aon_iomux_cfgsaif_syscfg120; -#[doc = "aon_iomux_cfgsaif_syscfg124 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg124`] +pub mod gmac0_txd0; +#[doc = "gmac0_txd1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_txd1`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG124 = - crate::Reg; +pub type GMAC0_TXD1 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 124"] -pub mod aon_iomux_cfgsaif_syscfg124; -#[doc = "aon_iomux_cfgsaif_syscfg128 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg128`] +pub mod gmac0_txd1; +#[doc = "gmac0_txd2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_txd2`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG128 = - crate::Reg; +pub type GMAC0_TXD2 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 128"] -pub mod aon_iomux_cfgsaif_syscfg128; -#[doc = "aon_iomux_cfgsaif_syscfg132 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg132`] +pub mod gmac0_txd2; +#[doc = "gmac0_txd3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_txd3`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG132 = - crate::Reg; +pub type GMAC0_TXD3 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 132"] -pub mod aon_iomux_cfgsaif_syscfg132; -#[doc = "aon_iomux_cfgsaif_syscfg136 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg136`] +pub mod gmac0_txd3; +#[doc = "gmac0_txen (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_txen`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG136 = - crate::Reg; +pub type GMAC0_TXEN = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 136"] -pub mod aon_iomux_cfgsaif_syscfg136; -#[doc = "aon_iomux_cfgsaif_syscfg140 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg140`] +pub mod gmac0_txen; +#[doc = "gmac0_txc (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_txc`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG140 = - crate::Reg; +pub type GMAC0_TXC = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 140"] -pub mod aon_iomux_cfgsaif_syscfg140; -#[doc = "aon_iomux_cfgsaif_syscfg144 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg144`] +pub mod gmac0_txc; +#[doc = "gmac0_rxc_func_sel (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxc_func_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxc_func_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac0_rxc_func_sel`] module"] -pub type AON_IOMUX_CFGSAIF_SYSCFG144 = - crate::Reg; +pub type GMAC0_RXC_FUNC_SEL = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 144"] -pub mod aon_iomux_cfgsaif_syscfg144; +pub mod gmac0_rxc_func_sel; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs deleted file mode 100644 index 7a6eb49..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg100` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg100` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_rxd1_syscon` reader - padcfg_pad_gmac0_rxd1_syscon"] -pub type PADCFG_PAD_GMAC0_RXD1_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_rxd1_syscon` writer - padcfg_pad_gmac0_rxd1_syscon"] -pub type PADCFG_PAD_GMAC0_RXD1_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd1_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_rxd1_syscon(&self) -> PADCFG_PAD_GMAC0_RXD1_SYSCON_R { - PADCFG_PAD_GMAC0_RXD1_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd1_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_rxd1_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_RXD1_SYSCON_W { - PADCFG_PAD_GMAC0_RXD1_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg100::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg100::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG100_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG100_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg100::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG100_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg100::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG100_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs deleted file mode 100644 index c7f5618..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg104` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg104` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_rxd2_syscon` reader - padcfg_pad_gmac0_rxd2_syscon"] -pub type PADCFG_PAD_GMAC0_RXD2_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_rxd2_syscon` writer - padcfg_pad_gmac0_rxd2_syscon"] -pub type PADCFG_PAD_GMAC0_RXD2_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd2_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_rxd2_syscon(&self) -> PADCFG_PAD_GMAC0_RXD2_SYSCON_R { - PADCFG_PAD_GMAC0_RXD2_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd2_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_rxd2_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_RXD2_SYSCON_W { - PADCFG_PAD_GMAC0_RXD2_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg104::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg104::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG104_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG104_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg104::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG104_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg104::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG104_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs deleted file mode 100644 index 31aaf9e..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg108` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg108` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_rxd3_syscon` reader - padcfg_pad_gmac0_rxd3_syscon"] -pub type PADCFG_PAD_GMAC0_RXD3_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_rxd3_syscon` writer - padcfg_pad_gmac0_rxd3_syscon"] -pub type PADCFG_PAD_GMAC0_RXD3_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd3_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_rxd3_syscon(&self) -> PADCFG_PAD_GMAC0_RXD3_SYSCON_R { - PADCFG_PAD_GMAC0_RXD3_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd3_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_rxd3_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_RXD3_SYSCON_W { - PADCFG_PAD_GMAC0_RXD3_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg108::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg108::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG108_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG108_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg108::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG108_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg108::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG108_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs deleted file mode 100644 index 7b68d46..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg112` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg112` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_rxdv_syscon` reader - padcfg_pad_gmac0_rxdv_syscon"] -pub type PADCFG_PAD_GMAC0_RXDV_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_rxdv_syscon` writer - padcfg_pad_gmac0_rxdv_syscon"] -pub type PADCFG_PAD_GMAC0_RXDV_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxdv_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_rxdv_syscon(&self) -> PADCFG_PAD_GMAC0_RXDV_SYSCON_R { - PADCFG_PAD_GMAC0_RXDV_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxdv_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_rxdv_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_RXDV_SYSCON_W { - PADCFG_PAD_GMAC0_RXDV_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg112::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg112::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG112_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG112_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg112::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG112_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg112::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG112_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs deleted file mode 100644 index 5a9c872..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg116` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg116` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_rxc_syscon` reader - padcfg_pad_gmac0_rxc_syscon"] -pub type PADCFG_PAD_GMAC0_RXC_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_rxc_syscon` writer - padcfg_pad_gmac0_rxc_syscon"] -pub type PADCFG_PAD_GMAC0_RXC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxc_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_rxc_syscon(&self) -> PADCFG_PAD_GMAC0_RXC_SYSCON_R { - PADCFG_PAD_GMAC0_RXC_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxc_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_rxc_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_RXC_SYSCON_W { - PADCFG_PAD_GMAC0_RXC_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg116::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg116::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG116_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG116_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg116::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG116_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg116::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG116_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs deleted file mode 100644 index 71a2e97..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg120` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg120` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_txd0_syscon` reader - padcfg_pad_gmac0_txd0_syscon"] -pub type PADCFG_PAD_GMAC0_TXD0_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_txd0_syscon` writer - padcfg_pad_gmac0_txd0_syscon"] -pub type PADCFG_PAD_GMAC0_TXD0_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd0_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_txd0_syscon(&self) -> PADCFG_PAD_GMAC0_TXD0_SYSCON_R { - PADCFG_PAD_GMAC0_TXD0_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd0_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_txd0_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_TXD0_SYSCON_W { - PADCFG_PAD_GMAC0_TXD0_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg120::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg120::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG120_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG120_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg120::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG120_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg120::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG120_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs deleted file mode 100644 index dda00ba..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg124` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg124` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_txd1_syscon` reader - padcfg_pad_gmac0_txd1_syscon"] -pub type PADCFG_PAD_GMAC0_TXD1_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_txd1_syscon` writer - padcfg_pad_gmac0_txd1_syscon"] -pub type PADCFG_PAD_GMAC0_TXD1_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd1_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_txd1_syscon(&self) -> PADCFG_PAD_GMAC0_TXD1_SYSCON_R { - PADCFG_PAD_GMAC0_TXD1_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd1_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_txd1_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_TXD1_SYSCON_W { - PADCFG_PAD_GMAC0_TXD1_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg124::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg124::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG124_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG124_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg124::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG124_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg124::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG124_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs deleted file mode 100644 index 18bc4c0..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg128` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg128` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_txd2_syscon` reader - padcfg_pad_gmac0_txd2_syscon"] -pub type PADCFG_PAD_GMAC0_TXD2_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_txd2_syscon` writer - padcfg_pad_gmac0_txd2_syscon"] -pub type PADCFG_PAD_GMAC0_TXD2_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd2_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_txd2_syscon(&self) -> PADCFG_PAD_GMAC0_TXD2_SYSCON_R { - PADCFG_PAD_GMAC0_TXD2_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd2_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_txd2_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_TXD2_SYSCON_W { - PADCFG_PAD_GMAC0_TXD2_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg128::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg128::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG128_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG128_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg128::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG128_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg128::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG128_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs deleted file mode 100644 index b8888c2..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg132` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg132` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_txd3_syscon` reader - padcfg_pad_gmac0_txd3_syscon"] -pub type PADCFG_PAD_GMAC0_TXD3_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_txd3_syscon` writer - padcfg_pad_gmac0_txd3_syscon"] -pub type PADCFG_PAD_GMAC0_TXD3_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd3_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_txd3_syscon(&self) -> PADCFG_PAD_GMAC0_TXD3_SYSCON_R { - PADCFG_PAD_GMAC0_TXD3_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd3_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_txd3_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_TXD3_SYSCON_W { - PADCFG_PAD_GMAC0_TXD3_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg132::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg132::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG132_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG132_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg132::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG132_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg132::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG132_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs deleted file mode 100644 index 1423c0e..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg136` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg136` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_txen_syscon` reader - padcfg_pad_gmac0_txen_syscon"] -pub type PADCFG_PAD_GMAC0_TXEN_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_txen_syscon` writer - padcfg_pad_gmac0_txen_syscon"] -pub type PADCFG_PAD_GMAC0_TXEN_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txen_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_txen_syscon(&self) -> PADCFG_PAD_GMAC0_TXEN_SYSCON_R { - PADCFG_PAD_GMAC0_TXEN_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txen_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_txen_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_TXEN_SYSCON_W { - PADCFG_PAD_GMAC0_TXEN_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg136::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg136::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG136_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG136_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg136::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG136_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg136::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG136_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs deleted file mode 100644 index 3328694..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg140` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg140` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_txc_syscon` reader - padcfg_pad_gmac0_txc_syscon"] -pub type PADCFG_PAD_GMAC0_TXC_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_txc_syscon` writer - padcfg_pad_gmac0_txc_syscon"] -pub type PADCFG_PAD_GMAC0_TXC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txc_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_txc_syscon(&self) -> PADCFG_PAD_GMAC0_TXC_SYSCON_R { - PADCFG_PAD_GMAC0_TXC_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_txc_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_txc_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_TXC_SYSCON_W { - PADCFG_PAD_GMAC0_TXC_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg140::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg140::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG140_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG140_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg140::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG140_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg140::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG140_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs deleted file mode 100644 index 4e9cfe6..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg144` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg144` writer"] -pub type W = crate::W; -#[doc = "Field `pad_gmac0_rxc_func_sel` reader - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] -pub type PAD_GMAC0_RXC_FUNC_SEL_R = crate::FieldReader; -#[doc = "Field `pad_gmac0_rxc_func_sel` writer - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] -pub type PAD_GMAC0_RXC_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] - #[inline(always)] - pub fn pad_gmac0_rxc_func_sel(&self) -> PAD_GMAC0_RXC_FUNC_SEL_R { - PAD_GMAC0_RXC_FUNC_SEL_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] - #[inline(always)] - #[must_use] - pub fn pad_gmac0_rxc_func_sel( - &mut self, - ) -> PAD_GMAC0_RXC_FUNC_SEL_W { - PAD_GMAC0_RXC_FUNC_SEL_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg144::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg144::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG144_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG144_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg144::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG144_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg144::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG144_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs deleted file mode 100644 index 6e37db2..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg48` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg48` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_testen_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_TESTEN_POS_R = crate::BitReader; -#[doc = "Field `padcfg_pad_testen_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_TESTEN_POS_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - pub fn padcfg_pad_testen_pos(&self) -> PADCFG_PAD_TESTEN_POS_R { - PADCFG_PAD_TESTEN_POS_R::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_testen_pos( - &mut self, - ) -> PADCFG_PAD_TESTEN_POS_W { - PADCFG_PAD_TESTEN_POS_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg48::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg48::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG48_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG48_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg48::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG48_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg48::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG48_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs deleted file mode 100644 index e6eee84..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs +++ /dev/null @@ -1,149 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg52` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg52` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_rgpio0_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO0_IE_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio0_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO0_IE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio0_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO0_DS_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_rgpio0_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO0_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `padcfg_pad_rgpio0_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO0_PU_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio0_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO0_PU_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio0_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO0_PD_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio0_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO0_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio0_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO0_SLEW_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio0_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO0_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio0_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO0_SMT_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio0_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO0_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio0_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO0_POS_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio0_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO0_POS_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_ie(&self) -> PADCFG_PAD_RGPIO0_IE_R { - PADCFG_PAD_RGPIO0_IE_R::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_ds(&self) -> PADCFG_PAD_RGPIO0_DS_R { - PADCFG_PAD_RGPIO0_DS_R::new(((self.bits >> 1) & 3) as u8) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_pu(&self) -> PADCFG_PAD_RGPIO0_PU_R { - PADCFG_PAD_RGPIO0_PU_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_pd(&self) -> PADCFG_PAD_RGPIO0_PD_R { - PADCFG_PAD_RGPIO0_PD_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_slew(&self) -> PADCFG_PAD_RGPIO0_SLEW_R { - PADCFG_PAD_RGPIO0_SLEW_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_smt(&self) -> PADCFG_PAD_RGPIO0_SMT_R { - PADCFG_PAD_RGPIO0_SMT_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio0_pos(&self) -> PADCFG_PAD_RGPIO0_POS_R { - PADCFG_PAD_RGPIO0_POS_R::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_ie( - &mut self, - ) -> PADCFG_PAD_RGPIO0_IE_W { - PADCFG_PAD_RGPIO0_IE_W::new(self, 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_ds( - &mut self, - ) -> PADCFG_PAD_RGPIO0_DS_W { - PADCFG_PAD_RGPIO0_DS_W::new(self, 1) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_pu( - &mut self, - ) -> PADCFG_PAD_RGPIO0_PU_W { - PADCFG_PAD_RGPIO0_PU_W::new(self, 3) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_pd( - &mut self, - ) -> PADCFG_PAD_RGPIO0_PD_W { - PADCFG_PAD_RGPIO0_PD_W::new(self, 4) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_slew( - &mut self, - ) -> PADCFG_PAD_RGPIO0_SLEW_W { - PADCFG_PAD_RGPIO0_SLEW_W::new(self, 5) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_smt( - &mut self, - ) -> PADCFG_PAD_RGPIO0_SMT_W { - PADCFG_PAD_RGPIO0_SMT_W::new(self, 6) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio0_pos( - &mut self, - ) -> PADCFG_PAD_RGPIO0_POS_W { - PADCFG_PAD_RGPIO0_POS_W::new(self, 7) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg52::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg52::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG52_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG52_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg52::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG52_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg52::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG52_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs deleted file mode 100644 index e4df2d1..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs +++ /dev/null @@ -1,149 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg56` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg56` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_rgpio1_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO1_IE_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio1_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO1_IE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio1_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO1_DS_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_rgpio1_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO1_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `padcfg_pad_rgpio1_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO1_PU_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio1_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO1_PU_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio1_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO1_PD_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio1_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO1_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio1_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO1_SLEW_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio1_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO1_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio1_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO1_SMT_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio1_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO1_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio1_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO1_POS_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio1_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO1_POS_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_ie(&self) -> PADCFG_PAD_RGPIO1_IE_R { - PADCFG_PAD_RGPIO1_IE_R::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_ds(&self) -> PADCFG_PAD_RGPIO1_DS_R { - PADCFG_PAD_RGPIO1_DS_R::new(((self.bits >> 1) & 3) as u8) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_pu(&self) -> PADCFG_PAD_RGPIO1_PU_R { - PADCFG_PAD_RGPIO1_PU_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_pd(&self) -> PADCFG_PAD_RGPIO1_PD_R { - PADCFG_PAD_RGPIO1_PD_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_slew(&self) -> PADCFG_PAD_RGPIO1_SLEW_R { - PADCFG_PAD_RGPIO1_SLEW_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_smt(&self) -> PADCFG_PAD_RGPIO1_SMT_R { - PADCFG_PAD_RGPIO1_SMT_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio1_pos(&self) -> PADCFG_PAD_RGPIO1_POS_R { - PADCFG_PAD_RGPIO1_POS_R::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_ie( - &mut self, - ) -> PADCFG_PAD_RGPIO1_IE_W { - PADCFG_PAD_RGPIO1_IE_W::new(self, 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_ds( - &mut self, - ) -> PADCFG_PAD_RGPIO1_DS_W { - PADCFG_PAD_RGPIO1_DS_W::new(self, 1) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_pu( - &mut self, - ) -> PADCFG_PAD_RGPIO1_PU_W { - PADCFG_PAD_RGPIO1_PU_W::new(self, 3) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_pd( - &mut self, - ) -> PADCFG_PAD_RGPIO1_PD_W { - PADCFG_PAD_RGPIO1_PD_W::new(self, 4) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_slew( - &mut self, - ) -> PADCFG_PAD_RGPIO1_SLEW_W { - PADCFG_PAD_RGPIO1_SLEW_W::new(self, 5) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_smt( - &mut self, - ) -> PADCFG_PAD_RGPIO1_SMT_W { - PADCFG_PAD_RGPIO1_SMT_W::new(self, 6) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio1_pos( - &mut self, - ) -> PADCFG_PAD_RGPIO1_POS_W { - PADCFG_PAD_RGPIO1_POS_W::new(self, 7) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg56::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg56::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG56_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG56_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg56::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG56_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg56::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG56_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs deleted file mode 100644 index 5a6586e..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs +++ /dev/null @@ -1,149 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg60` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg60` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_rgpio2_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO2_IE_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio2_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO2_IE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio2_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO2_DS_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_rgpio2_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO2_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `padcfg_pad_rgpio2_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO2_PU_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio2_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO2_PU_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio2_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO2_PD_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio2_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO2_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio2_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO2_SLEW_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio2_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO2_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio2_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO2_SMT_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio2_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO2_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio2_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO2_POS_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio2_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO2_POS_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_ie(&self) -> PADCFG_PAD_RGPIO2_IE_R { - PADCFG_PAD_RGPIO2_IE_R::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_ds(&self) -> PADCFG_PAD_RGPIO2_DS_R { - PADCFG_PAD_RGPIO2_DS_R::new(((self.bits >> 1) & 3) as u8) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_pu(&self) -> PADCFG_PAD_RGPIO2_PU_R { - PADCFG_PAD_RGPIO2_PU_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_pd(&self) -> PADCFG_PAD_RGPIO2_PD_R { - PADCFG_PAD_RGPIO2_PD_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_slew(&self) -> PADCFG_PAD_RGPIO2_SLEW_R { - PADCFG_PAD_RGPIO2_SLEW_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_smt(&self) -> PADCFG_PAD_RGPIO2_SMT_R { - PADCFG_PAD_RGPIO2_SMT_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio2_pos(&self) -> PADCFG_PAD_RGPIO2_POS_R { - PADCFG_PAD_RGPIO2_POS_R::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_ie( - &mut self, - ) -> PADCFG_PAD_RGPIO2_IE_W { - PADCFG_PAD_RGPIO2_IE_W::new(self, 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_ds( - &mut self, - ) -> PADCFG_PAD_RGPIO2_DS_W { - PADCFG_PAD_RGPIO2_DS_W::new(self, 1) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_pu( - &mut self, - ) -> PADCFG_PAD_RGPIO2_PU_W { - PADCFG_PAD_RGPIO2_PU_W::new(self, 3) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_pd( - &mut self, - ) -> PADCFG_PAD_RGPIO2_PD_W { - PADCFG_PAD_RGPIO2_PD_W::new(self, 4) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_slew( - &mut self, - ) -> PADCFG_PAD_RGPIO2_SLEW_W { - PADCFG_PAD_RGPIO2_SLEW_W::new(self, 5) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_smt( - &mut self, - ) -> PADCFG_PAD_RGPIO2_SMT_W { - PADCFG_PAD_RGPIO2_SMT_W::new(self, 6) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio2_pos( - &mut self, - ) -> PADCFG_PAD_RGPIO2_POS_W { - PADCFG_PAD_RGPIO2_POS_W::new(self, 7) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg60::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg60::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG60_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG60_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg60::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG60_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg60::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG60_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs deleted file mode 100644 index 8dfbee5..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs +++ /dev/null @@ -1,149 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg64` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg64` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_rgpio3_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO3_IE_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio3_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO3_IE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio3_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO3_DS_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_rgpio3_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO3_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `padcfg_pad_rgpio3_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO3_PU_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio3_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO3_PU_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio3_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO3_PD_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio3_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO3_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio3_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO3_SLEW_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio3_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO3_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio3_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO3_SMT_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio3_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO3_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rgpio3_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO3_POS_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rgpio3_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO3_POS_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_ie(&self) -> PADCFG_PAD_RGPIO3_IE_R { - PADCFG_PAD_RGPIO3_IE_R::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_ds(&self) -> PADCFG_PAD_RGPIO3_DS_R { - PADCFG_PAD_RGPIO3_DS_R::new(((self.bits >> 1) & 3) as u8) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_pu(&self) -> PADCFG_PAD_RGPIO3_PU_R { - PADCFG_PAD_RGPIO3_PU_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_pd(&self) -> PADCFG_PAD_RGPIO3_PD_R { - PADCFG_PAD_RGPIO3_PD_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_slew(&self) -> PADCFG_PAD_RGPIO3_SLEW_R { - PADCFG_PAD_RGPIO3_SLEW_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_smt(&self) -> PADCFG_PAD_RGPIO3_SMT_R { - PADCFG_PAD_RGPIO3_SMT_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - pub fn padcfg_pad_rgpio3_pos(&self) -> PADCFG_PAD_RGPIO3_POS_R { - PADCFG_PAD_RGPIO3_POS_R::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_ie( - &mut self, - ) -> PADCFG_PAD_RGPIO3_IE_W { - PADCFG_PAD_RGPIO3_IE_W::new(self, 0) - } - #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_ds( - &mut self, - ) -> PADCFG_PAD_RGPIO3_DS_W { - PADCFG_PAD_RGPIO3_DS_W::new(self, 1) - } - #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_pu( - &mut self, - ) -> PADCFG_PAD_RGPIO3_PU_W { - PADCFG_PAD_RGPIO3_PU_W::new(self, 3) - } - #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_pd( - &mut self, - ) -> PADCFG_PAD_RGPIO3_PD_W { - PADCFG_PAD_RGPIO3_PD_W::new(self, 4) - } - #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_slew( - &mut self, - ) -> PADCFG_PAD_RGPIO3_SLEW_W { - PADCFG_PAD_RGPIO3_SLEW_W::new(self, 5) - } - #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_smt( - &mut self, - ) -> PADCFG_PAD_RGPIO3_SMT_W { - PADCFG_PAD_RGPIO3_SMT_W::new(self, 6) - } - #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rgpio3_pos( - &mut self, - ) -> PADCFG_PAD_RGPIO3_POS_W { - PADCFG_PAD_RGPIO3_POS_W::new(self, 7) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg64::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg64::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG64_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG64_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg64::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG64_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg64::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG64_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs deleted file mode 100644 index 6c5a65b..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs +++ /dev/null @@ -1,64 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg68` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg68` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_rstn_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] -pub type PADCFG_PAD_RSTN_SMT_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rstn_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] -pub type PADCFG_PAD_RSTN_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `padcfg_pad_rstn_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RSTN_POS_R = crate::BitReader; -#[doc = "Field `padcfg_pad_rstn_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RSTN_POS_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] - #[inline(always)] - pub fn padcfg_pad_rstn_smt(&self) -> PADCFG_PAD_RSTN_SMT_R { - PADCFG_PAD_RSTN_SMT_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - pub fn padcfg_pad_rstn_pos(&self) -> PADCFG_PAD_RSTN_POS_R { - PADCFG_PAD_RSTN_POS_R::new(((self.bits >> 1) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rstn_smt( - &mut self, - ) -> PADCFG_PAD_RSTN_SMT_W { - PADCFG_PAD_RSTN_SMT_W::new(self, 0) - } - #[doc = "Bit 1 - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rstn_pos( - &mut self, - ) -> PADCFG_PAD_RSTN_POS_W { - PADCFG_PAD_RSTN_POS_W::new(self, 1) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg68::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg68::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG68_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG68_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg68::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG68_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg68::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG68_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs deleted file mode 100644 index 452613c..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs +++ /dev/null @@ -1,45 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg76` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg76` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_rtc_ds` reader - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] -pub type PADCFG_PAD_RTC_DS_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_rtc_ds` writer - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] -pub type PADCFG_PAD_RTC_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] - #[inline(always)] - pub fn padcfg_pad_rtc_ds(&self) -> PADCFG_PAD_RTC_DS_R { - PADCFG_PAD_RTC_DS_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_rtc_ds(&mut self) -> PADCFG_PAD_RTC_DS_W { - PADCFG_PAD_RTC_DS_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg76::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg76::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG76_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG76_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg76::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG76_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg76::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG76_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs deleted file mode 100644 index 067aebb..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs +++ /dev/null @@ -1,45 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg84` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg84` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_osc_ds` reader - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] -pub type PADCFG_PAD_OSC_DS_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_osc_ds` writer - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] -pub type PADCFG_PAD_OSC_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] - #[inline(always)] - pub fn padcfg_pad_osc_ds(&self) -> PADCFG_PAD_OSC_DS_R { - PADCFG_PAD_OSC_DS_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_osc_ds(&mut self) -> PADCFG_PAD_OSC_DS_W { - PADCFG_PAD_OSC_DS_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg84::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg84::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG84_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG84_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg84::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG84_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg84::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG84_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs deleted file mode 100644 index f744712..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg88` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg88` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_mdc_syscon` reader - padcfg_pad_gmac0_mdc_syscon"] -pub type PADCFG_PAD_GMAC0_MDC_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_mdc_syscon` writer - padcfg_pad_gmac0_mdc_syscon"] -pub type PADCFG_PAD_GMAC0_MDC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_mdc_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_mdc_syscon(&self) -> PADCFG_PAD_GMAC0_MDC_SYSCON_R { - PADCFG_PAD_GMAC0_MDC_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_mdc_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_mdc_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_MDC_SYSCON_W { - PADCFG_PAD_GMAC0_MDC_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg88::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg88::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG88_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG88_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg88::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG88_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg88::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG88_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs deleted file mode 100644 index fd12b7e..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg92` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg92` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_mdio_syscon` reader - padcfg_pad_gmac0_mdio_syscon"] -pub type PADCFG_PAD_GMAC0_MDIO_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_mdio_syscon` writer - padcfg_pad_gmac0_mdio_syscon"] -pub type PADCFG_PAD_GMAC0_MDIO_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_mdio_syscon"] - #[inline(always)] - pub fn padcfg_pad_gmac0_mdio_syscon(&self) -> PADCFG_PAD_GMAC0_MDIO_SYSCON_R { - PADCFG_PAD_GMAC0_MDIO_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - padcfg_pad_gmac0_mdio_syscon"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_mdio_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_MDIO_SYSCON_W { - PADCFG_PAD_GMAC0_MDIO_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg92::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg92::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG92_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG92_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg92::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG92_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg92::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG92_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs deleted file mode 100644 index 3f8dabd..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg96` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg96` writer"] -pub type W = crate::W; -#[doc = "Field `padcfg_pad_gmac0_rxd0_syscon` reader - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] -pub type PADCFG_PAD_GMAC0_RXD0_SYSCON_R = crate::FieldReader; -#[doc = "Field `padcfg_pad_gmac0_rxd0_syscon` writer - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] -pub type PADCFG_PAD_GMAC0_RXD0_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] - #[inline(always)] - pub fn padcfg_pad_gmac0_rxd0_syscon(&self) -> PADCFG_PAD_GMAC0_RXD0_SYSCON_R { - PADCFG_PAD_GMAC0_RXD0_SYSCON_R::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] - #[inline(always)] - #[must_use] - pub fn padcfg_pad_gmac0_rxd0_syscon( - &mut self, - ) -> PADCFG_PAD_GMAC0_RXD0_SYSCON_W { - PADCFG_PAD_GMAC0_RXD0_SYSCON_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg96::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg96::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG96_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG96_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg96::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG96_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg96::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG96_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs deleted file mode 100644 index 1bb9c0c..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux0` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux0` writer"] -pub type W = crate::W; -#[doc = "Field `aon_iomux_gpo0_doen_cfg` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO0_DOEN_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo0_doen_cfg` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO0_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `aon_iomux_gpo1_doen_cfg` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO1_DOEN_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo1_doen_cfg` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO1_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `aon_iomux_gpo2_doen_cfg` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO2_DOEN_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo2_doen_cfg` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO2_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `aon_iomux_gpo3_doen_cfg` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO3_DOEN_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo3_doen_cfg` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO3_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:2 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo0_doen_cfg(&self) -> AON_IOMUX_GPO0_DOEN_CFG_R { - AON_IOMUX_GPO0_DOEN_CFG_R::new((self.bits & 7) as u8) - } - #[doc = "Bits 8:10 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo1_doen_cfg(&self) -> AON_IOMUX_GPO1_DOEN_CFG_R { - AON_IOMUX_GPO1_DOEN_CFG_R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 16:18 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo2_doen_cfg(&self) -> AON_IOMUX_GPO2_DOEN_CFG_R { - AON_IOMUX_GPO2_DOEN_CFG_R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bits 24:26 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo3_doen_cfg(&self) -> AON_IOMUX_GPO3_DOEN_CFG_R { - AON_IOMUX_GPO3_DOEN_CFG_R::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo0_doen_cfg( - &mut self, - ) -> AON_IOMUX_GPO0_DOEN_CFG_W { - AON_IOMUX_GPO0_DOEN_CFG_W::new(self, 0) - } - #[doc = "Bits 8:10 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo1_doen_cfg( - &mut self, - ) -> AON_IOMUX_GPO1_DOEN_CFG_W { - AON_IOMUX_GPO1_DOEN_CFG_W::new(self, 8) - } - #[doc = "Bits 16:18 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo2_doen_cfg( - &mut self, - ) -> AON_IOMUX_GPO2_DOEN_CFG_W { - AON_IOMUX_GPO2_DOEN_CFG_W::new(self, 16) - } - #[doc = "Bits 24:26 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo3_doen_cfg( - &mut self, - ) -> AON_IOMUX_GPO3_DOEN_CFG_W { - AON_IOMUX_GPO3_DOEN_CFG_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_FMUX0_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_FMUX0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_fmux0::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_fmux0::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs deleted file mode 100644 index 045b180..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux1` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux1` writer"] -pub type W = crate::W; -#[doc = "Field `aon_iomux_gpo0_dout_cfg` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO0_DOUT_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo0_dout_cfg` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO0_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `aon_iomux_gpo1_dout_cfg` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO1_DOUT_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo1_dout_cfg` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO1_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `aon_iomux_gpo2_dout_cfg` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO2_DOUT_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo2_dout_cfg` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO2_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `aon_iomux_gpo3_dout_cfg` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO3_DOUT_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpo3_dout_cfg` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO3_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo0_dout_cfg(&self) -> AON_IOMUX_GPO0_DOUT_CFG_R { - AON_IOMUX_GPO0_DOUT_CFG_R::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 8:11 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo1_dout_cfg(&self) -> AON_IOMUX_GPO1_DOUT_CFG_R { - AON_IOMUX_GPO1_DOUT_CFG_R::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 16:19 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo2_dout_cfg(&self) -> AON_IOMUX_GPO2_DOUT_CFG_R { - AON_IOMUX_GPO2_DOUT_CFG_R::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 24:27 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - pub fn aon_iomux_gpo3_dout_cfg(&self) -> AON_IOMUX_GPO3_DOUT_CFG_R { - AON_IOMUX_GPO3_DOUT_CFG_R::new(((self.bits >> 24) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo0_dout_cfg( - &mut self, - ) -> AON_IOMUX_GPO0_DOUT_CFG_W { - AON_IOMUX_GPO0_DOUT_CFG_W::new(self, 0) - } - #[doc = "Bits 8:11 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo1_dout_cfg( - &mut self, - ) -> AON_IOMUX_GPO1_DOUT_CFG_W { - AON_IOMUX_GPO1_DOUT_CFG_W::new(self, 8) - } - #[doc = "Bits 16:19 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo2_dout_cfg( - &mut self, - ) -> AON_IOMUX_GPO2_DOUT_CFG_W { - AON_IOMUX_GPO2_DOUT_CFG_W::new(self, 16) - } - #[doc = "Bits 24:27 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpo3_dout_cfg( - &mut self, - ) -> AON_IOMUX_GPO3_DOUT_CFG_W { - AON_IOMUX_GPO3_DOUT_CFG_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_FMUX1_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_FMUX1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_fmux1::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_fmux1::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs deleted file mode 100644 index a8f9ba4..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs +++ /dev/null @@ -1,114 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux2` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux2` writer"] -pub type W = crate::W; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W<'a, REG> = - crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W<'a, REG> = - crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W<'a, REG> = - crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_R = crate::FieldReader; -#[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W<'a, REG> = - crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:2 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg( - &self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_R { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_R::new((self.bits & 7) as u8) - } - #[doc = "Bits 8:10 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg( - &self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_R { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 16:18 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg( - &self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_R { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bits 24:26 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg( - &self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_R { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_R::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg( - &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W - { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W::new(self, 0) - } - #[doc = "Bits 8:10 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg( - &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W - { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W::new(self, 8) - } - #[doc = "Bits 16:18 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg( - &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W - { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W::new(self, 16) - } - #[doc = "Bits 24:26 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] - #[inline(always)] - #[must_use] - pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg( - &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W - { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_fmux2::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_fmux2::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs deleted file mode 100644 index 94cc018..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs +++ /dev/null @@ -1,45 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux3` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_fmux3` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpioen_0_reg` reader - Enable GPIO IRQ function."] -pub type AON_GPIOEN_0_REG_R = crate::BitReader; -#[doc = "Field `aon_gpioen_0_reg` writer - Enable GPIO IRQ function."] -pub type AON_GPIOEN_0_REG_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Enable GPIO IRQ function."] - #[inline(always)] - pub fn aon_gpioen_0_reg(&self) -> AON_GPIOEN_0_REG_R { - AON_GPIOEN_0_REG_R::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Enable GPIO IRQ function."] - #[inline(always)] - #[must_use] - pub fn aon_gpioen_0_reg(&mut self) -> AON_GPIOEN_0_REG_W { - AON_GPIOEN_0_REG_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_FMUX3_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_FMUX3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_fmux3::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_fmux3::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_FMUX3_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs deleted file mode 100644 index 71d7011..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq10` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq10` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpiomis_0_reg` reader - The masked GPIO IRQ status."] -pub type AON_GPIOMIS_0_REG_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - The masked GPIO IRQ status."] - #[inline(always)] - pub fn aon_gpiomis_0_reg(&self) -> AON_GPIOMIS_0_REG_R { - AON_GPIOMIS_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq10::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq10::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq10::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs deleted file mode 100644 index 6e7f217..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq11` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq11` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpio_in_sync2_0_reg` reader - Status of gpio_in after synchronization."] -pub type AON_GPIO_IN_SYNC2_0_REG_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Status of gpio_in after synchronization."] - #[inline(always)] - pub fn aon_gpio_in_sync2_0_reg(&self) -> AON_GPIO_IN_SYNC2_0_REG_R { - AON_GPIO_IN_SYNC2_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq11::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq11::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq11::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs deleted file mode 100644 index f984d07..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs +++ /dev/null @@ -1,45 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq4` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq4` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpiois_0_reg` reader - 1: Edge trigger, 0: Level trigger"] -pub type AON_GPIOIS_0_REG_R = crate::FieldReader; -#[doc = "Field `aon_gpiois_0_reg` writer - 1: Edge trigger, 0: Level trigger"] -pub type AON_GPIOIS_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - 1: Edge trigger, 0: Level trigger"] - #[inline(always)] - pub fn aon_gpiois_0_reg(&self) -> AON_GPIOIS_0_REG_R { - AON_GPIOIS_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - 1: Edge trigger, 0: Level trigger"] - #[inline(always)] - #[must_use] - pub fn aon_gpiois_0_reg(&mut self) -> AON_GPIOIS_0_REG_W { - AON_GPIOIS_0_REG_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq4::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq4::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq4::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs deleted file mode 100644 index 91bc1c3..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs +++ /dev/null @@ -1,45 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq5` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq5` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpioic_0_reg` reader - 1: Do not clear the register, 0: Clear the register"] -pub type AON_GPIOIC_0_REG_R = crate::FieldReader; -#[doc = "Field `aon_gpioic_0_reg` writer - 1: Do not clear the register, 0: Clear the register"] -pub type AON_GPIOIC_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - 1: Do not clear the register, 0: Clear the register"] - #[inline(always)] - pub fn aon_gpioic_0_reg(&self) -> AON_GPIOIC_0_REG_R { - AON_GPIOIC_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - 1: Do not clear the register, 0: Clear the register"] - #[inline(always)] - #[must_use] - pub fn aon_gpioic_0_reg(&mut self) -> AON_GPIOIC_0_REG_W { - AON_GPIOIC_0_REG_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq5::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq5::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq5::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs deleted file mode 100644 index 925eb89..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq6` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq6` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpioibe_0_reg` reader - 1: Trigger on both edges, 0: Trigger on a single edge"] -pub type AON_GPIOIBE_0_REG_R = crate::FieldReader; -#[doc = "Field `aon_gpioibe_0_reg` writer - 1: Trigger on both edges, 0: Trigger on a single edge"] -pub type AON_GPIOIBE_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - 1: Trigger on both edges, 0: Trigger on a single edge"] - #[inline(always)] - pub fn aon_gpioibe_0_reg(&self) -> AON_GPIOIBE_0_REG_R { - AON_GPIOIBE_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - 1: Trigger on both edges, 0: Trigger on a single edge"] - #[inline(always)] - #[must_use] - pub fn aon_gpioibe_0_reg( - &mut self, - ) -> AON_GPIOIBE_0_REG_W { - AON_GPIOIBE_0_REG_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq6::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq6::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq6::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs deleted file mode 100644 index 353765a..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq7` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq7` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpioiev_0_reg` reader - 1: Positive/Low, 0: Negative/High"] -pub type AON_GPIOIEV_0_REG_R = crate::FieldReader; -#[doc = "Field `aon_gpioiev_0_reg` writer - 1: Positive/Low, 0: Negative/High"] -pub type AON_GPIOIEV_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - 1: Positive/Low, 0: Negative/High"] - #[inline(always)] - pub fn aon_gpioiev_0_reg(&self) -> AON_GPIOIEV_0_REG_R { - AON_GPIOIEV_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - 1: Positive/Low, 0: Negative/High"] - #[inline(always)] - #[must_use] - pub fn aon_gpioiev_0_reg( - &mut self, - ) -> AON_GPIOIEV_0_REG_W { - AON_GPIOIEV_0_REG_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq7::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq7::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq7::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs deleted file mode 100644 index cd46c19..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs +++ /dev/null @@ -1,45 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq8` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq8` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpioie_0_reg` reader - 1: Unmask, 0: Mask"] -pub type AON_GPIOIE_0_REG_R = crate::FieldReader; -#[doc = "Field `aon_gpioie_0_reg` writer - 1: Unmask, 0: Mask"] -pub type AON_GPIOIE_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - 1: Unmask, 0: Mask"] - #[inline(always)] - pub fn aon_gpioie_0_reg(&self) -> AON_GPIOIE_0_REG_R { - AON_GPIOIE_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - 1: Unmask, 0: Mask"] - #[inline(always)] - #[must_use] - pub fn aon_gpioie_0_reg(&mut self) -> AON_GPIOIE_0_REG_W { - AON_GPIOIE_0_REG_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq8::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq8::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq8::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs deleted file mode 100644 index 72caae7..0000000 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq9` reader"] -pub type R = crate::R; -#[doc = "Register `aon_iomux_cfgsaif_syscfg_ioirq9` writer"] -pub type W = crate::W; -#[doc = "Field `aon_gpioris_0_reg` reader - Status of the edge trigger, can be cleared by writing gpioic."] -pub type AON_GPIORIS_0_REG_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Status of the edge trigger, can be cleared by writing gpioic."] - #[inline(always)] - pub fn aon_gpioris_0_reg(&self) -> AON_GPIORIS_0_REG_R { - AON_GPIORIS_0_REG_R::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq9::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9_SPEC; -impl crate::RegisterSpec for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`aon_iomux_cfgsaif_syscfg_ioirq9::R`](R) reader structure"] -impl crate::Readable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9_SPEC {} -#[doc = "`write(|w| ..)` method takes [`aon_iomux_cfgsaif_syscfg_ioirq9::W`](W) writer structure"] -impl crate::Writable for AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_0.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_0.rs new file mode 100644 index 0000000..2d9da31 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_0.rs @@ -0,0 +1,94 @@ +#[doc = "Register `fmux_0` reader"] +pub type R = crate::R; +#[doc = "Register `fmux_0` writer"] +pub type W = crate::W; +#[doc = "Field `gpo_doen_0` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_0_R = crate::FieldReader; +#[doc = "Field `gpo_doen_0` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `gpo_doen_1` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_1_R = crate::FieldReader; +#[doc = "Field `gpo_doen_1` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `gpo_doen_2` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_2_R = crate::FieldReader; +#[doc = "Field `gpo_doen_2` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `gpo_doen_3` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_3_R = crate::FieldReader; +#[doc = "Field `gpo_doen_3` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOEN_3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_doen_0(&self) -> GPO_DOEN_0_R { + GPO_DOEN_0_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 8:10 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_doen_1(&self) -> GPO_DOEN_1_R { + GPO_DOEN_1_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 16:18 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_doen_2(&self) -> GPO_DOEN_2_R { + GPO_DOEN_2_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 24:26 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_doen_3(&self) -> GPO_DOEN_3_R { + GPO_DOEN_3_R::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_doen_0(&mut self) -> GPO_DOEN_0_W { + GPO_DOEN_0_W::new(self, 0) + } + #[doc = "Bits 8:10 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_doen_1(&mut self) -> GPO_DOEN_1_W { + GPO_DOEN_1_W::new(self, 8) + } + #[doc = "Bits 16:18 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_doen_2(&mut self) -> GPO_DOEN_2_W { + GPO_DOEN_2_W::new(self, 16) + } + #[doc = "Bits 24:26 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_doen_3(&mut self) -> GPO_DOEN_3_W { + GPO_DOEN_3_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FMUX_0_SPEC; +impl crate::RegisterSpec for FMUX_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmux_0::R`](R) reader structure"] +impl crate::Readable for FMUX_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fmux_0::W`](W) writer structure"] +impl crate::Writable for FMUX_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets fmux_0 to value 0"] +impl crate::Resettable for FMUX_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_1.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_1.rs new file mode 100644 index 0000000..df4e9b5 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_1.rs @@ -0,0 +1,94 @@ +#[doc = "Register `fmux_1` reader"] +pub type R = crate::R; +#[doc = "Register `fmux_1` writer"] +pub type W = crate::W; +#[doc = "Field `gpo_dout_0` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_0_R = crate::FieldReader; +#[doc = "Field `gpo_dout_0` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `gpo_dout_1` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_1_R = crate::FieldReader; +#[doc = "Field `gpo_dout_1` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `gpo_dout_2` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_2_R = crate::FieldReader; +#[doc = "Field `gpo_dout_2` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `gpo_dout_3` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_3_R = crate::FieldReader; +#[doc = "Field `gpo_dout_3` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] +pub type GPO_DOUT_3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_dout_0(&self) -> GPO_DOUT_0_R { + GPO_DOUT_0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:11 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_dout_1(&self) -> GPO_DOUT_1_R { + GPO_DOUT_1_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_dout_2(&self) -> GPO_DOUT_2_R { + GPO_DOUT_2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + pub fn gpo_dout_3(&self) -> GPO_DOUT_3_R { + GPO_DOUT_3_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_dout_0(&mut self) -> GPO_DOUT_0_W { + GPO_DOUT_0_W::new(self, 0) + } + #[doc = "Bits 8:11 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_dout_1(&mut self) -> GPO_DOUT_1_W { + GPO_DOUT_1_W::new(self, 8) + } + #[doc = "Bits 16:19 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_dout_2(&mut self) -> GPO_DOUT_2_W { + GPO_DOUT_2_W::new(self, 16) + } + #[doc = "Bits 24:27 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] + #[inline(always)] + #[must_use] + pub fn gpo_dout_3(&mut self) -> GPO_DOUT_3_W { + GPO_DOUT_3_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FMUX_1_SPEC; +impl crate::RegisterSpec for FMUX_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmux_1::R`](R) reader structure"] +impl crate::Readable for FMUX_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fmux_1::W`](W) writer structure"] +impl crate::Writable for FMUX_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets fmux_1 to value 0"] +impl crate::Resettable for FMUX_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_2.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_2.rs new file mode 100644 index 0000000..d43da5a --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_2.rs @@ -0,0 +1,94 @@ +#[doc = "Register `fmux_2` reader"] +pub type R = crate::R; +#[doc = "Register `fmux_2` writer"] +pub type W = crate::W; +#[doc = "Field `gpi_pmu_wakeup_0` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_0_R = crate::FieldReader; +#[doc = "Field `gpi_pmu_wakeup_0` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `gpi_pmu_wakeup_1` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_1_R = crate::FieldReader; +#[doc = "Field `gpi_pmu_wakeup_1` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `gpi_pmu_wakeup_2` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_2_R = crate::FieldReader; +#[doc = "Field `gpi_pmu_wakeup_2` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `gpi_pmu_wakeup_3` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_3_R = crate::FieldReader; +#[doc = "Field `gpi_pmu_wakeup_3` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] +pub type GPI_PMU_WAKEUP_3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + pub fn gpi_pmu_wakeup_0(&self) -> GPI_PMU_WAKEUP_0_R { + GPI_PMU_WAKEUP_0_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 8:10 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + pub fn gpi_pmu_wakeup_1(&self) -> GPI_PMU_WAKEUP_1_R { + GPI_PMU_WAKEUP_1_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 16:18 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + pub fn gpi_pmu_wakeup_2(&self) -> GPI_PMU_WAKEUP_2_R { + GPI_PMU_WAKEUP_2_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 24:26 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + pub fn gpi_pmu_wakeup_3(&self) -> GPI_PMU_WAKEUP_3_R { + GPI_PMU_WAKEUP_3_R::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + #[must_use] + pub fn gpi_pmu_wakeup_0(&mut self) -> GPI_PMU_WAKEUP_0_W { + GPI_PMU_WAKEUP_0_W::new(self, 0) + } + #[doc = "Bits 8:10 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + #[must_use] + pub fn gpi_pmu_wakeup_1(&mut self) -> GPI_PMU_WAKEUP_1_W { + GPI_PMU_WAKEUP_1_W::new(self, 8) + } + #[doc = "Bits 16:18 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + #[must_use] + pub fn gpi_pmu_wakeup_2(&mut self) -> GPI_PMU_WAKEUP_2_W { + GPI_PMU_WAKEUP_2_W::new(self, 16) + } + #[doc = "Bits 24:26 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] + #[inline(always)] + #[must_use] + pub fn gpi_pmu_wakeup_3(&mut self) -> GPI_PMU_WAKEUP_3_W { + GPI_PMU_WAKEUP_3_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FMUX_2_SPEC; +impl crate::RegisterSpec for FMUX_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmux_2::R`](R) reader structure"] +impl crate::Readable for FMUX_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fmux_2::W`](W) writer structure"] +impl crate::Writable for FMUX_2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets fmux_2 to value 0"] +impl crate::Resettable for FMUX_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_3.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_3.rs new file mode 100644 index 0000000..5cfcc65 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/fmux_3.rs @@ -0,0 +1,49 @@ +#[doc = "Register `fmux_3` reader"] +pub type R = crate::R; +#[doc = "Register `fmux_3` writer"] +pub type W = crate::W; +#[doc = "Field `gpen_0` reader - Enable GPIO IRQ function."] +pub type GPEN_0_R = crate::BitReader; +#[doc = "Field `gpen_0` writer - Enable GPIO IRQ function."] +pub type GPEN_0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable GPIO IRQ function."] + #[inline(always)] + pub fn gpen_0(&self) -> GPEN_0_R { + GPEN_0_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable GPIO IRQ function."] + #[inline(always)] + #[must_use] + pub fn gpen_0(&mut self) -> GPEN_0_W { + GPEN_0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmux_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmux_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FMUX_3_SPEC; +impl crate::RegisterSpec for FMUX_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmux_3::R`](R) reader structure"] +impl crate::Readable for FMUX_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fmux_3::W`](W) writer structure"] +impl crate::Writable for FMUX_3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets fmux_3 to value 0"] +impl crate::Resettable for FMUX_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_mdc.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_mdc.rs new file mode 100644 index 0000000..5e2cf8b --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_mdc.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_mdc` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_mdc` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_mdc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_mdc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_MDC_SPEC; +impl crate::RegisterSpec for GMAC0_MDC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_mdc::R`](R) reader structure"] +impl crate::Readable for GMAC0_MDC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_mdc::W`](W) writer structure"] +impl crate::Writable for GMAC0_MDC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_mdc to value 0"] +impl crate::Resettable for GMAC0_MDC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_mdio.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_mdio.rs new file mode 100644 index 0000000..b24ded7 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_mdio.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_mdio` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_mdio` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_mdio::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_mdio::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_MDIO_SPEC; +impl crate::RegisterSpec for GMAC0_MDIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_mdio::R`](R) reader structure"] +impl crate::Readable for GMAC0_MDIO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_mdio::W`](W) writer structure"] +impl crate::Writable for GMAC0_MDIO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_mdio to value 0"] +impl crate::Resettable for GMAC0_MDIO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxc.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxc.rs new file mode 100644 index 0000000..8afdb42 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxc.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxc` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxc` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXC_SPEC; +impl crate::RegisterSpec for GMAC0_RXC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxc::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxc::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxc to value 0"] +impl crate::Resettable for GMAC0_RXC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxc_func_sel.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxc_func_sel.rs new file mode 100644 index 0000000..b80809d --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxc_func_sel.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxc_func_sel` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxc_func_sel` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxc_func_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxc_func_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXC_FUNC_SEL_SPEC; +impl crate::RegisterSpec for GMAC0_RXC_FUNC_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxc_func_sel::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXC_FUNC_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxc_func_sel::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXC_FUNC_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxc_func_sel to value 0"] +impl crate::Resettable for GMAC0_RXC_FUNC_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd0.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd0.rs new file mode 100644 index 0000000..c4e8839 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxd0` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxd0` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXD0_SPEC; +impl crate::RegisterSpec for GMAC0_RXD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxd0::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxd0::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxd0 to value 0"] +impl crate::Resettable for GMAC0_RXD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd1.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd1.rs new file mode 100644 index 0000000..6109d76 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxd1` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxd1` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXD1_SPEC; +impl crate::RegisterSpec for GMAC0_RXD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxd1::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxd1::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxd1 to value 0"] +impl crate::Resettable for GMAC0_RXD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd2.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd2.rs new file mode 100644 index 0000000..0686f72 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd2.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxd2` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxd2` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXD2_SPEC; +impl crate::RegisterSpec for GMAC0_RXD2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxd2::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXD2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxd2::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXD2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxd2 to value 0"] +impl crate::Resettable for GMAC0_RXD2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd3.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd3.rs new file mode 100644 index 0000000..097dfe4 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxd3.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxd3` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxd3` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxd3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXD3_SPEC; +impl crate::RegisterSpec for GMAC0_RXD3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxd3::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXD3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxd3::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXD3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxd3 to value 0"] +impl crate::Resettable for GMAC0_RXD3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxdv.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxdv.rs new file mode 100644 index 0000000..7b3062b --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_rxdv.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_rxdv` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_rxdv` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_rxdv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_rxdv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_RXDV_SPEC; +impl crate::RegisterSpec for GMAC0_RXDV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_rxdv::R`](R) reader structure"] +impl crate::Readable for GMAC0_RXDV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_rxdv::W`](W) writer structure"] +impl crate::Writable for GMAC0_RXDV_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_rxdv to value 0"] +impl crate::Resettable for GMAC0_RXDV_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txc.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txc.rs new file mode 100644 index 0000000..8c7bb7b --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txc.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_txc` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_txc` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_TXC_SPEC; +impl crate::RegisterSpec for GMAC0_TXC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_txc::R`](R) reader structure"] +impl crate::Readable for GMAC0_TXC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_txc::W`](W) writer structure"] +impl crate::Writable for GMAC0_TXC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_txc to value 0"] +impl crate::Resettable for GMAC0_TXC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd0.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd0.rs new file mode 100644 index 0000000..01ac307 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_txd0` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_txd0` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_TXD0_SPEC; +impl crate::RegisterSpec for GMAC0_TXD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_txd0::R`](R) reader structure"] +impl crate::Readable for GMAC0_TXD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_txd0::W`](W) writer structure"] +impl crate::Writable for GMAC0_TXD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_txd0 to value 0"] +impl crate::Resettable for GMAC0_TXD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd1.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd1.rs new file mode 100644 index 0000000..9d0651d --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_txd1` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_txd1` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_TXD1_SPEC; +impl crate::RegisterSpec for GMAC0_TXD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_txd1::R`](R) reader structure"] +impl crate::Readable for GMAC0_TXD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_txd1::W`](W) writer structure"] +impl crate::Writable for GMAC0_TXD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_txd1 to value 0"] +impl crate::Resettable for GMAC0_TXD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd2.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd2.rs new file mode 100644 index 0000000..f0823f4 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd2.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_txd2` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_txd2` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_TXD2_SPEC; +impl crate::RegisterSpec for GMAC0_TXD2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_txd2::R`](R) reader structure"] +impl crate::Readable for GMAC0_TXD2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_txd2::W`](W) writer structure"] +impl crate::Writable for GMAC0_TXD2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_txd2 to value 0"] +impl crate::Resettable for GMAC0_TXD2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd3.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd3.rs new file mode 100644 index 0000000..ce629d9 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txd3.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_txd3` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_txd3` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txd3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_TXD3_SPEC; +impl crate::RegisterSpec for GMAC0_TXD3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_txd3::R`](R) reader structure"] +impl crate::Readable for GMAC0_TXD3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_txd3::W`](W) writer structure"] +impl crate::Writable for GMAC0_TXD3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_txd3 to value 0"] +impl crate::Resettable for GMAC0_TXD3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txen.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txen.rs new file mode 100644 index 0000000..5f87204 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/gmac0_txen.rs @@ -0,0 +1,49 @@ +#[doc = "Register `gmac0_txen` reader"] +pub type R = crate::R; +#[doc = "Register `gmac0_txen` writer"] +pub type W = crate::W; +#[doc = "Field `value` reader - value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `value` writer - value"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac0_txen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac0_txen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC0_TXEN_SPEC; +impl crate::RegisterSpec for GMAC0_TXEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac0_txen::R`](R) reader structure"] +impl crate::Readable for GMAC0_TXEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac0_txen::W`](W) writer structure"] +impl crate::Writable for GMAC0_TXEN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gmac0_txen to value 0"] +impl crate::Resettable for GMAC0_TXEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_0.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_0.rs new file mode 100644 index 0000000..95929fe --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ioirq_0` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_0` writer"] +pub type W = crate::W; +#[doc = "Field `is` reader - 1: Edge trigger, 0: Level trigger"] +pub type IS_R = crate::FieldReader; +#[doc = "Field `is` writer - 1: Edge trigger, 0: Level trigger"] +pub type IS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - 1: Edge trigger, 0: Level trigger"] + #[inline(always)] + pub fn is(&self) -> IS_R { + IS_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - 1: Edge trigger, 0: Level trigger"] + #[inline(always)] + #[must_use] + pub fn is(&mut self) -> IS_W { + IS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_0_SPEC; +impl crate::RegisterSpec for IOIRQ_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_0::R`](R) reader structure"] +impl crate::Readable for IOIRQ_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_0::W`](W) writer structure"] +impl crate::Writable for IOIRQ_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_0 to value 0"] +impl crate::Resettable for IOIRQ_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_1.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_1.rs new file mode 100644 index 0000000..bf8010c --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ioirq_1` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_1` writer"] +pub type W = crate::W; +#[doc = "Field `ic` reader - 1: Do not clear the register, 0: Clear the register"] +pub type IC_R = crate::FieldReader; +#[doc = "Field `ic` writer - 1: Do not clear the register, 0: Clear the register"] +pub type IC_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - 1: Do not clear the register, 0: Clear the register"] + #[inline(always)] + pub fn ic(&self) -> IC_R { + IC_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - 1: Do not clear the register, 0: Clear the register"] + #[inline(always)] + #[must_use] + pub fn ic(&mut self) -> IC_W { + IC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_1_SPEC; +impl crate::RegisterSpec for IOIRQ_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_1::R`](R) reader structure"] +impl crate::Readable for IOIRQ_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_1::W`](W) writer structure"] +impl crate::Writable for IOIRQ_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_1 to value 0"] +impl crate::Resettable for IOIRQ_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_2.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_2.rs new file mode 100644 index 0000000..0a22287 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_2.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ioirq_2` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_2` writer"] +pub type W = crate::W; +#[doc = "Field `ibe` reader - 1: Trigger on both edges, 0: Trigger on a single edge"] +pub type IBE_R = crate::FieldReader; +#[doc = "Field `ibe` writer - 1: Trigger on both edges, 0: Trigger on a single edge"] +pub type IBE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - 1: Trigger on both edges, 0: Trigger on a single edge"] + #[inline(always)] + pub fn ibe(&self) -> IBE_R { + IBE_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - 1: Trigger on both edges, 0: Trigger on a single edge"] + #[inline(always)] + #[must_use] + pub fn ibe(&mut self) -> IBE_W { + IBE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_2_SPEC; +impl crate::RegisterSpec for IOIRQ_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_2::R`](R) reader structure"] +impl crate::Readable for IOIRQ_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_2::W`](W) writer structure"] +impl crate::Writable for IOIRQ_2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_2 to value 0"] +impl crate::Resettable for IOIRQ_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_3.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_3.rs new file mode 100644 index 0000000..0711733 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_3.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ioirq_3` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_3` writer"] +pub type W = crate::W; +#[doc = "Field `iev` reader - 1: Positive/Low, 0: Negative/High"] +pub type IEV_R = crate::FieldReader; +#[doc = "Field `iev` writer - 1: Positive/Low, 0: Negative/High"] +pub type IEV_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - 1: Positive/Low, 0: Negative/High"] + #[inline(always)] + pub fn iev(&self) -> IEV_R { + IEV_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - 1: Positive/Low, 0: Negative/High"] + #[inline(always)] + #[must_use] + pub fn iev(&mut self) -> IEV_W { + IEV_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_3_SPEC; +impl crate::RegisterSpec for IOIRQ_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_3::R`](R) reader structure"] +impl crate::Readable for IOIRQ_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_3::W`](W) writer structure"] +impl crate::Writable for IOIRQ_3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_3 to value 0"] +impl crate::Resettable for IOIRQ_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_4.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_4.rs new file mode 100644 index 0000000..689d0f1 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_4.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ioirq_4` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_4` writer"] +pub type W = crate::W; +#[doc = "Field `ie` reader - 1: Unmask, 0: Mask"] +pub type IE_R = crate::FieldReader; +#[doc = "Field `ie` writer - 1: Unmask, 0: Mask"] +pub type IE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - 1: Unmask, 0: Mask"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - 1: Unmask, 0: Mask"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_4_SPEC; +impl crate::RegisterSpec for IOIRQ_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_4::R`](R) reader structure"] +impl crate::Readable for IOIRQ_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_4::W`](W) writer structure"] +impl crate::Writable for IOIRQ_4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_4 to value 0"] +impl crate::Resettable for IOIRQ_4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_5.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_5.rs new file mode 100644 index 0000000..2da2125 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_5.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ioirq_5` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_5` writer"] +pub type W = crate::W; +#[doc = "Field `ris` reader - Status of the edge trigger, can be cleared by writing gpioic."] +pub type RIS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Status of the edge trigger, can be cleared by writing gpioic."] + #[inline(always)] + pub fn ris(&self) -> RIS_R { + RIS_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_5_SPEC; +impl crate::RegisterSpec for IOIRQ_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_5::R`](R) reader structure"] +impl crate::Readable for IOIRQ_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_5::W`](W) writer structure"] +impl crate::Writable for IOIRQ_5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_5 to value 0"] +impl crate::Resettable for IOIRQ_5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_6.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_6.rs new file mode 100644 index 0000000..8bbd513 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_6.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ioirq_6` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_6` writer"] +pub type W = crate::W; +#[doc = "Field `mis` reader - The masked GPIO IRQ status."] +pub type MIS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - The masked GPIO IRQ status."] + #[inline(always)] + pub fn mis(&self) -> MIS_R { + MIS_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_6_SPEC; +impl crate::RegisterSpec for IOIRQ_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_6::R`](R) reader structure"] +impl crate::Readable for IOIRQ_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_6::W`](W) writer structure"] +impl crate::Writable for IOIRQ_6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_6 to value 0"] +impl crate::Resettable for IOIRQ_6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_7.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_7.rs new file mode 100644 index 0000000..2f5aded --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/ioirq_7.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ioirq_7` reader"] +pub type R = crate::R; +#[doc = "Register `ioirq_7` writer"] +pub type W = crate::W; +#[doc = "Field `in_sync2` reader - Status of gpio_in after synchronization."] +pub type IN_SYNC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Status of gpio_in after synchronization."] + #[inline(always)] + pub fn in_sync2(&self) -> IN_SYNC2_R { + IN_SYNC2_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq_7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq_7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IOIRQ_7_SPEC; +impl crate::RegisterSpec for IOIRQ_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioirq_7::R`](R) reader structure"] +impl crate::Readable for IOIRQ_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ioirq_7::W`](W) writer structure"] +impl crate::Writable for IOIRQ_7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ioirq_7 to value 0"] +impl crate::Resettable for IOIRQ_7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/osc.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/osc.rs new file mode 100644 index 0000000..c224162 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/osc.rs @@ -0,0 +1,49 @@ +#[doc = "Register `osc` reader"] +pub type R = crate::R; +#[doc = "Register `osc` writer"] +pub type W = crate::W; +#[doc = "Field `ds` reader - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] +pub type DS_R = crate::FieldReader; +#[doc = "Field `ds` writer - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] + #[inline(always)] + #[must_use] + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`osc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`osc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OSC_SPEC; +impl crate::RegisterSpec for OSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`osc::R`](R) reader structure"] +impl crate::Readable for OSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`osc::W`](W) writer structure"] +impl crate::Writable for OSC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets osc to value 0"] +impl crate::Resettable for OSC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_0.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_0.rs new file mode 100644 index 0000000..9eb524e --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_0.rs @@ -0,0 +1,139 @@ +#[doc = "Register `rgpio_0` reader"] +pub type R = crate::R; +#[doc = "Register `rgpio_0` writer"] +pub type W = crate::W; +#[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_R = crate::BitReader; +#[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_R = crate::FieldReader; +#[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_R = crate::BitReader; +#[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_R = crate::BitReader; +#[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_R = crate::BitReader; +#[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_R = crate::BitReader; +#[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_R = crate::BitReader; +#[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pu(&self) -> PU_R { + PU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pd(&self) -> PD_R { + PD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + pub fn slew(&self) -> SLEW_R { + SLEW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + pub fn smt(&self) -> SMT_R { + SMT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + pub fn pos(&self) -> POS_R { + POS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + #[must_use] + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + #[must_use] + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + #[must_use] + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + #[must_use] + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RGPIO_0_SPEC; +impl crate::RegisterSpec for RGPIO_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rgpio_0::R`](R) reader structure"] +impl crate::Readable for RGPIO_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rgpio_0::W`](W) writer structure"] +impl crate::Writable for RGPIO_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets rgpio_0 to value 0"] +impl crate::Resettable for RGPIO_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_1.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_1.rs new file mode 100644 index 0000000..4232f2d --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_1.rs @@ -0,0 +1,139 @@ +#[doc = "Register `rgpio_1` reader"] +pub type R = crate::R; +#[doc = "Register `rgpio_1` writer"] +pub type W = crate::W; +#[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_R = crate::BitReader; +#[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_R = crate::FieldReader; +#[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_R = crate::BitReader; +#[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_R = crate::BitReader; +#[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_R = crate::BitReader; +#[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_R = crate::BitReader; +#[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_R = crate::BitReader; +#[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pu(&self) -> PU_R { + PU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pd(&self) -> PD_R { + PD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + pub fn slew(&self) -> SLEW_R { + SLEW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + pub fn smt(&self) -> SMT_R { + SMT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + pub fn pos(&self) -> POS_R { + POS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + #[must_use] + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + #[must_use] + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + #[must_use] + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + #[must_use] + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RGPIO_1_SPEC; +impl crate::RegisterSpec for RGPIO_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rgpio_1::R`](R) reader structure"] +impl crate::Readable for RGPIO_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rgpio_1::W`](W) writer structure"] +impl crate::Writable for RGPIO_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets rgpio_1 to value 0"] +impl crate::Resettable for RGPIO_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_2.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_2.rs new file mode 100644 index 0000000..fa5bca7 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_2.rs @@ -0,0 +1,139 @@ +#[doc = "Register `rgpio_2` reader"] +pub type R = crate::R; +#[doc = "Register `rgpio_2` writer"] +pub type W = crate::W; +#[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_R = crate::BitReader; +#[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_R = crate::FieldReader; +#[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_R = crate::BitReader; +#[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_R = crate::BitReader; +#[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_R = crate::BitReader; +#[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_R = crate::BitReader; +#[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_R = crate::BitReader; +#[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pu(&self) -> PU_R { + PU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pd(&self) -> PD_R { + PD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + pub fn slew(&self) -> SLEW_R { + SLEW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + pub fn smt(&self) -> SMT_R { + SMT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + pub fn pos(&self) -> POS_R { + POS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + #[must_use] + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + #[must_use] + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + #[must_use] + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + #[must_use] + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RGPIO_2_SPEC; +impl crate::RegisterSpec for RGPIO_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rgpio_2::R`](R) reader structure"] +impl crate::Readable for RGPIO_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rgpio_2::W`](W) writer structure"] +impl crate::Writable for RGPIO_2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets rgpio_2 to value 0"] +impl crate::Resettable for RGPIO_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_3.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_3.rs new file mode 100644 index 0000000..ca90310 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/rgpio_3.rs @@ -0,0 +1,139 @@ +#[doc = "Register `rgpio_3` reader"] +pub type R = crate::R; +#[doc = "Register `rgpio_3` writer"] +pub type W = crate::W; +#[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_R = crate::BitReader; +#[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_R = crate::FieldReader; +#[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_R = crate::BitReader; +#[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_R = crate::BitReader; +#[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_R = crate::BitReader; +#[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_R = crate::BitReader; +#[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_R = crate::BitReader; +#[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pu(&self) -> PU_R { + PU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + pub fn pd(&self) -> PD_R { + PD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + pub fn slew(&self) -> SLEW_R { + SLEW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + pub fn smt(&self) -> SMT_R { + SMT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + pub fn pos(&self) -> POS_R { + POS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) + } + #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] + #[inline(always)] + #[must_use] + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) + } + #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) + } + #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] + #[inline(always)] + #[must_use] + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) + } + #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] + #[inline(always)] + #[must_use] + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) + } + #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] + #[inline(always)] + #[must_use] + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) + } + #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + #[must_use] + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rgpio_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rgpio_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RGPIO_3_SPEC; +impl crate::RegisterSpec for RGPIO_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rgpio_3::R`](R) reader structure"] +impl crate::Readable for RGPIO_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rgpio_3::W`](W) writer structure"] +impl crate::Writable for RGPIO_3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets rgpio_3 to value 0"] +impl crate::Resettable for RGPIO_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/rstn.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/rstn.rs new file mode 100644 index 0000000..726d5e6 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/rstn.rs @@ -0,0 +1,64 @@ +#[doc = "Register `rstn` reader"] +pub type R = crate::R; +#[doc = "Register `rstn` writer"] +pub type W = crate::W; +#[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] +pub type SMT_R = crate::BitReader; +#[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_R = crate::BitReader; +#[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] + #[inline(always)] + pub fn smt(&self) -> SMT_R { + SMT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + pub fn pos(&self) -> POS_R { + POS_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] + #[inline(always)] + #[must_use] + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 0) + } + #[doc = "Bit 1 - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + #[must_use] + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstn::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstn::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RSTN_SPEC; +impl crate::RegisterSpec for RSTN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rstn::R`](R) reader structure"] +impl crate::Readable for RSTN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rstn::W`](W) writer structure"] +impl crate::Writable for RSTN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets rstn to value 0"] +impl crate::Resettable for RSTN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/rtc.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/rtc.rs new file mode 100644 index 0000000..04570ba --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/rtc.rs @@ -0,0 +1,49 @@ +#[doc = "Register `rtc` reader"] +pub type R = crate::R; +#[doc = "Register `rtc` writer"] +pub type W = crate::W; +#[doc = "Field `ds` reader - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] +pub type DS_R = crate::FieldReader; +#[doc = "Field `ds` writer - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] + #[inline(always)] + pub fn ds(&self) -> DS_R { + DS_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] + #[inline(always)] + #[must_use] + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RTC_SPEC; +impl crate::RegisterSpec for RTC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rtc::R`](R) reader structure"] +impl crate::Readable for RTC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rtc::W`](W) writer structure"] +impl crate::Writable for RTC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets rtc to value 0"] +impl crate::Resettable for RTC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/testen.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/testen.rs new file mode 100644 index 0000000..7bfe248 --- /dev/null +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/testen.rs @@ -0,0 +1,49 @@ +#[doc = "Register `testen` reader"] +pub type R = crate::R; +#[doc = "Register `testen` writer"] +pub type W = crate::W; +#[doc = "Field `testen_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type TESTEN_POS_R = crate::BitReader; +#[doc = "Field `testen_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] +pub type TESTEN_POS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + pub fn testen_pos(&self) -> TESTEN_POS_R { + TESTEN_POS_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] + #[inline(always)] + #[must_use] + pub fn testen_pos(&mut self) -> TESTEN_POS_W { + TESTEN_POS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AON IOMUX CFG SAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`testen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`testen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TESTEN_SPEC; +impl crate::RegisterSpec for TESTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`testen::R`](R) reader structure"] +impl crate::Readable for TESTEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`testen::W`](W) writer structure"] +impl crate::Writable for TESTEN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets testen to value 0"] +impl crate::Resettable for TESTEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +}