From 7ae1e973b84dd849ee0782f019c97c3715155148 Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Tue, 23 Jan 2024 23:41:41 +0300 Subject: [PATCH] write_raw --- CHANGELOG.md | 1 + src/generate/generic.rs | 14 +++++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 098ac4de..a6ed085b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/). ## [Unreleased] - Add `base-address-shift` config flag +- Add `write_raw` to all writtable registers ## [v0.31.5] - 2024-01-04 diff --git a/src/generate/generic.rs b/src/generate/generic.rs index 186d3364..762acff8 100644 --- a/src/generate/generic.rs +++ b/src/generate/generic.rs @@ -203,6 +203,18 @@ impl Reg { } } +impl Reg { + /// Writes raw value to register. + /// + /// # Safety + /// + /// Unsafe as it passes value without checks. + #[inline(always)] + pub unsafe fn write_raw(&self, bits: REG::Ux) { + self.register.set(bits); + } +} + impl Reg { /// Modifies the contents of the register by reading and then writing it. /// @@ -550,7 +562,7 @@ macro_rules! bit_proxy { pub const fn width(&self) -> u8 { Self::WIDTH } - + /// Field offset #[inline(always)] pub const fn offset(&self) -> u8 {