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nezha.dts
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nezha.dts
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/dts-v1/;
/ {
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "allwinner,sun20iw1p1";
model = "sun20iw1p1";
chosen {
bootargs = "LOG=warn:console=ttyS0,115200n8 debug loglevel=7,initcall_debug=1 init=/init earlycon=sbi";
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x0 0x40000000>;
};
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
timebase-frequency = <24000000>;
idle-states {
CPU_SLEEP: cpu-sleep {
compatible = "riscv,idle-state";
local-timer-stop;
entry-latency-us = <59>;
exit-latency-us = <59>;
min-residency-us = <5000>;
};
};
CPU0: cpu@0 {
device_type = "cpu";
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
clocks = <&ccu 135>;
clock-frequency = <24000000>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
#cooling-cells = <2>;
CPU0_intc: interrupt-controller {
#interrupt-cells = <0x01>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
spi0 = &spi0;
spi1 = &spi1;
twi0 = &twi0;
twi1 = &twi1;
twi2 = &twi2;
twi3 = &twi3;
mmc2 = &sdc2;
pwm0 = &pwm0;
pwm1 = &pwm1;
pwm2 = &pwm2;
pwm3 = &pwm3;
pwm4 = &pwm4;
pwm5 = &pwm5;
pwm6 = &pwm6;
pwm7 = &pwm7;
ir0 = &s_cir0;
ir1 = &ir1;
mmc0 = &sdc0;
tvd = &tvd;
tvd0 = &tvd0;
} ;
dram: dram {
device_type = "dram";
compatible = "allwinner,dram";
clocks = <&ccu 2>;
clock-names = "pll_ddr";
};
dump_reg: dump_reg@20000 {
compatible = "allwinner,sunxi-dump-reg";
reg = <0x0 0x00020000 0x0 0x0004>;
};
cpu_opp_table: cpu-opp-table {
compatible = "allwinner,sun50i-operating-points";
nvmem-cells = <&vf_table>;
nvmem-cell-names = "speed";
opp-shared;
opp@1008000000 {
opp-hz = /bits/ 64 <1008000000>;
clock-latency-ns = <244144>;
opp-microvolt-a0 = <1100000>;
};
};
dcxo24M: dcxo24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "dcxo24M";
};
rc_16m: rc16m_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <16000000>;
clock-accuracy = <300000000>;
clock-output-names = "rc-16m";
};
ext_32k: ext32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "ext-32k";
};
reg_pio1_8: pio-18 {
compatible = "regulator-fixed";
regulator-name = "pio-18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_pio3_3: pio-33 {
compatible = "regulator-fixed";
regulator-name = "pio-33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
thermal-zones {
cpu_thermal_zone {
polling-delay-passive = <500>;
polling-delay = <1000>;
thermal-sensors = <&ths 0>;
sustainable-power = <1200>;
cpu_trips: trips {
cpu_threshold: trip-point@0 {
temperature = <70000>;
type = "passive";
hysteresis = <0>;
};
cpu_target: trip-point@1 {
temperature = <90000>;
type = "passive";
hysteresis = <0>;
};
cpu_crit: cpu_crit@0 {
temperature = <110000>;
type = "critical";
hysteresis = <0>;
};
};
cooling-maps {
map0 {
trip = <&cpu_target>;
cooling-device = <&CPU0
(~0)
(~0)>;
contribution = <1024>;
};
};
};
};
mmu_aw: iommu@2010000 {
compatible = "allwinner,sunxi-iommu";
reg = <0x0 0x02010000 0x0 0x1000>;
interrupts-extended = <&plic0 80 4>;
interrupt-names = "iommu-irq";
clocks = <&ccu 48>;
clock-names = "iommu";
#iommu-cells = <2>;
status = "okay";
};
soc: soc@3000000 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
sram_ctrl: sram_ctrl@3000000 {
compatible = "allwinner,sram_ctrl";
reg = <0x0 0x3000000 0 0x16C>;
soc_ver {
offset = <0x24>;
mask = <0x7>;
shift = <0>;
ver_a = <0x18590000>;
ver_b = <0x18590002>;
};
soc_id {
offset = <0x200>;
mask = <0x1>;
shift = <22>;
};
soc_bin {
offset = <0x0>;
mask = <0x3ff>;
shift = <0x0>;
};
};
rtc_ccu: rtc_ccu@7090000 {
compatible = "allwinner,sun20iw1-rtc-ccu";
device_type = "rtc-ccu";
reg = <0x0 0x07090000 0x0 0x320>;
#clock-cells = <1>;
};
ccu: clock@2001000 {
compatible = "allwinner,sun20iw1-ccu";
reg = <0x0 0x02001000 0x0 0x1000>;
clocks = <&dcxo24M>, <&rtc_ccu 3>, <&rtc_ccu 0>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
r_ccu: clock@7010000 {
compatible = "allwinner,sun20iw1-r-ccu";
reg = <0x0 0x07010000 0x0 0x240>;
clocks = <&dcxo24M>, <&rtc_ccu 3>, <&rtc_ccu 0>,
<&ccu 4>;
clock-names = "hosc", "losc", "iosc", "pll-periph0";
#clock-cells = <1>;
#reset-cells = <1>;
};
plic0: interrupt-controller@10000000 {
compatible = "riscv,plic0";
#address-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0x10000000 0x0 0x4000000>;
interrupts-extended = <&CPU0_intc 0xffffffff &CPU0_intc 9>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev=<200>;
};
uart0: uart@2500000 {
compatible = "allwinner,sun20i-uart";
device_type = "uart0";
reg = <0x0 0x02500000 0x0 0x400>;
interrupts-extended = <&plic0 18 4>;
clocks = <&ccu 63>;
clock-names = "uart0";
resets = <&ccu 18>;
sunxi,uart-fifosize = <64>;
uart0_port = <0>;
uart0_type = <2>;
status = "okay";
};
uart1: uart@2500400 {
compatible = "allwinner,sun20i-uart";
device_type = "uart1";
reg = <0x0 0x02500400 0x0 0x400>;
interrupts-extended = <&plic0 19 4>;
sunxi,uart-fifosize = <256>;
clocks = <&ccu 64>;
clock-names = "uart1";
resets = <&ccu 19>;
uart1_port = <1>;
uart1_type = <4>;
status = "disabled";
};
uart2: uart@2500800 {
compatible = "allwinner,sun20i-uart";
device_type = "uart2";
reg = <0x0 0x02500800 0x0 0x400>;
interrupts-extended = <&plic0 20 4>;
sunxi,uart-fifosize = <256>;
clocks = <&ccu 65>;
clock-names = "uart2";
resets = <&ccu 20>;
uart2_port = <2>;
uart2_type = <4>;
status = "disabled";
};
uart3: uart@2500c00 {
compatible = "allwinner,sun20i-uart";
device_type = "uart3";
reg = <0x0 0x02500c00 0x0 0x400>;
interrupts-extended = <&plic0 21 4>;
sunxi,uart-fifosize = <256>;
clocks = <&ccu 66>;
clock-names = "uart3";
resets = <&ccu 21>;
uart3_port = <3>;
uart3_type = <4>;
status = "disabled";
};
uart4: uart@2501000 {
compatible = "allwinner,sun20i-uart";
device_type = "uart4";
reg = <0x0 0x02501000 0x0 0x400>;
interrupts-extended = <&plic0 22 4>;
sunxi,uart-fifosize = <256>;
clocks = <&ccu 67>;
clock-names = "uart4";
resets = <&ccu 22>;
uart4_port = <4>;
uart4_type = <2>;
status = "disabled";
};
uart5: uart@2501400 {
compatible = "allwinner,sun20i-uart";
device_type = "uart5";
reg = <0x0 0x02501400 0x0 0x400>;
interrupts-extended = <&plic0 23 4>;
sunxi,uart-fifosize = <256>;
clocks = <&ccu 68>;
clock-names = "uart5";
resets = <&ccu 23>;
uart5_port = <5>;
uart5_type = <2>;
status = "disabled";
};
cryptoengine: ce@03040000 {
compatible = "allwinner,sunxi-ce";
device_name = "ce";
reg = <0x0 0x03040000 0x0 0xa0>,
<0x0 0x03040800 0x0 0xa0>;
interrupts-extended = <&plic0 68 1>,
<&plic0 69 1>;
clock-frequency = <400000000>;
clocks = <&ccu 36>, <&ccu 35>, <&ccu 52>,
<&ccu 5>;
clock-names = "bus_ce", "ce_clk", "mbus_ce", "pll_periph0_2x";
resets = <&ccu 4>;
status = "okay";
};
s_cir0: s_cir@7040000 {
compatible = "allwinner,s_cir";
reg = <0x0 0x07040000 0x0 0x400>;
interrupts-extended = <&plic0 167 4>;
clocks = <&r_ccu 6>, <&dcxo24M>, <&r_ccu 5>;
clock-names = "bus", "pclk", "mclk";
resets = <&r_ccu 3>;
supply = "";
supply_vol = "";
status = "disabled";
};
ir1: ir@2003000 {
compatible = "allwinner,ir_tx";
reg = <0x0 0x02003000 0x0 0x400>;
interrupts-extended = <&plic0 35 4>;
clocks = <&ccu 82>, <&dcxo24M>, <&ccu 81>;
clock-names = "bus", "pclk", "mclk";
resets = <&ccu 33>;
status = "disabled";
};
di: deinterlace@5400000 {
compatible = "allwinner,sunxi-deinterlace";
reg = <0x0 0x05400000 0x0 0x0000ffff>;
interrupts-extended = <&plic0 104 4>;
clocks = <&ccu 31>,
<&ccu 32>,
<&ccu 5>;
clock-names = "clk_di",
"pll_periph",
"clk_bus_di";
resets = <&ccu 2>;
reset-names = "rst_bus_di";
assigned-clocks = <&ccu 31>;
assigned-clock-parents = <&ccu 5>;
assigned-clock-rates = <300000000>;
iommus = <&mmu_aw 4 1>;
status = "okay";
};
gmac0: eth@4500000 {
compatible = "allwinner,sunxi-gmac";
reg = <0x0 0x04500000 0x0 0x10000>,
<0x0 0x03000030 0x0 0x4>;
interrupts-extended = <&plic0 62 4>;
interrupt-names = "gmacirq";
clocks = <&ccu 80>, <&ccu 79>;
clock-names = "gmac", "ephy";
resets = <&ccu 32>;
device_type = "gmac0";
pinctrl-0 = <&gmac_pins_a>;
pinctrl-1 = <&gmac_pins_b>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii";
use_ephy25m = <1>;
tx-delay = <7>;
rx-delay = <31>;
phy-rst = <&pio 0 14 1>;
gmac-power0;
gmac-power1;
gmac-power2;
status = "disabled";
};
rtc: rtc@7090000 {
compatible = "allwinner,sun20iw1-rtc";
device_type = "rtc";
wakeup-source;
interrupts-extended = <&plic0 160 4>;
reg = <0x0 0x07090000 0x0 0x320>;
clocks = <&r_ccu 7>, <&rtc_ccu 8>, <&rtc_ccu 6>;
clock-names = "r-ahb-rtc", "rtc-spi", "rtc-1k";
resets = <&r_ccu 4>;
gpr_cur_pos = <6>;
};
dma: dma-controller@3002000 {
compatible = "allwinner,sun8i-riscv-dma";
reg = <0x0 0x03002000 0x0 0x1000>;
interrupts-extended = <&plic0 66 4>;
clocks = <&ccu 39>, <&ccu 50>;
clock-names = "bus", "mbus";
resets = <&ccu 6>;
dma-channels = <16>;
dma-requests = <48>;
#dma-cells = <1>;
status = "okay";
};
soc_timer0: timer@2050000 {
compatible = "allwinner,sun4i-a10-timer";
device_type = "soc_timer";
reg = <0x0 0x02050000 0x0 0xA0>;
interrupts-extended = <&plic0 75 4>;
clocks = <&dcxo24M>;
status = "okay";
};
wdt: watchdog@6011000 {
compatible = "allwinner,sun20i-wdt";
reg = <0x0 0x06011000 0x0 0x20>;
interrupts-extended = <&plic0 147 4>;
};
mbus0:mbus-comtroller@3102000 {
compatible = "allwinner,sun8i-mbus";
reg = <0x0 0x03102000 0x0 0x1000>;
#mbus-cells = <1>;
};
pmu: pmu {
compatible = "riscv,c910_pmu";
};
ilde: idle {
compatible = "riscv,idle";
};
pio: pinctrl@2000000 {
compatible = "allwinner,sun20iw1-pinctrl";
reg = <0x0 0x02000000 0x0 0x500>;
interrupts-extended = <&plic0 85 4>,
<&plic0 87 4>,
<&plic0 89 4>,
<&plic0 91 4>,
<&plic0 93 4>,
<&plic0 95 4>;
device_type = "pio";
clocks = <&ccu 26>, <&dcxo24M>, <&rtc_ccu 3>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
#size-cells = <0>;
vcc-pf-supply = <®_pio1_8>;
vcc-pfo-supply = <®_pio3_3>;
test_pins_a: test_pins@0 {
allwinner,pins = "PB0", "PB1";
allwinner,function = "test";
allwinner,muxsel = <0x7>;
allwinner,drive = <1>;
allwinner,pull = <1>;
};
test_pins_b: test_pins@1 {
pins = "PB0", "PB1";
function = "io_disabled";
allwinner,muxsel = <0xF>;
allwinner,drive = <1>;
allwinner,pull = <1>;
};
gmac_pins_a: gmac@0 {
pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA6", "PA7",
"PA8", "PA10", "PA11", "PA12",
"PA13", "PA17", "PA18", "PA28",
"PA29", "PA30", "PA31";
function = "gmac0";
drive-strength = <10>;
};
gmac_pins_b: gmac@1 {
pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA6", "PA7",
"PA8", "PA10", "PA11", "PA12",
"PA13", "PA17", "PA18", "PA28",
"PA29", "PA30", "PA31";
function = "gpio_in";
drive-strength = <10>;
};
ir1_pins_a: ir1@0 {
pins = "PG11";
function = "ir1";
drive-strength = <10>;
};
csi_mclk0_pins_a: csi_mclk0@0 {
pins = "PE3";
function = "csi0";
drive-strength = <10>;
};
csi_mclk0_pins_b: csi_mclk0@1 {
pins = "PE3";
function = "gpio_in";
};
csi0_pins_a: csi0@0 {
pins = "PE2", "PE0", "PE1", "PE4", "PE5",
"PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
function = "ncsi0";
drive-strength = <10>;
};
csi0_pins_b: csi0@1 {
pins = "PE2", "PE0", "PE1", "PE4", "PE5",
"PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
function = "io_disabled";
drive-strength = <10>;
};
lvds0_pins_a: lvds0@0 {
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
function = "lvds0";
drive-strength = <30>;
bias-disable;
};
lvds0_pins_b: lvds0@1 {
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
function = "io_disabled";
drive-strength = <30>;
bias-disable;
};
rgb24_pins_a: rgb24@0 {
pins = "PB2", "PB3", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PB4", "PB5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", "PB6", "PB7", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21";
function = "lcd0";
drive-strength = <30>;
bias-disable;
};
rgb24_pins_b: rgb24@1 {
pins = "PB2", "PB3", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PB4", "PB5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", "PB6", "PB7", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21";
function = "io_disabled";
bias-disable;
};
rgb18_pins_a: rgb18@0 {
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21";
function = "lcd0";
drive-strength = <30>;
bias-disable;
};
rgb18_pins_b: rgb18@1 {
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21";
function = "io_disabled";
bias-disable;
};
dsi4lane_pins_a: dsi4lane@0 {
pins = "PD0", "PD1", "PD2", "PD3","PD4", "PD5","PD6", "PD7", "PD8", "PD9";
function = "dsi";
drive-strength = <30>;
bias-disable;
};
dsi4lane_pins_b: dsi4lane@1 {
pins = "PD0", "PD1", "PD2", "PD3","PD4", "PD5","PD6", "PD7", "PD8", "PD9";
function = "io_disabled";
bias-disable;
};
};
spi0: spi@4025000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun20i-spi";
device_type = "spi0";
reg = <0x0 0x04025000 0x0 0x300>;
interrupts-extended = <&plic0 31 4>;
clocks = <&ccu 4>, <&ccu 75>, <&ccu 77>;
clock-names = "pll", "mod", "bus";
resets = <&ccu 30>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
spi0_cs_number = <1>;
spi0_cs_bitmap = <1>;
dmas = <&dma 22>, <&dma 22>;
dma-names = "tx", "rx";
status = "disabled";
};
spi1: spi@4026000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun20i-spi";
reg = <0x0 0x04026000 0x0 0x1000>;
interrupts-extended = <&plic0 32 4>;
clocks = <&ccu 4>, <&ccu 76>, <&ccu 78>;
clock-names = "pll", "mod", "bus";
resets = <&ccu 31>;
clock-frequency = <100000000>;
spi1_cs_number = <1>;
spi1_cs_bitmap = <1>;
dmas = <&dma 23>, <&dma 23>;
dma-names = "tx", "rx";
status = "disabled";
};
twi0: twi@2502000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun20i-twi";
device_type = "twi0";
reg = <0x0 0x02502000 0x0 0x400>;
interrupts-extended= <&plic0 25 4>;
clocks = <&ccu 69>;
resets = <&ccu 24>;
clock-names = "bus";
clock-frequency = <400000>;
dmas = <&dma 43>, <&dma 43>;
dma-names = "tx", "rx";
status = "disabled";
};
twi1: twi@2502400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun20i-twi";
device_type = "twi1";
reg = <0x0 0x02502400 0x0 0x400>;
interrupts-extended= <&plic0 26 4>;
clocks = <&ccu 70>;
resets = <&ccu 25>;
clock-names = "bus";
clock-frequency = <200000>;
dmas = <&dma 44>, <&dma 44>;
dma-names = "tx", "rx";
status = "disabled";
};
twi2: twi@2502800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun20i-twi";
device_type = "twi2";
reg = <0x0 0x02502800 0x0 0x400>;
interrupts-extended = <&plic0 27 4>;
clocks = <&ccu 71>;
resets = <&ccu 26>;
clock-names = "bus";
clock-frequency = <100000>;
dmas = <&dma 45>, <&dma 45>;
dma-names = "tx", "rx";
status = "disabled";
};
twi3: twi@2502c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun20i-twi";
device_type = "twi3";
reg = <0x0 0x02502c00 0x0 0x400>;
interrupts-extended = <&plic0 28 4>;
clocks = <&ccu 72>;
resets = <&ccu 27>;
clock-names = "bus";
clock-frequency = <100000>;
dmas = <&dma 46>, <&dma 46>;
dma-names = "tx", "rx";
status = "disabled";
};
ledc: ledc@2008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sunxi-leds";
reg = <0x0 0x02008000 0x0 0x400>;
interrupts-extended = <&plic0 36 4>;
interrupt-names = "ledcirq";
clocks = <&ccu 125>, <&ccu 126>;
clock-names = "clk_ledc", "clk_cpuapb";
dmas = <&dma 42>, <&dma 42>;
dma-names = "rx", "tx";
resets = <&ccu 61>;
reset-names = "ledc_reset";
status = "disable";
};
pwm: pwm@2000c00 {
#pwm-cells = <0x3>;
compatible = "allwinner,sunxi-pwm";
reg = <0x0 0x02000c00 0x0 0x3ff>;
clocks = <&ccu 47>;
resets = <&ccu 13>;
pwm-number = <8>;
pwm-base = <0x0>;
sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>,
<&pwm5>, <&pwm6>, <&pwm7>;
};
keyboard0: keyboard@2009800 {
compatible = "allwinner,keyboard_1350mv";
reg = <0x0 0x02009800 0x0 0x400>;
interrupts-extended = <&plic0 77 1>;
clocks = <&ccu 107>;
resets = <&ccu 49>;
key_cnt = <5>;
key0 = <210 115>;
key1 = <410 114>;
key2 = <590 139>;
key3 = <750 28>;
key4 = <880 172>;
status = "okay";
};
sid@3006000 {
compatible = "allwinner,sun20iw1p1-sid", "allwinner,sunxi-sid";
reg = <0x0 0x03006000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
chipid {
reg = <0x0 0>;
offset = <0x200>;
size = <0x10>;
};
secure_status {
reg = <0x0 0>;
offset = <0xa0>;
size = <0x4>;
};
vf_table: vf-table@00 {
reg = <0x00 2>;
};
ths_calib: calib@14 {
reg = <0x14 8>;
};
};
gpadc: gpadc@2009000 {
compatible = "allwinner,sunxi-gpadc";
reg = <0x0 0x02009000 0x0 0x400>;
interrupts-extended = <&plic0 73 4>;
clocks = <&ccu 83>;
clock-names = "bus";
resets = <&ccu 34>;
status = "okay";
};
ths: ths@02009400 {
compatible = "allwinner,sun20iw1p1-ths";
reg = <0x0 0x02009400 0x0 0x400>;
clocks = <&ccu 84>;
clock-names = "bus";
resets = <&ccu 35>;
nvmem-cells = <&ths_calib>;
nvmem-cell-names = "calibration";
#thermal-sensor-cells = <1>;
};
rtp:rtp@2009c00 {
compatible = "allwinner,sun8i-ts";
reg = <0x0 0x02009c00 0x0 0x400>;
clocks = <&ccu 130>, <&ccu 131>;
clock-names = "mod", "bus";
clock-frequency = <1000000>;
resets = <&ccu 63>;
interrupts-extended = <&plic0 78 4>;
};
codec:codec@2030000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sunxi-internal-codec";
reg = <0x0 0x02030000 0x0 0x34c>;
clocks = <&ccu 15>,
<&ccu 20>,
<&ccu 97>,
<&ccu 98>,
<&ccu 99>;
clock-names = "pll_audio0", "pll_audio1_div5",
"audio_clk_dac", "audio_clk_adc",
"audio_clk_bus";
resets = <&ccu 41>;
device_type = "codec";
status = "disabled";
};
dummy_cpudai:dummy_cpudai@203034c {
compatible = "allwinner,sunxi-dummy-cpudai";
reg = <0x0 0x0203034c 0x0 0x4>;
tx_fifo_size = <128>;
rx_fifo_size = <256>;
dac_txdata = <0x02030020>;
adc_txdata = <0x02030040>;
playback_cma = <128>;
capture_cma = <256>;
device_type = "cpudai";
dmas = <&dma 7>, <&dma 7>;
dma-names = "tx", "rx";
status = "disabled";
};
sndcodec:sound@2030340 {
compatible = "allwinner,sunxi-codec-machine";
reg = <0x0 0x02030340 0x0 0x4>;
interrupts-extended = <&plic0 41 4>;
sunxi,audio-codec = <&codec>;
sunxi,cpudai-controller = <&dummy_cpudai>;
device_type = "sndcodec";
status = "disabled";
};
sunxi_rpaf_dsp0:rpaf-dsp@203034c {
compatible = "allwinner,rpaf-dsp0";
device_type = "sunxi_rpaf_dsp0";
dsp_id = <0x0>;
status = "okay";
};
dmic:dmic@2031000{
#sound-dai-cells = <0>;
compatible = "allwinner,sunxi-dmic";
reg = <0x0 0x02031000 0x0 0x50>;
clocks = <&ccu 15>,
<&ccu 95>,
<&ccu 96>;
clock-names = "pll_audio", "dmic", "dmic_bus";
resets = <&ccu 40>;
dmas = <&dma 8>;
dma-names = "rx";
interrupts-extended = <&plic0 40 4>;
clk_parent = <0x1>;
capture_cma = <256>;
data_vol = <0xB0>;
dmic_rxsync_en = <0x0>;
rx_chmap = <0x76543210>;
device_type = "dmic";
status = "disabled";
};
dmic_codec:sound@2031050{
#sound-dai-cells = <0>;
compatible = "dmic-codec";
reg = <0x0 0x02031050 0x0 0x4>;
num-channels = <8>;
status = "disabled";
};
sounddmic:sounddmic@2031060 {
reg = <0x0 0x02031060 0x0 0x4>;
compatible = "sunxi,simple-audio-card";
simple-audio-card,name = "snddmic";
simple-audio-card,capture_only;
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&dmic>;
};
simple-audio-card,codec {
sound-dai = <&dmic_codec>;
};
};
daudio0:daudio@2032000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x02032000 0x0 0xa0>;
clocks = <&ccu 15>,
<&ccu 85>,
<&ccu 89>;
clock-names = "pll_audio", "i2s0", "i2s0_bus";
resets = <&ccu 36>;
dmas = <&dma 3>, <&dma 3>;
dma-names = "tx", "rx";
interrupts-extended = <&plic0 42 4>;
sign_extend = <0x00>;
tx_data_mode = <0x00>;
rx_data_mode = <0x00>;
msb_lsb_first = <0x00>;
daudio_rxsync_en = <0x00>;
pcm_lrck_period = <0x80>;
slot_width_select = <0x20>;
frametype = <0x00>;
tdm_config = <0x01>;
tdm_num = <0x00>;
mclk_div = <0x00>;
clk_parent = <0x01>;
capture_cma = <128>;
playback_cma = <128>;
tx_num = <4>;
tx_chmap1 = <0x76543210>;
tx_chmap0 = <0xFEDCBA98>;
rx_num = <4>;
rx_chmap3 = <0x03020100>;
rx_chmap2 = <0x07060504>;
rx_chmap1 = <0x0B0A0908>;
rx_chmap0 = <0x0F0E0D0C>;
asrc_function_en = <0x00>;
device_type = "daudio0";
status = "disabled";
};
sounddaudio0: sounddaudio0@20320a0 {
reg = <0x0 0x020320a0 0x0 0x4>;
compatible = "sunxi,simple-audio-card";
simple-audio-card,name = "snddaudio0";
simple-audio-card,format = "i2s";
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&daudio0>;
};
};
daudio1:daudio@2033000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x02033000 0x0 0xa0>;
clocks = <&ccu 15>,
<&ccu 86>,
<&ccu 90>;
clock-names = "pll_audio", "i2s1", "i2s1_bus";
resets = <&ccu 37>;
dmas = <&dma 4>, <&dma 4>;
dma-names = "tx", "rx";
interrupts-extended = <&plic0 43 4>;
sign_extend = <0x00>;
tx_data_mode = <0x00>;
rx_data_mode = <0x00>;
msb_lsb_first = <0x00>;
daudio_rxsync_en = <0x00>;
pcm_lrck_period = <0x80>;
slot_width_select = <0x20>;
frametype = <0x00>;
tdm_config = <0x01>;
tdm_num = <0x01>;
mclk_div = <0x00>;
clk_parent = <0x01>;
capture_cma = <128>;
playback_cma = <128>;
tx_num = <4>;
tx_chmap1 = <0x76543210>;
tx_chmap0 = <0xFEDCBA98>;
rx_num = <4>;
rx_chmap3 = <0x03020100>;
rx_chmap2 = <0x07060504>;
rx_chmap1 = <0x0B0A0908>;
rx_chmap0 = <0x0F0E0D0C>;
asrc_function_en = <0x00>;
device_type = "daudio1";
status = "disabled";
};
sounddaudio1: sounddaudio1@20330a0 {
reg = <0x0 0x020330a0 0x0 0x4>;
compatible = "sunxi,simple-audio-card";
simple-audio-card,name = "snddaudio1";
simple-audio-card,format = "i2s";
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&daudio1>;
};
};
daudio2:daudio@2034000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x02034000 0x0 0xa0>;
clocks = <&ccu 15>,
<&ccu 87>,
<&ccu 91>,
<&ccu 17>,
<&ccu 88>;
resets = <&ccu 38>;
dmas = <&dma 5>, <&dma 5>;
dma-names = "tx", "rx";
interrupts-extended = <&plic0 44 4>;
sign_extend = <0x00>;
tx_data_mode = <0x00>;
rx_data_mode = <0x00>;
msb_lsb_first = <0x00>;
daudio_rxsync_en = <0x00>;
pcm_lrck_period = <0x80>;
slot_width_select = <0x20>;
frametype = <0x00>;
tdm_config = <0x01>;
tdm_num = <0x02>;
mclk_div = <0x01>;
clk_parent = <0x01>;
capture_cma = <128>;
playback_cma = <128>;
tx_num = <4>;
tx_chmap1 = <0x76543210>;
tx_chmap0 = <0xFEDCBA98>;
rx_num = <4>;
rx_chmap3 = <0x03020100>;
rx_chmap2 = <0x07060504>;
rx_chmap1 = <0x0B0A0908>;
rx_chmap0 = <0x0F0E0D0C>;
asrc_function_en = <0x00>;
device_type = "daudio2";
status = "disabled";
};
sounddaudio2: sounddaudio2@20340a0 {
reg = <0x0 0x020340a0 0x0 0x4>;
compatible = "sunxi,simple-audio-card";
simple-audio-card,name = "snddaudio2";
simple-audio-card,format = "i2s";
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&daudio2>;
};
};
hdmiaudio: hdmiaudio@20340a4 {
#sound-dai-cells = <0>;
reg = <0x0 0x020340a4 0x0 0x4>;
compatible = "allwinner,sunxi-hdmiaudio";
status = "disabled";
};
spdif:spdif@2036000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sunxi-spdif";
reg = <0x0 0x02036000 0x0 0x58>;
clocks = <&ccu 15>,
<&ccu 92>,
<&ccu 94>,
<&ccu 18>,
<&ccu 20>,
<&ccu 93>;
clock-names = "pll_audio", "spdif", "spdif_bus",
"pll_audio1", "pll_audio1_div5", "spdif_rx";
resets = <&ccu 39>;
dmas = <&dma 2>, <&dma 2>;
dma-names = "tx", "rx";
interrupts-extended = <&plic0 41 4>;