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uartRx won't sample after sample_mid #68

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sequencer opened this issue Jun 23, 2018 · 0 comments
Open

uartRx won't sample after sample_mid #68

sequencer opened this issue Jun 23, 2018 · 0 comments
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sifive-blocks/src/main/scala/devices/uart/UART.scala

Line 167 in eb969e2

when (sample_mid) {

when sample_mid, the shifter take voter into its register.
so samples between sample_mid and sample_last won't be taken into voter.
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@a0u @sequencer