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  (text "TODO, maybe bank0?" (at 38.1 49.53 0)
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  (text "DRAM in few words...\n- RAS is generated by RAM CS, but refresh too must trigger a RAS.\n- refresh signal driving RAS is a bit delayed.\n- Between RAS and CAS assertion, DRAM address must be changed from row to column address.\n- CAS and DRAM address mux are only triggered by RAM_CS and RD (or WR?)."
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  (text "RAM\nRAM\nRAM\nALT RAM\nROM\nVIDEO RAM\nRAM\nRAM" (at 172.72 53.34 0)
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