From 61c7b4e973abc7aeee354caf47d2afb1e2dfe621 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Thu, 5 Dec 2024 20:15:52 +0100 Subject: [PATCH 01/15] Update for new pac --- Cargo.toml | 3 +- src/adc.rs | 170 ++++++++++++++------------- src/can.rs | 19 +-- src/crc.rs | 49 +++++--- src/dac.rs | 26 ++--- src/dma/bdma.rs | 120 ++++++++++--------- src/dma/dma.rs | 155 +++++++++++++------------ src/dma/macros.rs | 30 ++--- src/dma/mdma.rs | 188 +++++++++++++++--------------- src/dsi.rs | 112 +++++++++--------- src/ethernet/eth.rs | 104 ++++++++--------- src/exti.rs | 22 ++-- src/flash/mod.rs | 6 +- src/flash/operations.rs | 18 +-- src/fmc.rs | 2 +- src/gpio.rs | 16 ++- src/gpio/convert.rs | 8 +- src/gpio/erased.rs | 8 +- src/gpio/exti.rs | 36 +++--- src/gpio/partially_erased.rs | 12 +- src/i2c.rs | 78 +++++++------ src/independent_watchdog.rs | 88 +++++++------- src/ltdc.rs | 73 ++++++------ src/pwm.rs | 121 ++++++++++--------- src/pwr.rs | 92 ++++++++++----- src/qei.rs | 13 ++- src/rcc/backup.rs | 18 +-- src/rcc/mco.rs | 4 +- src/rcc/mod.rs | 134 ++++++++++----------- src/rcc/pll.rs | 50 ++++---- src/rcc/rec.rs | 142 +++++++++++------------ src/rcc/reset_reason.rs | 24 ++-- src/rng.rs | 6 +- src/rtc.rs | 217 ++++++++++++++++++----------------- src/sai/i2s.rs | 34 +++--- src/sai/mod.rs | 90 +++++++-------- src/sai/pdm.rs | 26 ++--- src/sdmmc.rs | 128 ++++++++++----------- src/serial.rs | 189 +++++++++++++++--------------- src/spi.rs | 208 +++++++++++++++++---------------- src/system_watchdog.rs | 34 ++++-- src/timer.rs | 188 +++++++++++++++--------------- src/usb_hs.rs | 16 +-- src/xspi/mod.rs | 80 ++++++------- src/xspi/octospi.rs | 44 +++---- src/xspi/qspi.rs | 30 ++--- 46 files changed, 1698 insertions(+), 1533 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index e2c1df3d..4ca12586 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -32,7 +32,8 @@ embedded-hal = { version = "0.2.6", features = ["unproven"] } embedded-dma = "0.2.0" cortex-m = { version = "^0.7.7", features = ["critical-section-single-core"] } defmt = { version = ">=0.2.0,<0.4", optional = true } -stm32h7 = { version = "^0.15.1", default-features = false } +#stm32h7 = { version = "^0.15.1", default-features = false } +stm32h7 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies", default-features = false } void = { version = "1.0.2", default-features = false } cast = { version = "0.3.0", default-features = false } nb = "1.0.0" diff --git a/src/adc.rs b/src/adc.rs index 5f1c6a9e..09026474 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -25,9 +25,9 @@ use crate::stm32::{ADC1, ADC2}; use crate::stm32::{ADC3, ADC3_COMMON}; #[cfg(feature = "rm0455")] -use crate::stm32::adc12_common::ccr::PRESC_A; +use crate::stm32::adc12_common::ccr::PRESC; #[cfg(not(feature = "rm0455"))] -use crate::stm32::adc3_common::ccr::PRESC_A; +use crate::stm32::adc3_common::ccr::PRESC; use crate::gpio::{self, Analog}; use crate::pwr::{current_vos, VoltageScale}; @@ -36,9 +36,9 @@ use crate::rcc::{rec, CoreClocks, ResetEnable}; use crate::time::Hertz; #[cfg(any(feature = "rm0433", feature = "rm0399"))] -pub type Resolution = crate::stm32::adc3::cfgr::RES_A; +pub type Resolution = crate::stm32::adc3::cfgr::RES; #[cfg(any(feature = "rm0455", feature = "rm0468"))] -pub type Resolution = crate::stm32::adc1::cfgr::RES_A; +pub type Resolution = crate::stm32::adc1::cfgr::RES; trait NumberOfBits { fn number_of_bits(&self) -> u32; @@ -214,7 +214,7 @@ macro_rules! adc_internal { let common = unsafe { &*$INT_ADC_COMMON::ptr() }; - common.ccr.modify(|_, w| w.$en().enabled()); + common.ccr().modify(|_, w| w.$en().enabled()); } /// Disables the internal voltage/sdissor /// ADC must be disabled. @@ -222,7 +222,7 @@ macro_rules! adc_internal { let common = unsafe { &*$INT_ADC_COMMON::ptr() }; - common.ccr.modify(|_, w| w.$en().disabled()); + common.ccr().modify(|_, w| w.$en().disabled()); } } @@ -598,23 +598,23 @@ macro_rules! adc_hal { let f_target = f_adc.raw(); let (divider, presc) = match ker_ck.raw().div_ceil(f_target) { - 1 => (1, PRESC_A::Div1), - 2 => (2, PRESC_A::Div2), - 3..=4 => (4, PRESC_A::Div4), - 5..=6 => (6, PRESC_A::Div6), - 7..=8 => (8, PRESC_A::Div8), - 9..=10 => (10, PRESC_A::Div10), - 11..=12 => (12, PRESC_A::Div12), - 13..=16 => (16, PRESC_A::Div16), - 17..=32 => (32, PRESC_A::Div32), - 33..=64 => (64, PRESC_A::Div64), - 65..=128 => (128, PRESC_A::Div128), - 129..=256 => (256, PRESC_A::Div256), + 1 => (1, PRESC::Div1), + 2 => (2, PRESC::Div2), + 3..=4 => (4, PRESC::Div4), + 5..=6 => (6, PRESC::Div6), + 7..=8 => (8, PRESC::Div8), + 9..=10 => (10, PRESC::Div10), + 11..=12 => (12, PRESC::Div12), + 13..=16 => (16, PRESC::Div16), + 17..=32 => (32, PRESC::Div32), + 33..=64 => (64, PRESC::Div64), + 65..=128 => (128, PRESC::Div128), + 129..=256 => (256, PRESC::Div256), _ => panic!("Selecting the ADC clock required a prescaler > 256, \ which is not possible in hardware. Either increase the ADC \ clock frequency or decrease the kernel clock frequency"), }; - unsafe { &*$ADC_COMMON::ptr() }.ccr.modify(|_, w| w.presc().variant(presc)); + unsafe { &*$ADC_COMMON::ptr() }.ccr().modify(|_, w| w.presc().variant(presc)); // Calculate actual value. See RM0433 Rev 7 - Figure 136. #[cfg(feature = "revision_v")] @@ -633,7 +633,7 @@ macro_rules! adc_hal { /// Note: After power-up, a [`calibration`](#method.calibrate) shall be run pub fn power_up(&mut self, delay: &mut impl DelayUs) { // Refer to RM0433 Rev 7 - Chapter 25.4.6 - self.rb.cr.modify(|_, w| + self.rb.cr().modify(|_, w| w.deeppwd().clear_bit() .advregen().set_bit() ); @@ -643,7 +643,7 @@ macro_rules! adc_hal { $( #[cfg(feature = "revision_v")] while { - let $ldordy = self.rb.isr.read().bits() & 0x1000; + let $ldordy = self.rb.isr().read().bits() & 0x1000; $ldordy == 0 }{} )* @@ -654,7 +654,7 @@ macro_rules! adc_hal { /// Note: This resets the [`calibration`](#method.calibrate) of the ADC pub fn power_down(&mut self) { // Refer to RM0433 Rev 7 - Chapter 25.4.6 - self.rb.cr.modify(|_, w| + self.rb.cr().modify(|_, w| w.deeppwd().set_bit() .advregen().clear_bit() ); @@ -668,17 +668,17 @@ macro_rules! adc_hal { self.check_calibration_conditions(); // single channel (INNx equals to V_ref-) - self.rb.cr.modify(|_, w| + self.rb.cr().modify(|_, w| w.adcaldif().clear_bit() .adcallin().set_bit() ); // calibrate - self.rb.cr.modify(|_, w| w.adcal().set_bit()); - while self.rb.cr.read().adcal().bit_is_set() {} + self.rb.cr().modify(|_, w| w.adcal().set_bit()); + while self.rb.cr().read().adcal().bit_is_set() {} } fn check_calibration_conditions(&self) { - let cr = self.rb.cr.read(); + let cr = self.rb.cr().read(); if cr.aden().bit_is_set() { panic!("Cannot start calibration when the ADC is enabled"); } @@ -699,14 +699,14 @@ macro_rules! adc_hal { /// Sets channels to single ended mode fn configure_channels_dif_mode(&mut self) { - self.rb.difsel.reset(); + self.rb.difsel().reset(); } /// Configuration process immediately after enabling the ADC fn configure(&mut self) { // Single conversion mode, Software trigger // Refer to RM0433 Rev 7 - Chapters 25.4.15, 25.4.19 - self.rb.cfgr.modify(|_, w| + self.rb.cfgr().modify(|_, w| w.cont().clear_bit() .exten().disabled() .discen().set_bit() @@ -716,9 +716,9 @@ macro_rules! adc_hal { // // Refer to RM0433 Rev 7 - Chapter 25.4.3 #[cfg(not(feature = "revision_v"))] - self.rb.cr.modify(|_, w| w.boost().set_bit()); + self.rb.cr().modify(|_, w| w.boost().set_bit()); #[cfg(feature = "revision_v")] - self.rb.cr.modify(|_, w| { + self.rb.cr().modify(|_, w| { if self.clock.raw() <= 6_250_000 { w.boost().lt6_25() } else if self.clock.raw() <= 12_500_000 { @@ -734,10 +734,10 @@ macro_rules! adc_hal { /// Enable ADC pub fn enable(mut self) -> Adc<$ADC, Enabled> { // Refer to RM0433 Rev 7 - Chapter 25.4.9 - self.rb.isr.modify(|_, w| w.adrdy().set_bit()); - self.rb.cr.modify(|_, w| w.aden().set_bit()); - while self.rb.isr.read().adrdy().bit_is_clear() {} - self.rb.isr.modify(|_, w| w.adrdy().set_bit()); + self.rb.isr().modify(|_, w| w.adrdy().set_bit()); + self.rb.cr().modify(|_, w| w.aden().set_bit()); + while self.rb.isr().read().adrdy().bit_is_clear() {} + self.rb.isr().modify(|_, w| w.adrdy().set_bit()); self.configure(); @@ -755,19 +755,20 @@ macro_rules! adc_hal { impl Adc<$ADC, Enabled> { fn stop_regular_conversion(&mut self) { - self.rb.cr.modify(|_, w| w.adstp().set_bit()); - while self.rb.cr.read().adstp().bit_is_set() {} + self.rb.cr().modify(|_, w| w.adstp().set_bit()); + while self.rb.cr().read().adstp().bit_is_set() {} } fn stop_injected_conversion(&mut self) { - self.rb.cr.modify(|_, w| w.jadstp().set_bit()); - while self.rb.cr.read().jadstp().bit_is_set() {} + self.rb.cr().modify(|_, w| w.jadstp().set_bit()); + while self.rb.cr().read().jadstp().bit_is_set() {} } fn set_chan_smp(&mut self, chan: u8) { let t = self.get_sample_time().into(); if chan <= 9 { - self.rb.smpr1.modify(|_, w| match chan { + //NOTE(unsafe) Only valid bit patterns written + self.rb.smpr1().modify(|_, w| unsafe { match chan { 0 => w.smp0().bits(t), 1 => w.smp1().bits(t), 2 => w.smp2().bits(t), @@ -779,9 +780,10 @@ macro_rules! adc_hal { 8 => w.smp8().bits(t), 9 => w.smp9().bits(t), _ => unreachable!(), - }) + }}); } else { - self.rb.smpr2.modify(|_, w| match chan { + //NOTE(unsafe) Only valid bit patterns written + self.rb.smpr2().modify(|_, w| unsafe { match chan { 10 => w.smp10().bits(t), 11 => w.smp11().bits(t), 12 => w.smp12().bits(t), @@ -793,7 +795,7 @@ macro_rules! adc_hal { 18 => w.smp18().bits(t), 19 => w.smp19().bits(t), _ => unreachable!(), - }) + }}); } } @@ -802,19 +804,22 @@ macro_rules! adc_hal { self.check_conversion_conditions(); // Set LSHIFT[3:0] - self.rb.cfgr2.modify(|_, w| w.lshift().bits(self.get_lshift().value())); + //NOTE(unsafe) Only valid bit patterns written + unsafe { + self.rb.cfgr2().modify(|_, w| w.lshift().bits(self.get_lshift().value())); + } // Select channel (with preselection, refer to RM0433 Rev 7 - Chapter 25.4.12) - self.rb.pcsel.modify(|r, w| unsafe { w.pcsel().bits(r.pcsel().bits() | (1 << chan)) }); + self.rb.pcsel().modify(|r, w| unsafe { w.pcsel().bits(r.pcsel().bits() | (1 << chan)) }); self.set_chan_smp(chan); - self.rb.sqr1.modify(|_, w| unsafe { + self.rb.sqr1().modify(|_, w| unsafe { w.sq1().bits(chan) .l().bits(0) }); self.current_channel = Some(chan); // Perform conversion - self.rb.cr.modify(|_, w| w.adstart().set_bit()); + self.rb.cr().modify(|_, w| w.adstart().set_bit()); } /// Start conversion @@ -829,9 +834,9 @@ macro_rules! adc_hal { assert!(chan <= 19); // Set resolution - self.rb.cfgr.modify(|_, w| unsafe { w.res().bits(self.get_resolution().into()) }); + self.rb.cfgr().modify(|_, w| unsafe { w.res().bits(self.get_resolution().into()) }); // Set discontinuous mode - self.rb.cfgr.modify(|_, w| w.cont().clear_bit().discen().set_bit()); + self.rb.cfgr().modify(|_, w| w.cont().clear_bit().discen().set_bit()); self.start_conversion_common(chan); } @@ -847,16 +852,19 @@ macro_rules! adc_hal { assert!(chan <= 19); // Set resolution - self.rb.cfgr.modify(|_, w| unsafe { w.res().bits(self.get_resolution().into()) }); + self.rb.cfgr().modify(|_, w| unsafe { w.res().bits(self.get_resolution().into()) }); - self.rb.cfgr.modify(|_, w| w.dmngt().bits(match mode { - AdcDmaMode::OneShot => 0b01, - AdcDmaMode::Circular => 0b11, - })); + //NOTE(unsafe) Only valid bit patterns written + unsafe { + self.rb.cfgr().modify(|_, w| w.dmngt().bits(match mode { + AdcDmaMode::OneShot => 0b01, + AdcDmaMode::Circular => 0b11, + })); + } // Set continuous mode - self.rb.cfgr.modify(|_, w| w.cont().set_bit().discen().clear_bit() ); + self.rb.cfgr().modify(|_, w| w.cont().set_bit().discen().clear_bit() ); self.start_conversion_common(chan); } @@ -871,21 +879,21 @@ macro_rules! adc_hal { let chan = self.current_channel.expect("No channel was selected, use start_conversion first"); // Check if the conversion is finished - if self.rb.isr.read().eoc().bit_is_clear() { + if self.rb.isr().read().eoc().bit_is_clear() { return Err(nb::Error::WouldBlock); } // Disable preselection of this channel, refer to RM0433 Rev 7 - Chapter 25.4.12 - self.rb.pcsel.modify(|r, w| unsafe { w.pcsel().bits(r.pcsel().bits() & !(1 << chan)) }); + self.rb.pcsel().modify(|r, w| unsafe { w.pcsel().bits(r.pcsel().bits() & !(1 << chan)) }); self.current_channel = None; // Retrieve result - let result = self.rb.dr.read().bits(); + let result = self.rb.dr().read().bits(); nb::Result::Ok(result) } fn check_conversion_conditions(&self) { - let cr = self.rb.cr.read(); + let cr = self.rb.cr().read(); // Ensure that no conversions are ongoing if cr.adstart().bit_is_set() { panic!("Cannot start conversion because a regular conversion is ongoing"); @@ -904,7 +912,7 @@ macro_rules! adc_hal { /// Disable ADC pub fn disable(mut self) -> Adc<$ADC, Disabled> { - let cr = self.rb.cr.read(); + let cr = self.rb.cr().read(); // Refer to RM0433 Rev 7 - Chapter 25.4.9 if cr.adstart().bit_is_set() { self.stop_regular_conversion(); @@ -913,8 +921,8 @@ macro_rules! adc_hal { self.stop_injected_conversion(); } - self.rb.cr.modify(|_, w| w.addis().set_bit()); - while self.rb.cr.read().aden().bit_is_set() {} + self.rb.cr().modify(|_, w| w.addis().set_bit()); + while self.rb.cr().read().aden().bit_is_set() {} Adc { rb: self.rb, @@ -1043,7 +1051,7 @@ macro_rules! adc_hal { /// Returns the offset calibration value for single ended channel pub fn read_offset_calibration_value(&self) -> AdcCalOffset { - AdcCalOffset(self.rb.calfact.read().calfact_s().bits()) + AdcCalOffset(self.rb.calfact().read().calfact_s().bits()) } /// Returns the linear calibration values stored in an array in the following order: @@ -1055,40 +1063,40 @@ macro_rules! adc_hal { self.check_linear_read_conditions(); // Read 1st block of linear correction - self.rb.cr.modify(|_, w| w.lincalrdyw1().clear_bit()); - while self.rb.cr.read().lincalrdyw1().bit_is_set() {} - let res_1 = self.rb.calfact2.read().lincalfact().bits(); + self.rb.cr().modify(|_, w| w.lincalrdyw1().clear_bit()); + while self.rb.cr().read().lincalrdyw1().bit_is_set() {} + let res_1 = self.rb.calfact2().read().lincalfact().bits(); // Read 2nd block of linear correction - self.rb.cr.modify(|_, w| w.lincalrdyw2().clear_bit()); - while self.rb.cr.read().lincalrdyw2().bit_is_set() {} - let res_2 = self.rb.calfact2.read().lincalfact().bits(); + self.rb.cr().modify(|_, w| w.lincalrdyw2().clear_bit()); + while self.rb.cr().read().lincalrdyw2().bit_is_set() {} + let res_2 = self.rb.calfact2().read().lincalfact().bits(); // Read 3rd block of linear correction - self.rb.cr.modify(|_, w| w.lincalrdyw3().clear_bit()); - while self.rb.cr.read().lincalrdyw3().bit_is_set() {} - let res_3 = self.rb.calfact2.read().lincalfact().bits(); + self.rb.cr().modify(|_, w| w.lincalrdyw3().clear_bit()); + while self.rb.cr().read().lincalrdyw3().bit_is_set() {} + let res_3 = self.rb.calfact2().read().lincalfact().bits(); // Read 4th block of linear correction - self.rb.cr.modify(|_, w| w.lincalrdyw4().clear_bit()); - while self.rb.cr.read().lincalrdyw4().bit_is_set() {} - let res_4 = self.rb.calfact2.read().lincalfact().bits(); + self.rb.cr().modify(|_, w| w.lincalrdyw4().clear_bit()); + while self.rb.cr().read().lincalrdyw4().bit_is_set() {} + let res_4 = self.rb.calfact2().read().lincalfact().bits(); // Read 5th block of linear correction - self.rb.cr.modify(|_, w| w.lincalrdyw5().clear_bit()); - while self.rb.cr.read().lincalrdyw5().bit_is_set() {} - let res_5 = self.rb.calfact2.read().lincalfact().bits(); + self.rb.cr().modify(|_, w| w.lincalrdyw5().clear_bit()); + while self.rb.cr().read().lincalrdyw5().bit_is_set() {} + let res_5 = self.rb.calfact2().read().lincalfact().bits(); // Read 6th block of linear correction - self.rb.cr.modify(|_, w| w.lincalrdyw6().clear_bit()); - while self.rb.cr.read().lincalrdyw6().bit_is_set() {} - let res_6 = self.rb.calfact2.read().lincalfact().bits(); + self.rb.cr().modify(|_, w| w.lincalrdyw6().clear_bit()); + while self.rb.cr().read().lincalrdyw6().bit_is_set() {} + let res_6 = self.rb.calfact2().read().lincalfact().bits(); AdcCalLinear([res_1, res_2, res_3, res_4, res_5, res_6]) } fn check_linear_read_conditions(&self) { - let cr = self.rb.cr.read(); + let cr = self.rb.cr().read(); // Ensure the ADC is enabled and is not in deeppowerdown-mode if cr.deeppwd().bit_is_set() { panic!("Cannot read linear calibration value when the ADC is in deeppowerdown-mode"); diff --git a/src/can.rs b/src/can.rs index 0e30e3b9..38091200 100644 --- a/src/can.rs +++ b/src/can.rs @@ -94,15 +94,15 @@ macro_rules! message_ram_layout { let mut word_adr: u16 = $start_word_addr; // 11-bit filter - $can.sidfc + $can.sidfc() .modify(|_, w| unsafe { w.flssa().bits(word_adr) }); word_adr += STANDARD_FILTER_MAX as u16; // 29-bit filter - $can.xidfc + $can.xidfc() .modify(|_, w| unsafe { w.flesa().bits(word_adr) }); word_adr += 2 * EXTENDED_FILTER_MAX as u16; // Rx FIFO 0 - $can.rxf0c.modify(|_, w| unsafe { + $can.rxf0c().modify(|_, w| unsafe { w.f0sa() .bits(word_adr) .f0s() @@ -112,7 +112,7 @@ macro_rules! message_ram_layout { }); word_adr += 18 * RX_FIFO_MAX as u16; // Rx FIFO 1 - $can.rxf1c.modify(|_, w| unsafe { + $can.rxf1c().modify(|_, w| unsafe { w.f1sa() .bits(word_adr) .f1s() @@ -123,7 +123,7 @@ macro_rules! message_ram_layout { word_adr += 18 * RX_FIFO_MAX as u16; // Rx buffer - see below // Tx event FIFO - $can.txefc.modify(|_, w| unsafe { + $can.txefc().modify(|_, w| unsafe { w.efsa() .bits(word_adr) .efs() @@ -133,22 +133,23 @@ macro_rules! message_ram_layout { }); word_adr += 2 * TX_EVENT_MAX as u16; // Tx buffers - $can.txbc.modify(|_, w| unsafe { + $can.txbc().modify(|_, w| unsafe { w.tbsa().bits(word_adr).tfqs().bits(TX_FIFO_MAX) }); word_adr += 18 * TX_FIFO_MAX as u16; // Rx Buffer - not used - $can.rxbc.modify(|_, w| unsafe { w.rbsa().bits(word_adr) }); + $can.rxbc() + .modify(|_, w| unsafe { w.rbsa().bits(word_adr) }); // TX event FIFO? // Trigger memory? // Set the element sizes to 16 bytes - $can.rxesc.modify(|_, w| unsafe { + $can.rxesc().modify(|_, w| unsafe { w.rbds().bits(0b111).f1ds().bits(0b111).f0ds().bits(0b111) }); - $can.txesc.modify(|_, w| unsafe { w.tbds().bits(0b111) }); + $can.txesc().modify(|_, w| unsafe { w.tbds().bits(0b111) }); }; } diff --git a/src/crc.rs b/src/crc.rs index 41af5e96..bf688600 100644 --- a/src/crc.rs +++ b/src/crc.rs @@ -37,7 +37,8 @@ impl Crc { // manual says unit must be reset (or DR read) before change of polynomial // (technically only in case of ongoing calculation, but DR is buffered) - self.reg.cr.modify(|_, w| { + //NOTE(unsafe) Only valid bit patterns are written + self.reg.cr().modify(|_, w| unsafe { w.polysize() .bits(config.poly.polysize()) .rev_in() @@ -47,8 +48,14 @@ impl Crc { .reset() .set_bit() }); - self.reg.pol.write(|w| w.pol().bits(config.poly.pol())); - self.reg.init.write(|w| w.init().bits(config.initial)); + //NOTE(unsafe) All bit patterns are valid + self.reg + .pol() + .write(|w| unsafe { w.pol().bits(config.poly.pol()) }); + //NOTE(unsafe) All bit patterns are valid + self.reg + .init() + .write(|w| unsafe { w.init().bits(config.initial) }); // writing to INIT sets DR to its value } @@ -60,18 +67,23 @@ impl Crc { let mut words = data.chunks_exact(4); for word in words.by_ref() { let word = u32::from_be_bytes(word.try_into().unwrap()); - self.reg.dr().write(|w| w.dr().bits(word)); + //NOTE(unsafe) All bit patterns are valid + self.reg.dr().write(|w| unsafe { w.dr().bits(word) }); } // there will be at most 3 bytes remaining, so 1 half-word and 1 byte let mut half_word = words.remainder().chunks_exact(2); if let Some(half_word) = half_word.next() { let half_word = u16::from_be_bytes(half_word.try_into().unwrap()); - self.reg.dr16().write(|w| w.dr16().bits(half_word)); + //NOTE(unsafe) All bit patterns are valid + self.reg + .dr16() + .write(|w| unsafe { w.dr16().bits(half_word) }); } if let Some(byte) = half_word.remainder().first() { - self.reg.dr8().write(|w| w.dr8().bits(*byte)); + //NOTE(unsafe) All bit patterns are valid + self.reg.dr8().write(|w| unsafe { w.dr8().bits(*byte) }); } } @@ -87,7 +99,7 @@ impl Crc { /// This does not reset the configuration options. pub fn finish(&mut self) -> u32 { let result = self.read_crc(); - self.reg.cr.modify(|_, w| w.reset().set_bit()); + self.reg.cr().modify(|_, w| w.reset().set_bit()); result } @@ -105,7 +117,7 @@ impl Crc { /// algorithm that does not apply an output XOR or reverse the output bits. pub fn read_state(&self) -> u32 { let state = self.read_crc_no_xor(); - if self.reg.cr.read().rev_out().is_reversed() { + if self.reg.cr().read().rev_out().is_reversed() { state.reverse_bits() } else { state @@ -123,14 +135,15 @@ impl Crc { /// /// The IDR is not involved with CRC calculation. pub fn set_idr(&mut self, value: u32) { - self.reg.idr.write(|w| w.idr().bits(value)); + //NOTE(unsafe) All bit patterns are valid + self.reg.idr().write(|w| unsafe { w.idr().bits(value) }); } /// Get the current value of the independent data register. /// /// The IDR is not involved with CRC calculation. pub fn get_idr(&self) -> u32 { - self.reg.idr.read().idr().bits() + self.reg.idr().read().idr().bits() } /// Returns a reference to the inner peripheral @@ -226,10 +239,10 @@ impl Polynomial { /// Return POLYSIZE register value. const fn polysize(self) -> u8 { (match self.0 { - Poly::B7(_) => crc::cr::POLYSIZE_A::Polysize7, - Poly::B8(_) => crc::cr::POLYSIZE_A::Polysize8, - Poly::B16(_) => crc::cr::POLYSIZE_A::Polysize16, - Poly::B32(_) => crc::cr::POLYSIZE_A::Polysize32, + Poly::B7(_) => crc::cr::POLYSIZE::Polysize7, + Poly::B8(_) => crc::cr::POLYSIZE::Polysize8, + Poly::B16(_) => crc::cr::POLYSIZE::Polysize16, + Poly::B32(_) => crc::cr::POLYSIZE::Polysize32, }) as u8 } @@ -307,11 +320,11 @@ enum Poly { #[repr(u8)] pub enum BitReversal { /// Each input byte has its bits reversed. `0x1A2B3C4D` becomes `0x58D43CB2`. - Byte = crc::cr::REV_IN_A::Byte as u8, + Byte = crc::cr::REV_IN::Byte as u8, /// Bits reversed by half-word. `0x1A2B3C4D` becomes `0xD458B23C`. - HalfWord = crc::cr::REV_IN_A::HalfWord as u8, + HalfWord = crc::cr::REV_IN::HalfWord as u8, /// Bits reversed by word. `0x1A2B3C4D` becomes `0xB23CD458`. - Word = crc::cr::REV_IN_A::Word as u8, + Word = crc::cr::REV_IN::Word as u8, } /// CRC unit configuration. @@ -368,7 +381,7 @@ impl Config { fn get_reverse_input(&self) -> u8 { self.reverse_input .map(|rev| rev as u8) - .unwrap_or(crc::cr::REV_IN_A::Normal as u8) + .unwrap_or(crc::cr::REV_IN::Normal as u8) } /// Set whether to reverse the bits of the output. diff --git a/src/dac.rs b/src/dac.rs index 0617739b..a6233a39 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -88,8 +88,8 @@ macro_rules! dac { pub fn enable(self) -> $CX<$DAC, Enabled> { let dac = unsafe { &(*$DAC::ptr()) }; - dac.mcr.modify(|_, w| unsafe { w.$mode().bits(0) }); - dac.cr.modify(|_, w| w.$en().set_bit()); + dac.mcr().modify(|_, w| unsafe { w.$mode().bits(0) }); + dac.cr().modify(|_, w| w.$en().set_bit()); $CX { _dac: PhantomData, @@ -100,8 +100,8 @@ macro_rules! dac { pub fn enable_unbuffered(self) -> $CX<$DAC, EnabledUnbuffered> { let dac = unsafe { &(*$DAC::ptr()) }; - dac.mcr.modify(|_, w| unsafe { w.$mode().bits(2) }); - dac.cr.modify(|_, w| w.$en().set_bit()); + dac.mcr().modify(|_, w| unsafe { w.$mode().bits(2) }); + dac.cr().modify(|_, w| w.$en().set_bit()); $CX { _dac: PhantomData, @@ -130,19 +130,19 @@ macro_rules! dac { T: DelayUs, { let dac = unsafe { &(*$DAC::ptr()) }; - dac.cr.modify(|_, w| w.$en().clear_bit()); - dac.mcr.modify(|_, w| unsafe { w.$mode().bits(0) }); - dac.cr.modify(|_, w| w.$cen().set_bit()); + dac.cr().modify(|_, w| w.$en().clear_bit()); + dac.mcr().modify(|_, w| unsafe { w.$mode().bits(0) }); + dac.cr().modify(|_, w| w.$cen().set_bit()); let mut trim = 0; while true { - dac.ccr.modify(|_, w| unsafe { w.$trim().bits(trim) }); + dac.ccr().modify(|_, w| unsafe { w.$trim().bits(trim) }); delay.delay_us(64_u32); - if dac.sr.read().$cal_flag().bit() { + if dac.sr().read().$cal_flag().bit() { break; } trim += 1; } - dac.cr.modify(|_, w| w.$cen().clear_bit()); + dac.cr().modify(|_, w| w.$cen().clear_bit()); $CX { _dac: PhantomData, @@ -153,7 +153,7 @@ macro_rules! dac { /// Disable the DAC channel pub fn disable(self) -> $CX<$DAC, Disabled> { let dac = unsafe { &(*$DAC::ptr()) }; - dac.cr.modify(|_, w| w.$en().clear_bit()); + dac.cr().modify(|_, w| w.$en().clear_bit()); $CX { _dac: PhantomData, @@ -166,12 +166,12 @@ macro_rules! dac { impl DacOut for $CX<$DAC, ED> { fn set_value(&mut self, val: u16) { let dac = unsafe { &(*$DAC::ptr()) }; - dac.$dhrx.write(|w| unsafe { w.bits(val as u32) }); + dac.$dhrx().write(|w| unsafe { w.bits(val as u32) }); } fn get_value(&mut self) -> u16 { let dac = unsafe { &(*$DAC::ptr()) }; - dac.$dor.read().bits() as u16 + dac.$dor().read().bits() as u16 } } }; diff --git a/src/dma/bdma.rs b/src/dma/bdma.rs index f2b560e6..f01501c3 100644 --- a/src/dma/bdma.rs +++ b/src/dma/bdma.rs @@ -265,11 +265,11 @@ trait InstanceStream { impl StreamX { unsafe fn stream() -> &'static BDMAStream { - &(*I::ptr()).ch[S as usize] + &(*I::ptr()).ch(S as usize) } unsafe fn dmamux_ccr() -> &'static pac::dmamux2::CCR { let dmamux = &*I::mux_ptr(); - &dmamux.ccr[S as usize + I::DMA_MUX_STREAM_OFFSET] + &dmamux.ccr(S as usize + I::DMA_MUX_STREAM_OFFSET) } } @@ -318,12 +318,12 @@ where #[inline(always)] unsafe fn enable(&mut self) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::stream().cr.modify(|_, w| w.en().set_bit()); + Self::stream().cr().modify(|_, w| w.en().set_bit()); } #[inline(always)] fn is_enabled() -> bool { //NOTE(unsafe) Atomic read with no side effects - unsafe { Self::stream() }.cr.read().en().bit_is_set() + unsafe { Self::stream() }.cr().read().en().bit_is_set() } fn disable(&mut self) { if Self::is_enabled() { @@ -334,7 +334,7 @@ where //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::stream() } - .cr + .cr() .modify(|_, w| w.en().clear_bit()); while Self::is_enabled() {} @@ -353,15 +353,18 @@ where #[inline(always)] fn set_priority(&mut self, priority: config::Priority) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() } - .cr - .modify(|_, w| w.pl().bits(priority.bits())); + //NOTE(unsafe) We only write valid bit patterns + unsafe { + Self::stream() + .cr() + .modify(|_, w| w.pl().bits(priority.bits())); + } } #[inline(always)] fn disable_interrupts(&mut self) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmacr = &unsafe { Self::stream() }.cr; + let dmacr = &unsafe { Self::stream() }.cr(); dmacr.modify(|_, w| { w.tcie().clear_bit().teie().clear_bit().htie().clear_bit() }); @@ -371,7 +374,7 @@ where #[inline(always)] fn enable_interrupts(&mut self, interrupt: Self::Interrupts) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() }.cr.modify(|_, w| { + unsafe { Self::stream() }.cr().modify(|_, w| { w.tcie() .bit(interrupt.transfer_complete) .teie() @@ -384,7 +387,7 @@ where #[inline(always)] fn get_interrupts_enable() -> Self::Interrupts { //NOTE(unsafe) We only access the registers that belongs to the StreamX - let cr = unsafe { Self::stream() }.cr.read(); + let cr = unsafe { Self::stream() }.cr().read(); BdmaInterrupts { transfer_complete: cr.tcie().bit_is_set(), @@ -399,7 +402,7 @@ where transfer_complete_interrupt: bool, ) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmacr = &unsafe { Self::stream() }.cr; + let dmacr = &unsafe { Self::stream() }.cr(); dmacr.modify(|_, w| w.tcie().bit(transfer_complete_interrupt)); let _ = dmacr.read(); let _ = dmacr.read(); // Delay 2 peripheral clocks @@ -410,7 +413,7 @@ where transfer_error_interrupt: bool, ) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmacr = &unsafe { Self::stream() }.cr; + let dmacr = &unsafe { Self::stream() }.cr(); dmacr.modify(|_, w| w.teie().bit(transfer_error_interrupt)); let _ = dmacr.read(); let _ = dmacr.read(); // Delay 2 peripheral clocks @@ -424,7 +427,7 @@ where #[inline(always)] unsafe fn set_peripheral_address(&mut self, value: usize) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::stream().par.write(|w| w.pa().bits(value as u32)); + Self::stream().par().write(|w| w.pa().bits(value as u32)); } #[inline(always)] @@ -436,10 +439,10 @@ where //NOTE(unsafe) We only access the registers that belongs to the StreamX match buffer { CurrentBuffer::Buffer0 => { - Self::stream().m0ar.write(|w| w.ma().bits(value as u32)) + Self::stream().m0ar().write(|w| w.ma().bits(value as u32)); } CurrentBuffer::Buffer1 => { - Self::stream().m1ar.write(|w| w.ma().bits(value as u32)) + Self::stream().m1ar().write(|w| w.ma().bits(value as u32)); } } } @@ -449,10 +452,10 @@ where //NOTE(unsafe) We only access the registers that belongs to the StreamX let addr = match buffer { CurrentBuffer::Buffer0 => { - unsafe { Self::stream() }.m0ar.read().ma().bits() + unsafe { Self::stream() }.m0ar().read().ma().bits() } CurrentBuffer::Buffer1 => { - unsafe { Self::stream() }.m1ar.read().ma().bits() + unsafe { Self::stream() }.m1ar().read().ma().bits() } }; addr as usize @@ -461,32 +464,33 @@ where #[inline(always)] fn set_number_of_transfers(&mut self, value: u16) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() } - .ndtr - .write(|w| w.ndt().bits(value)); + //NOTE(unsafe) All bit patterns are valid for ndt + unsafe { + Self::stream().ndtr().write(|w| w.ndt().bits(value)); + } } #[inline(always)] fn get_number_of_transfers() -> u16 { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() }.ndtr.read().ndt().bits() + unsafe { Self::stream() }.ndtr().read().ndt().bits() } #[inline(always)] unsafe fn set_memory_size(&mut self, size: u8) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::stream().cr.modify(|_, w| w.msize().bits(size)); + Self::stream().cr().modify(|_, w| w.msize().bits(size)); } #[inline(always)] unsafe fn set_peripheral_size(&mut self, size: u8) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::stream().cr.modify(|_, w| w.psize().bits(size)); + Self::stream().cr().modify(|_, w| w.psize().bits(size)); } #[inline(always)] fn set_memory_increment(&mut self, increment: bool) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::stream() } - .cr + .cr() .modify(|_, w| w.minc().bit(increment)); } @@ -494,24 +498,26 @@ where fn set_peripheral_increment(&mut self, increment: bool) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::stream() } - .cr + .cr() .modify(|_, w| w.pinc().bit(increment)); } #[inline(always)] fn set_direction(&mut self, direction: DmaDirection) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() }.cr.modify(|_, w| match direction { - DmaDirection::PeripheralToMemory => { - w.dir().peripheral_to_memory().mem2mem().disabled() - } - DmaDirection::MemoryToPeripheral => { - w.dir().memory_to_peripheral().mem2mem().disabled() - } - DmaDirection::MemoryToMemory => { - w.mem2mem().enabled().dir().clear_bit() - } - }); + unsafe { Self::stream() } + .cr() + .modify(|_, w| match direction { + DmaDirection::PeripheralToMemory => { + w.dir().peripheral_to_memory().mem2mem().disabled() + } + DmaDirection::MemoryToPeripheral => { + w.dir().memory_to_peripheral().mem2mem().disabled() + } + DmaDirection::MemoryToMemory => { + w.mem2mem().enabled().dir().clear_bit() + } + }); } #[inline(always)] @@ -524,7 +530,7 @@ where fn set_circular_buffer(&mut self, circular_buffer: bool) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::stream() } - .cr + .cr() .modify(|_, w| w.circ().bit(circular_buffer)); } @@ -532,14 +538,14 @@ where fn set_double_buffer(&mut self, double_buffer: bool) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::stream() } - .cr + .cr() .modify(|_, w| w.dbm().bit(double_buffer)); } #[inline(always)] fn get_current_buffer() -> CurrentBuffer { //NOTE(unsafe) Atomic read with no side effects - if unsafe { Self::stream() }.cr.read().ct().bit_is_set() { + if unsafe { Self::stream() }.cr().read().ct().bit_is_set() { CurrentBuffer::Buffer0 } else { CurrentBuffer::Buffer1 @@ -549,7 +555,7 @@ where #[inline(always)] fn get_inactive_buffer() -> Option { //NOTE(unsafe) Atomic read with no side effects - let cr = unsafe { Self::stream() }.cr.read(); + let cr = unsafe { Self::stream() }.cr().read(); if cr.dbm().bit_is_set() { Some(if cr.ct().bit_is_set() { CurrentBuffer::Buffer0 @@ -567,7 +573,7 @@ where half_transfer_interrupt: bool, ) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmacr = &unsafe { Self::stream() }.cr; + let dmacr = &unsafe { Self::stream() }.cr(); dmacr.modify(|_, w| w.htie().bit(half_transfer_interrupt)); let _ = dmacr.read(); let _ = dmacr.read(); // Delay 2 peripheral clocks @@ -599,14 +605,14 @@ macro_rules! bdma_stream { //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX let dma = unsafe { &*I::ptr() }; - dma.$ifcr.write(|w| w + dma.$ifcr().write(|w| w .$tcif().set_bit() //Clear transfer complete interrupt flag .$htif().set_bit() //Clear half transfer interrupt flag .$teif().set_bit() //Clear transfer error interrupt flag .$gif().set_bit() //Clear global interrupt flag ); - let _ = dma.$isr.read(); - let _ = dma.$isr.read(); // Delay 2 peripheral clocks + let _ = dma.$isr().read(); + let _ = dma.$isr().read(); // Delay 2 peripheral clocks } #[inline(always)] @@ -614,7 +620,7 @@ macro_rules! bdma_stream { //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX let dma = unsafe { &*I::ptr() }; - dma.$ifcr.write(|w| w.$tcif().set_bit()); + dma.$ifcr().write(|w| w.$tcif().set_bit()); } #[inline(always)] @@ -622,8 +628,8 @@ macro_rules! bdma_stream { self.stream_clear_transfer_complete_flag(); //NOTE(unsafe) Atomic read with no side-effects. let dma = unsafe { &*I::ptr() }; - let _ = dma.$isr.read(); - let _ = dma.$isr.read(); // Delay 2 peripheral clocks + let _ = dma.$isr().read(); + let _ = dma.$isr().read(); // Delay 2 peripheral clocks } #[inline(always)] @@ -631,23 +637,23 @@ macro_rules! bdma_stream { //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX let dma = unsafe { &*I::ptr() }; - dma.$ifcr.write(|w| w.$teif().set_bit()); - let _ = dma.$isr.read(); - let _ = dma.$isr.read(); // Delay 2 peripheral clocks + dma.$ifcr().write(|w| w.$teif().set_bit()); + let _ = dma.$isr().read(); + let _ = dma.$isr().read(); // Delay 2 peripheral clocks } #[inline(always)] fn stream_get_transfer_complete_flag() -> bool { //NOTE(unsafe) Atomic read with no side effects let dma = unsafe { &*I::ptr() }; - dma.$isr.read().$tcisr().bit_is_set() + dma.$isr().read().$tcisr().bit_is_set() } #[inline(always)] fn stream_get_half_transfer_flag() -> bool { //NOTE(unsafe) Atomic read with no side effects let dma = unsafe { &*I::ptr() }; - dma.$isr.read().$htisr().bit_is_set() + dma.$isr().read().$htisr().bit_is_set() } #[inline(always)] @@ -655,9 +661,9 @@ macro_rules! bdma_stream { //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX let dma = unsafe { &*I::ptr() }; - dma.$ifcr.write(|w| w.$htif().set_bit()); - let _ = dma.$isr.read(); - let _ = dma.$isr.read(); // Delay 2 peripheral clocks + dma.$ifcr().write(|w| w.$htif().set_bit()); + let _ = dma.$isr().read(); + let _ = dma.$isr().read(); // Delay 2 peripheral clocks } } )+ @@ -740,7 +746,7 @@ bdma_stream!( /// Type alias for the DMA Request Multiplexer /// -pub type DMAReq = pac::dmamux2::ccr::DMAREQ_ID_A; +pub type DMAReq = pac::dmamux2::ccr::DMAREQ_ID; type P2M = PeripheralToMemory; type M2P = MemoryToPeripheral; diff --git a/src/dma/dma.rs b/src/dma/dma.rs index 4d901891..1cd433a9 100644 --- a/src/dma/dma.rs +++ b/src/dma/dma.rs @@ -342,19 +342,22 @@ trait InstanceStream { impl StreamX { unsafe fn stream() -> &'static pac::dma1::ST { - &(*I::ptr()).st[S as usize] + &(*I::ptr()).st(S as usize) } unsafe fn dmamux_ccr() -> &'static pac::dmamux1::CCR { let dmamux = &*I::mux_ptr(); - &dmamux.ccr[S as usize + I::DMA_MUX_STREAM_OFFSET] + &dmamux.ccr(S as usize + I::DMA_MUX_STREAM_OFFSET) } #[inline(always)] fn set_fifo_threshold(&mut self, fifo_threshold: config::FifoThreshold) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() } - .fcr - .modify(|_, w| w.fth().bits(fifo_threshold.bits())); + //NOTE(unsafe) We only write valid bit patterns + unsafe { + Self::stream() + .fcr() + .modify(|_, w| w.fth().bits(fifo_threshold.bits())); + } } #[inline(always)] @@ -362,30 +365,36 @@ impl StreamX { //NOTE(unsafe) We only access the registers that belongs to the StreamX //Register is actually direct mode disable rather than fifo enable unsafe { Self::stream() } - .fcr + .fcr() .modify(|_, w| w.dmdis().bit(fifo_enable)); } #[inline(always)] fn set_memory_burst(&mut self, memory_burst: config::BurstMode) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() } - .cr - .modify(|_, w| w.mburst().bits(memory_burst.bits())); + //NOTE(unsafe) We only write valid bit patterns + unsafe { + Self::stream() + .cr() + .modify(|_, w| w.mburst().bits(memory_burst.bits())); + } } #[inline(always)] fn set_peripheral_burst(&mut self, peripheral_burst: config::BurstMode) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() } - .cr - .modify(|_, w| w.pburst().bits(peripheral_burst.bits())); + //NOTE(unsafe) We only write valid bit patterns + unsafe { + Self::stream() + .cr() + .modify(|_, w| w.pburst().bits(peripheral_burst.bits())); + } } #[inline(always)] pub fn fifo_level() -> FifoLevel { //NOTE(unsafe) Atomic read with no side effects - unsafe { Self::stream() }.fcr.read().fs().bits().into() + unsafe { Self::stream() }.fcr().read().fs().bits().into() } #[inline(always)] @@ -394,7 +403,7 @@ impl StreamX { direct_mode_error_interrupt: bool, ) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmacr = &unsafe { Self::stream() }.cr; + let dmacr = &unsafe { Self::stream() }.cr(); dmacr.modify(|_, w| w.dmeie().bit(direct_mode_error_interrupt)); let _ = dmacr.read(); let _ = dmacr.read(); // Delay 2 peripheral clocks @@ -406,7 +415,7 @@ impl StreamX { fifo_error_interrupt: bool, ) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmafcr = &unsafe { Self::stream() }.fcr; + let dmafcr = &unsafe { Self::stream() }.fcr(); dmafcr.modify(|_, w| w.feie().bit(fifo_error_interrupt)); let _ = dmafcr.read(); let _ = dmafcr.read(); // Delay 2 peripheral clocks @@ -467,13 +476,13 @@ where #[inline(always)] unsafe fn enable(&mut self) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::stream().cr.modify(|_, w| w.en().set_bit()); + Self::stream().cr().modify(|_, w| w.en().set_bit()); } #[inline(always)] fn is_enabled() -> bool { //NOTE(unsafe) Atomic read with no side effects - unsafe { Self::stream() }.cr.read().en().bit_is_set() + unsafe { Self::stream() }.cr().read().en().bit_is_set() } fn disable(&mut self) { @@ -485,7 +494,7 @@ where //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::stream() } - .cr + .cr() .modify(|_, w| w.en().clear_bit()); while Self::is_enabled() {} @@ -505,15 +514,18 @@ where #[inline(always)] fn set_priority(&mut self, priority: config::Priority) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() } - .cr - .modify(|_, w| w.pl().bits(priority.bits())); + //NOTE(unsafe) We only write valid bit patterns + unsafe { + Self::stream() + .cr() + .modify(|_, w| w.pl().bits(priority.bits())); + } } #[inline(always)] fn disable_interrupts(&mut self) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() }.cr.modify(|_, w| { + unsafe { Self::stream() }.cr().modify(|_, w| { w.tcie() .clear_bit() .teie() @@ -523,7 +535,7 @@ where .dmeie() .clear_bit() }); - let dmafcr = &unsafe { Self::stream() }.fcr; + let dmafcr = &unsafe { Self::stream() }.fcr(); dmafcr.modify(|_, w| w.feie().clear_bit()); let _ = dmafcr.read(); let _ = dmafcr.read(); // Delay 2 peripheral clocks @@ -532,7 +544,7 @@ where #[inline(always)] fn enable_interrupts(&mut self, interrupt: DmaInterrupts) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() }.cr.modify(|_, w| { + unsafe { Self::stream() }.cr().modify(|_, w| { w.tcie() .bit(interrupt.transfer_complete) .htie() @@ -543,15 +555,15 @@ where .bit(interrupt.direct_mode_error) }); unsafe { Self::stream() } - .fcr + .fcr() .modify(|_, w| w.feie().bit(interrupt.fifo_error)); } #[inline(always)] fn get_interrupts_enable() -> DmaInterrupts { //NOTE(unsafe) We only access the registers that belongs to the StreamX - let cr = unsafe { Self::stream() }.cr.read(); - let fcr = unsafe { Self::stream() }.fcr.read(); + let cr = unsafe { Self::stream() }.cr().read(); + let fcr = unsafe { Self::stream() }.fcr().read(); DmaInterrupts { transfer_complete: cr.tcie().bit_is_set(), @@ -568,7 +580,7 @@ where transfer_complete_interrupt: bool, ) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmacr = &unsafe { Self::stream() }.cr; + let dmacr = &unsafe { Self::stream() }.cr(); dmacr.modify(|_, w| w.tcie().bit(transfer_complete_interrupt)); let _ = dmacr.read(); let _ = dmacr.read(); // Delay 2 peripheral clocks @@ -580,7 +592,7 @@ where transfer_error_interrupt: bool, ) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmacr = &unsafe { Self::stream() }.cr; + let dmacr = &unsafe { Self::stream() }.cr(); dmacr.modify(|_, w| w.teie().bit(transfer_error_interrupt)); let _ = dmacr.read(); let _ = dmacr.read(); // Delay 2 peripheral clocks @@ -594,7 +606,7 @@ where #[inline(always)] unsafe fn set_peripheral_address(&mut self, value: usize) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::stream().par.write(|w| w.pa().bits(value as u32)); + Self::stream().par().write(|w| w.pa().bits(value as u32)); } #[inline(always)] @@ -606,12 +618,12 @@ where //NOTE(unsafe) We only access the registers that belongs to the StreamX match buffer { CurrentBuffer::Buffer0 => { - Self::stream().m0ar.write(|w| w.m0a().bits(value as u32)) + Self::stream().m0ar().write(|w| w.m0a().bits(value as u32)) } CurrentBuffer::Buffer1 => { - Self::stream().m1ar.write(|w| w.m1a().bits(value as u32)) + Self::stream().m1ar().write(|w| w.m1a().bits(value as u32)) } - } + }; } #[inline(always)] @@ -619,10 +631,10 @@ where //NOTE(unsafe) We only access the registers that belongs to the StreamX let addr = match buffer { CurrentBuffer::Buffer0 => { - unsafe { Self::stream() }.m0ar.read().m0a().bits() + unsafe { Self::stream() }.m0ar().read().m0a().bits() } CurrentBuffer::Buffer1 => { - unsafe { Self::stream() }.m1ar.read().m1a().bits() + unsafe { Self::stream() }.m1ar().read().m1a().bits() } }; addr as usize @@ -631,33 +643,34 @@ where #[inline(always)] fn set_number_of_transfers(&mut self, value: u16) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() } - .ndtr - .write(|w| w.ndt().bits(value)); + //NOTE(unsafe) All bit pattern for ndt are valid + unsafe { + Self::stream().ndtr().write(|w| w.ndt().bits(value)); + } } #[inline(always)] fn get_number_of_transfers() -> u16 { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() }.ndtr.read().ndt().bits() + unsafe { Self::stream() }.ndtr().read().ndt().bits() } #[inline(always)] unsafe fn set_memory_size(&mut self, size: u8) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::stream().cr.modify(|_, w| w.msize().bits(size)); + Self::stream().cr().modify(|_, w| w.msize().bits(size)); } #[inline(always)] unsafe fn set_peripheral_size(&mut self, size: u8) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::stream().cr.modify(|_, w| w.psize().bits(size)); + Self::stream().cr().modify(|_, w| w.psize().bits(size)); } #[inline(always)] fn set_memory_increment(&mut self, increment: bool) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::stream() } - .cr + .cr() .modify(|_, w| w.minc().bit(increment)); } @@ -665,14 +678,14 @@ where fn set_peripheral_increment(&mut self, increment: bool) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::stream() } - .cr + .cr() .modify(|_, w| w.pinc().bit(increment)); } #[inline(always)] fn set_direction(&mut self, direction: DmaDirection) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::stream() }.cr.modify(|_, w| unsafe { + unsafe { Self::stream() }.cr().modify(|_, w| unsafe { match direction { DmaDirection::PeripheralToMemory => w.dir().bits(0), DmaDirection::MemoryToPeripheral => w.dir().bits(1), @@ -686,7 +699,7 @@ where fn set_trbuff(&mut self, trbuff: bool) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::stream() } - .cr + .cr() .modify(|_, w| w.trbuff().bit(trbuff)); } @@ -694,7 +707,7 @@ where fn set_circular_buffer(&mut self, circular_buffer: bool) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::stream() } - .cr + .cr() .modify(|_, w| w.circ().bit(circular_buffer)); } @@ -702,7 +715,7 @@ where fn set_double_buffer(&mut self, double_buffer: bool) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::stream() } - .cr + .cr() .modify(|_, w| w.dbm().bit(double_buffer)); } @@ -710,7 +723,7 @@ where fn get_current_buffer() -> CurrentBuffer { //NOTE(unsafe) Atomic read with no side effects - if unsafe { Self::stream() }.cr.read().ct().bit_is_set() { + if unsafe { Self::stream() }.cr().read().ct().bit_is_set() { CurrentBuffer::Buffer0 } else { CurrentBuffer::Buffer1 @@ -720,7 +733,7 @@ where #[inline(always)] fn get_inactive_buffer() -> Option { //NOTE(unsafe) Atomic read with no side effects - let cr = unsafe { Self::stream() }.cr.read(); + let cr = unsafe { Self::stream() }.cr().read(); if cr.dbm().bit_is_set() { Some(if cr.ct().bit_is_set() { CurrentBuffer::Buffer0 @@ -738,7 +751,7 @@ where half_transfer_interrupt: bool, ) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmacr = &unsafe { Self::stream() }.cr; + let dmacr = &unsafe { Self::stream() }.cr(); dmacr.modify(|_, w| w.htie().bit(half_transfer_interrupt)); let _ = dmacr.read(); let _ = dmacr.read(); // Delay 2 peripheral clocks @@ -770,15 +783,15 @@ macro_rules! dma_stream { //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX let dma = unsafe { &*I::ptr() }; - dma.$ifcr.write(|w| w + dma.$ifcr().write(|w| w .$tcif().set_bit() //Clear transfer complete interrupt flag .$htif().set_bit() //Clear half transfer interrupt flag .$teif().set_bit() //Clear transfer error interrupt flag .$dmeif().set_bit() //Clear direct mode error interrupt flag .$feif().set_bit() //Clear fifo error interrupt flag ); - let _ = dma.$isr.read(); - let _ = dma.$isr.read(); // Delay 2 peripheral clocks + let _ = dma.$isr().read(); + let _ = dma.$isr().read(); // Delay 2 peripheral clocks } #[inline(always)] @@ -786,7 +799,7 @@ macro_rules! dma_stream { //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX let dma = unsafe { &*I::ptr() }; - dma.$ifcr.write(|w| w.$tcif().set_bit()); + dma.$ifcr().write(|w| w.$tcif().set_bit()); } #[inline(always)] @@ -794,8 +807,8 @@ macro_rules! dma_stream { self.stream_clear_transfer_complete_flag(); //NOTE(unsafe) Atomic read with no side-effects. let dma = unsafe { &*I::ptr() }; - let _ = dma.$isr.read(); - let _ = dma.$isr.read(); // Delay 2 peripheral clocks + let _ = dma.$isr().read(); + let _ = dma.$isr().read(); // Delay 2 peripheral clocks } #[inline(always)] @@ -803,23 +816,23 @@ macro_rules! dma_stream { //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX let dma = unsafe { &*I::ptr() }; - dma.$ifcr.write(|w| w.$teif().set_bit()); - let _ = dma.$isr.read(); - let _ = dma.$isr.read(); // Delay 2 peripheral clocks + dma.$ifcr().write(|w| w.$teif().set_bit()); + let _ = dma.$isr().read(); + let _ = dma.$isr().read(); // Delay 2 peripheral clocks } #[inline(always)] fn stream_get_transfer_complete_flag() -> bool { //NOTE(unsafe) Atomic read with no side effects let dma = unsafe { &*I::ptr() }; - dma.$isr.read().$tcisr().bit_is_set() + dma.$isr().read().$tcisr().bit_is_set() } #[inline(always)] fn stream_get_half_transfer_flag() -> bool { //NOTE(unsafe) Atomic read with no side effects let dma = unsafe { &*I::ptr() }; - dma.$isr.read().$htisr().bit_is_set() + dma.$isr().read().$htisr().bit_is_set() } #[inline(always)] @@ -827,9 +840,9 @@ macro_rules! dma_stream { //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX let dma = unsafe { &*I::ptr() }; - dma.$ifcr.write(|w| w.$htif().set_bit()); - let _ = dma.$isr.read(); - let _ = dma.$isr.read(); // Delay 2 peripheral clocks + dma.$ifcr().write(|w| w.$htif().set_bit()); + let _ = dma.$isr().read(); + let _ = dma.$isr().read(); // Delay 2 peripheral clocks } } @@ -839,18 +852,18 @@ macro_rules! dma_stream { //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX let dma = unsafe { &*I::ptr() }; - dma.$ifcr.write(|w| w.$dmeif().set_bit()); - let _ = dma.$isr.read(); - let _ = dma.$isr.read(); // Delay 2 peripheral clocks + dma.$ifcr().write(|w| w.$dmeif().set_bit()); + let _ = dma.$isr().read(); + let _ = dma.$isr().read(); // Delay 2 peripheral clocks } #[inline(always)] pub fn clear_fifo_error_interrupt(&mut self) { //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX let dma = unsafe { &*I::ptr() }; - dma.$ifcr.write(|w| w.$feif().set_bit()); - let _ = dma.$isr.read(); - let _ = dma.$isr.read(); // Delay 2 peripheral clocks + dma.$ifcr().write(|w| w.$feif().set_bit()); + let _ = dma.$isr().read(); + let _ = dma.$isr().read(); // Delay 2 peripheral clocks } } )+ @@ -914,7 +927,7 @@ macro_rules! peripheral_register_markers { peripheral_register_markers!(CCR1, CCR2, CCR3, CCR4, DMAR, ARR); /// Type alias for the DMA Request Multiplexer -pub type DMAReq = pac::dmamux1::ccr::DMAREQ_ID_A; +pub type DMAReq = pac::dmamux1::ccr::DMAREQ_ID; type P2M = PeripheralToMemory; type M2P = MemoryToPeripheral; diff --git a/src/dma/macros.rs b/src/dma/macros.rs index ff9c7ae6..adcad844 100644 --- a/src/dma/macros.rs +++ b/src/dma/macros.rs @@ -17,7 +17,7 @@ macro_rules! peripheral_target_instance { unsafe impl TargetAddress<$dir> for $peripheral { #[inline(always)] fn address(&self) -> usize { - &self.$register as *const _ as usize + &self.$register() as *const _ as usize } type MemSize = $size; @@ -33,7 +33,7 @@ macro_rules! peripheral_target_instance { unsafe impl TargetAddress<$dir> for $peripheral { #[inline(always)] fn address(&self) -> usize { - &self.$channel().$register as *const _ as usize + &self.$channel().$register() as *const _ as usize } type MemSize = $size; @@ -51,7 +51,7 @@ macro_rules! peripheral_target_instance { unsafe impl TargetAddress<$dir> for $peripheral { #[inline(always)] fn address(&self) -> usize { - &self.$register as *const _ as usize + &self.$register() as *const _ as usize } type MemSize = $size; @@ -64,7 +64,7 @@ macro_rules! peripheral_target_instance { unsafe impl TargetAddress<$dir> for $hal<$peripheral $(, $generic)*> { #[inline(always)] fn address(&self) -> usize { - &self.inner().$register as *const _ as usize + &self.inner().$register() as *const _ as usize } type MemSize = $size; @@ -82,7 +82,7 @@ macro_rules! peripheral_target_instance { unsafe impl TargetAddress<$dir> for $hal { #[inline(always)] fn address(&self) -> usize { - &self.inner().$register as *const _ as usize + &self.inner().$register() as *const _ as usize } type MemSize = $size; @@ -101,7 +101,7 @@ macro_rules! peripheral_target_instance { unsafe impl TargetAddress for $peripheral { #[inline(always)] fn address(&self) -> usize { - &self.$txreg as *const _ as usize + &self.$txreg() as *const _ as usize } type MemSize = u8; @@ -112,7 +112,7 @@ macro_rules! peripheral_target_instance { unsafe impl TargetAddress for $peripheral { #[inline(always)] fn address(&self) -> usize { - &self.$rxreg as *const _ as usize + &self.$rxreg() as *const _ as usize } type MemSize = u8; @@ -126,7 +126,7 @@ macro_rules! peripheral_target_instance { #[inline(always)] fn address(&self) -> usize { use spi::HalSpi; - &self.inner().$txreg as *const _ as usize + &self.inner().$txreg() as *const _ as usize } type MemSize = $size; @@ -138,7 +138,7 @@ macro_rules! peripheral_target_instance { #[inline(always)] fn address(&self) -> usize { use spi::HalSpi; - &self.inner().$rxreg as *const _ as usize + &self.inner().$rxreg() as *const _ as usize } type MemSize = $size; @@ -153,7 +153,7 @@ macro_rules! peripheral_target_instance { unsafe impl TargetAddress for $peripheral { #[inline(always)] fn address(&self) -> usize { - &self.$txreg as *const _ as usize + &self.$txreg() as *const _ as usize } type MemSize = u8; @@ -165,7 +165,7 @@ macro_rules! peripheral_target_instance { unsafe impl TargetAddress for $peripheral { #[inline(always)] fn address(&self) -> usize { - &self.$rxreg as *const _ as usize + &self.$rxreg() as *const _ as usize } type MemSize = u8; @@ -177,7 +177,7 @@ macro_rules! peripheral_target_instance { unsafe impl TargetAddress for serial::Serial<$peripheral> { #[inline(always)] fn address(&self) -> usize { - &self.usart.$txreg as *const _ as usize + &self.usart.$txreg() as *const _ as usize } type MemSize = u8; @@ -189,7 +189,7 @@ macro_rules! peripheral_target_instance { unsafe impl TargetAddress for serial::Serial<$peripheral> { #[inline(always)] fn address(&self) -> usize { - &self.usart.$rxreg as *const _ as usize + &self.usart.$rxreg() as *const _ as usize } type MemSize = u8; @@ -202,7 +202,7 @@ macro_rules! peripheral_target_instance { #[inline(always)] fn address(&self) -> usize { // unsafe: only the Tx part accesses the Tx register - &unsafe { &*<$peripheral>::ptr() }.$txreg as *const _ as usize + &unsafe { &*<$peripheral>::ptr() }.$txreg() as *const _ as usize } type MemSize = u8; @@ -215,7 +215,7 @@ macro_rules! peripheral_target_instance { #[inline(always)] fn address(&self) -> usize { // unsafe: only the Rx part accesses the Rx register - &unsafe { &*<$peripheral>::ptr() }.$rxreg as *const _ as usize + &unsafe { &*<$peripheral>::ptr() }.$rxreg() as *const _ as usize } type MemSize = u8; diff --git a/src/dma/mdma.rs b/src/dma/mdma.rs index 49f7b53f..4b9d66c4 100644 --- a/src/dma/mdma.rs +++ b/src/dma/mdma.rs @@ -722,7 +722,7 @@ where fn clear_interrupts(&mut self) { //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX - unsafe { Self::channel() }.ifcr.write( + unsafe { Self::channel() }.ifcr().write( |w| { w.cctcif() .set_bit() //Clear transfer complete flag @@ -736,8 +736,8 @@ where .set_bit() }, //Clear block repeat transfer complete flag ); - let _ = unsafe { Self::channel() }.isr.read(); - let _ = unsafe { Self::channel() }.isr.read(); // Delay 2 peripheral clocks + let _ = unsafe { Self::channel() }.isr().read(); + let _ = unsafe { Self::channel() }.isr().read(); // Delay 2 peripheral clocks } #[inline(always)] @@ -745,10 +745,10 @@ where //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX unsafe { Self::channel() } - .ifcr + .ifcr() .write(|w| w.cteif().set_bit()); - let _ = unsafe { Self::channel() }.isr.read(); - let _ = unsafe { Self::channel() }.isr.read(); // Delay 2 peripheral clocks + let _ = unsafe { Self::channel() }.isr().read(); + let _ = unsafe { Self::channel() }.isr().read(); // Delay 2 peripheral clocks } #[inline(always)] @@ -756,39 +756,39 @@ where //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX unsafe { Self::channel() } - .ifcr + .ifcr() .write(|w| w.cctcif().set_bit()); } #[inline(always)] fn clear_transfer_complete_interrupt(&mut self) { self.clear_transfer_complete_flag(); - let _ = unsafe { Self::channel() }.isr.read(); - let _ = unsafe { Self::channel() }.isr.read(); // Delay 2 peripheral clocks + let _ = unsafe { Self::channel() }.isr().read(); + let _ = unsafe { Self::channel() }.isr().read(); // Delay 2 peripheral clocks } #[inline(always)] fn get_transfer_complete_flag() -> bool { //NOTE(unsafe) Atomic read with no side effects - unsafe { Self::channel() }.isr.read().ctcif().bit_is_set() + unsafe { Self::channel() }.isr().read().ctcif().bit_is_set() } #[inline(always)] unsafe fn enable(&mut self) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::channel().cr.modify(|_, w| w.en().set_bit()); + Self::channel().cr().modify(|_, w| w.en().set_bit()); // If this channel is configured as software triggered, then // we also active the request - if Self::channel().tcr.read().swrm().bit_is_set() { - Self::channel().cr.modify(|_, w| w.swrq().set_bit()); + if Self::channel().tcr().read().swrm().bit_is_set() { + Self::channel().cr().modify(|_, w| w.swrq().set_bit()); } } #[inline(always)] fn is_enabled() -> bool { //NOTE(unsafe) Atomic read with no side effects - unsafe { Self::channel() }.cr.read().en().bit_is_set() + unsafe { Self::channel() }.cr().read().en().bit_is_set() } fn disable(&mut self) { @@ -800,7 +800,7 @@ where self.disable_interrupts(); unsafe { Self::channel() } - .cr + .cr() .modify(|_, w| w.en().clear_bit()); while !Self::get_transfer_complete_flag() {} @@ -820,14 +820,14 @@ where fn set_priority(&mut self, priority: config::Priority) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::channel() } - .cr + .cr() .modify(|_, w| unsafe { w.pl().bits(priority.bits()) }); } #[inline(always)] fn disable_interrupts(&mut self) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::channel() }.cr.modify(|_, w| { + unsafe { Self::channel() }.cr().modify(|_, w| { w.ctcie() .clear_bit() .teie() @@ -839,14 +839,14 @@ where .brtie() .clear_bit() }); - let _ = unsafe { Self::channel() }.cr.read(); - let _ = unsafe { Self::channel() }.cr.read(); // Delay 2 peripheral clocks + let _ = unsafe { Self::channel() }.cr().read(); + let _ = unsafe { Self::channel() }.cr().read(); // Delay 2 peripheral clocks } #[inline(always)] fn enable_interrupts(&mut self, interrupt: Self::Interrupts) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::channel() }.cr.modify(|_, w| { + unsafe { Self::channel() }.cr().modify(|_, w| { w.ctcie() .bit(interrupt.transfer_complete) .teie() @@ -863,7 +863,7 @@ where #[inline(always)] fn get_interrupts_enable() -> Self::Interrupts { //NOTE(unsafe) We only access the registers that belongs to the StreamX - let cr = unsafe { Self::channel() }.cr.read(); + let cr = unsafe { Self::channel() }.cr().read(); MdmaInterrupts { transfer_complete: cr.ctcie().bit_is_set(), @@ -881,10 +881,10 @@ where ) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::channel() } - .cr + .cr() .modify(|_, w| w.ctcie().bit(transfer_complete_interrupt)); - let _ = unsafe { Self::channel() }.cr.read(); - let _ = unsafe { Self::channel() }.cr.read(); // Delay 2 peripheral clocks + let _ = unsafe { Self::channel() }.cr().read(); + let _ = unsafe { Self::channel() }.cr().read(); // Delay 2 peripheral clocks } #[inline(always)] @@ -894,10 +894,10 @@ where ) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::channel() } - .cr + .cr() .modify(|_, w| w.teie().bit(transfer_error_interrupt)); - let _ = unsafe { Self::channel() }.cr.read(); - let _ = unsafe { Self::channel() }.cr.read(); // Delay 2 peripheral clocks + let _ = unsafe { Self::channel() }.cr().read(); + let _ = unsafe { Self::channel() }.cr().read(); // Delay 2 peripheral clocks } } @@ -908,84 +908,86 @@ where #[inline(always)] unsafe fn set_source_address(&mut self, value: usize) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::channel().sar.write(|w| w.sar().bits(value as u32)); + Self::channel().sar().write(|w| w.sar().bits(value as u32)); Self::channel() - .tbr + .tbr() .modify(|_, w| w.sbus().bit(is_ahb_port(value))); } #[inline(always)] unsafe fn set_destination_address(&mut self, value: usize) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::channel().dar.write(|w| w.dar().bits(value as u32)); + Self::channel().dar().write(|w| w.dar().bits(value as u32)); Self::channel() - .tbr + .tbr() .modify(|_, w| w.dbus().bit(is_ahb_port(value))); } #[inline(always)] unsafe fn set_source_burst_size(&mut self, value: u8) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::channel().tcr.modify(|_, w| w.sburst().bits(value)); + Self::channel().tcr().modify(|_, w| w.sburst().bits(value)); } #[inline(always)] unsafe fn set_destination_burst_size(&mut self, value: u8) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::channel().tcr.modify(|_, w| w.dburst().bits(value)); + Self::channel().tcr().modify(|_, w| w.dburst().bits(value)); } #[inline(always)] fn get_source_burst_size() -> u8 { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::channel() }.tcr.read().sburst().bits() + unsafe { Self::channel() }.tcr().read().sburst().bits() } #[inline(always)] fn get_destination_burst_size() -> u8 { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::channel() }.tcr.read().dburst().bits() + unsafe { Self::channel() }.tcr().read().dburst().bits() } #[inline(always)] fn set_software_triggered(&mut self, sw_triggered: bool) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::channel() } - .tcr + .tcr() .modify(|_, w| w.swrm().bit(sw_triggered)); } #[inline(always)] fn set_trigger_selection(&mut self, trigger: u8) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::channel() } - .tbr + .tbr() .modify(|_, w| unsafe { w.tsel().bits(trigger) }); } #[inline(always)] fn set_trigger_mode(&mut self, trigger_mode: MdmaTrigger) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::channel() } - .tcr + .tcr() .modify(|_, w| unsafe { w.trgm().bits(trigger_mode as u8) }); } #[inline(always)] unsafe fn set_transfer_length(&mut self, value: u8) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::channel().tcr.modify(|_, w| w.tlen().bits(value - 1)); + Self::channel() + .tcr() + .modify(|_, w| w.tlen().bits(value - 1)); } #[inline(always)] fn get_transfer_length() -> u8 { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::channel() }.tcr.read().tlen().bits() + 1 + unsafe { Self::channel() }.tcr().read().tlen().bits() + 1 } #[inline(always)] unsafe fn set_block_bytes(&mut self, value: u32) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - Self::channel().bndtr.modify(|_, w| w.bndt().bits(value)); + Self::channel().bndtr().modify(|_, w| w.bndt().bits(value)); } #[inline(always)] fn get_block_bytes() -> u32 { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::channel() }.bndtr.read().bndt().bits() + unsafe { Self::channel() }.bndtr().read().bndt().bits() } fn source_destination_size_offset( @@ -1034,7 +1036,7 @@ where unsafe fn set_source_size(&mut self, size: MdmaSize) { //NOTE(unsafe) We only access the registers that belongs to the StreamX Self::channel() - .tcr + .tcr() .modify(|_, w| w.ssize().bits(size as u8)); } @@ -1042,7 +1044,7 @@ where fn get_source_size() -> MdmaSize { //NOTE(unsafe) We only access the registers that belongs to the StreamX MdmaSize::from_register( - unsafe { Self::channel() }.tcr.read().ssize().bits(), + unsafe { Self::channel() }.tcr().read().ssize().bits(), ) } @@ -1050,7 +1052,7 @@ where unsafe fn set_source_offset(&mut self, offset: MdmaSize) { //NOTE(unsafe) We only access the registers that belongs to the StreamX Self::channel() - .tcr + .tcr() .modify(|_, w| w.sincos().bits(offset as u8)); } @@ -1058,7 +1060,7 @@ where unsafe fn set_destination_size(&mut self, size: MdmaSize) { //NOTE(unsafe) We only access the registers that belongs to the StreamX Self::channel() - .tcr + .tcr() .modify(|_, w| w.dsize().bits(size as u8)); } @@ -1066,7 +1068,7 @@ where fn get_destination_size() -> MdmaSize { //NOTE(unsafe) We only access the registers that belongs to the StreamX MdmaSize::from_register( - unsafe { Self::channel() }.tcr.read().dsize().bits(), + unsafe { Self::channel() }.tcr().read().dsize().bits(), ) } @@ -1074,7 +1076,7 @@ where unsafe fn set_destination_offset(&mut self, offset: MdmaSize) { //NOTE(unsafe) We only access the registers that belongs to the StreamX Self::channel() - .tcr + .tcr() .modify(|_, w| w.dincos().bits(offset as u8)); } @@ -1083,16 +1085,16 @@ where //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX unsafe { Self::channel() } - .ifcr + .ifcr() .write(|w| w.cltcif().set_bit()); - let _ = unsafe { Self::channel() }.isr.read(); - let _ = unsafe { Self::channel() }.isr.read(); // Delay 2 peripheral clocks + let _ = unsafe { Self::channel() }.isr().read(); + let _ = unsafe { Self::channel() }.isr().read(); // Delay 2 peripheral clocks } #[inline(always)] fn get_buffer_transfer_complete_flag() -> bool { //NOTE(unsafe) Atomic read with no side effects - unsafe { Self::channel() }.isr.read().tcif().bit_is_set() + unsafe { Self::channel() }.isr().read().tcif().bit_is_set() } #[inline(always)] @@ -1100,16 +1102,16 @@ where //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX unsafe { Self::channel() } - .ifcr + .ifcr() .write(|w| w.cbtif().set_bit()); - let _ = unsafe { Self::channel() }.isr.read(); - let _ = unsafe { Self::channel() }.isr.read(); // Delay 2 peripheral clocks + let _ = unsafe { Self::channel() }.isr().read(); + let _ = unsafe { Self::channel() }.isr().read(); // Delay 2 peripheral clocks } #[inline(always)] fn get_block_transfer_complete_flag() -> bool { //NOTE(unsafe) Atomic read with no side effects - unsafe { Self::channel() }.isr.read().btif().bit_is_set() + unsafe { Self::channel() }.isr().read().btif().bit_is_set() } #[inline(always)] @@ -1117,16 +1119,16 @@ where //NOTE(unsafe) Atomic write with no side-effects and we only access the bits // that belongs to the StreamX unsafe { Self::channel() } - .ifcr + .ifcr() .write(|w| w.cbrtif().set_bit()); - let _ = unsafe { Self::channel() }.isr.read(); - let _ = unsafe { Self::channel() }.isr.read(); // Delay 2 peripheral clocks + let _ = unsafe { Self::channel() }.isr().read(); + let _ = unsafe { Self::channel() }.isr().read(); // Delay 2 peripheral clocks } #[inline(always)] fn get_block_repeat_transfer_complete_flag() -> bool { //NOTE(unsafe) Atomic read with no side effects - unsafe { Self::channel() }.isr.read().brtif().bit_is_set() + unsafe { Self::channel() }.isr().read().brtif().bit_is_set() } #[inline(always)] @@ -1136,10 +1138,10 @@ where ) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::channel() } - .cr + .cr() .modify(|_, w| w.tcie().bit(buffer_transfer_complete_interrupt)); - let _ = unsafe { Self::channel() }.cr.read(); - let _ = unsafe { Self::channel() }.cr.read(); // Delay 2 peripheral clocks + let _ = unsafe { Self::channel() }.cr().read(); + let _ = unsafe { Self::channel() }.cr().read(); // Delay 2 peripheral clocks } #[inline(always)] @@ -1149,10 +1151,10 @@ where ) { //NOTE(unsafe) We only access the registers that belongs to the StreamX unsafe { Self::channel() } - .cr + .cr() .modify(|_, w| w.btie().bit(block_transfer_complete_interrupt)); - let _ = unsafe { Self::channel() }.cr.read(); - let _ = unsafe { Self::channel() }.cr.read(); // Delay 2 peripheral clocks + let _ = unsafe { Self::channel() }.cr().read(); + let _ = unsafe { Self::channel() }.cr().read(); // Delay 2 peripheral clocks } #[inline(always)] @@ -1161,11 +1163,11 @@ where block_repeat_transfer_complete_interrupt: bool, ) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::channel() }.cr.modify(|_, w| { + unsafe { Self::channel() }.cr().modify(|_, w| { w.brtie().bit(block_repeat_transfer_complete_interrupt) }); - let _ = unsafe { Self::channel() }.cr.read(); - let _ = unsafe { Self::channel() }.cr.read(); // Delay 2 peripheral clocks + let _ = unsafe { Self::channel() }.cr().read(); + let _ = unsafe { Self::channel() }.cr().read(); // Delay 2 peripheral clocks } } @@ -1174,11 +1176,11 @@ where // The implementation does the heavy lifting of mapping to the right fields on // the stream macro_rules! mdma_stream { - ($( ($name:ident, $channel:ident, $number:expr) ),+$(,)*) => { + ($( ($name:ident, $number:expr) ),+$(,)*) => { $( impl InstanceStream for StreamX { unsafe fn channel() -> &'static pac::mdma::CH { - &(*I::ptr()).$channel + &(*I::ptr()).ch($number) } #[inline(always)] @@ -1186,7 +1188,7 @@ macro_rules! mdma_stream { use MdmaPackingAlignment::*; //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::channel() }.tcr.modify(|_,w| unsafe { + unsafe { Self::channel() }.tcr().modify(|_,w| unsafe { w .pke().bit(pack == Packed) .pam().bits(match pack { @@ -1199,17 +1201,17 @@ macro_rules! mdma_stream { #[inline(always)] fn set_word_endianness_exchange(&mut self, exchange: bool) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::channel() }.cr.modify(|_, w| w.wex().bit(exchange)); + unsafe { Self::channel() }.cr().modify(|_, w| w.wex().bit(exchange)); } #[inline(always)] fn set_half_word_endianness_exchange(&mut self, exchange: bool) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::channel() }.cr.modify(|_, w| w.hex().bit(exchange)); + unsafe { Self::channel() }.cr().modify(|_, w| w.hex().bit(exchange)); } #[inline(always)] fn set_byte_endianness_exchange(&mut self, exchange: bool) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::channel() }.cr.modify(|_, w| w.bex().bit(exchange)); + unsafe { Self::channel() }.cr().modify(|_, w| w.bex().bit(exchange)); } #[inline(always)] @@ -1217,7 +1219,7 @@ macro_rules! mdma_stream { use MdmaIncrement::*; //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::channel() }.tcr.modify(|_, w| unsafe { + unsafe { Self::channel() }.tcr().modify(|_, w| unsafe { w.dinc().bits(match increment { Fixed => 0b00, Increment | IncrementWithOffset(_) => 0b10, @@ -1230,7 +1232,7 @@ macro_rules! mdma_stream { use MdmaIncrement::*; //NOTE(unsafe) We only access the registers that belongs to the StreamX - unsafe { Self::channel() }.tcr.modify(|_, w| unsafe { + unsafe { Self::channel() }.tcr().modify(|_, w| unsafe { w.sinc().bits(match increment { Fixed => 0b00, Increment | IncrementWithOffset(_) => 0b10, @@ -1244,22 +1246,22 @@ macro_rules! mdma_stream { } mdma_stream!( - (Stream0, ch0, 0), - (Stream1, ch1, 1), - (Stream2, ch2, 2), - (Stream3, ch3, 3), - (Stream4, ch4, 4), - (Stream5, ch5, 5), - (Stream6, ch6, 6), - (Stream7, ch7, 7), - (Stream8, ch8, 8), - (Stream9, ch9, 9), - (Stream10, ch10, 10), - (Stream11, ch11, 11), - (Stream12, ch12, 12), - (Stream13, ch13, 13), - (Stream14, ch14, 14), - (Stream15, ch15, 15), + (Stream0, 0), + (Stream1, 1), + (Stream2, 2), + (Stream3, 3), + (Stream4, 4), + (Stream5, 5), + (Stream6, 6), + (Stream7, 7), + (Stream8, 8), + (Stream9, 9), + (Stream10, 10), + (Stream11, 11), + (Stream12, 12), + (Stream13, 13), + (Stream14, 14), + (Stream15, 15), ); type P2M = PeripheralToMemory; diff --git a/src/dsi.rs b/src/dsi.rs index 499e5592..03df1d1b 100644 --- a/src/dsi.rs +++ b/src/dsi.rs @@ -153,10 +153,10 @@ impl DsiHost { let cycles_1ms = clocks.sysclk().raw() / 1_000; // Enable regulator - dsi.wrpcr.modify(|_, w| w.regen().set_bit()); + dsi.wrpcr().modify(|_, w| w.regen().set_bit()); // Wait for it to be ready block_with_timeout( - || dsi.wisr.read().rrs() == false, + || dsi.wisr().read().rrs() == false, DSI_TIMEOUT_MS, cycles_1ms, Error::RegTimeout, @@ -168,7 +168,7 @@ impl DsiHost { // let ndiv = 102; // let idf = 5; // let odf = 0b00; - dsi.wrpcr.modify(|_, w| unsafe { + dsi.wrpcr().modify(|_, w| unsafe { w.ndiv() .bits(pll_config.ndiv) // allowed: 10 ..= 125 .idf() @@ -177,22 +177,22 @@ impl DsiHost { .bits(pll_config.odf) // div1: 0b00, div2: 0b01, div4: 0b10, div8: 0b11 }); // Enable PLL - dsi.wrpcr.modify(|_, w| w.pllen().set_bit()); + dsi.wrpcr().modify(|_, w| w.pllen().set_bit()); // Required to wait 400us before checking PLLLS flag cortex_m::asm::delay(cycles_1ms / 2); // Wait for the lock block_with_timeout( - || dsi.wisr.read().pllls() == false, + || dsi.wisr().read().pllls() == false, DSI_TIMEOUT_MS, cycles_1ms, Error::PllTimeout, )?; // Clock and digital section enable - dsi.pctlr.modify(|_, w| w.cke().set_bit().den().set_bit()); + dsi.pctlr().modify(|_, w| w.cke().set_bit().den().set_bit()); // Clock lane config - dsi.clcr.modify( + dsi.clcr().modify( |_, w| { w.dpcc() .set_bit() // 1: lanes are running in high speed mode @@ -235,31 +235,31 @@ impl DsiHost { dsi.wpcr0 .modify(|_, w| unsafe { w.uix4().bits(uix4 as u8) }); // debug!("f_phy={}, uix4=override=8", f_phy); - // dsi.wpcr0.modify(|_, w| unsafe { w.uix4().bits(8) }); + // dsi.wpcr0().modify(|_, w| unsafe { w.uix4().bits(8) }); match dsi_config.interrupts { DsiInterrupts::None => { // Disable all error interrupts for now and reset the error mask - dsi.ier0.write(|w| unsafe { w.bits(0) }); - dsi.ier1.write(|w| unsafe { w.bits(0) }); + dsi.ier0().write(|w| unsafe { w.bits(0) }); + dsi.ier1().write(|w| unsafe { w.bits(0) }); } DsiInterrupts::All => { // Enable all error interrupts - dsi.ier0.write(|w| unsafe { + dsi.ier0().write(|w| unsafe { w.bits(0b00000000_00011111_11111111_11111111) }); - dsi.ier1.write(|w| unsafe { w.bits(0b00011111_11111111) }); + dsi.ier1().write(|w| unsafe { w.bits(0b00011111_11111111) }); // Enable wrapper interrupts - dsi.wier.write(|w| w.teie().set_bit().erie().set_bit()); + dsi.wier().write(|w| w.teie().set_bit().erie().set_bit()); } } match dsi_config.mode { DsiMode::Video { mode } => { // Select video mode - dsi.mcr.modify(|_, w| w.cmdm().clear_bit()); // 0 - video mode, 1 - command mode - dsi.wcfgr.modify(|_, w| { + dsi.mcr().modify(|_, w| w.cmdm().clear_bit()); // 0 - video mode, 1 - command mode + dsi.wcfgr().modify(|_, w| { w // 0 - video mode, 1 - adapted command mode .dsim() @@ -276,7 +276,7 @@ impl DsiHost { }); // Video mode transmission type, p. 1346 - dsi.vmcr.modify(|_, w| unsafe { + dsi.vmcr().modify(|_, w| unsafe { w.vmt() .bits(mode as u8) // 0b00 - non-burst with sync pulses, 0b01 - non-burst with sync event, 0b1x - burst mode .lpvsae() @@ -299,7 +299,7 @@ impl DsiHost { // Packet size, 14 bits max // TODO: Might be incorrect for 16 or 18bit - dsi.vpcr.modify(|_, w| unsafe { + dsi.vpcr().modify(|_, w| unsafe { w.vpsize().bits(display_config.active_width) }); @@ -309,10 +309,10 @@ impl DsiHost { // If set to 0 or 1, the video line is transmitted in a single packet. // If set to 1, the packet is part of a chunk, so a null packet follows it if NPSIZE > 0. Otherwise, // multiple chunks are used to transmit each video line. - dsi.vccr.modify(|_, w| unsafe { w.numc().bits(1) }); + dsi.vccr().modify(|_, w| unsafe { w.numc().bits(1) }); // Size of the null packet - dsi.vnpcr.modify(|_, w| unsafe { w.npsize().bits(0) }); + dsi.vnpcr().modify(|_, w| unsafe { w.npsize().bits(0) }); // Horizontal sync active (HSA) in lane byte clock cycles let f_ltdc_khz = dsi_config.ltdc_freq.to_kHz(); @@ -320,14 +320,14 @@ impl DsiHost { / f_ltdc_khz) as u16; #[cfg(feature = "log")] debug!("hsa={}", hsa); - dsi.vhsacr.modify(|_, w| unsafe { w.hsa().bits(hsa) }); + dsi.vhsacr().modify(|_, w| unsafe { w.hsa().bits(hsa) }); // Horizontal back porch (HBP) in lane byte clock cycles let hbp = ((display_config.h_back_porch as u32) * f_pix_khz / f_ltdc_khz) as u16; #[cfg(feature = "log")] debug!("hbp={}", hbp); - dsi.vhbpcr.modify(|_, w| unsafe { w.hbp().bits(hbp) }); + dsi.vhbpcr().modify(|_, w| unsafe { w.hbp().bits(hbp) }); // Total line time, HLINE = HSA + HBP + HACT + HFP let hline = display_config.h_sync @@ -338,31 +338,31 @@ impl DsiHost { // let hsync = f_phy * 3 * hline as u32 / 8; #[cfg(feature = "log")] debug!("hline={}", hline); - dsi.vlcr.modify(|_, w| unsafe { w.hline().bits(hline) }); + dsi.vlcr().modify(|_, w| unsafe { w.hline().bits(hline) }); // Vertical sync active (VSA) - dsi.vvsacr.modify(|_, w| unsafe { + dsi.vvsacr().modify(|_, w| unsafe { w.vsa().bits(display_config.v_sync) }); // Vertical back porch (VBP) - dsi.vvbpcr.modify(|_, w| unsafe { + dsi.vvbpcr().modify(|_, w| unsafe { w.vbp().bits(display_config.v_back_porch) }); // Vertical front porch (VFP) - dsi.vvfpcr.modify(|_, w| unsafe { + dsi.vvfpcr().modify(|_, w| unsafe { w.vfp().bits(display_config.v_front_porch) }); // Vertical active period - dsi.vvacr.modify(|_, w| unsafe { + dsi.vvacr().modify(|_, w| unsafe { w.va().bits(display_config.active_height) }); } DsiMode::AdaptedCommand { tear_effect } => { // Select command mode - dsi.mcr.modify(|_, w| w.cmdm().set_bit()); // 0 - video mode, 1 - command mode + dsi.mcr().modify(|_, w| w.cmdm().set_bit()); // 0 - video mode, 1 - command mode let (is_external_pin, auto_refresh) = match tear_effect { Some(te) => ( te.source == TearEffectSource::ExternalPin, @@ -370,7 +370,7 @@ impl DsiHost { ), None => (false, false), }; - dsi.wcfgr.modify(|_, w| { + dsi.wcfgr().modify(|_, w| { w // 0 - video mode, 1 - adapted command mode .dsim() @@ -390,12 +390,12 @@ impl DsiHost { }); // Maximum allowed size for memory write command - dsi.lccr.modify(|_, w| unsafe { + dsi.lccr().modify(|_, w| unsafe { w.cmdsize().bits(display_config.active_width) }); // Tearing effect acknowledge request - dsi.cmcr.modify(|_, w| w.teare().set_bit()) + dsi.cmcr().modify(|_, w| w.teare().set_bit()) } } @@ -404,7 +404,7 @@ impl DsiHost { .modify(|_, w| unsafe { w.vcid().bits(dsi_config.channel as u8) }); // Polarity - dsi.lpcr.modify(|_, w| { + dsi.lpcr().modify(|_, w| { w.dep().clear_bit().vsp().clear_bit().hsp().clear_bit() }); @@ -413,7 +413,7 @@ impl DsiHost { dsi_config.color_coding_host, ColorCoding::EighteenBitsConfig1 | ColorCoding::EighteenBitsConfig2 ); - dsi.lcolcr.modify(|_, w| unsafe { + dsi.lcolcr().modify(|_, w| unsafe { w.lpe() .bit(lpe) // loosely packed: 18bits .colc() @@ -421,11 +421,11 @@ impl DsiHost { }); // Color coding for the wrapper - dsi.wcfgr.modify(|_, w| unsafe { + dsi.wcfgr().modify(|_, w| unsafe { w.colmux().bits(dsi_config.color_coding_wrapper as u8) }); - dsi.lpmcr.modify(|_, w| unsafe { + dsi.lpmcr().modify(|_, w| unsafe { w.lpsize() .bits(dsi_config.lp_size) // Low power largest packet size .vlpsize() @@ -447,7 +447,7 @@ impl DsiHost { DsiCmdModeTransmissionKind::AllInHighSpeed => false, DsiCmdModeTransmissionKind::AllInLowPower => true, }; - self.dsi.cmcr.modify(|_, w| { + self.dsi.cmcr().modify(|_, w| { w.gsw0tx() .bit(is_low_power) .gsw1tx() @@ -473,15 +473,15 @@ impl DsiHost { .mrdps() .bit(is_low_power) }); - self.dsi.cmcr.modify(|_, w| w.are().clear_bit()); // FIXME: might be incorrect + self.dsi.cmcr().modify(|_, w| w.are().clear_bit()); // FIXME: might be incorrect } pub fn configure_phy_timers(&mut self, phy_timers: DsiPhyTimers) { let max_time = max(phy_timers.clock_lp2hs, phy_timers.clock_hs2lp); - self.dsi.cltcr.modify(|_, w| unsafe { + self.dsi.cltcr().modify(|_, w| unsafe { w.hs2lp_time().bits(max_time).lp2hs_time().bits(max_time) }); - self.dsi.dltcr.modify(|_, w| unsafe { + self.dsi.dltcr().modify(|_, w| unsafe { w.mrd_time() .bits(phy_timers.dataline_max_read_time) .hs2lp_time() @@ -489,13 +489,13 @@ impl DsiHost { .lp2hs_time() .bits(phy_timers.dataline_lp2hs) }); - self.dsi.pconfr.modify(|_, w| unsafe { + self.dsi.pconfr().modify(|_, w| unsafe { w.sw_time().bits(phy_timers.stop_wait_time) }); } pub fn force_rx_low_power(&mut self, force: bool) { - self.dsi.wpcr1.modify(|_, w| w.flprxlpm().bit(force)); + self.dsi.wpcr1().modify(|_, w| w.flprxlpm().bit(force)); } fn long_write( @@ -517,7 +517,7 @@ impl DsiHost { for (i, byte) in buf.iter().take(3).enumerate() { fifoword |= (*byte as u32) << (8 + 8 * i); } - self.dsi.gpdr.write(|w| unsafe { w.bits(fifoword) }); + self.dsi.gpdr().write(|w| unsafe { w.bits(fifoword) }); //debug!("gpdr = {fifoword:08x}"); // Put the rest of the data, assuming that GPDR is accumulated in the hardware in some buffer. @@ -526,7 +526,7 @@ impl DsiHost { for chunk in &mut iter { let fifoword: [u8; 4] = chunk.try_into().unwrap(); let fifoword = u32::from_ne_bytes(fifoword); //.swap_bytes(); - self.dsi.gpdr.write(|w| unsafe { w.bits(fifoword) }); + self.dsi.gpdr().write(|w| unsafe { w.bits(fifoword) }); //debug!("gpdr = {fifoword:08x}"); } if !iter.remainder().is_empty() { @@ -534,7 +534,7 @@ impl DsiHost { for (i, byte) in iter.remainder().iter().enumerate() { fifoword |= (*byte as u32) << (8 * i); } - self.dsi.gpdr.write(|w| unsafe { w.bits(fifoword) }); + self.dsi.gpdr().write(|w| unsafe { w.bits(fifoword) }); //debug!("gpdr = {fifoword:08x}"); } } @@ -546,7 +546,7 @@ impl DsiHost { } fn ghcr_write(&mut self, msb: u8, lsb: u8, dt: u8) { - self.dsi.ghcr.write(|w| unsafe { + self.dsi.ghcr().write(|w| unsafe { w // GHCR p. 1354 .wcmsb() .bits(msb) @@ -560,12 +560,12 @@ impl DsiHost { } pub fn start(&mut self) { - self.dsi.cr.modify(|_, w| w.en().set_bit()); - self.dsi.wcr.modify(|_, w| w.dsien().set_bit()); + self.dsi.cr().modify(|_, w| w.en().set_bit()); + self.dsi.wcr().modify(|_, w| w.dsien().set_bit()); } pub fn refresh(&mut self) { - self.dsi.wcr.modify(|_, w| w.ltdcen().set_bit()); + self.dsi.wcr().modify(|_, w| w.ltdcen().set_bit()); } pub fn refresh_handle(&self) -> DsiRefreshHandle { @@ -574,13 +574,13 @@ impl DsiHost { } pub fn enable_bus_turn_around(&mut self) { - self.dsi.pcr.modify(|_, w| w.btae().set_bit()); // Enable bus turn around + self.dsi.pcr().modify(|_, w| w.btae().set_bit()); // Enable bus turn around } } impl DsiRefreshHandle { pub fn refresh_now(&mut self) { - self.dsi.wcr.modify(|_, w| w.ltdcen().set_bit()); + self.dsi.wcr().modify(|_, w| w.ltdcen().set_bit()); } // pub fn refresh_when_te_happens(&mut self) { @@ -597,7 +597,7 @@ impl DsiHostCtrlIo for DsiHost { // debug!("DSI write: {:x?}", kind); // wait for command fifo to be empty block_with_timeout( - || self.dsi.gpsr.read().cmdfe() == false, + || self.dsi.gpsr().read().cmdfe() == false, DSI_TIMEOUT_MS, self.cycles_1ms, Error::FifoTimeout, @@ -636,8 +636,8 @@ impl DsiHostCtrlIo for DsiHost { ) -> Result<(), Error> { // println!("DSI read: {:x?}", kind); if buf.len() > 2 && buf.len() <= 65_535 { - self.write(DsiWriteCommand::SetMaximumReturnPacketSize( - buf.len() as u16 + self().write(DsiWriteCommand::SetMaximumReturnPacketSize( + buf.len() as u16, ))?; } else if buf.len() > 65_535 { return Err(Error::BufferIsToBig); @@ -663,9 +663,9 @@ impl DsiHostCtrlIo for DsiHost { block_with_timeout( || { if bytes_left > 0 { - if self.dsi.gpsr.read().prdfe().bit_is_clear() { + if self.dsi.gpsr().read().prdfe().bit_is_clear() { // GPSR: p. 1355 - let fifoword = self.dsi.gpdr.read().bits(); + let fifoword = self.dsi.gpdr().read().bits(); //debug!("fifoword read: {fifoword:08x}"); for b in fifoword // .swap_bytes() @@ -682,8 +682,8 @@ impl DsiHostCtrlIo for DsiHost { // issued to the panel and the read data is not captured by the DSI Host // which returns Packet Size Error. // Need to ensure that the Read command has finished before checking PSE - if self.dsi.gpsr.read().rcb().bit_is_clear() - && self.dsi.isr1.read().pse().bit_is_set() + if self.dsi.gpsr().read().rcb().bit_is_clear() + && self.dsi.isr1().read().pse().bit_is_set() { return false; } diff --git a/src/ethernet/eth.rs b/src/ethernet/eth.rs index 7a5e1a7b..1ec8b828 100644 --- a/src/ethernet/eth.rs +++ b/src/ethernet/eth.rs @@ -133,10 +133,10 @@ impl TDesRing { // before the DMA engine is enabled.) unsafe { let dma = &*stm32::ETHERNET_DMA::ptr(); - dma.dmactx_dlar + dma.dmactx_dlar() .write(|w| w.bits(&self.td[0] as *const _ as u32)); - dma.dmactx_rlr.write(|w| w.tdrl().bits(TD as u16 - 1)); - dma.dmactx_dtpr + dma.dmactx_rlr().write(|w| w.tdrl().bits(TD as u16 - 1)); + dma.dmactx_dtpr() .write(|w| w.bits(&self.td[0] as *const _ as u32)); } } @@ -171,7 +171,7 @@ impl TDesRing { let x = (x + 1) % TD; unsafe { let dma = &*stm32::ETHERNET_DMA::ptr(); - dma.dmactx_dtpr + dma.dmactx_dtpr() .write(|w| w.bits(&(self.td[x]) as *const _ as u32)); } @@ -280,9 +280,9 @@ impl RDesRing { // Initialise pointers in the DMA engine unsafe { let dma = &*stm32::ETHERNET_DMA::ptr(); - dma.dmacrx_dlar + dma.dmacrx_dlar() .write(|w| w.bits(&self.rd[0] as *const _ as u32)); - dma.dmacrx_rlr.write(|w| w.rdrl().bits(RD as u16 - 1)); + dma.dmacrx_rlr().write(|w| w.rdrl().bits(RD as u16 - 1)); } // Release descriptors to the DMA engine @@ -324,7 +324,7 @@ impl RDesRing { // Move the tail pointer (TPR) to this descriptor unsafe { let dma = &*stm32::ETHERNET_DMA::ptr(); - dma.dmacrx_dtpr + dma.dmacrx_dtpr() .write(|w| w.bits(&(self.rd[x]) as *const _ as u32)); } @@ -457,7 +457,7 @@ pub unsafe fn new_unchecked( let syscfg = &*stm32::SYSCFG::ptr(); // Ensure syscfg is enabled (for PMCR) - rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit()); + rcc.apb4enr().modify(|_, w| w.syscfgen().set_bit()); // AHB1 ETH1MACEN prec.enable(); @@ -465,28 +465,28 @@ pub unsafe fn new_unchecked( // Also need to enable the transmission and reception clocks, which // don't have prec objects. They don't have prec objects because they // can't be reset. - rcc.ahb1enr + rcc.ahb1enr() .modify(|_, w| w.eth1txen().set_bit().eth1rxen().set_bit()); - syscfg.pmcr.modify(|_, w| w.epis().bits(0b100)); // RMII + syscfg.pmcr().modify(|_, w| w.epis().bits(0b100)); // RMII } // reset ETH_MAC - write 1 then 0 - //rcc.ahb1rstr.modify(|_, w| w.eth1macrst().set_bit()); - //rcc.ahb1rstr.modify(|_, w| w.eth1macrst().clear_bit()); + //rcc.ahb1rstr().modify(|_, w| w.eth1macrst().set_bit()); + //rcc.ahb1rstr().modify(|_, w| w.eth1macrst().clear_bit()); cortex_m::interrupt::free(|_cs| { // reset ETH_DMA - write 1 and wait for 0 - eth_dma.dmamr.modify(|_, w| w.swr().set_bit()); - while eth_dma.dmamr.read().swr().bit_is_set() {} + eth_dma.dmamr().modify(|_, w| w.swr().set_bit()); + while eth_dma.dmamr().read().swr().bit_is_set() {} // 200 MHz eth_mac - .mac1ustcr + .mac1ustcr() .modify(|_, w| w.tic_1us_cntr().bits(200 - 1)); // Configuration Register - eth_mac.maccr.modify(|_, w| { + eth_mac.maccr().modify(|_, w| { w.arpen() .clear_bit() .ipc() @@ -517,7 +517,7 @@ pub unsafe fn new_unchecked( .dr() .set_bit() }); - eth_mac.macecr.modify(|_, w| { + eth_mac.macecr().modify(|_, w| { w.eipgen() .clear_bit() .usp() @@ -530,12 +530,12 @@ pub unsafe fn new_unchecked( // Set the MAC address. // Writes to LR trigger both registers to be loaded into the MAC, // so write to LR last. - eth_mac.maca0hr.write(|w| { + eth_mac.maca0hr().write(|w| { w.addrhi().bits( u16::from(mac_addr.0[4]) | (u16::from(mac_addr.0[5]) << 8), ) }); - eth_mac.maca0lr.write(|w| { + eth_mac.maca0lr().write(|w| { w.addrlo().bits( u32::from(mac_addr.0[0]) | (u32::from(mac_addr.0[1]) << 8) @@ -544,7 +544,7 @@ pub unsafe fn new_unchecked( ) }); // frame filter register - eth_mac.macpfr.modify(|_, w| { + eth_mac.macpfr().modify(|_, w| { w.dntu() .clear_bit() .ipfe() @@ -576,20 +576,20 @@ pub unsafe fn new_unchecked( .pr() .clear_bit() }); - eth_mac.macwtr.write(|w| w.pwe().clear_bit()); + eth_mac.macwtr().write(|w| w.pwe().clear_bit()); // Flow Control Register - eth_mac.macqtx_fcr.modify(|_, w| { + eth_mac.macqtx_fcr().modify(|_, w| { // Pause time w.pt().bits(0x100) }); - eth_mac.macrx_fcr.modify(|_, w| w); + eth_mac.macrx_fcr().modify(|_, w| w); // Mask away Ethernet MAC MMC RX/TX interrupts. These are statistics // counter interrupts and are enabled by default. We need to manually // disable various ethernet interrupts so they don't unintentionally // hang the device. The user is free to re-enable them later to provide // ethernet MAC-related statistics - eth_mac.mmc_rx_interrupt_mask.modify(|_, w| { + eth_mac.mmc_rx_interrupt_mask().modify(|_, w| { w.rxlpiuscim() .set_bit() .rxucgpim() @@ -600,7 +600,7 @@ pub unsafe fn new_unchecked( .set_bit() }); - eth_mac.mmc_tx_interrupt_mask.modify(|_, w| { + eth_mac.mmc_tx_interrupt_mask().modify(|_, w| { w.txlpiuscim() .set_bit() .txgpktim() @@ -615,13 +615,13 @@ pub unsafe fn new_unchecked( // modify them. Instead, as a workaround, we manually manipulate the // bits eth_mac - .mmc_tx_interrupt_mask + .mmc_tx_interrupt_mask() .modify(|r, w| w.bits(r.bits() | (1 << 27))); eth_mac - .mmc_rx_interrupt_mask + .mmc_rx_interrupt_mask() .modify(|r, w| w.bits(r.bits() | (1 << 27))); - eth_mtl.mtlrx_qomr.modify(|_, w| { + eth_mtl.mtlrx_qomr().modify(|_, w| { w // Receive store and forward .rsf() @@ -636,7 +636,7 @@ pub unsafe fn new_unchecked( .fup() .clear_bit() }); - eth_mtl.mtltx_qomr.modify(|_, w| { + eth_mtl.mtltx_qomr().modify(|_, w| { w // Transmit store and forward .tsf() @@ -644,7 +644,7 @@ pub unsafe fn new_unchecked( }); // operation mode register - eth_dma.dmamr.modify(|_, w| { + eth_dma.dmamr().modify(|_, w| { w.intm() .bits(0b00) // Rx Tx priority ratio 1:1 @@ -656,7 +656,7 @@ pub unsafe fn new_unchecked( .clear_bit() }); // bus mode register - eth_dma.dmasbmr.modify(|_, w| { + eth_dma.dmasbmr().modify(|_, w| { // Address-aligned beats w.aal() .set_bit() @@ -665,9 +665,9 @@ pub unsafe fn new_unchecked( .set_bit() }); eth_dma - .dmaccr + .dmaccr() .modify(|_, w| w.dsl().bits(0).pblx8().clear_bit().mss().bits(536)); - eth_dma.dmactx_cr.modify(|_, w| { + eth_dma.dmactx_cr().modify(|_, w| { w // Tx DMA PBL .txpbl() @@ -679,7 +679,7 @@ pub unsafe fn new_unchecked( .clear_bit() }); - eth_dma.dmacrx_cr.modify(|_, w| { + eth_dma.dmacrx_cr().modify(|_, w| { w // receive buffer size .rbsz() @@ -700,20 +700,20 @@ pub unsafe fn new_unchecked( cortex_m::asm::dsb(); // Manage MAC transmission and reception - eth_mac.maccr.modify(|_, w| { + eth_mac.maccr().modify(|_, w| { w.re() .bit(true) // Receiver Enable .te() .bit(true) // Transmiter Enable }); - eth_mtl.mtltx_qomr.modify(|_, w| w.ftq().set_bit()); + eth_mtl.mtltx_qomr().modify(|_, w| w.ftq().set_bit()); // Manage DMA transmission and reception - eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit()); - eth_dma.dmacrx_cr.modify(|_, w| w.sr().set_bit()); + eth_dma.dmactx_cr().modify(|_, w| w.st().set_bit()); + eth_dma.dmacrx_cr().modify(|_, w| w.sr().set_bit()); eth_dma - .dmacsr + .dmacsr() .modify(|_, w| w.tps().set_bit().rps().set_bit()); }); @@ -760,8 +760,8 @@ impl EthernetMAC { impl StationManagement for EthernetMAC { /// Read a register over SMI. fn smi_read(&mut self, reg: u8) -> u16 { - while self.eth_mac.macmdioar.read().mb().bit_is_set() {} - self.eth_mac.macmdioar.modify(|_, w| unsafe { + while self.eth_mac.macmdioar().read().mb().bit_is_set() {} + self.eth_mac.macmdioar().modify(|_, w| unsafe { w.pa() .bits(self.eth_phy_addr) .rda() @@ -773,17 +773,17 @@ impl StationManagement for EthernetMAC { .mb() .set_bit() }); - while self.eth_mac.macmdioar.read().mb().bit_is_set() {} - self.eth_mac.macmdiodr.read().md().bits() + while self.eth_mac.macmdioar().read().mb().bit_is_set() {} + self.eth_mac.macmdiodr().read().md().bits() } /// Write a register over SMI. fn smi_write(&mut self, reg: u8, val: u16) { - while self.eth_mac.macmdioar.read().mb().bit_is_set() {} + while self.eth_mac.macmdioar().read().mb().bit_is_set() {} self.eth_mac - .macmdiodr + .macmdiodr() .write(|w| unsafe { w.md().bits(val) }); - self.eth_mac.macmdioar.modify(|_, w| unsafe { + self.eth_mac.macmdioar().modify(|_, w| unsafe { w.pa() .bits(self.eth_phy_addr) .rda() @@ -795,7 +795,7 @@ impl StationManagement for EthernetMAC { .mb() .set_bit() }); - while self.eth_mac.macmdioar.read().mb().bit_is_set() {} + while self.eth_mac.macmdioar().read().mb().bit_is_set() {} } } @@ -874,7 +874,7 @@ impl EthernetDMA { /// Return the number of packets dropped since this method was /// last called pub fn number_packets_dropped(&self) -> u32 { - self.eth_dma.dmacmfcr.read().mfc().bits() as u32 + self.eth_dma.dmacmfcr().read().mfc().bits() as u32 } } @@ -886,10 +886,10 @@ impl EthernetDMA { pub unsafe fn interrupt_handler() { let eth_dma = &*stm32::ETHERNET_DMA::ptr(); eth_dma - .dmacsr + .dmacsr() .write(|w| w.nis().set_bit().ri().set_bit().ti().set_bit()); - let _ = eth_dma.dmacsr.read(); - let _ = eth_dma.dmacsr.read(); // Delay 2 peripheral clocks + let _ = eth_dma.dmacsr().read(); + let _ = eth_dma.dmacsr().read(); // Delay 2 peripheral clocks } /// Enables the Ethernet Interrupt. The following interrupts are enabled: @@ -904,6 +904,6 @@ pub unsafe fn interrupt_handler() { pub unsafe fn enable_interrupt() { let eth_dma = &*stm32::ETHERNET_DMA::ptr(); eth_dma - .dmacier + .dmacier() .modify(|_, w| w.nie().set_bit().rie().set_bit().tie().set_bit()); } diff --git a/src/exti.rs b/src/exti.rs index 7c90b6f2..0cdeebbd 100644 --- a/src/exti.rs +++ b/src/exti.rs @@ -106,31 +106,31 @@ pub enum Event { #[cfg(not(feature = "rm0399"))] macro_rules! reg_for_cpu { ($self:ident, imr1) => { - $self.cpuimr1 + $self.cpuimr1() }; ($self:ident, imr2) => { - $self.cpuimr2 + $self.cpuimr2() }; ($self:ident, imr3) => { - $self.cpuimr3 + $self.cpuimr3() }; ($self:ident, emr1) => { - $self.cpuemr1 + $self.cpuemr1() }; ($self:ident, emr2) => { - $self.cpuemr2 + $self.cpuemr2() }; ($self:ident, emr3) => { - $self.cpuemr3 + $self.cpuemr3() }; ($self:ident, pr1) => { - $self.cpupr1 + $self.cpupr1() }; ($self:ident, pr2) => { - $self.cpupr2 + $self.cpupr2() }; ($self:ident, pr3) => { - $self.cpupr3 + $self.cpupr3() }; } @@ -216,8 +216,8 @@ impl ExtiExt for EXTI { .modify(|r, w| w.bits(r.bits() | (1 << (line - 32)))), 64..=80 | 82 | 84..=88 => reg_for_cpu!(self, imr3) .modify(|r, w| w.bits(r.bits() | (1 << (line - 64)))), - _ => {} - } + _ => 0, + }; } } diff --git a/src/flash/mod.rs b/src/flash/mod.rs index 76435d8c..78880a78 100644 --- a/src/flash/mod.rs +++ b/src/flash/mod.rs @@ -277,9 +277,9 @@ const UNLOCK_KEY2: u32 = 0xCDEF_89AB; #[allow(unused_unsafe)] fn unlock(bank: &BANK) { - bank.keyr.write(|w| unsafe { w.keyr().bits(UNLOCK_KEY1) }); - bank.keyr.write(|w| unsafe { w.keyr().bits(UNLOCK_KEY2) }); - assert!(!bank.cr.read().lock().bit()) + bank.keyr().write(|w| unsafe { w.keyr().bits(UNLOCK_KEY1) }); + bank.keyr().write(|w| unsafe { w.keyr().bits(UNLOCK_KEY2) }); + assert!(!bank.cr().read().lock().bit()) } impl nor_flash::ErrorType for LockedFlashBank { diff --git a/src/flash/operations.rs b/src/flash/operations.rs index 762a3460..3e440215 100644 --- a/src/flash/operations.rs +++ b/src/flash/operations.rs @@ -52,7 +52,7 @@ impl NorFlashError for Error { impl Error { fn read(flash_bank: &BANK) -> Option { - let sr = flash_bank.sr.read(); + let sr = flash_bank.sr().read(); if sr.pgserr().bit() { Some(Error::ProgrammingSequence) } else if sr.wrperr().bit() { @@ -75,7 +75,7 @@ impl Error { } } fn clear_error_flags(regs: &BANK) { - regs.sr.modify(|_, w| { + regs.sr().modify(|_, w| { w.pgserr() .set_bit() .wrperr() @@ -92,7 +92,7 @@ fn clear_error_flags(regs: &BANK) { .set_bit() .dbeccerr() .set_bit() - }) + }); } /// Result of `FlashExt::unlocked()` @@ -129,7 +129,7 @@ pub struct UnlockedFlashBank<'a> { /// Automatically lock flash erase/program when leaving scope impl Drop for UnlockedFlashBank<'_> { fn drop(&mut self) { - self.bank.cr.modify(|_, w| w.lock().set_bit()); + self.bank.cr().modify(|_, w| w.lock().set_bit()); } } @@ -166,7 +166,7 @@ impl UnlockedFlashBank<'_> { clear_error_flags(self.bank); #[rustfmt::skip] - self.bank.cr.modify(|_, w| unsafe { + self.bank.cr().modify(|_, w| unsafe { w // start .start().set_bit() @@ -213,7 +213,7 @@ impl UnlockedFlashBank<'_> { while bytes.peek().is_some() { #[rustfmt::skip] #[allow(unused_unsafe)] - self.bank.cr.modify(|_, w| unsafe { + self.bank.cr().modify(|_, w| unsafe { w // double-word parallelism .psize().bits(0b11) @@ -250,19 +250,19 @@ impl UnlockedFlashBank<'_> { // The write buffer should be empty (WBNE=0) immediately, but wait // for this nonetheless. Then wait for the write queue while { - let sr = self.bank.sr.read(); + let sr = self.bank.sr().read(); sr.wbne().bit_is_set() | sr.qw().bit_is_set() } {} self.ok()?; } - self.bank.cr.modify(|_, w| w.pg().clear_bit()); + self.bank.cr().modify(|_, w| w.pg().clear_bit()); self.wait_ready(); self.ok() } fn wait_ready(&self) { - while self.bank.sr.read().bsy().bit() {} + while self.bank.sr().read().bsy().bit() {} } fn ok(&self) -> Result<(), Error> { diff --git a/src/fmc.rs b/src/fmc.rs index 64c6201c..f67e256b 100644 --- a/src/fmc.rs +++ b/src/fmc.rs @@ -169,7 +169,7 @@ unsafe impl FmcPeripheral for FMC { fn memory_controller_enable(&mut self) { // The FMCEN bit of the FMC_BCR2..4 registers is don’t // care. It is only enabled through the FMC_BCR1 register. - self.fmc.bcr1.modify(|_, w| w.fmcen().set_bit()); + self.fmc.bcr1().modify(|_, w| w.fmcen().set_bit()); } fn source_clock_hz(&self) -> u32 { diff --git a/src/gpio.rs b/src/gpio.rs index 43b57890..4ae7a173 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -317,7 +317,7 @@ where let offset = 2 * { N }; unsafe { - (*Gpio::

::ptr()).ospeedr.modify(|r, w| { + (*Gpio::

::ptr()).ospeedr().modify(|r, w| { w.bits( (r.bits() & !(0b11 << offset)) | ((speed as u32) << offset), ) @@ -341,7 +341,7 @@ where let offset = 2 * { N }; let value = resistor as u32; unsafe { - (*Gpio::

::ptr()).pupdr.modify(|r, w| { + (*Gpio::

::ptr()).pupdr().modify(|r, w| { w.bits((r.bits() & !(0b11 << offset)) | (value << offset)) }); } @@ -427,22 +427,26 @@ impl Pin { #[inline(always)] fn _set_high(&mut self) { // NOTE(unsafe) atomic write to a stateless register - unsafe { (*Gpio::

::ptr()).bsrr.write(|w| w.bits(1 << N)) } + unsafe { + (*Gpio::

::ptr()).bsrr().write(|w| w.bits(1 << N)); + } } #[inline(always)] fn _set_low(&mut self) { // NOTE(unsafe) atomic write to a stateless register - unsafe { (*Gpio::

::ptr()).bsrr.write(|w| w.bits(1 << (16 + N))) } + unsafe { + (*Gpio::

::ptr()).bsrr().write(|w| w.bits(1 << (16 + N))); + } } #[inline(always)] fn _is_set_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*Gpio::

::ptr()).odr.read().bits() & (1 << N) == 0 } + unsafe { (*Gpio::

::ptr()).odr().read().bits() & (1 << N) == 0 } } #[inline(always)] fn _is_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*Gpio::

::ptr()).idr.read().bits() & (1 << N) == 0 } + unsafe { (*Gpio::

::ptr()).idr().read().bits() & (1 << N) == 0 } } } diff --git a/src/gpio/convert.rs b/src/gpio/convert.rs index e1dfd665..ca1ed9c6 100644 --- a/src/gpio/convert.rs +++ b/src/gpio/convert.rs @@ -259,7 +259,7 @@ impl Pin { unsafe { if MODE::OTYPER != M::OTYPER { if let Some(otyper) = M::OTYPER { - (*Gpio::

::ptr()).otyper.modify(|r, w| { + (*Gpio::

::ptr()).otyper().modify(|r, w| { w.bits(r.bits() & !(0b1 << N) | (otyper << N)) }); } @@ -269,7 +269,7 @@ impl Pin { if let Some(afr) = M::AFR { if N < 8 { let offset2 = 4 * { N }; - (*Gpio::

::ptr()).afrl.modify(|r, w| { + (*Gpio::

::ptr()).afrl().modify(|r, w| { w.bits( (r.bits() & !(0b1111 << offset2)) | (afr << offset2), @@ -277,7 +277,7 @@ impl Pin { }); } else { let offset2 = 4 * { N - 8 }; - (*Gpio::

::ptr()).afrh.modify(|r, w| { + (*Gpio::

::ptr()).afrh().modify(|r, w| { w.bits( (r.bits() & !(0b1111 << offset2)) | (afr << offset2), @@ -288,7 +288,7 @@ impl Pin { } if MODE::MODER != M::MODER { - (*Gpio::

::ptr()).moder.modify(|r, w| { + (*Gpio::

::ptr()).moder().modify(|r, w| { w.bits( (r.bits() & !(0b11 << offset)) | (M::MODER << offset), ) diff --git a/src/gpio/erased.rs b/src/gpio/erased.rs index 02301138..00e9f2e9 100644 --- a/src/gpio/erased.rs +++ b/src/gpio/erased.rs @@ -82,7 +82,7 @@ impl ErasedPin> { #[inline(always)] pub fn set_high(&mut self) { // NOTE(unsafe) atomic write to a stateless register - unsafe { self.block().bsrr.write(|w| w.bits(1 << self.pin_id())) }; + unsafe { self.block().bsrr().write(|w| w.bits(1 << self.pin_id())) }; } /// Drives the pin low @@ -91,7 +91,7 @@ impl ErasedPin> { // NOTE(unsafe) atomic write to a stateless register unsafe { self.block() - .bsrr + .bsrr() .write(|w| w.bits(1 << (self.pin_id() + 16))) }; } @@ -124,7 +124,7 @@ impl ErasedPin> { /// Is the pin in drive low mode? #[inline(always)] pub fn is_set_low(&self) -> bool { - self.block().odr.read().bits() & (1 << self.pin_id()) == 0 + self.block().odr().read().bits() & (1 << self.pin_id()) == 0 } /// Toggle pin output @@ -151,6 +151,6 @@ where /// Is the input pin low? #[inline(always)] pub fn is_low(&self) -> bool { - self.block().idr.read().bits() & (1 << self.pin_id()) == 0 + self.block().idr().read().bits() & (1 << self.pin_id()) == 0 } } diff --git a/src/gpio/exti.rs b/src/gpio/exti.rs index 6f0c268f..fb64ba47 100644 --- a/src/gpio/exti.rs +++ b/src/gpio/exti.rs @@ -43,22 +43,22 @@ where let offset = 4 * (i % 4); match i { 0..=3 => { - syscfg.exticr1.modify(|r, w| unsafe { + syscfg.exticr1().modify(|r, w| unsafe { w.bits((r.bits() & !(0xf << offset)) | (port << offset)) }); } 4..=7 => { - syscfg.exticr2.modify(|r, w| unsafe { + syscfg.exticr2().modify(|r, w| unsafe { w.bits((r.bits() & !(0xf << offset)) | (port << offset)) }); } 8..=11 => { - syscfg.exticr3.modify(|r, w| unsafe { + syscfg.exticr3().modify(|r, w| unsafe { w.bits((r.bits() & !(0xf << offset)) | (port << offset)) }); } 12..=15 => { - syscfg.exticr4.modify(|r, w| unsafe { + syscfg.exticr4().modify(|r, w| unsafe { w.bits((r.bits() & !(0xf << offset)) | (port << offset)) }); } @@ -72,21 +72,21 @@ where let i = self.pin_id(); match edge { Edge::Rising => { - exti.rtsr1 + exti.rtsr1() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); - exti.ftsr1 + exti.ftsr1() .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << i)) }); } Edge::Falling => { - exti.ftsr1 + exti.ftsr1() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); - exti.rtsr1 + exti.rtsr1() .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << i)) }); } Edge::RisingFalling => { - exti.rtsr1 + exti.rtsr1() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); - exti.ftsr1 + exti.ftsr1() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); } } @@ -96,7 +96,7 @@ where #[inline(always)] fn enable_interrupt(&mut self, exti: &mut EXTI) { #[cfg(not(feature = "rm0399"))] - let imr1 = &exti.cpuimr1; + let imr1 = &exti.cpuimr1(); #[cfg(all(feature = "rm0399", feature = "cm7"))] let imr1 = &exti.c1imr1; #[cfg(all(feature = "rm0399", feature = "cm4"))] @@ -109,11 +109,11 @@ where #[inline(always)] fn disable_interrupt(&mut self, exti: &mut EXTI) { #[cfg(not(feature = "rm0399"))] - let imr1 = &exti.cpuimr1; + let imr1 = &exti.cpuimr1(); #[cfg(all(feature = "rm0399", feature = "cm7"))] - let imr1 = &exti.c1imr1; + let imr1 = &exti.c1imr1(); #[cfg(all(feature = "rm0399", feature = "cm4"))] - let imr1 = &exti.c2imr1; + let imr1 = &exti.c2imr1(); imr1.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.pin_id())) }); } @@ -123,11 +123,11 @@ where fn clear_interrupt_pending_bit(&mut self) { unsafe { #[cfg(not(feature = "rm0399"))] - let pr1 = &(*EXTI::ptr()).cpupr1; + let pr1 = &(*EXTI::ptr()).cpupr1(); #[cfg(all(feature = "rm0399", feature = "cm7"))] - let pr1 = &(*EXTI::ptr()).c1pr1; + let pr1 = &(*EXTI::ptr()).c1pr1(); #[cfg(all(feature = "rm0399", feature = "cm4"))] - let pr1 = &(*EXTI::ptr()).c2pr1; + let pr1 = &(*EXTI::ptr()).c2pr1(); pr1.write(|w| w.bits(1 << self.pin_id())); let _ = pr1.read(); @@ -140,7 +140,7 @@ where fn check_interrupt(&self) -> bool { unsafe { #[cfg(not(feature = "rm0399"))] - let pr1 = &(*EXTI::ptr()).cpupr1; + let pr1 = &(*EXTI::ptr()).cpupr1(); #[cfg(all(feature = "rm0399", feature = "cm7"))] let pr1 = &(*EXTI::ptr()).c1pr1; #[cfg(all(feature = "rm0399", feature = "cm4"))] diff --git a/src/gpio/partially_erased.rs b/src/gpio/partially_erased.rs index 90f2ef9a..f88bbb3b 100644 --- a/src/gpio/partially_erased.rs +++ b/src/gpio/partially_erased.rs @@ -62,7 +62,9 @@ impl PartiallyErasedPin> { #[inline(always)] pub fn set_high(&mut self) { // NOTE(unsafe) atomic write to a stateless register - unsafe { (*Gpio::

::ptr()).bsrr.write(|w| w.bits(1 << self.i)) } + unsafe { + (*Gpio::

::ptr()).bsrr().write(|w| w.bits(1 << self.i)); + } } /// Drives the pin low @@ -71,8 +73,8 @@ impl PartiallyErasedPin> { // NOTE(unsafe) atomic write to a stateless register unsafe { (*Gpio::

::ptr()) - .bsrr - .write(|w| w.bits(1 << (self.i + 16))) + .bsrr() + .write(|w| w.bits(1 << (self.i + 16))); } } @@ -105,7 +107,7 @@ impl PartiallyErasedPin> { #[inline(always)] pub fn is_set_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*Gpio::

::ptr()).odr.read().bits() & (1 << self.i) == 0 } + unsafe { (*Gpio::

::ptr()).odr().read().bits() & (1 << self.i) == 0 } } /// Toggle pin output @@ -133,7 +135,7 @@ where #[inline(always)] pub fn is_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*Gpio::

::ptr()).idr.read().bits() & (1 << self.i) == 0 } + unsafe { (*Gpio::

::ptr()).idr().read().bits() & (1 << self.i) == 0 } } } diff --git a/src/i2c.rs b/src/i2c.rs index 7f0bebaf..c1f24aa2 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -111,13 +111,16 @@ pub trait I2cExt: Sized { macro_rules! flush_txdr { ($i2c:expr) => { // If a pending TXIS flag is set, write dummy data to TXDR - if $i2c.isr.read().txis().bit_is_set() { - $i2c.txdr.write(|w| w.txdata().bits(0)); + if $i2c.isr().read().txis().bit_is_set() { + unsafe { + //NOTE(unsafe) 0 is a valid bit pattern + $i2c.txdr().write(|w| w.txdata().bits(0)); + } } // If TXDR is not flagged as empty, write 1 to flush it - if $i2c.isr.read().txe().is_not_empty() { - $i2c.isr.write(|w| w.txe().set_bit()); + if $i2c.isr().read().txe().is_not_empty() { + $i2c.isr().write(|w| w.txe().set_bit()); } }; } @@ -125,18 +128,19 @@ macro_rules! flush_txdr { macro_rules! busy_wait { ($i2c:expr, $flag:ident, $variant:ident) => { loop { - let isr = $i2c.isr.read(); + let isr = $i2c.isr().read(); if isr.$flag().$variant() { break; } else if isr.berr().is_error() { - $i2c.icr.write(|w| w.berrcf().set_bit()); + $i2c.icr().write(|w| w.berrcf().set_bit()); return Err(Error::Bus); } else if isr.arlo().is_lost() { - $i2c.icr.write(|w| w.arlocf().set_bit()); + $i2c.icr().write(|w| w.arlocf().set_bit()); return Err(Error::Arbitration); } else if isr.nackf().bit_is_set() { - $i2c.icr.write(|w| w.stopcf().set_bit().nackcf().set_bit()); + $i2c.icr() + .write(|w| w.stopcf().set_bit().nackcf().set_bit()); flush_txdr!($i2c); return Err(Error::NotAcknowledge); } else { @@ -291,16 +295,17 @@ macro_rules! i2c { let i2c_clk: u32 = clocks.$pclkX().raw(); // Clear PE bit in I2C_CR1 - i2c.cr1.modify(|_, w| w.pe().clear_bit()); + i2c.cr1().modify(|_, w| w.pe().clear_bit()); // Enable the Analog Noise Filter by setting // ANFOFF (Analog Noise Filter OFF) to 0. This is // usually enabled by default - i2c.cr1.modify(|_, w| w.anfoff().clear_bit()); + i2c.cr1().modify(|_, w| w.anfoff().clear_bit()); // Configure timing let (presc_reg, scll, sclh, sdadel, scldel) = i2c_timing!(i2c_clk, freq); - i2c.timingr.write(|w| + //NOTE(unsafe) Only valid bit patterns written, checked by i2c_timing + i2c.timingr().write(|w| unsafe { w.presc() .bits(presc_reg) .scll() @@ -311,10 +316,10 @@ macro_rules! i2c { .bits(sdadel) .scldel() .bits(scldel) - ); + }); // Enable the peripheral - i2c.cr1.write(|w| w.pe().set_bit()); + i2c.cr1().write(|w| w.pe().set_bit()); I2c { i2c } } @@ -331,17 +336,17 @@ macro_rules! i2c { /// Enable or disable the DMA mode for reception pub fn rx_dma(&mut self, enable: bool) { - self.i2c.cr1.modify(|_,w| w.rxdmaen().bit(enable)); + self.i2c.cr1().modify(|_,w| w.rxdmaen().bit(enable)); } /// Enable or disable the DMA mode for transmission pub fn tx_dma(&mut self, enable: bool) { - self.i2c.cr1.modify(|_,w| w.txdmaen().bit(enable)); + self.i2c.cr1().modify(|_,w| w.txdmaen().bit(enable)); } /// Start listening for `event` pub fn listen(&mut self, event: Event) { - self.i2c.cr1.modify(|_,w| { + self.i2c.cr1().modify(|_,w| { match event { Event::Transmit => w.txie().set_bit(), Event::Receive => w.rxie().set_bit(), @@ -355,7 +360,7 @@ macro_rules! i2c { /// Stop listening for `event` pub fn unlisten(&mut self, event: Event) { - self.i2c.cr1.modify(|_,w| { + self.i2c.cr1().modify(|_,w| { match event { Event::Transmit => w.txie().clear_bit(), Event::Receive => w.rxie().clear_bit(), @@ -365,13 +370,13 @@ macro_rules! i2c { Event::NotAcknowledge => w.nackie().clear_bit(), } }); - let _ = self.i2c.cr1.read(); - let _ = self.i2c.cr1.read(); // Delay 2 peripheral clocks + let _ = self.i2c.cr1().read(); + let _ = self.i2c.cr1().read(); // Delay 2 peripheral clocks } /// Clears interrupt flag for `event` pub fn clear_irq(&mut self, event: Event) { - self.i2c.icr.write(|w| { + self.i2c.icr().write(|w| { match event { Event::Stop => w.stopcf().set_bit(), Event::Errors => w @@ -382,8 +387,8 @@ macro_rules! i2c { _ => w } }); - let _ = self.i2c.isr.read(); - let _ = self.i2c.isr.read(); // Delay 2 peripheral clocks + let _ = self.i2c.isr().read(); + let _ = self.i2c.isr().read(); // Delay 2 peripheral clocks } /// Releases the I2C peripheral @@ -420,12 +425,13 @@ macro_rules! i2c { // Wait for any previous address sequence to end // automatically. This could be up to 50% of a bus // cycle (ie. up to 0.5/freq) - while self.i2c.cr2.read().start().bit_is_set() {}; + while self.i2c.cr2().read().start().bit_is_set() {}; // Set START and prepare to receive bytes into // `buffer`. The START bit can be set even if the bus // is BUSY or I2C is in slave mode. - self.i2c.cr2.write(|w| { + //NOTE(unsafe) Only valid bit patterns written + self.i2c.cr2().write(|w| unsafe { w.sadd() .bits((addr << 1 | 0) as u16) .rd_wrn() @@ -452,12 +458,13 @@ macro_rules! i2c { // Wait for any previous address sequence to end // automatically. This could be up to 50% of a bus // cycle (ie. up to 0.5/freq) - while self.i2c.cr2.read().start().bit_is_set() {}; + while self.i2c.cr2().read().start().bit_is_set() {}; // Set START and prepare to send `bytes`. The // START bit can be set even if the bus is BUSY or // I2C is in slave mode. - self.i2c.cr2.write(|w| { + //NOTE(unsafe) Only valid bit patterns written + self.i2c.cr2().write(|w| unsafe { w.start() .set_bit() .sadd() @@ -485,7 +492,8 @@ macro_rules! i2c { pub fn master_re_start(&mut self, addr: u8, length: usize, stop: Stop) { assert!(length < 256 && length > 0); - self.i2c.cr2.write(|w| { + //NOTE(unsafe) Only valid bit patterns written + self.i2c.cr2().write(|w| unsafe { w.sadd() .bits(u16(addr << 1 | 1)) .add10().clear_bit() @@ -509,7 +517,7 @@ macro_rules! i2c { /// Slave: ... /// ``` pub fn master_stop(&mut self) { - self.i2c.cr2.write(|w| w.stop().set_bit()); + self.i2c.cr2().write(|w| w.stop().set_bit()); } } @@ -576,7 +584,10 @@ macro_rules! i2c { busy_wait!(self.i2c, txis, is_empty); // Put byte on the wire - self.i2c.txdr.write(|w| w.txdata().bits(*byte)); + //NOTE(unsafe) All bit bit patterns are valid + unsafe { + self.i2c.txdr().write(|w| w.txdata().bits(*byte)); + } } // Wait until the write finishes @@ -616,7 +627,10 @@ macro_rules! i2c { busy_wait!(self.i2c, txis, is_empty); // Put byte on the wire - self.i2c.txdr.write(|w| w.txdata().bits(*byte)); + //NOTE(unsafe) All bit patterns are valid + unsafe { + self.i2c.txdr().write(|w| w.txdata().bits(*byte)); + } } // Wait until the write finishes before beginning to read. @@ -631,7 +645,7 @@ macro_rules! i2c { // Wait until we have received something busy_wait!(self.i2c, rxne, is_not_empty); - *byte = self.i2c.rxdr.read().rxdata().bits(); + *byte = self.i2c.rxdr().read().rxdata().bits(); } // Wait for automatic stop @@ -658,7 +672,7 @@ macro_rules! i2c { // Wait until we have received something busy_wait!(self.i2c, rxne, is_not_empty); - *byte = self.i2c.rxdr.read().rxdata().bits(); + *byte = self.i2c.rxdr().read().rxdata().bits(); } // Wait for automatic stop diff --git a/src/independent_watchdog.rs b/src/independent_watchdog.rs index b43f3bf5..864c67f1 100644 --- a/src/independent_watchdog.rs +++ b/src/independent_watchdog.rs @@ -22,17 +22,17 @@ use crate::{prelude::*, time::MilliSeconds}; #[cfg(any(feature = "rm0433", feature = "rm0455"))] -use crate::stm32::iwdg::pr::PR_A; +use crate::stm32::iwdg::pr::PR; #[cfg(any(feature = "rm0433", feature = "rm0455"))] use crate::stm32::IWDG; #[cfg(any(all(feature = "rm0399", feature = "cm7"), feature = "rm0468"))] -use crate::stm32::iwdg1::pr::PR_A; +use crate::stm32::iwdg1::pr::PR; #[cfg(any(all(feature = "rm0399", feature = "cm7"), feature = "rm0468"))] use crate::stm32::IWDG1 as IWDG; #[cfg(all(feature = "rm0399", feature = "cm4"))] -use crate::stm32::iwdg2::pr::PR_A; +use crate::stm32::iwdg2::pr::PR; #[cfg(all(feature = "rm0399", feature = "cm4"))] use crate::stm32::IWDG2 as IWDG; @@ -44,38 +44,38 @@ pub struct IndependentWatchdog { impl IndependentWatchdog { const CLOCK_SPEED: u32 = 32000; const MAX_COUNTER_VALUE: u32 = 0x00000FFF; - const MAX_MILLIS_FOR_PRESCALER: [(PR_A, u32); 8] = [ + const MAX_MILLIS_FOR_PRESCALER: [(PR, u32); 8] = [ ( - PR_A::DivideBy4, + PR::DivideBy4, (Self::MAX_COUNTER_VALUE * 1000) / (Self::CLOCK_SPEED / 4), ), ( - PR_A::DivideBy8, + PR::DivideBy8, (Self::MAX_COUNTER_VALUE * 1000) / (Self::CLOCK_SPEED / 8), ), ( - PR_A::DivideBy16, + PR::DivideBy16, (Self::MAX_COUNTER_VALUE * 1000) / (Self::CLOCK_SPEED / 16), ), ( - PR_A::DivideBy32, + PR::DivideBy32, (Self::MAX_COUNTER_VALUE * 1000) / (Self::CLOCK_SPEED / 32), ), ( - PR_A::DivideBy64, + PR::DivideBy64, (Self::MAX_COUNTER_VALUE * 1000) / (Self::CLOCK_SPEED / 64), ), ( - PR_A::DivideBy128, + PR::DivideBy128, (Self::MAX_COUNTER_VALUE * 1000) / (Self::CLOCK_SPEED / 128), ), ( - PR_A::DivideBy256, + PR::DivideBy256, (Self::MAX_COUNTER_VALUE * 1000) / (Self::CLOCK_SPEED / 256), ), ( - PR_A::DivideBy256bis, - (Self::MAX_COUNTER_VALUE * 1000) / (Self::CLOCK_SPEED / 256), + PR::DivideBy256, + (Self::MAX_COUNTER_VALUE * 1000) / (Self::CLOCK_SPEED / 256), // TODO: Can we remove this element now? ), ]; @@ -86,7 +86,7 @@ impl IndependentWatchdog { /// Feed the watchdog, resetting the timer to 0 pub fn feed(&mut self) { - self.iwdg.kr.write(|w| w.key().reset()); + self.iwdg.kr().write(|w| w.key().feed()); } /// Start the watchdog where it must be fed before the max time is over and @@ -100,27 +100,31 @@ impl IndependentWatchdog { let max_window_time: MilliSeconds = max_window_time.into(); // Start the watchdog - self.iwdg.kr.write(|w| w.key().start()); + self.iwdg.kr().write(|w| w.key().start()); // Enable register access - self.iwdg.kr.write(|w| w.key().enable()); + self.iwdg.kr().write(|w| w.key().unlock()); // Set the prescaler let (prescaler, _) = Self::MAX_MILLIS_FOR_PRESCALER .iter() .find(|(_, max_millis)| *max_millis >= max_window_time.to_millis()) .expect("IWDG max time is greater than is possible"); - while self.iwdg.sr.read().pvu().bit_is_set() { + while self.iwdg.sr().read().pvu().bit_is_set() { cortex_m::asm::nop(); } - self.iwdg.pr.write(|w| w.pr().variant(*prescaler)); + self.iwdg.pr().write(|w| w.pr().variant(*prescaler)); // Reset the window value - while self.iwdg.sr.read().wvu().bit_is_set() { + while self.iwdg.sr().read().wvu().bit_is_set() { cortex_m::asm::nop(); } - self.iwdg - .winr - .write(|w| w.win().bits(Self::MAX_COUNTER_VALUE as u16)); + + //NOTE(unsafe) 0xFFF is a valid bit patterns for w.win() + unsafe { + self.iwdg + .winr() + .write(|w| w.win().bits(Self::MAX_COUNTER_VALUE as u16)); + } // Calculate the counter values let reload_value = max_window_time.to_millis() @@ -131,25 +135,32 @@ impl IndependentWatchdog { / Self::get_prescaler_divider(prescaler); // Set the reload value - while self.iwdg.sr.read().rvu().bit_is_set() { + while self.iwdg.sr().read().rvu().bit_is_set() { cortex_m::asm::nop(); } - self.iwdg.rlr.write(|w| w.rl().bits(reload_value as u16)); + //NOTE(unsafe) Only valid bit patterns written, values are checked above for maximum value + unsafe { + self.iwdg.rlr().write(|w| w.rl().bits(reload_value as u16)); + } self.feed(); // Enable register access - self.iwdg.kr.write(|w| w.key().enable()); + self.iwdg.kr().write(|w| w.key().unlock()); // Set the window value - while self.iwdg.sr.read().wvu().bit_is_set() { + while self.iwdg.sr().read().wvu().bit_is_set() { cortex_m::asm::nop(); } - self.iwdg - .winr - .write(|w| w.win().bits((reload_value - window_value) as u16)); + + // TODO: There is nothing preventing this from underflowing right? + unsafe { + self.iwdg + .winr() + .write(|w| w.win().bits((reload_value - window_value) as u16)); + } // Wait until everything is set - while self.iwdg.sr.read().bits() != 0 { + while self.iwdg.sr().read().bits() != 0 { cortex_m::asm::nop(); } @@ -161,16 +172,15 @@ impl IndependentWatchdog { self.start_windowed(0_u32.millis(), max_time.into()); } - fn get_prescaler_divider(prescaler: &PR_A) -> u32 { + fn get_prescaler_divider(prescaler: &PR) -> u32 { match prescaler { - PR_A::DivideBy4 => 4, - PR_A::DivideBy8 => 8, - PR_A::DivideBy16 => 16, - PR_A::DivideBy32 => 32, - PR_A::DivideBy64 => 64, - PR_A::DivideBy128 => 128, - PR_A::DivideBy256 => 256, - PR_A::DivideBy256bis => 256, + PR::DivideBy4 => 4, + PR::DivideBy8 => 8, + PR::DivideBy16 => 16, + PR::DivideBy32 => 32, + PR::DivideBy64 => 64, + PR::DivideBy128 => 128, + PR::DivideBy256 => 256, } } } diff --git a/src/ltdc.rs b/src/ltdc.rs index 6ad84eba..2269b2a1 100644 --- a/src/ltdc.rs +++ b/src/ltdc.rs @@ -44,7 +44,7 @@ macro_rules! declare_layer { type Target = stm32::ltdc::LAYER; #[inline(always)] fn deref(&self) -> &Self::Target { - unsafe { &(*LTDC::ptr()).$layer } + unsafe { &(*LTDC::ptr()).$layer() } } } #[doc=$doc] @@ -97,13 +97,13 @@ impl Ltdc { /// Enables the shadow register reload interrupt pub fn listen(&mut self) { - self.ltdc.ier.modify(|_, w| w.rrie().set_bit()); + self.ltdc.ier().modify(|_, w| w.rrie().set_bit()); } /// Clear interrupt flags pub fn unpend() { // unsafe: clear write-one interrupt flag - unsafe { (*LTDC::ptr()).icr.write(|w| w.crrif().set_bit()) }; + unsafe { (*LTDC::ptr()).icr().write(|w| w.crrif().clear()) }; } /// Returns a reference to the inner peripheral @@ -127,10 +127,10 @@ impl DisplayController for Ltdc { /// function will stall the bus. fn init(&mut self, config: DisplayConfiguration) { // Check bus access - assert!(self.ltdc.gcr.read().bits() == 0x2220); // Reset value + assert!(self.ltdc.gcr().read().bits() == 0x2220); // Reset value // Configure the HS, VS, DE and PC polarity - self.ltdc.gcr.modify(|_, w| { + self.ltdc.gcr().modify(|_, w| { w.hspol() .bit(config.h_sync_pol) .vspol() @@ -142,7 +142,8 @@ impl DisplayController for Ltdc { }); // Set synchronization pulse width - self.ltdc.sscr.modify(|_, w| { + // TODO: The h_sync and v_sync values are not checked + self.ltdc.sscr().modify(|_, w| unsafe { w.vsh() .bits(config.v_sync - 1) .hsw() @@ -150,7 +151,8 @@ impl DisplayController for Ltdc { }); // Set accumulated back porch - self.ltdc.bpcr.modify(|_, w| { + // TODO: The values are not checked + self.ltdc.bpcr().modify(|_, w| unsafe { w.avbp() .bits(config.v_sync + config.v_back_porch - 1) .ahbp() @@ -162,9 +164,9 @@ impl DisplayController for Ltdc { config.v_sync + config.v_back_porch + config.active_height - 1; let aa_width = config.h_sync + config.h_back_porch + config.active_width - 1; - self.ltdc - .awcr - .modify(|_, w| w.aah().bits(aa_height).aaw().bits(aa_width)); + self.ltdc.awcr().modify(|_, w| unsafe { + w.aah().bits(aa_height).aaw().bits(aa_width) + }); // Set total width and height let total_height: u16 = config.v_sync @@ -177,20 +179,21 @@ impl DisplayController for Ltdc { + config.active_width + config.h_front_porch - 1; - self.ltdc.twcr.modify(|_, w| { + // TODO: total_width is not checked + self.ltdc.twcr().modify(|_, w| unsafe { w.totalh().bits(total_height).totalw().bits(total_width) }); // Set the background color value - self.ltdc.bccr.reset(); + self.ltdc.bccr().reset(); // Enable the Transfer Error and FIFO underrun interrupts self.ltdc - .ier + .ier() .modify(|_, w| w.terrie().set_bit().fuie().set_bit()); // Enable LTDC by setting LTDCEN bit - self.ltdc.gcr.modify(|_, w| w.ltdcen().set_bit()); + self.ltdc.gcr().modify(|_, w| w.ltdcen().set_bit()); // Save config self.config = Some(config); @@ -249,44 +252,46 @@ macro_rules! impl_layer { // Configure the horizontal start and stop position let h_win_start = - self.window_x0 + ltdc.bpcr.read().ahbp().bits() + 1; + self.window_x0 + ltdc.bpcr().read().ahbp().bits() + 1; let h_win_stop = - self.window_x1 + ltdc.bpcr.read().ahbp().bits(); - layer.whpcr.modify(|_, w| { + self.window_x1 + ltdc.bpcr().read().ahbp().bits(); + layer.whpcr().modify(|_, w| { w.whstpos().bits(h_win_start).whsppos().bits(h_win_stop) }); // Configure the vertical start and stop position let v_win_start = - self.window_y0 + ltdc.bpcr.read().avbp().bits() + 1; + self.window_y0 + ltdc.bpcr().read().avbp().bits() + 1; let v_win_stop = - self.window_y1 + ltdc.bpcr.read().avbp().bits(); - layer.wvpcr.modify(|_, w| { + self.window_y1 + ltdc.bpcr().read().avbp().bits(); + layer.wvpcr().modify(|_, w| { w.wvstpos().bits(v_win_start).wvsppos().bits(v_win_stop) }); } // Set the pixel format - layer.pfcr.modify(|_, w| w.pf().bits(pixel_format as u8)); + layer.pfcr().modify(|_, w| w.pf().bits(pixel_format as u8)); // Set the default color value - layer.dccr.reset(); // Transparent black + layer.dccr().reset(); // Transparent black // Set the global constant alpha value let alpha = 0xFF; - layer.cacr.modify(|_, w| w.consta().bits(alpha)); + layer.cacr().modify(|_, w| w.consta().bits(alpha)); // Set the blending factors let blending_factor1 = ltdc_blending_options::LTDC_BLENDING_FACTOR1_PA_X_CA; let blending_factor2 = ltdc_blending_options::LTDC_BLENDING_FACTOR2_PA_X_CA; - layer.bfcr.modify(|_, w| { + layer.bfcr().modify(|_, w| { w.bf1().bits(blending_factor1).bf2().bits(blending_factor2) }); // Set frame buffer - layer.cfbar.modify(|_, w| w.cfbadd().bits(start_ptr as u32)); + layer + .cfbar() + .modify(|_, w| w.cfbadd().bits(start_ptr as u32)); // Calculate framebuffer pitch in bytes self.bytes_per_pixel = match pixel_format { @@ -300,7 +305,7 @@ macro_rules! impl_layer { let height = self.window_y1 - self.window_y0; // Framebuffer pitch and line length - layer.cfblr.modify(|_, w| { + layer.cfblr().modify(|_, w| { w.cfbp() .bits(width * self.bytes_per_pixel) .cfbll() @@ -308,13 +313,13 @@ macro_rules! impl_layer { }); // Framebuffer line number - layer.cfblnr.modify(|_, w| w.cfblnbr().bits(height)); + layer.cfblnr().modify(|_, w| w.cfblnbr().bits(height)); // Enable LTDC_Layer by setting LEN bit - layer.cr.modify(|_, w| w.len().set_bit()); + layer.cr().modify(|_, w| w.len().set_bit()); // Reload this layer immediately - (*LTDC::ptr()).srcr.write(|w| w.imr().set_bit()); + (*LTDC::ptr()).srcr().write(|w| w.imr().set_bit()); } /// Resizes the framebuffer pitch. This does not change the output window @@ -341,10 +346,10 @@ macro_rules! impl_layer { ); // Modify CFBP - self.layer.cfblr.modify(|_, w| w.cfbp().bits(pitch_bytes)); + self.layer.cfblr().modify(|_, w| w.cfbp().bits(pitch_bytes)); // Immediate reload - (*LTDC::ptr()).srcr.write(|w| w.imr().set_bit()); + (*LTDC::ptr()).srcr().write(|w| w.imr().set_bit()); } /// Swap the framebuffer to a new one. @@ -359,11 +364,11 @@ macro_rules! impl_layer { ) { // Set the new frame buffer address self.layer - .cfbar + .cfbar() .modify(|_, w| w.cfbadd().bits(start_ptr as u32)); // Configure a shadow reload for the next blanking period - (*LTDC::ptr()).srcr.write(|w| w.vbr().set_bit()); + (*LTDC::ptr()).srcr().write(|w| w.vbr().set_bit()); } /// Indicates if a framebuffer swap is pending. In this situation, @@ -375,7 +380,7 @@ macro_rules! impl_layer { cortex_m::asm::dsb(); // unsafe: Read bit - unsafe { (*LTDC::ptr()).srcr.read().vbr().bit_is_set() } + unsafe { (*LTDC::ptr()).srcr().read().vbr().bit_is_set() } } } }; diff --git a/src/pwm.rs b/src/pwm.rs index ef6baae0..aac3930a 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -1142,19 +1142,21 @@ macro_rules! tim_hal { }; // Write prescale - tim.psc.write(|w| { w.psc().bits(prescale as u16) }); + //NOTE(unsafe) Only valid bit patterns written, checked by calculate_frequency_{16,32}bit + tim.psc().write(|w| unsafe { w.psc().bits(prescale as u16) }); // Write period - tim.arr.write(|w| { w.arr().bits(period as $typ) }); + //NOTE(unsafe) Only valid bit patterns written, checked by calculate_frequency_{16,32}bit + tim.arr().write(|w| unsafe { w.arr().bits(period as $typ) }); // BDTR: Advanced-control timers $( // Set CCxP = OCxREF / CCxNP = !OCxREF // Refer to RM0433 Rev 6 - Table 324. - tim.$bdtr.write(|w| w.moe().$moe_set()); + tim.$bdtr().write(|w| w.moe().$moe_set()); )? - tim.cr1.write(|w| w.cen().enabled()); + tim.cr1().write(|w| w.cen().enabled()); PINS::split() } @@ -1208,20 +1210,22 @@ macro_rules! tim_hal { }; // Write prescaler - tim.psc.write(|w| w.psc().bits(prescaler as u16)); + //NOTE(unsafe) Only valid bit patterns written, checked by calculate_frequency_{16,32}bit + tim.psc().write(|w| unsafe { w.psc().bits(prescaler as u16) }); // Write period - tim.arr.write(|w| w.arr().bits(period as $typ)); + //NOTE(unsafe) Only valid bit patterns written, checked by calculate_frequency_{16,32}bit + tim.arr().write(|w| unsafe { w.arr().bits(period as $typ) }); $( let (dtg, ckd) = calculate_deadtime(self.base_freq, self.deadtime); match ckd { - 1 => tim.cr1.modify(|_, w| w.ckd().div1()), - 2 => tim.cr1.modify(|_, w| w.ckd().div2()), - 4 => tim.cr1.modify(|_, w| w.ckd().div4()), + 1 => tim.cr1().modify(|_, w| w.ckd().div1()), + 2 => tim.cr1().modify(|_, w| w.ckd().div2()), + 4 => tim.cr1().modify(|_, w| w.ckd().div4()), _ => panic!("Should be unreachable, invalid deadtime prescaler"), - } + }; let bkp = match self.fault_polarity { Polarity::ActiveLow => false, @@ -1235,12 +1239,12 @@ macro_rules! tim_hal { // BKE = 1 -> break is enabled // BKP = 0 for active low, 1 for active high // Safety: bkf is set to a constant value (1) that is a valid value for the field per the reference manual - unsafe { tim.$bdtr.write(|w| w.dtg().bits(dtg).bkf().bits(1).aoe().clear_bit().bke().set_bit().bkp().bit(bkp).moe().$moe_set()); } + unsafe { tim.$bdtr().write(|w| w.dtg().bits(dtg).bkf().bits(1).aoe().clear_bit().bke().set_bit().bkp().bit(bkp).moe().$moe_set()); } // AF1: // BKINE = 1 -> break input enabled // BKINP should make input active high (BDTR BKP will set polarity), bit value varies timer to timer - tim.$af1.write(|w| w.bkine().set_bit().bkinp().$bkinp_setting()); + tim.$af1().write(|w| w.bkine().set_bit().bkinp().$bkinp_setting()); } $( // Not all timers that have break inputs have break2 inputs @@ -1251,37 +1255,37 @@ macro_rules! tim_hal { // BK2E = 1 -> break is enabled // BK2P = 0 for active low, 1 for active high // Safety: bkf is set to a constant value (1) that is a valid value for the field per the reference manual - unsafe { tim.$bdtr.write(|w| w.dtg().bits(dtg).bk2f().bits(1).aoe().clear_bit().bk2e().set_bit().bk2p().bit(bkp).moe().$moe_set()); } + unsafe { tim.$bdtr().write(|w| w.dtg().bits(dtg).bk2f().bits(1).aoe().clear_bit().bk2e().set_bit().bk2p().bit(bkp).moe().$moe_set()); } // AF1: // BKINE = 1 -> break input enabled // BKINP should make input active high (BDTR BKP will set polarity), bit value varies timer to timer - tim.af2.write(|w| w.bk2ine().set_bit().bk2inp().$bk2inp_setting()); + tim.af2().write(|w| w.bk2ine().set_bit().bk2inp().$bk2inp_setting()); } )? else { // Safety: the DTG field of BDTR allows any 8-bit deadtime value and the dtg variable is u8 unsafe { - tim.$bdtr.write(|w| w.dtg().bits(dtg).aoe().clear_bit().moe().$moe_set()); + tim.$bdtr().write(|w| w.dtg().bits(dtg).aoe().clear_bit().moe().$moe_set()); } } // BDTR: Advanced-control timers // Set CCxP = OCxREF / CCxNP = !OCxREF // Refer to RM0433 Rev 6 - Table 324. - tim.$bdtr.modify(|_, w| w.moe().$moe_set()); + tim.$bdtr().modify(|_, w| w.moe().$moe_set()); )? $( match self.alignment { Alignment::Left => { }, - Alignment::Right => { tim.cr1.modify(|_, w| w.dir().down()); }, - Alignment::Center => { tim.cr1.modify(|_, w| w.$cms().center_aligned3()); } + Alignment::Right => { tim.cr1().modify(|_, w| w.dir().down()); }, + Alignment::Center => { tim.cr1().modify(|_, w| w.$cms().center_aligned3()); } } )? - tim.cr1.modify(|_, w| w.cen().enabled()); + tim.cr1().modify(|_, w| w.cen().enabled()); (PwmControl::new(), PINS::split()) } @@ -1391,19 +1395,19 @@ macro_rules! tim_hal { fn is_fault_active(&self) -> bool { let tim = unsafe { &*<$TIMX>::ptr() }; - !tim.$bdtr.read().moe().bit() + !tim.$bdtr().read().moe().bit() } fn clear_fault(&mut self) { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.$bdtr.modify(|_, w| w.moe().set_bit()); + tim.$bdtr().modify(|_, w| w.moe().set_bit()); } fn set_fault(&mut self) { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.$bdtr.modify(|_, w| w.moe().clear_bit()); + tim.$bdtr().modify(|_, w| w.moe().clear_bit()); } } )? @@ -1474,13 +1478,13 @@ macro_rules! tim_pin_hal { fn get_duty(&self) -> Self::Duty { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.ccr[$CH as usize].read().ccr().bits() + tim.ccr($CH as usize).read().ccr().bits() } fn get_max_duty(&self) -> Self::Duty { let tim = unsafe { &*<$TIMX>::ptr() }; - let arr = tim.arr.read().arr().bits(); + let arr = tim.arr().read().arr().bits(); // One PWM cycle is ARR+1 counts long // Valid PWM duty cycles are 0 to ARR+1 @@ -1497,7 +1501,8 @@ macro_rules! tim_pin_hal { fn set_duty(&mut self, duty: Self::Duty) { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.ccr[$CH as usize].write(|w| w.ccr().bits(duty)); + //NOTE(unsafe) All bit patterns are valid + tim.ccr($CH as usize).write(|w| unsafe { w.ccr().bits(duty) }); } } @@ -1508,12 +1513,12 @@ macro_rules! tim_pin_hal { fn ccer_enable(&mut self) { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.ccer.modify(|r, w| unsafe { w.bits(r.bits() | Ch::::EN) }); + tim.ccer().modify(|r, w| unsafe { w.bits(r.bits() | Ch::::EN) }); } fn ccer_disable(&mut self) { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.ccer.modify(|r, w| unsafe { w.bits(r.bits() & !Ch::::EN) }); + tim.ccer().modify(|r, w| unsafe { w.bits(r.bits() & !Ch::::EN) }); } } @@ -1522,7 +1527,7 @@ macro_rules! tim_pin_hal { pub fn set_polarity(&mut self, pol: Polarity) { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.ccer.modify(|r, w| unsafe { w.bits(match pol { + tim.ccer().modify(|r, w| unsafe { w.bits(match pol { Polarity::ActiveLow => r.bits() | Ch::::POL, Polarity::ActiveHigh => r.bits() & !Ch::::POL, })}); @@ -1550,12 +1555,12 @@ macro_rules! tim_pin_hal { fn ccer_enable(&mut self) { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.ccer.modify(|r, w| unsafe { w.bits(r.bits() | Ch::::EN) }); + tim.ccer().modify(|r, w| unsafe { w.bits(r.bits() | Ch::::EN) }); } fn ccer_disable(&mut self) { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.ccer.modify(|r, w| unsafe { w.bits(r.bits() & !Ch::::EN) }); + tim.ccer().modify(|r, w| unsafe { w.bits(r.bits() & !Ch::::EN) }); } } @@ -1564,12 +1569,12 @@ macro_rules! tim_pin_hal { fn ccer_enable(&mut self) { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.ccer.modify(|r, w| unsafe { w.bits(r.bits() | Ch::::EN | Ch::::N_EN) }); + tim.ccer().modify(|r, w| unsafe { w.bits(r.bits() | Ch::::EN | Ch::::N_EN) }); } fn ccer_disable(&mut self) { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.ccer.modify(|r, w| unsafe { w.bits(r.bits() & !Ch::::EN & !Ch::::N_EN) }); + tim.ccer().modify(|r, w| unsafe { w.bits(r.bits() & !Ch::::EN & !Ch::::N_EN) }); } } @@ -1579,7 +1584,7 @@ macro_rules! tim_pin_hal { // Make sure we aren't switching to complementary after we enable the channel let tim = unsafe { &*<$TIMX>::ptr() }; - let enabled = (tim.ccer.read().bits() & Ch::::EN) != 0; + let enabled = (tim.ccer().read().bits() & Ch::::EN) != 0; assert!(!enabled); @@ -1591,7 +1596,7 @@ macro_rules! tim_pin_hal { pub fn set_comp_polarity(&mut self, pol: Polarity) { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.ccer.modify(|r, w| unsafe { w.bits(match pol { + tim.ccer().modify(|r, w| unsafe { w.bits(match pol { Polarity::ActiveLow => r.bits() | Ch::::N_POL, Polarity::ActiveHigh => r.bits() & !Ch::::N_POL, })}); @@ -1725,16 +1730,16 @@ macro_rules! lptim_hal { assert!(reload < 128 * (1 << 16)); // Calculate prescaler - use pac::$timX::cfgr::PRESC_A; + use pac::$timX::cfgr::PRESC; let (prescale, prescale_div) = match reload / (1 << 16) { - 0 => (PRESC_A::Div1, 1), - 1 => (PRESC_A::Div2, 2), - 2..=3 => (PRESC_A::Div4, 4), - 4..=7 => (PRESC_A::Div8, 8), - 8..=15 => (PRESC_A::Div16, 16), - 16..=31 => (PRESC_A::Div32, 32), - 32..=63 => (PRESC_A::Div64, 64), - _ => (PRESC_A::Div128, 128), + 0 => (PRESC::Div1, 1), + 1 => (PRESC::Div2, 2), + 2..=3 => (PRESC::Div4, 4), + 4..=7 => (PRESC::Div8, 8), + 8..=15 => (PRESC::Div16, 16), + 16..=31 => (PRESC::Div32, 32), + 32..=63 => (PRESC::Div64, 64), + _ => (PRESC::Div128, 128), }; // Calcuate reload @@ -1743,19 +1748,20 @@ macro_rules! lptim_hal { assert!(arr > 0); // CFGR - tim.cfgr.modify(|_, w| w.presc().variant(prescale)); + tim.cfgr().modify(|_, w| w.presc().variant(prescale)); // Enable - tim.cr.modify(|_, w| w.enable().enabled()); + tim.cr().modify(|_, w| w.enable().enabled()); // Write ARR: LPTIM must be enabled - tim.arr.write(|w| w.arr().bits(arr as u16)); - while !tim.isr.read().arrok().is_set() {} - tim.icr.write(|w| w.arrokcf().clear()); + //NOTE(unsafe) All bit patterns are valid + tim.arr().write(|w| unsafe { w.arr().bits(arr as u16) }); + while !tim.isr().read().arrok().is_set() {} + tim.icr().write(|w| w.arrokcf().clear()); // PWM output is disabled by default, disable the // entire timer - tim.cr.modify(|_, w| w.enable().disabled()); + tim.cr().modify(|_, w| w.enable().disabled()); PINS::split() } @@ -1771,34 +1777,35 @@ macro_rules! lptim_hal { // LPTIM only has one output, so we disable the // entire timer - tim.cr.modify(|_, w| w.enable().disabled()); + tim.cr().modify(|_, w| w.enable().disabled()); } fn enable(&mut self) { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.cr.modify(|_, w| w.enable().enabled()); - tim.cr.modify(|_, w| w.cntstrt().start()); + tim.cr().modify(|_, w| w.enable().enabled()); + tim.cr().modify(|_, w| w.cntstrt().start()); } fn get_duty(&self) -> u16 { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.cmp.read().cmp().bits() + tim.cmp().read().cmp().bits() } fn get_max_duty(&self) -> u16 { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.arr.read().arr().bits() + tim.arr().read().arr().bits() } fn set_duty(&mut self, duty: u16) { let tim = unsafe { &*<$TIMX>::ptr() }; - tim.cmp.write(|w| w.cmp().bits(duty)); - while !tim.isr.read().cmpok().is_set() {} - tim.icr.write(|w| w.cmpokcf().clear()); + //NOTE(unsafe) All bit patterns are valid + tim.cmp().write(|w| unsafe { w.cmp().bits(duty) }); + while !tim.isr().read().cmpok().is_set() {} + tim.icr().write(|w| w.cmpokcf().clear()); } } )+ diff --git a/src/pwr.rs b/src/pwr.rs index 5f9258c6..fdc00eb5 100644 --- a/src/pwr.rs +++ b/src/pwr.rs @@ -210,13 +210,13 @@ macro_rules! smps_en { #[cfg(not(feature = "rm0455"))] macro_rules! d3cr { ($e:expr) => { - $e.d3cr + $e.d3cr() }; } #[cfg(feature = "rm0455")] macro_rules! d3cr { ($e:expr) => { - $e.srdcr + $e.srdcr() }; } @@ -227,7 +227,7 @@ pub(crate) fn current_vos() -> VoltageScale { feature = "revision_v", any(feature = "rm0433", feature = "rm0399") ))] - if unsafe { (*SYSCFG::ptr()).pwrcr.read().oden().bit_is_set() } { + if unsafe { (*SYSCFG::ptr()).pwrcr().read().oden().bit_is_set() } { return VoltageScale::Scale0; } @@ -276,42 +276,74 @@ impl Pwr { match self.supply_configuration { LDOSupply => { assert!( - smps_en!(self.rb.cr3.read()).bit_is_clear(), + smps_en!(self.rb.cr3().read()).bit_is_clear(), "{}", error ); - assert!(self.rb.cr3.read().ldoen().bit_is_set(), "{}", error); + assert!(self.rb.cr3().read().ldoen().bit_is_set(), "{}", error); } DirectSMPS => { - assert!(smps_en!(self.rb.cr3.read()).bit_is_set(), "{}", error); - assert!(self.rb.cr3.read().ldoen().bit_is_clear(), "{}", error); + assert!( + smps_en!(self.rb.cr3().read()).bit_is_set(), + "{}", + error + ); + assert!( + self.rb.cr3().read().ldoen().bit_is_clear(), + "{}", + error + ); } SMPSFeedsIntoLDO1V8 => { - assert!(smps_en!(self.rb.cr3.read()).bit_is_set(), "{}", error); - assert!(self.rb.cr3.read().ldoen().bit_is_clear(), "{}", error); assert!( - smps_level!(self.rb.cr3.read()).bits() == 1, + smps_en!(self.rb.cr3().read()).bit_is_set(), + "{}", + error + ); + assert!( + self.rb.cr3().read().ldoen().bit_is_clear(), + "{}", + error + ); + assert!( + smps_level!(self.rb.cr3().read()).bits() == 1, "{}", error ); } SMPSFeedsIntoLDO2V5 => { - assert!(smps_en!(self.rb.cr3.read()).bit_is_set(), "{}", error); - assert!(self.rb.cr3.read().ldoen().bit_is_clear(), "{}", error); assert!( - smps_level!(self.rb.cr3.read()).bits() == 2, + smps_en!(self.rb.cr3().read()).bit_is_set(), + "{}", + error + ); + assert!( + self.rb.cr3().read().ldoen().bit_is_clear(), + "{}", + error + ); + assert!( + smps_level!(self.rb.cr3().read()).bits() == 2, "{}", error ); } Bypass => { assert!( - smps_en!(self.rb.cr3.read()).bit_is_clear(), + smps_en!(self.rb.cr3().read()).bit_is_clear(), + "{}", + error + ); + assert!( + self.rb.cr3().read().ldoen().bit_is_clear(), + "{}", + error + ); + assert!( + self.rb.cr3().read().bypass().bit_is_set(), "{}", error ); - assert!(self.rb.cr3.read().ldoen().bit_is_clear(), "{}", error); - assert!(self.rb.cr3.read().bypass().bit_is_set(), "{}", error); } Default => {} // Default configuration is NOT verified } @@ -445,12 +477,12 @@ impl Pwr { // know what happened between the previous POR and here. #[cfg(not(feature = "smps"))] - self.rb.cr3.modify(|_, w| { + self.rb.cr3().modify(|_, w| { w.scuen().set_bit().ldoen().set_bit().bypass().clear_bit() }); #[cfg(feature = "smps")] - self.rb.cr3.modify(|_, w| { + self.rb.cr3().modify(|_, w| { use SupplyConfiguration::*; match self.supply_configuration { @@ -489,7 +521,7 @@ impl Pwr { // in the D3CR.VOS and CR3.SDLEVEL fields. By default after reset // VOS = Scale 3, so check that the voltage on the VCAP pins = // 1.0V. - while self.rb.csr1.read().actvosrdy().bit_is_clear() {} + while self.rb.csr1().read().actvosrdy().bit_is_clear() {} // We have now entered Run mode. See RM0433 Rev 7 Section 6.6.1 @@ -510,9 +542,13 @@ impl Pwr { ))] if matches!(self.target_vos, VoltageScale::Scale0) { unsafe { - (*RCC::ptr()).apb4enr.modify(|_, w| w.syscfgen().enabled()) + (*RCC::ptr()) + .apb4enr() + .modify(|_, w| w.syscfgen().enabled()) + }; + unsafe { + (*SYSCFG::ptr()).pwrcr().modify(|_, w| w.oden().set_bit()) }; - unsafe { (*SYSCFG::ptr()).pwrcr.modify(|_, w| w.oden().set_bit()) }; while d3cr!(self.rb).read().vosrdy().bit_is_clear() {} vos = VoltageScale::Scale0; } @@ -525,27 +561,27 @@ impl Pwr { // RM0468 section 6.8.6 says that before being able to use VOS0, // D3CR.VOS must equal CSR1.ACTVOS and CSR1.ACTVOSRDY must be set. while d3cr!(self.rb).read().vos().bits() - != self.rb.csr1.read().actvos().bits() + != self.rb.csr1().read().actvos().bits() {} - while self.rb.csr1.read().actvosrdy().bit_is_clear() {} + while self.rb.csr1().read().actvosrdy().bit_is_clear() {} } #[cfg(all(feature = "revision_v", feature = "rm0455"))] if matches!(self.target_vos, VoltageScale::Scale0) { // RM0455 section 6.8.6 says that CSR1.ACTVOSRDY must be set, // before VOS0 can be changed. - while self.rb.csr1.read().actvosrdy().bit_is_clear() {} + while self.rb.csr1().read().actvosrdy().bit_is_clear() {} vos = VoltageScale::Scale0; self.voltage_scaling_transition(vos); } // Disable backup power domain write protection - self.rb.cr1.modify(|_, w| w.dbp().set_bit()); - while self.rb.cr1.read().dbp().bit_is_clear() {} + self.rb.cr1().modify(|_, w| w.dbp().set_bit()); + while self.rb.cr1().read().dbp().bit_is_clear() {} if self.backup_regulator { - self.rb.cr2.modify(|_, w| w.bren().set_bit()); - while self.rb.cr2.read().brrdy().bit_is_clear() {} + self.rb.cr2().modify(|_, w| w.bren().set_bit()); + while self.rb.cr2().read().brrdy().bit_is_clear() {} } let backup = unsafe { BackupREC::new_singleton(self.backup_regulator) }; diff --git a/src/qei.rs b/src/qei.rs index d780d8b8..ad08ee43 100644 --- a/src/qei.rs +++ b/src/qei.rs @@ -171,7 +171,7 @@ macro_rules! tim_hal { }); // enable and configure to capture on rising edge - tim.ccer.write(|w| { + tim.ccer().write(|w| { w.cc1e() .set_bit() .cc1p() @@ -183,11 +183,12 @@ macro_rules! tim_hal { }); // configure as quadrature encoder - tim.smcr.write(|w| { w.sms().bits(3) }); + //NOTE(unsafe) 3 is a valid bit patterns for w.sms() + tim.smcr().write(|w| unsafe { w.sms().bits(3) }); #[allow(unused_unsafe)] // method is safe for some timers - tim.arr.write(|w| unsafe { w.bits(u32::MAX) }); - tim.cr1.write(|w| w.cen().set_bit()); + tim.arr().write(|w| unsafe { w.bits(u32::MAX) }); + tim.cr1().write(|w| w.cen().set_bit()); Qei { tim } } @@ -214,11 +215,11 @@ macro_rules! tim_hal { type Count = $bits; fn count(&self) -> $bits { - self.tim.cnt.read().bits() as $bits + self.tim.cnt().read().bits() as $bits } fn direction(&self) -> Direction { - if self.tim.cr1.read().dir().bit_is_clear() { + if self.tim.cr1().read().dir().bit_is_clear() { hal::Direction::Upcounting } else { hal::Direction::Downcounting diff --git a/src/rcc/backup.rs b/src/rcc/backup.rs index 253c646f..221569c0 100644 --- a/src/rcc/backup.rs +++ b/src/rcc/backup.rs @@ -78,7 +78,7 @@ mod rtc { fn enable(self) -> Self { // unsafe: Owned exclusive access to this bitfield interrupt::free(|_| { - let bdcr = unsafe { &(*RCC::ptr()).bdcr }; + let bdcr = unsafe { &(*RCC::ptr()).bdcr() }; bdcr.modify(|_, w| w.rtcen().set_bit()); }); self @@ -87,7 +87,7 @@ mod rtc { fn disable(self) -> Self { // unsafe: Owned exclusive access to this bitfield interrupt::free(|_| { - let bdcr = unsafe { &(*RCC::ptr()).bdcr }; + let bdcr = unsafe { &(*RCC::ptr()).bdcr() }; bdcr.modify(|_, w| w.rtcen().clear_bit()); }); self @@ -96,7 +96,7 @@ mod rtc { fn reset(self) -> Self { // unsafe: Owned exclusive access to this bitfield interrupt::free(|_| { - let bdcr = unsafe { &(*RCC::ptr()).bdcr }; + let bdcr = unsafe { &(*RCC::ptr()).bdcr() }; #[cfg(not(feature = "rm0455"))] bdcr.modify(|_, w| w.bdrst().set_bit()); @@ -104,23 +104,23 @@ mod rtc { bdcr.modify(|_, w| w.bdrst().clear_bit()); #[cfg(feature = "rm0455")] - bdcr.modify(|_, w| w.vswrst().set_bit()); + bdcr().modify(|_, w| w.vswrst().set_bit()); #[cfg(feature = "rm0455")] - bdcr.modify(|_, w| w.vswrst().set_bit()); + bdcr().modify(|_, w| w.vswrst().set_bit()); }); self } } /// RTC kernel clock source selection - pub type RtcClkSel = crate::stm32::rcc::bdcr::RTCSEL_A; + pub type RtcClkSel = crate::stm32::rcc::bdcr::RTCSEL; impl Rtc { /// Returns true if the RTC is enabled. pub fn is_enabled(&self) -> bool { // unsafe: Owned exclusive access to this bitfield interrupt::free(|_| { - let bdcr = unsafe { &(*RCC::ptr()).bdcr }; + let bdcr = unsafe { &(*RCC::ptr()).bdcr() }; bdcr.read().rtcen().bit_is_set() }) } @@ -136,7 +136,7 @@ mod rtc { pub fn kernel_clk_mux(&mut self, sel: RtcClkSel) { // unsafe: Owned exclusive access to this bitfield interrupt::free(|_| { - let bdcr = unsafe { &(*RCC::ptr()).bdcr }; + let bdcr = unsafe { &(*RCC::ptr()).bdcr() }; bdcr.modify(|_, w| w.rtcsel().variant(sel)); }); } @@ -144,7 +144,7 @@ mod rtc { /// Return the current kernel clock selection pub fn get_kernel_clk_mux(&self) -> RtcClkSel { // unsafe: We only read from this bitfield - let bdcr = unsafe { &(*RCC::ptr()).bdcr }; + let bdcr = unsafe { &(*RCC::ptr()).bdcr() }; bdcr.read().rtcsel().variant() } } diff --git a/src/rcc/mco.rs b/src/rcc/mco.rs index 315bc75c..00053573 100644 --- a/src/rcc/mco.rs +++ b/src/rcc/mco.rs @@ -3,8 +3,8 @@ use super::Rcc; use crate::time::Hertz; -pub use crate::stm32::rcc::cfgr::MCO1_A as MCO1; -pub use crate::stm32::rcc::cfgr::MCO2_A as MCO2; +pub use crate::stm32::rcc::cfgr::MCO1; +pub use crate::stm32::rcc::cfgr::MCO2; /// Clock settings for Micro-Controller Out 1 (MCO1) pub struct MCO1Config { diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index 2e1c5111..38fc9a16 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -144,23 +144,23 @@ use crate::pwr::PowerConfiguration; use crate::pwr::VoltageScale as Voltage; -use crate::stm32::rcc::cfgr::SW_A as SW; -use crate::stm32::rcc::cfgr::TIMPRE_A as TIMPRE; -use crate::stm32::rcc::pllckselr::PLLSRC_A as PLLSRC; +use crate::stm32::rcc::cfgr::SW; +use crate::stm32::rcc::cfgr::TIMPRE; +use crate::stm32::rcc::pllckselr::PLLSRC; use crate::stm32::{RCC, SYSCFG}; use crate::time::Hertz; #[cfg(feature = "rm0455")] -use crate::stm32::rcc::cdcfgr1::HPRE_A as HPRE; +use crate::stm32::rcc::cdcfgr1::HPRE; #[cfg(not(feature = "rm0455"))] -use crate::stm32::rcc::d1cfgr::HPRE_A as HPRE; +use crate::stm32::rcc::d1cfgr::HPRE; #[cfg(feature = "log")] use log::debug; #[cfg(feature = "rm0455")] -use crate::stm32::rcc::cdccipr::CKPERSEL_A as CKPERSEL; +use crate::stm32::rcc::cdccipr::CKPERSEL; #[cfg(not(feature = "rm0455"))] -use crate::stm32::rcc::d1ccipr::CKPERSEL_A as CKPERSEL; +use crate::stm32::rcc::d1ccipr::CKPERSEL; pub mod backup; mod core_clocks; @@ -576,10 +576,10 @@ impl Rcc { let flash = unsafe { &(*FLASH::ptr()) }; // Adjust flash wait states - flash.acr.write(|w| unsafe { + flash.acr().write(|w| unsafe { w.wrhighfreq().bits(progr_delay).latency().bits(wait_states) }); - while flash.acr.read().latency().bits() != wait_states {} + while flash.acr().read().latency().bits() != wait_states {} } /// Setup sys_ck @@ -696,16 +696,19 @@ impl Rcc { // do so it would need to ensure all PLLxON bits are clear // before changing the value of HSIDIV let hsi = HSI; - assert!(rcc.cr.read().hsion().is_on(), "HSI oscillator must be on!"); - assert!(rcc.cr.read().hsidiv().is_div1()); + assert!( + rcc.cr().read().hsion().is_on(), + "HSI oscillator must be on!" + ); + assert!(rcc.cr().read().hsidiv().is_div1()); let csi = CSI; let hsi48 = HSI48; // Enable LSI for RTC, IWDG, AWU, or MCO2 let lsi = LSI; - rcc.csr.modify(|_, w| w.lsion().on()); - while rcc.csr.read().lsirdy().is_not_ready() {} + rcc.csr().modify(|_, w| w.lsion().on()); + while rcc.csr().read().lsirdy().is_not_ready() {} // per_ck from HSI by default let (per_ck, ckpersel) = @@ -821,18 +824,19 @@ impl Rcc { Self::flash_setup(rcc_aclk, pwrcfg.vos); // Ensure CSI is on and stable - rcc.cr.modify(|_, w| w.csion().on()); - while rcc.cr.read().csirdy().is_not_ready() {} + rcc.cr().modify(|_, w| w.csion().on()); + while rcc.cr().read().csirdy().is_not_ready() {} // Ensure HSI48 is on and stable - rcc.cr.modify(|_, w| w.hsi48on().on()); - while rcc.cr.read().hsi48rdy().is_not_ready() {} + rcc.cr().modify(|_, w| w.hsi48on().on()); + while rcc.cr().read().hsi48rdy().is_not_ready() {} // Set the MCO outputs. // // It is highly recommended to configure these bits only after // reset, before enabling the external oscillators and the PLLs. - rcc.cfgr.modify(|_, w| { + //NOTE(unsafe) Only valid bit patterns written + rcc.cfgr().modify(|_, w| unsafe { w.mco1() .variant(self.config.mco1.source) .mco1pre() @@ -847,10 +851,10 @@ impl Rcc { let hse_ck = match self.config.hse { Some(hse) => { // Ensure HSE is on and stable - rcc.cr.modify(|_, w| { + rcc.cr().modify(|_, w| { w.hseon().on().hsebyp().bit(self.config.bypass_hse) }); - while rcc.cr.read().hserdy().is_not_ready() {} + while rcc.cr().read().hserdy().is_not_ready() {} Some(Hertz::from_raw(hse)) } @@ -863,32 +867,32 @@ impl Rcc { } else { PLLSRC::Hsi }; - rcc.pllckselr.modify(|_, w| w.pllsrc().variant(pllsrc)); + rcc.pllckselr().modify(|_, w| w.pllsrc().variant(pllsrc)); // PLL1 if pll1_p_ck.is_some() { // Enable PLL and wait for it to stabilise - rcc.cr.modify(|_, w| w.pll1on().on()); - while rcc.cr.read().pll1rdy().is_not_ready() {} + rcc.cr().modify(|_, w| w.pll1on().on()); + while rcc.cr().read().pll1rdy().is_not_ready() {} } // PLL2 if pll2_p_ck.is_some() { // Enable PLL and wait for it to stabilise - rcc.cr.modify(|_, w| w.pll2on().on()); - while rcc.cr.read().pll2rdy().is_not_ready() {} + rcc.cr().modify(|_, w| w.pll2on().on()); + while rcc.cr().read().pll2rdy().is_not_ready() {} } // PLL3 if pll3_p_ck.is_some() { // Enable PLL and wait for it to stabilise - rcc.cr.modify(|_, w| w.pll3on().on()); - while rcc.cr.read().pll3rdy().is_not_ready() {} + rcc.cr().modify(|_, w| w.pll3on().on()); + while rcc.cr().read().pll3rdy().is_not_ready() {} } // Core Prescaler / AHB Prescaler / APB3 Prescaler #[cfg(not(feature = "rm0455"))] - rcc.d1cfgr.modify(|_, w| unsafe { + rcc.d1cfgr().modify(|_, w| unsafe { w.d1cpre() .bits(d1cpre_bits) .d1ppre() // D1 contains APB3 @@ -897,7 +901,7 @@ impl Rcc { .variant(hpre_bits) }); #[cfg(feature = "rm0455")] - rcc.cdcfgr1.modify(|_, w| unsafe { + rcc.cdcfgr1().modify(|_, w| unsafe { w.cdcpre() .bits(d1cpre_bits) .cdppre() // D1/CD contains APB3 @@ -908,20 +912,20 @@ impl Rcc { // Ensure core prescaler value is valid before future lower // core voltage #[cfg(not(feature = "rm0455"))] - while rcc.d1cfgr.read().d1cpre().bits() != d1cpre_bits {} + while rcc.d1cfgr().read().d1cpre().bits() != d1cpre_bits {} #[cfg(feature = "rm0455")] - while rcc.cdcfgr1.read().cdcpre().bits() != d1cpre_bits {} + while rcc.cdcfgr1().read().cdcpre().bits() != d1cpre_bits {} // APB1 / APB2 Prescaler #[cfg(not(feature = "rm0455"))] - rcc.d2cfgr.modify(|_, w| unsafe { + rcc.d2cfgr().modify(|_, w| unsafe { w.d2ppre1() // D2 contains APB1 .bits(ppre1_bits) .d2ppre2() // D2 also contains APB2 .bits(ppre2_bits) }); #[cfg(feature = "rm0455")] - rcc.cdcfgr2.modify(|_, w| unsafe { + rcc.cdcfgr2().modify(|_, w| unsafe { w.cdppre1() // D2/CD contains APB1 .bits(ppre1_bits) .cdppre2() // D2/CD also contains APB2 @@ -930,24 +934,24 @@ impl Rcc { // APB4 Prescaler #[cfg(not(feature = "rm0455"))] - rcc.d3cfgr.modify(|_, w| unsafe { + rcc.d3cfgr().modify(|_, w| unsafe { w.d3ppre() // D3 contains APB4 .bits(ppre4_bits) }); #[cfg(feature = "rm0455")] - rcc.srdcfgr.modify(|_, w| unsafe { + rcc.srdcfgr().modify(|_, w| unsafe { w.srdppre() // D3 contains APB4 .bits(ppre4_bits) }); // Peripheral Clock (per_ck) #[cfg(not(feature = "rm0455"))] - rcc.d1ccipr.modify(|_, w| w.ckpersel().variant(ckpersel)); + rcc.d1ccipr().modify(|_, w| w.ckpersel().variant(ckpersel)); #[cfg(feature = "rm0455")] - rcc.cdccipr.modify(|_, w| w.ckpersel().variant(ckpersel)); + rcc.cdccipr().modify(|_, w| w.ckpersel().variant(ckpersel)); // Set timer clocks prescaler setting - rcc.cfgr.modify(|_, w| w.timpre().variant(timpre)); + rcc.cfgr().modify(|_, w| w.timpre().variant(timpre)); // Select system clock source let swbits = match (sys_use_pll1_p, self.config.hse.is_some()) { @@ -955,19 +959,19 @@ impl Rcc { (false, true) => SW::Hse as u8, _ => SW::Hsi as u8, }; - rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(swbits) }); - while rcc.cfgr.read().sws().bits() != swbits {} + rcc.cfgr().modify(|_, w| unsafe { w.sw().bits(swbits) }); + while rcc.cfgr().read().sws().bits() != swbits {} // IO compensation cell - Requires CSI clock and SYSCFG - assert!(rcc.cr.read().csirdy().is_ready()); - rcc.apb4enr.modify(|_, w| w.syscfgen().enabled()); + assert!(rcc.cr().read().csirdy().is_ready()); + rcc.apb4enr().modify(|_, w| w.syscfgen().enabled()); // Enable the compensation cell, using back-bias voltage code // provide by the cell. - syscfg.cccsr.modify(|_, w| { + syscfg.cccsr().modify(|_, w| { w.en().set_bit().cs().clear_bit().hslv().clear_bit() }); - while syscfg.cccsr.read().ready().bit_is_clear() {} + while syscfg.cccsr().read().ready().bit_is_clear() {} // This section prints the final register configuration for the main RCC registers: // - System Clock and PLL Source MUX @@ -978,7 +982,7 @@ impl Rcc { { debug!("--- RCC register settings"); - let cfgr = rcc.cfgr.read(); + let cfgr = rcc.cfgr().read(); debug!( "CFGR register: SWS (System Clock Mux)={:?}", cfgr.sws().variant().unwrap() @@ -986,30 +990,30 @@ impl Rcc { #[cfg(not(feature = "rm0455"))] { - let d1cfgr = rcc.d1cfgr.read(); + let d1cfgr = rcc.d1cfgr().read(); debug!( "D1CFGR register: D1CPRE={:?} HPRE={:?} D1PPRE={:?}", - d1cfgr.d1cpre().variant().unwrap(), - d1cfgr.hpre().variant().unwrap(), - d1cfgr.d1ppre().variant().unwrap(), + d1cfgr.d1cpre().variant(), + d1cfgr.hpre().variant(), + d1cfgr.d1ppre().variant(), ); - let d2cfgr = rcc.d2cfgr.read(); + let d2cfgr = rcc.d2cfgr().read(); debug!( "D2CFGR register: D2PPRE1={:?} D2PPRE1={:?}", - d2cfgr.d2ppre1().variant().unwrap(), - d2cfgr.d2ppre2().variant().unwrap(), + d2cfgr.d2ppre1().variant(), + d2cfgr.d2ppre2().variant(), ); - let d3cfgr = rcc.d3cfgr.read(); + let d3cfgr = rcc.d3cfgr().read(); debug!( "D3CFGR register: D3PPRE={:?}", - d3cfgr.d3ppre().variant().unwrap(), + d3cfgr.d3ppre().variant(), ); } #[cfg(feature = "rm0455")] { - let cdcfgr1 = rcc.cdcfgr1.read(); + let cdcfgr1 = rcc.cdcfgr1().read(); debug!( "CDCFGR1 register: CDCPRE={:?} HPRE={:?} CDPPRE={:?}", cdcfgr1.cdcpre().variant().unwrap(), @@ -1017,21 +1021,21 @@ impl Rcc { cdcfgr1.cdppre().variant().unwrap(), ); - let cdcfgr2 = rcc.cdcfgr2.read(); + let cdcfgr2 = rcc.cdcfgr2().read(); debug!( "CDCFGR2 register: CDPPRE1={:?} CDPPRE1={:?}", cdcfgr2.cdppre1().variant().unwrap(), cdcfgr2.cdppre2().variant().unwrap(), ); - let srdcfgr = rcc.srdcfgr.read(); + let srdcfgr = rcc.srdcfgr().read(); debug!( "SRDCFGR register: SRDPPRE={:?}", srdcfgr.srdppre().bits(), ); } - let pllckselr = rcc.pllckselr.read(); + let pllckselr = rcc.pllckselr().read(); debug!( "PLLCKSELR register: PLLSRC={:?} DIVM1={:#x} DIVM2={:#x} DIVM3={:#x}", pllckselr.pllsrc().variant(), @@ -1040,7 +1044,7 @@ impl Rcc { pllckselr.divm3().bits(), ); - let pllcfgr = rcc.pllcfgr.read(); + let pllcfgr = rcc.pllcfgr().read(); debug!( "PLLCKSELR register (PLL1): PLL1FRACEN={:?} PLL1VCOSEL={:?} PLL1RGE={:?} DIVP1EN={:?} DIVQ1EN={:?} DIVR1EN={:?}", pllcfgr.pll1fracen().variant(), @@ -1069,7 +1073,7 @@ impl Rcc { pllcfgr.divr3en().variant(), ); - let pll1divr = rcc.pll1divr.read(); + let pll1divr = rcc.pll1divr().read(); debug!( "PLL1DIVR register: DIVN1={:#x} DIVP1={:#x} DIVQ1={:#x} DIVR1={:#x}", pll1divr.divn1().bits(), @@ -1078,13 +1082,13 @@ impl Rcc { pll1divr.divr1().bits(), ); - let pll1fracr = rcc.pll1fracr.read(); + let pll1fracr = rcc.pll1fracr().read(); debug!( "PLL1FRACR register: FRACN1={:#x}", pll1fracr.fracn1().bits(), ); - let pll2divr = rcc.pll2divr.read(); + let pll2divr = rcc.pll2divr().read(); debug!( "PLL2DIVR register: DIVN2={:#x} DIVP2={:#x} DIVQ2={:#x} DIVR2={:#x}", pll2divr.divn2().bits(), @@ -1093,13 +1097,13 @@ impl Rcc { pll2divr.divr2().bits(), ); - let pll2fracr = rcc.pll2fracr.read(); + let pll2fracr = rcc.pll2fracr().read(); debug!( "PLL2FRACR register: FRACN2={:#x}", pll2fracr.fracn2().bits(), ); - let pll3divr = rcc.pll3divr.read(); + let pll3divr = rcc.pll3divr().read(); debug!( "PLL3DIVR register: DIVN3={:#x} DIVP3={:#x} DIVQ3={:#x} DIVR3={:#x}", pll3divr.divn3().bits(), @@ -1108,7 +1112,7 @@ impl Rcc { pll3divr.divr3().bits(), ); - let pll3fracr = rcc.pll3fracr.read(); + let pll3fracr = rcc.pll3fracr().read(); debug!( "PLL3FRACR register: FRACN3={:#x}", pll3fracr.fracn3().bits(), diff --git a/src/rcc/pll.rs b/src/rcc/pll.rs index ec9d9e81..028e7c79 100644 --- a/src/rcc/pll.rs +++ b/src/rcc/pll.rs @@ -105,7 +105,7 @@ macro_rules! vco_setup { assert!((1_000_000..=2_000_000).contains(&ref_x_ck)); // Configure VCO - $rcc.pllcfgr.modify(|_, w| { + $rcc.pllcfgr().modify(|_, w| { w.$pllXvcosel() .medium_vco() // 150 - 420MHz Medium VCO .$pllXrge() @@ -158,11 +158,11 @@ macro_rules! vco_setup { assert!((2_000_000..=16_000_000).contains(&ref_x_ck)); // Configure VCO - $rcc.pllcfgr.modify(|_, w| { + $rcc.pllcfgr().modify(|_, w| { w.$pllXvcosel() .wide_vco() // Wide Range VCO }); - $rcc.pllcfgr.modify(|_, w| { + $rcc.pllcfgr().modify(|_, w| { match ref_x_ck { 2_000_000 ..= 3_999_999 => // ref_x_ck is 2 - 4 MHz w.$pllXrge().range2(), @@ -226,13 +226,14 @@ macro_rules! pll_setup { let pll_x_n = vco_ck_target / ref_x_ck; // Write dividers - rcc.pllckselr.modify(|_, w| { + //NOTE(unsafe) Only valid bit patterns written, checked by vco_setup + rcc.pllckselr().modify(|_, w| unsafe { w.$divmX().bits(pll_x_m as u8) // ref prescaler }); // unsafe as not all values are permitted: see RM0433 assert!(pll_x_n >= 4); assert!(pll_x_n <= 512); - rcc.$pllXdivr + rcc.$pllXdivr() .modify(|_, w| unsafe { w.$divnX().bits((pll_x_n - 1) as u16) }); // Configure N divider. Returns the resulting VCO frequency @@ -241,12 +242,13 @@ macro_rules! pll_setup { // Calculate FRACN let pll_x_fracn = calc_fracn(ref_x_ck as f32, pll_x_n as f32, pll_x as f32, output as f32); //RCC_PLL1FRACR - rcc.$pllXfracr.modify(|_, w| { + //NOTE(unsafe) Only valid bit patterns written, checked by calc_fracn + rcc.$pllXfracr().modify(|_, w| unsafe { w.$fracnx().bits(pll_x_fracn) }); // Enable FRACN - rcc.pllcfgr.modify(|_, w| { - w.$pllXfracen().set() + rcc.pllcfgr().modify(|_, w| { + w.$pllXfracen().set_() }); calc_vco_ck(ref_x_ck, pll_x_n, pll_x_fracn) @@ -257,12 +259,14 @@ macro_rules! pll_setup { // Round up instead of down for FractionalNotLess pll_x_fracn += 1; //RCC_PLL1FRACR - rcc.$pllXfracr.modify(|_, w| { + // TODO: This cant be right, calc_fracn only checks that pll_x_fracn <= the max value, + // since we have now incremented it by 1, that check does no longer hold? + rcc.$pllXfracr().modify(|_, w| unsafe { w.$fracnx().bits(pll_x_fracn) }); // Enable FRACN - rcc.pllcfgr.modify(|_, w| { - w.$pllXfracen().set() + rcc.pllcfgr().modify(|_, w| { + w.$pllXfracen().set_() }); calc_vco_ck(ref_x_ck, pll_x_n, pll_x_fracn) @@ -271,7 +275,7 @@ macro_rules! pll_setup { // Iterative _ => { // No FRACN - rcc.pllcfgr.modify(|_, w| { + rcc.pllcfgr().modify(|_, w| { w.$pllXfracen().reset() }); @@ -301,16 +305,16 @@ macro_rules! pll_setup { "Cannot achieve output frequency this low: Maximum PLL divider is 128"); // Setup divider - rcc.$pllXdivr + rcc.$pllXdivr() .modify(|_, w| $($unsafe)* { w.$div().bits((dividers.$DD - 1) as u8) }); - rcc.pllcfgr.modify(|_, w| w.$diven().enabled()); + rcc.pllcfgr().modify(|_, w| w.$diven().enabled()); Some(Hertz::from_raw(vco_ck / dividers.$DD)) }, None => { - rcc.pllcfgr.modify(|_, w| w.$diven().disabled()); + rcc.pllcfgr().modify(|_, w| w.$diven().disabled()); None } }, @@ -372,23 +376,23 @@ impl Rcc { OUTPUTS: [ // unsafe as not all values are permitted: see RM0433 p_ck: (divp1, divp1en, 0, unsafe), - q_ck: (divq1, divq1en, 1), - r_ck: (divr1, divr1en, 2) ], + q_ck: (divq1, divq1en, 1, unsafe), + r_ck: (divr1, divr1en, 2, unsafe) ], pll1_p) } pll_setup! { pll2_setup: (pll2vcosel, pll2rge, pll2fracen, pll2divr, divn2, divm2, pll2fracr, fracn2, OUTPUTS: [ - p_ck: (divp2, divp2en, 0), - q_ck: (divq2, divq2en, 1), - r_ck: (divr2, divr2en, 2)]) + p_ck: (divp2, divp2en, 0, unsafe), + q_ck: (divq2, divq2en, 1, unsafe), + r_ck: (divr2, divr2en, 2, unsafe)]) } pll_setup! { pll3_setup: (pll3vcosel, pll3rge, pll3fracen, pll3divr, divn3, divm3, pll3fracr, fracn3, OUTPUTS: [ - p_ck: (divp3, divp3en, 0), - q_ck: (divq3, divq3en, 1), - r_ck: (divr3, divr3en, 2)]) + p_ck: (divp3, divp3en, 0, unsafe), + q_ck: (divq3, divq3en, 1, unsafe), + r_ck: (divr3, divr3en, 2, unsafe)]) } } diff --git a/src/rcc/rec.rs b/src/rcc/rec.rs index a4533f77..7b70096c 100644 --- a/src/rcc/rec.rs +++ b/src/rcc/rec.rs @@ -76,6 +76,8 @@ use super::Rcc; use crate::stm32::{rcc, RCC}; use cortex_m::interrupt; +//const X: stm32h7::stm32h743v::rcc::d1ccipr::FMCSEL = (); + /// A trait for Resetting, Enabling and Disabling a single peripheral pub trait ResetEnable { /// Enable this peripheral @@ -134,8 +136,8 @@ macro_rules! peripheral_reset_and_enable_control { $( $( #[ $pmeta:meta ] )* $(($Auto:ident))* $p:ident - $([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $ccip:ident $clk_doc:expr ])* - $([ group clk: $pk_g:ident $( $(($Variant_g:ident))* $ccip_g:ident $clk_doc_g:expr )* ])* + $([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $pk_alias:ident $ccip:ident $clk_doc:expr ])* + $([ group clk: $pk_g:ident $( $(($Variant_g:ident))* $pk_g_alias:ident $ccip_g:ident $clk_doc_g:expr )* ])* $([ fixed clk: $clk_doc_f:expr ])* ),* ];)+) => { @@ -182,10 +184,10 @@ macro_rules! peripheral_reset_and_enable_control { $AXBn, $(($Auto))* $p, [< $p:upper >], [< $p:lower >], $( $pmeta )* $( - [kernel $clk: $pk $(($Variant))* $ccip $clk_doc] + [kernel $clk: $pk $(($Variant))* $pk_alias $ccip $clk_doc] )* $( - [group clk: $pk_g [< $pk_g:lower >] $( $(($Variant_g))* $ccip_g $clk_doc_g )* ] + [group clk: $pk_g [< $pk_g:lower >] $( $(($Variant_g))* $pk_g_alias $ccip_g $clk_doc_g )* ] )* $( [fixed clk: $clk_doc_f] @@ -211,8 +213,8 @@ macro_rules! peripheral_reset_and_enable_control_generator { $p_lower:ident, // comments, equivalent to with the paste macro. $( $pmeta:meta )* - $([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $ccip:ident $clk_doc:expr ])* - $([ group clk: $pk_g:ident $pk_g_lower:ident $( $(($Variant_g:ident))* $ccip_g:ident $clk_doc_g:expr )* ])* + $([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $pk_alias:ident $ccip:ident $clk_doc:expr ])* + $([ group clk: $pk_g:ident $pk_g_lower:ident $( $(($Variant_g:ident))* $pk_g_alias:ident $ccip_g:ident $clk_doc_g:expr )* ])* $([ fixed clk: $clk_doc_f:expr ])* ) => { paste::item! { @@ -285,7 +287,7 @@ macro_rules! peripheral_reset_and_enable_control_generator { interrupt::free(|_| { // LPEN let lpenr = unsafe { - &(*RCC::ptr()).[< $AXBn:lower lpenr >] + &(*RCC::ptr()).[< $AXBn:lower lpenr >]() }; lpenr.modify(|_, w| w.[< $p:lower lpen >]() .bit(lpm != LowPowerMode::Off)); @@ -308,7 +310,7 @@ macro_rules! peripheral_reset_and_enable_control_generator { // unsafe: Owned exclusive access to this bitfield interrupt::free(|_| { let enr = unsafe { - &(*RCC::ptr()).[< $AXBn:lower enr >] + &(*RCC::ptr()).[< $AXBn:lower enr >]() }; enr.modify(|_, w| w. [< $p:lower en >]().set_bit()); @@ -320,7 +322,7 @@ macro_rules! peripheral_reset_and_enable_control_generator { // unsafe: Owned exclusive access to this bitfield interrupt::free(|_| { let enr = unsafe { - &(*RCC::ptr()).[< $AXBn:lower enr >] + &(*RCC::ptr()).[< $AXBn:lower enr >]() }; enr.modify(|_, w| w. [< $p:lower en >]().clear_bit()); @@ -332,7 +334,7 @@ macro_rules! peripheral_reset_and_enable_control_generator { // unsafe: Owned exclusive access to this bitfield interrupt::free(|_| { let rstr = unsafe { - &(*RCC::ptr()).[< $AXBn:lower rstr >] + &(*RCC::ptr()).[< $AXBn:lower rstr >]() }; rstr.modify(|_, w| w. [< $p:lower rst >]().set_bit()); @@ -359,7 +361,7 @@ macro_rules! peripheral_reset_and_enable_control_generator { // unsafe: Owned exclusive access to this bitfield interrupt::free(|_| { let ccip = unsafe { - &(*RCC::ptr()).[< $ccip r >] + &(*RCC::ptr()).[< $ccip r >]() }; ccip.modify(|_, w| w. [< $pk:lower sel >]().variant(sel)); @@ -374,7 +376,7 @@ macro_rules! peripheral_reset_and_enable_control_generator { { // unsafe: We only read from this bitfield let ccip = unsafe { - &(*RCC::ptr()).[< $ccip r >] + &(*RCC::ptr()).[< $ccip r >]() }; ccip.read().[< $pk:lower sel >]().variant() } @@ -384,7 +386,7 @@ macro_rules! peripheral_reset_and_enable_control_generator { #[doc=$clk_doc] /// kernel clock source selection pub type [< $pk ClkSel >] = - rcc::[< $ccip r >]::[< $pk:upper SEL_A >]; + rcc::[< $ccip r >]::[< $pk_alias SEL >]; )* $( // Group kernel clocks impl [< $pk_g ClkSelGetter >] for $p {} @@ -394,7 +396,7 @@ macro_rules! peripheral_reset_and_enable_control_generator { #[doc=$clk_doc_g] /// kernel clock source selection. pub type [< $pk_g ClkSel >] = - rcc::[< $ccip_g r >]::[< $pk_g:upper SEL_A >]; + rcc::[< $ccip_g r >]::[< $pk_g_alias SEL >]; /// Can return #[doc=$clk_doc_g] @@ -410,7 +412,7 @@ macro_rules! peripheral_reset_and_enable_control_generator { { // unsafe: We only read from this bitfield let ccip = unsafe { - &(*RCC::ptr()).[< $ccip_g r >] + &(*RCC::ptr()).[< $ccip_g r >]() }; ccip.read().[< $pk_g:lower sel >]().variant() } @@ -432,7 +434,7 @@ macro_rules! peripheral_reset_and_enable_control_generator { // unsafe: Owned exclusive access to this bitfield interrupt::free(|_| { let ccip = unsafe { - &(*RCC::ptr()).[< $ccip_g r >] + &(*RCC::ptr()).[< $ccip_g r >]() }; ccip.modify(|_, w| w. [< $pk_g:lower sel >]().variant(sel)); @@ -459,13 +461,13 @@ macro_rules! variant_return_type { #[cfg(not(feature = "rm0455"))] macro_rules! autonomous { ($Auto:ident) => { - &(*RCC::ptr()).d3amr + &(*RCC::ptr()).d3amr() }; } #[cfg(feature = "rm0455")] macro_rules! autonomous { ($Auto:ident) => { - &(*RCC::ptr()).srdamr + &(*RCC::ptr()).srdamr() }; } @@ -494,8 +496,8 @@ peripheral_reset_and_enable_control! { AHB1, "" => [ Eth1Mac, #[cfg(any(feature = "rm0399"))] Art, - Adc12 [group clk: Adc(Variant) d3ccip "ADC"], - Usb1Otg [group clk: Usb d2ccip2 "USB"] + Adc12 [group clk: Adc(Variant) ADC d3ccip "ADC"], + Usb1Otg [group clk: Usb USB d2ccip2 "USB"] ]; #[cfg(any(feature = "rm0433", feature = "rm0399"))] AHB1, "" => [ @@ -504,8 +506,8 @@ peripheral_reset_and_enable_control! { #[cfg(feature = "rm0455")] AHB1, "" => [ Crc, - Usb1Otg [group clk: Usb cdccip2 "USB"], - Adc12 [group clk: Adc(Variant) srdccip "ADC"] + Usb1Otg [group clk: Usb USB cdccip2 "USB"], + Adc12 [group clk: Adc(Variant) ADC12 srdccip "ADC"] ]; @@ -516,11 +518,11 @@ peripheral_reset_and_enable_control! { ]; #[cfg(not(feature = "rm0455"))] AHB2, "" => [ - Rng [kernel clk: Rng d2ccip2 "RNG"] + Rng [kernel clk: Rng RNG d2ccip2 "RNG"] ]; #[cfg(feature = "rm0455")] AHB2, "" => [ - Rng [kernel clk: Rng cdccip2 "RNG"] + Rng [kernel clk: Rng RNG cdccip2 "RNG"] ]; #[cfg(feature = "rm0468")] AHB2, "" => [ @@ -534,25 +536,25 @@ peripheral_reset_and_enable_control! { ]; #[cfg(not(feature = "rm0455"))] AHB3, "" => [ - Sdmmc1 [group clk: Sdmmc d1ccip "SDMMC"], - Fmc [kernel clk: Fmc d1ccip "FMC"] + Sdmmc1 [group clk: Sdmmc SDMMC d1ccip "SDMMC"], + Fmc [kernel clk: Fmc FMC d1ccip "FMC"] ]; #[cfg(any(feature = "rm0433", feature = "rm0399"))] AHB3, "" => [ Jpgdec, - Qspi [kernel clk: Qspi d1ccip "QUADSPI"] + Qspi [kernel clk: Qspi FMC d1ccip "QUADSPI"] ]; #[cfg(feature = "rm0455")] AHB3, "" => [ Jpgdec, - Sdmmc1 [group clk: Sdmmc cdccip "SDMMC"], - Fmc [kernel clk: Fmc cdccip "FMC"], - Octospi1 [group clk: Octospi cdccip "OCTOSPI"], + Sdmmc1 [group clk: Sdmmc SDMMC cdccip "SDMMC"], + Fmc [kernel clk: Fmc FMC cdccip "FMC"], + Octospi1 [group clk: Octospi FMC cdccip "OCTOSPI"], Octospi2 [group clk: Octospi] ]; #[cfg(feature = "rm0468")] AHB3, "" => [ - Octospi1 [group clk: Octospi d1ccip "OCTOSPI"], + Octospi1 [group clk: Octospi FMC d1ccip "OCTOSPI"], Octospi2 [group clk: Octospi] ]; @@ -590,13 +592,13 @@ peripheral_reset_and_enable_control! { APB1L, "" => [ Dac12, - Cec [kernel clk: Cec(Variant) d2ccip2 "CEC"], - Lptim1 [kernel clk: Lptim1(Variant) d2ccip2 "LPTIM1"], - Usart2 [group clk: Usart234578(Variant) d2ccip2 "USART2/3/4/5/7/8"] + Cec [kernel clk: Cec(Variant) CEC d2ccip2 "CEC"], + Lptim1 [kernel clk: Lptim1(Variant) LPTIM1 d2ccip2 "LPTIM1"], + Usart2 [group clk: Usart234578(Variant) USART234578 d2ccip2 "USART2/3/4/5/7/8"] ]; #[cfg(any(feature = "rm0433", feature = "rm0399"))] APB1L, "" => [ - I2c1 [group clk: I2c123 d2ccip2 "I2C1/2/3"], + I2c1 [group clk: I2c123 I2C123 d2ccip2 "I2C1/2/3"], I2c2 [group clk: I2c123], I2c3 [group clk: I2c123] ]; @@ -604,16 +606,16 @@ peripheral_reset_and_enable_control! { APB1L, "" => [ Dac1, - I2c1 [group clk: I2c123 cdccip2 "I2C1/2/3"], + I2c1 [group clk: I2c123 I2C123 cdccip2 "I2C1/2/3"], I2c2 [group clk: I2c123], I2c3 [group clk: I2c123], - Cec [kernel clk: Cec(Variant) cdccip2 "CEC"], - Lptim1 [kernel clk: Lptim1(Variant) cdccip2 "LPTIM1"], - Usart2 [group clk: Usart234578(Variant) cdccip2 "USART2/3/4/5/7/8"] + Cec [kernel clk: Cec(Variant) CEC cdccip2 "CEC"], + Lptim1 [kernel clk: Lptim1(Variant) LPTIM1 cdccip2 "LPTIM1"], + Usart2 [group clk: Usart234578(Variant) USART234578 cdccip2 "USART2/3/4/5/7/8"] ]; #[cfg(feature = "rm0468")] APB1L, "" => [ - I2c1 [group clk: I2c1235 d2ccip2 "I2C1/2/3/5"], + I2c1 [group clk: I2c1235 I2C1235 d2ccip2 "I2C1/2/3/5"], I2c2 [group clk: I2c1235], I2c3 [group clk: I2c1235], I2c5 [group clk: I2c1235] @@ -626,20 +628,20 @@ peripheral_reset_and_enable_control! { ]; #[cfg(not(feature = "rm0455"))] APB1H, "" => [ - Fdcan [kernel clk: Fdcan(Variant) d2ccip1 "FDCAN"] + Fdcan [kernel clk: Fdcan(Variant) FDCAN d2ccip1 "FDCAN"] ]; #[cfg(any(feature = "rm0433", feature = "rm0399"))] APB1H, "" => [ - Swp [kernel clk: Swp d2ccip1 "SWPMI"] + Swp [kernel clk: Swp SWP d2ccip1 "SWPMI"] ]; #[cfg(feature = "rm0455")] APB1H, "" => [ - Fdcan [kernel clk: Fdcan(Variant) cdccip1 "FDCAN"], - Swpmi [kernel clk: Swpmi cdccip1 "SWPMI"] + Fdcan [kernel clk: Fdcan(Variant) FDCAN cdccip1 "FDCAN"], + Swpmi [kernel clk: Swpmi SWPMI cdccip1 "SWPMI"] ]; #[cfg(feature = "rm0468")] APB1H, "" => [ - Swpmi [kernel clk: Swpmi d2ccip1 "SWPMI"], + Swpmi [kernel clk: Swpmi SWPMI d2ccip1 "SWPMI"], Tim23, Tim24 ]; @@ -647,50 +649,48 @@ peripheral_reset_and_enable_control! { #[cfg(all())] APB2, "Advanced Peripheral Bus 2 (APB2) peripherals" => [ - Tim1, Tim8, Tim15, Tim16, Tim17 + Tim1, Tim8, Tim15, Tim16, Tim17, Hrtim ]; #[cfg(not(feature = "rm0455"))] APB2, "" => [ - Dfsdm1 [kernel clk: Dfsdm1 d2ccip1 "DFSDM1"], + Dfsdm1 [kernel clk: Dfsdm1 DFSDM1 d2ccip1 "DFSDM1"], - Sai1 [kernel clk: Sai1(Variant) d2ccip1 "SAI1"], + Sai1 [kernel clk: Sai1(Variant) SAI1 d2ccip1 "SAI1"], - Spi1 [group clk: Spi123(Variant) d2ccip1 "SPI1/2/3"], - Spi4 [group clk: Spi45(Variant) d2ccip1 "SPI4/5"], + Spi1 [group clk: Spi123(Variant) SAI1 d2ccip1 "SPI1/2/3"], + Spi4 [group clk: Spi45(Variant) SPI45 d2ccip1 "SPI4/5"], Spi5 [group clk: Spi45] ]; #[cfg(any(feature = "rm0433", feature = "rm0399"))] APB2, "" => [ - Hrtim, - - Sai2 [group clk: Sai23(Variant) d2ccip1 "SAI2/3"], + Sai2 [group clk: Sai23(Variant) SAI1 d2ccip1 "SAI2/3"], Sai3 [group clk: Sai23], - Usart1 [group clk: Usart16(Variant) d2ccip2 "USART1/6"], + Usart1 [group clk: Usart16(Variant) USART16 d2ccip2 "USART1/6"], Usart6 [group clk: Usart16] ]; #[cfg(feature = "rm0455")] APB2, "" => [ - Dfsdm1 [kernel clk: Dfsdm1 cdccip1 "DFSDM1"], + Dfsdm1 [kernel clk: Dfsdm1 DFSDM1 cdccip1 "DFSDM1"], - Sai1 [kernel clk: Sai1(Variant) cdccip1 "SAI1"], - Sai2 [kernel clk_a: Sai2A(Variant) cdccip1 + Sai1 [kernel clk: Sai1(Variant) SAI1 cdccip1 "SAI1"], + Sai2 [kernel clk_a: Sai2A(Variant) SAI1 cdccip1 "Sub-Block A of SAI2"] - [kernel clk_b: Sai2B(Variant) cdccip1 + [kernel clk_b: Sai2B(Variant) SAI1 cdccip1 "Sub-Block B of SAI2"], - Spi1 [group clk: Spi123(Variant) cdccip1 "SPI1/2/3"], - Spi4 [group clk: Spi45(Variant) cdccip1 "SPI4/5"], + Spi1 [group clk: Spi123(Variant) SAI1 cdccip1 "SPI1/2/3"], + Spi4 [group clk: Spi45(Variant) SPI45 cdccip1 "SPI4/5"], Spi5 [group clk: Spi45], - Usart1 [group clk: Usart16910(Variant) cdccip2 "USART1/6/9/10"], + Usart1 [group clk: Usart16910(Variant) USART16 cdccip2 "USART1/6/9/10"], Usart6 [group clk: Usart16910], Uart9 [group clk: Usart16910], Usart10 [group clk: Usart16910] ]; #[cfg(feature = "rm0468")] APB2, "" => [ - Usart1 [group clk: Usart16910(Variant) d2ccip2 "USART1/6/9/10"], + Usart1 [group clk: Usart16910(Variant) USART16910 d2ccip2 "USART1/6/9/10"], Usart6 [group clk: Usart16910], Uart9 [group clk: Usart16910], Usart10 [group clk: Usart16910] @@ -711,26 +711,26 @@ peripheral_reset_and_enable_control! { ]; #[cfg(not(feature = "rm0455"))] APB4, "" => [ - (Auto) Lptim2 [kernel clk: Lptim2(Variant) d3ccip "LPTIM2"], - (Auto) Lptim3 [group clk: Lptim345(Variant) d3ccip "LPTIM3/4/5"], + (Auto) Lptim2 [kernel clk: Lptim2(Variant) LPTIM2 d3ccip "LPTIM2"], + (Auto) Lptim3 [group clk: Lptim345(Variant) LPTIM2 d3ccip "LPTIM3/4/5"], (Auto) Lptim4 [group clk: Lptim345], (Auto) Lptim5 [group clk: Lptim345], - (Auto) I2c4 [kernel clk: I2c4 d3ccip "I2C4"], - (Auto) Spi6 [kernel clk: Spi6(Variant) d3ccip "SPI6"], - (Auto) Sai4 [kernel clk_a: Sai4A(Variant) d3ccip + (Auto) I2c4 [kernel clk: I2c4 I2C4 d3ccip "I2C4"], + (Auto) Spi6 [kernel clk: Spi6(Variant) SPI6 d3ccip "SPI6"], + (Auto) Sai4 [kernel clk_a: Sai4A(Variant) SAI4A d3ccip "Sub-Block A of SAI4"] - [kernel clk_b: Sai4B(Variant) d3ccip + [kernel clk_b: Sai4B(Variant) SAI4A d3ccip "Sub-Block B of SAI4"] ]; #[cfg(feature = "rm0455")] APB4, "" => [ (Auto) Dac2, - (Auto) Lptim2 [kernel clk: Lptim2(Variant) srdccip "LPTIM2"], + (Auto) Lptim2 [kernel clk: Lptim2(Variant) LPTIM2 srdccip "LPTIM2"], (Auto) Lptim3,// TODO [group clk: Lptim3(Variant) srdccip "LPTIM3"], - (Auto) I2c4 [kernel clk: I2c4 srdccip "I2C4"], - (Auto) Spi6 [kernel clk: Spi6(Variant) srdccip "SPI6"] + (Auto) I2c4 [kernel clk: I2c4 I2C4 srdccip "I2C4"], + (Auto) Spi6 [kernel clk: Spi6(Variant) SPI6 srdccip "SPI6"] ]; } diff --git a/src/rcc/reset_reason.rs b/src/rcc/reset_reason.rs index 4a57770b..aa4c7b3d 100644 --- a/src/rcc/reset_reason.rs +++ b/src/rcc/reset_reason.rs @@ -6,24 +6,24 @@ use core::fmt::Display; /// Gets and clears the reason of why the mcu was reset #[rustfmt::skip] pub fn get_reset_reason(rcc: &mut crate::stm32::RCC) -> ResetReason { - let reset_reason = rcc.rsr.read(); + let reset_reason = rcc.rsr().read(); // Clear the register - rcc.rsr.modify(|_, w| w.rmvf().clear()); + rcc.rsr().modify(|_, w| w.rmvf().clear_bit()); #[cfg(not(feature = "rm0455"))] // See R0433 Rev 7 Section 8.4.4 Reset source identification match ( - reset_reason.lpwrrstf().is_reset_occourred(), - reset_reason.wwdg1rstf().is_reset_occourred(), - reset_reason.iwdg1rstf().is_reset_occourred(), - reset_reason.sftrstf().is_reset_occourred(), - reset_reason.porrstf().is_reset_occourred(), - reset_reason.pinrstf().is_reset_occourred(), - reset_reason.borrstf().is_reset_occourred(), - reset_reason.d2rstf().is_reset_occourred(), - reset_reason.d1rstf().is_reset_occourred(), - reset_reason.cpurstf().is_reset_occourred(), + reset_reason.lpwrrstf().is_reset_occurred(), + reset_reason.wwdg1rstf().is_reset_occurred(), + reset_reason.iwdg1rstf().is_reset_occurred(), + reset_reason.sftrstf().is_reset_occurred(), + reset_reason.porrstf().is_reset_occurred(), + reset_reason.pinrstf().is_reset_occurred(), + reset_reason.borrstf().is_reset_occurred(), + reset_reason.d2rstf().is_reset_occurred(), + reset_reason.d1rstf().is_reset_occurred(), + reset_reason.cpurstf().is_reset_occurred(), ) { (false, false, false, false, true, true, true, true, true, true) => { ResetReason::PowerOnReset diff --git a/src/rng.rs b/src/rng.rs index 8db9d0c1..14c58ff1 100644 --- a/src/rng.rs +++ b/src/rng.rs @@ -61,7 +61,7 @@ impl RngExt for RNG { // See RM0433 Rev 6 Section 33.3.6 assert!(rng_clk > hclk / 32, "RNG: Clock too slow"); - self.cr.modify(|_, w| w.ced().enabled().rngen().enabled()); + self.cr().modify(|_, w| w.ced().enabled().rngen().enabled()); Rng { rb: self } } @@ -80,7 +80,7 @@ impl Rng { /// Returns 32 bits of randomness, or error pub fn value(&mut self) -> Result { loop { - let status = self.rb.sr.read(); + let status = self.rb.sr().read(); if status.cecs().bit() { return Err(ErrorKind::ClockError); } @@ -88,7 +88,7 @@ impl Rng { return Err(ErrorKind::SeedError); } if status.drdy().bit() { - return Ok(self.rb.dr.read().rndata().bits()); + return Ok(self.rb.dr().read().rndata().bits()); } } } diff --git a/src/rtc.rs b/src/rtc.rs index be18633f..492c845b 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -113,13 +113,13 @@ impl Rtc { } let rcc = unsafe { &*RCC::ptr() }; - let bdcr = rcc.bdcr.read(); + let bdcr = rcc.bdcr().read(); let clock_source_matches = match (clock_source, prec.get_kernel_clk_mux()) { (RtcClock::Lsi, backup::RtcClkSel::Lsi) => true, (RtcClock::Hse { divider }, backup::RtcClkSel::Hse) => { - rcc.cfgr.read().rtcpre().bits() == divider + rcc.cfgr().read().rtcpre().bits() == divider } (RtcClock::Lse { bypass, css, .. }, backup::RtcClkSel::Lse) => { bdcr.lseon().is_on() @@ -159,17 +159,19 @@ impl Rtc { let ker_ck = match clock_source { RtcClock::Lse { bypass, freq, .. } => { // Set LSEBYP before enabling - rcc.bdcr.modify(|_, w| w.lsebyp().bit(bypass)); + rcc.bdcr().modify(|_, w| w.lsebyp().bit(bypass)); // Ensure LSE is on and stable - rcc.bdcr.modify(|_, w| w.lseon().on()); - while rcc.bdcr.read().lserdy().is_not_ready() {} + rcc.bdcr().modify(|_, w| w.lseon().on()); + while rcc.bdcr().read().lserdy().is_not_ready() {} Some(freq) } RtcClock::Hse { divider } => { // Set HSE divider assert!(divider < 64, "HSE Divider larger than 63"); - rcc.cfgr.modify(|_, w| w.rtcpre().bits(divider)); + //NOTE(unsafe) Value is checked above + rcc.cfgr() + .modify(|_, w| unsafe { w.rtcpre().bits(divider) }); clocks.hse_ck().map(|x| x / u32(divider)) } @@ -189,19 +191,19 @@ impl Rtc { // Now we can enable CSS, if required if let RtcClock::Lse { css: true, .. } = clock_source { - rcc.bdcr.modify(|_, w| w.lsecsson().security_on()); + rcc.bdcr().modify(|_, w| w.lsecsson().security_on()); } // Disable RTC register write protection - rtc.wpr.write(|w| unsafe { w.bits(0xCA) }); - rtc.wpr.write(|w| unsafe { w.bits(0x53) }); + rtc.wpr().write(|w| unsafe { w.bits(0xCA) }); + rtc.wpr().write(|w| unsafe { w.bits(0x53) }); // Enter initialization mode - rtc.isr.modify(|_, w| w.init().set_bit()); - while rtc.isr.read().initf().bit_is_clear() {} + rtc.isr().modify(|_, w| w.init().set_bit()); + while rtc.isr().read().initf().bit_is_clear() {} // Enable Shadow Register Bypass - rtc.cr.modify(|_, w| w.bypshad().set_bit()); + rtc.cr().modify(|_, w| w.bypshad().set_bit()); // Configure prescaler for 1Hz clock // Want to maximize a_pre_max for power reasons, though it reduces the @@ -230,7 +232,8 @@ impl Rtc { "Invalid RTC prescaler value" ); - rtc.prer.write(|w| { + //NOTE(unsafe) Only valid bit patterns are writte, values are checked above + rtc.prer().write(|w| unsafe { w.prediv_s() .bits(u16(s_pre - 1).unwrap()) .prediv_a() @@ -238,7 +241,7 @@ impl Rtc { }); // Exit initialization mode - rtc.isr.modify(|_, w| w.init().clear_bit()); + rtc.isr().modify(|_, w| w.init().clear_bit()); Rtc { reg: rtc, prec } } @@ -249,7 +252,7 @@ impl Rtc { /// /// Panics if `reg` is greater than 31. pub fn read_backup_reg(&self, reg: u8) -> u32 { - self.reg.bkpr[reg as usize].read().bkp().bits() + self.reg.bkpr(reg as usize).read().bkp().bits() } /// Writes `value` to a 32-bit backup register @@ -258,7 +261,10 @@ impl Rtc { /// /// Panics if `reg` is greater than 31. pub fn write_backup_reg(&mut self, reg: u8, value: u32) { - self.reg.bkpr[reg as usize].write(|w| w.bkp().bits(value)); + //NOTE(unsafe) All bit patterns are valid + self.reg + .bkpr(reg as usize) + .write(|w| unsafe { w.bkp().bits(value) }); } /// Sets the date and time of the RTC @@ -269,8 +275,8 @@ impl Rtc { /// when debug assertions are enabled. pub fn set_date_time(&mut self, date_time: NaiveDateTime) { // Enter initialization mode - self.reg.isr.modify(|_, w| w.init().set_bit()); - while self.reg.isr.read().initf().bit_is_clear() {} + self.reg.isr().modify(|_, w| w.init().set_bit()); + while self.reg.isr().read().initf().bit_is_clear() {} let hour = date_time.hour() as u8; let ht = hour / 10; @@ -284,7 +290,8 @@ impl Rtc { let st = second / 10; let su = second % 10; - self.reg.tr.write(|w| { + //NOTE(unsafe) Only valid bit patterns are written + self.reg.tr().write(|w| unsafe { w.pm() .clear_bit() .ht() @@ -316,7 +323,7 @@ impl Rtc { let dt = day / 10; let du = day % 10; - self.reg.dr.write(|w| unsafe { + self.reg.dr().write(|w| unsafe { w.yt() .bits(yt) .yu() @@ -334,7 +341,7 @@ impl Rtc { }); // Exit initialization mode - self.reg.isr.modify(|_, w| w.init().clear_bit()); + self.reg.isr().modify(|_, w| w.init().clear_bit()); } /// De-initializes the calendar and clock @@ -342,19 +349,19 @@ impl Rtc { /// For when you lose confidince in the stored time e.g. if the LSE clock fails. pub fn clear_date_time(&mut self) { // Enter initialization mode - self.reg.isr.modify(|_, w| w.init().set_bit()); - while self.reg.isr.read().initf().bit_is_clear() {} + self.reg.isr().modify(|_, w| w.init().set_bit()); + while self.reg.isr().read().initf().bit_is_clear() {} - self.reg.tr.reset(); - self.reg.dr.reset(); + self.reg.tr().reset(); + self.reg.dr().reset(); // Exit initialization mode - self.reg.isr.modify(|_, w| w.init().clear_bit()); + self.reg.isr().modify(|_, w| w.init().clear_bit()); } /// Returns `None` if the calendar is uninitialized fn calendar_initialized(&self) -> Option<()> { - match self.reg.isr.read().inits().bit() { + match self.reg.isr().read().inits().bit() { true => Some(()), false => None, } @@ -365,7 +372,7 @@ impl Rtc { /// Returns `None` if the calendar has not been initialized pub fn date(&self) -> Option { self.calendar_initialized()?; - let data = self.reg.dr.read(); + let data = self.reg.dr().read(); let year = 2000 + i32(data.yt().bits()) * 10 + i32(data.yu().bits()); let month = data.mt().bit_is_set() as u8 * 10 + data.mu().bits(); let day = data.dt().bits() * 10 + data.du().bits(); @@ -378,12 +385,12 @@ impl Rtc { pub fn time(&self) -> Option { loop { self.calendar_initialized()?; - let ss = self.reg.ssr.read().ss().bits(); - let data = self.reg.tr.read(); + let ss = self.reg.ssr().read().ss().bits(); + let data = self.reg.tr().read(); // If an RTCCLK edge occurs during read we may see inconsistent values // so read ssr again and see if it has changed. (see RM0433 Rev 7 46.3.9) - let ss_after = self.reg.ssr.read().ss().bits(); + let ss_after = self.reg.ssr().read().ss().bits(); if ss == ss_after { let mut hour = data.ht().bits() * 10 + data.hu().bits(); if data.pm().bit_is_set() { @@ -409,13 +416,13 @@ impl Rtc { pub fn date_time(&self) -> Option { loop { self.calendar_initialized()?; - let ss = self.reg.ssr.read().ss().bits(); - let dr = self.reg.dr.read(); - let tr = self.reg.tr.read(); + let ss = self.reg.ssr().read().ss().bits(); + let dr = self.reg.dr().read(); + let tr = self.reg.tr().read(); // If an RTCCLK edge occurs during read we may see inconsistent values // so read ssr again and see if it has changed. (see RM0433 Rev 7 46.3.9) - let ss_after = self.reg.ssr.read().ss().bits(); + let ss_after = self.reg.ssr().read().ss().bits(); if ss == ss_after { let year = 2000 + i32(dr.yt().bits()) * 10 + i32(dr.yu().bits()); @@ -451,14 +458,14 @@ impl Rtc { /// crystal this value has a resolution of 1/256 of a second. pub fn subseconds(&self) -> Option { self.calendar_initialized()?; - let ss = f32(self.reg.ssr.read().ss().bits()); - let prediv_s = f32(self.reg.prer.read().prediv_s().bits()); + let ss = f32(self.reg.ssr().read().ss().bits()); + let prediv_s = f32(self.reg.prer().read().prediv_s().bits()); Some((prediv_s - ss) / (prediv_s + 1.0)) } fn ss_to_us(&self, ss: u16) -> u32 { let ss = u32(ss); - let prediv_s = u32(self.reg.prer.read().prediv_s().bits()); + let prediv_s = u32(self.reg.prer().read().prediv_s().bits()); assert!(ss <= prediv_s); // See RM0433 Rev 7 46.6.10, shift operations not supported // Multiplying (prediv_s - ss) by 1,000,000 could overflow a u32 if prediv_s is large enough. @@ -472,8 +479,8 @@ impl Rtc { /// as a number of milliseconds rounded to the nearest whole number. pub fn subsec_millis(&self) -> Option { self.calendar_initialized()?; - let ss = u32(self.reg.ssr.read().ss().bits()); - let prediv_s = u32(self.reg.prer.read().prediv_s().bits()); + let ss = u32(self.reg.ssr().read().ss().bits()); + let prediv_s = u32(self.reg.prer().read().prediv_s().bits()); Some(u16(((prediv_s - ss) * 1_000) / (prediv_s + 1)).unwrap()) } @@ -481,7 +488,7 @@ impl Rtc { /// as a number of microseconds rounded to the nearest whole number. pub fn subsec_micros(&self) -> Option { self.calendar_initialized()?; - let ss = self.reg.ssr.read().ss().bits(); + let ss = self.reg.ssr().read().ss().bits(); Some(self.ss_to_us(ss)) } @@ -490,7 +497,7 @@ impl Rtc { /// This counts up to `self.subsec_res()` then resets to zero once per second. pub fn subsec_raw(&self) -> Option { self.calendar_initialized()?; - Some(self.reg.ssr.read().ss().bits()) + Some(self.reg.ssr().read().ss().bits()) } /// Returns the resolution of subsecond values @@ -498,12 +505,12 @@ impl Rtc { /// The RTC counter increments this number of times per second. pub fn subsec_res(&self) -> Option { self.calendar_initialized()?; - Some(self.reg.prer.read().prediv_s().bits()) + Some(self.reg.prer().read().prediv_s().bits()) } /// Returns the stored Daylight Savings Time status pub fn dst(&self) -> DstState { - if self.reg.cr.read().bkp().bit_is_set() { + if self.reg.cr().read().bkp().bit_is_set() { DstState::Dst } else { DstState::Standard @@ -512,7 +519,9 @@ impl Rtc { /// Sets the stored Daylight Savings Time status without adjusting the clock pub fn set_dst(&mut self, dst: DstState) { - self.reg.cr.modify(|_, w| w.bkp().bit(dst == DstState::Dst)); + self.reg + .cr() + .modify(|_, w| w.bkp().bit(dst == DstState::Dst)); } /// Begin Daylight Savings Time @@ -523,11 +532,11 @@ impl Rtc { pub fn begin_dst(&mut self) -> Result<(), DstError> { self.calendar_initialized() .ok_or(DstError::ClockNotInitialized)?; - if self.reg.cr.read().bkp().bit_is_set() { + if self.reg.cr().read().bkp().bit_is_set() { return Err(DstError::AlreadyDst); } self.reg - .cr + .cr() .modify(|_, w| w.add1h().set_bit().bkp().set_bit()); Ok(()) } @@ -541,15 +550,15 @@ impl Rtc { pub fn end_dst(&mut self) -> Result<(), DstError> { self.calendar_initialized() .ok_or(DstError::ClockNotInitialized)?; - if self.reg.cr.read().bkp().bit_is_clear() { + if self.reg.cr().read().bkp().bit_is_clear() { return Err(DstError::AlreadyStandardTime); } - let time = self.reg.tr.read(); + let time = self.reg.tr().read(); if time.ht().bits() == 0 && time.hu().bits() == 0 { return Err(DstError::CannotSubtract); } self.reg - .cr + .cr() .modify(|_, w| w.sub1h().set_bit().bkp().clear_bit()); Ok(()) } @@ -560,74 +569,76 @@ impl Rtc { /// /// Panics if interval is greater than 2¹⁷-1. pub fn enable_wakeup(&mut self, interval: u32) { - self.reg.cr.modify(|_, w| w.wute().clear_bit()); - self.reg.isr.modify(|_, w| w.wutf().clear_bit()); - while self.reg.isr.read().wutwf().bit_is_clear() {} + self.reg.cr().modify(|_, w| w.wute().clear_bit()); + self.reg.isr().modify(|_, w| w.wutf().clear_bit()); + while self.reg.isr().read().wutwf().bit_is_clear() {} if interval > 1 << 16 { self.reg - .cr + .cr() .modify(|_, w| unsafe { w.wucksel().bits(0b110) }); let interval = u16(interval - (1 << 16) - 1) .expect("Interval was too large for wakeup timer"); - self.reg.wutr.write(|w| w.wut().bits(interval)); + //NOTE(unsafe) Value is checked before being written + self.reg.wutr().write(|w| unsafe { w.wut().bits(interval) }); } else { self.reg - .cr + .cr() .modify(|_, w| unsafe { w.wucksel().bits(0b100) }); let interval = u16(interval - 1) .expect("Interval was too large for wakeup timer"); - self.reg.wutr.write(|w| w.wut().bits(interval)); + //NOTE(unsafe) Value is checked before being written + self.reg.wutr().write(|w| unsafe { w.wut().bits(interval) }); } - self.reg.cr.modify(|_, w| w.wute().set_bit()); + self.reg.cr().modify(|_, w| w.wute().set_bit()); } /// Disables the wakeup timer pub fn disable_wakeup(&mut self) { - self.reg.cr.modify(|_, w| w.wute().clear_bit()); - self.reg.isr.modify(|_, w| w.wutf().clear_bit()); + self.reg.cr().modify(|_, w| w.wute().clear_bit()); + self.reg.isr().modify(|_, w| w.wutf().clear_bit()); } /// Configures the timestamp to be captured when the RTC switches to Vbat power pub fn enable_vbat_timestamp(&mut self) { - self.reg.cr.modify(|_, w| w.tse().clear_bit()); - self.reg.isr.modify(|_, w| w.tsf().clear_bit()); - self.reg.cr.modify(|_, w| w.itse().set_bit()); - self.reg.cr.modify(|_, w| w.tse().set_bit()); + self.reg.cr().modify(|_, w| w.tse().clear_bit()); + self.reg.isr().modify(|_, w| w.tsf().clear_bit()); + self.reg.cr().modify(|_, w| w.itse().set_bit()); + self.reg.cr().modify(|_, w| w.tse().set_bit()); } /// Disables the timestamp pub fn disable_timestamp(&mut self) { - self.reg.cr.modify(|_, w| w.tse().clear_bit()); - self.reg.isr.modify(|_, w| w.tsf().clear_bit()); + self.reg.cr().modify(|_, w| w.tse().clear_bit()); + self.reg.isr().modify(|_, w| w.tsf().clear_bit()); } /// Reads the stored value of the timestamp if present /// /// Clears the timestamp interrupt flags. pub fn read_timestamp(&self) -> Option { - if !self.reg.isr.read().tsf().bit_is_clear() { + if !self.reg.isr().read().tsf().bit_is_clear() { return None; } // Timestamp doesn't include year, get it from the main calendar - let data = self.reg.dr.read(); + let data = self.reg.dr().read(); let year = 2000 + i32(data.yt().bits()) * 10 + i32(data.yu().bits()); - let data = self.reg.tsdr.read(); + let data = self.reg.tsdr().read(); let month = data.mt().bit_is_set() as u8 * 10 + data.mu().bits(); let day = data.dt().bits() * 10 + data.du().bits(); let date = NaiveDate::from_ymd_opt(year, u32(month), u32(day))?; - let data = self.reg.tstr.read(); + let data = self.reg.tstr().read(); let mut hour = data.ht().bits() * 10 + data.hu().bits(); if data.pm().bit_is_set() { hour += 12; // Shouldn't be configured this way, but handle it anyway } let minute = data.mnt().bits() * 10 + data.mnu().bits(); let second = data.st().bits() * 10 + data.su().bits(); - let micro = self.ss_to_us(self.reg.tsssr.read().ss().bits()); + let micro = self.ss_to_us(self.reg.tsssr().read().ss().bits()); let time = NaiveTime::from_hms_micro_opt( u32(hour), u32(minute), @@ -638,7 +649,7 @@ impl Rtc { // Clear timestamp interrupt and internal timestamp interrupt (VBat transition) // TODO: Timestamp overflow flag self.reg - .isr + .isr() .modify(|_, w| w.tsf().clear_bit().itsf().clear_bit()); Some(date.and_time(time)) @@ -663,28 +674,28 @@ impl Rtc { match event { Event::LseCss => { exti.listen(ExtiEvent::RTC_OTHER); - exti.rtsr1.modify(|_, w| w.tr18().enabled()); - rcc.cier.modify(|_, w| w.lsecssie().enabled()); + exti.rtsr1().modify(|_, w| w.tr18().enabled()); + rcc.cier().modify(|_, w| w.lsecssie().enabled()); } Event::AlarmA => { exti.listen(ExtiEvent::RTC_ALARM); - exti.rtsr1.modify(|_, w| w.tr17().enabled()); - self.reg.cr.modify(|_, w| w.alraie().set_bit()); + exti.rtsr1().modify(|_, w| w.tr17().enabled()); + self.reg.cr().modify(|_, w| w.alraie().set_bit()); } Event::AlarmB => { exti.listen(ExtiEvent::RTC_ALARM); - exti.rtsr1.modify(|_, w| w.tr17().enabled()); - self.reg.cr.modify(|_, w| w.alrbie().set_bit()); + exti.rtsr1().modify(|_, w| w.tr17().enabled()); + self.reg.cr().modify(|_, w| w.alrbie().set_bit()); } Event::Wakeup => { exti.listen(ExtiEvent::RTC_WAKEUP); - exti.rtsr1.modify(|_, w| w.tr19().enabled()); - self.reg.cr.modify(|_, w| w.wutie().set_bit()); + exti.rtsr1().modify(|_, w| w.tr19().enabled()); + self.reg.cr().modify(|_, w| w.wutie().set_bit()); } Event::Timestamp => { exti.listen(ExtiEvent::RTC_OTHER); - exti.rtsr1.modify(|_, w| w.tr18().enabled()); - self.reg.cr.modify(|_, w| w.tsie().set_bit()); + exti.rtsr1().modify(|_, w| w.tr18().enabled()); + self.reg.cr().modify(|_, w| w.tsie().set_bit()); } } } @@ -697,29 +708,29 @@ impl Rtc { match event { Event::LseCss => { - rcc.cier.modify(|_, w| w.lsecssie().disabled()); + rcc.cier().modify(|_, w| w.lsecssie().disabled()); exti.unlisten(ExtiEvent::RTC_OTHER); - exti.rtsr1.modify(|_, w| w.tr18().disabled()); + exti.rtsr1().modify(|_, w| w.tr18().disabled()); } Event::AlarmA => { - self.reg.cr.modify(|_, w| w.alraie().clear_bit()); + self.reg.cr().modify(|_, w| w.alraie().clear_bit()); exti.unlisten(ExtiEvent::RTC_ALARM); - exti.rtsr1.modify(|_, w| w.tr17().disabled()); + exti.rtsr1().modify(|_, w| w.tr17().disabled()); } Event::AlarmB => { - self.reg.cr.modify(|_, w| w.alrbie().clear_bit()); + self.reg.cr().modify(|_, w| w.alrbie().clear_bit()); exti.unlisten(ExtiEvent::RTC_ALARM); - exti.rtsr1.modify(|_, w| w.tr17().disabled()); + exti.rtsr1().modify(|_, w| w.tr17().disabled()); } Event::Wakeup => { - self.reg.cr.modify(|_, w| w.wutie().clear_bit()); + self.reg.cr().modify(|_, w| w.wutie().clear_bit()); exti.unlisten(ExtiEvent::RTC_WAKEUP); - exti.rtsr1.modify(|_, w| w.tr19().disabled()); + exti.rtsr1().modify(|_, w| w.tr19().disabled()); } Event::Timestamp => { - self.reg.cr.modify(|_, w| w.tsie().clear_bit()); + self.reg.cr().modify(|_, w| w.tsie().clear_bit()); exti.unlisten(ExtiEvent::RTC_OTHER); - exti.rtsr1.modify(|_, w| w.tr18().disabled()); + exti.rtsr1().modify(|_, w| w.tr18().disabled()); } } } @@ -730,11 +741,11 @@ impl Rtc { let rcc = unsafe { &*RCC::ptr() }; match event { - Event::LseCss => rcc.cifr.read().lsecssf().bit_is_set(), - Event::AlarmA => self.reg.isr.read().alraf().bit_is_set(), - Event::AlarmB => self.reg.isr.read().alrbf().bit_is_set(), - Event::Wakeup => self.reg.isr.read().wutf().bit_is_set(), - Event::Timestamp => self.reg.isr.read().tsf().bit_is_set(), + Event::LseCss => rcc.cifr().read().lsecssf().bit_is_set(), + Event::AlarmA => self.reg.isr().read().alraf().bit_is_set(), + Event::AlarmB => self.reg.isr().read().alrbf().bit_is_set(), + Event::Wakeup => self.reg.isr().read().wutf().bit_is_set(), + Event::Timestamp => self.reg.isr().read().tsf().bit_is_set(), } } @@ -746,23 +757,23 @@ impl Rtc { match event { Event::LseCss => { - rcc.cicr.write(|w| w.lsecssc().clear()); + rcc.cicr().write(|w| w.lsecssc().clear()); exti.unpend(ExtiEvent::RTC_OTHER); } Event::AlarmA => { - self.reg.isr.modify(|_, w| w.alraf().clear_bit()); + self.reg.isr().modify(|_, w| w.alraf().clear_bit()); exti.unpend(ExtiEvent::RTC_ALARM); } Event::AlarmB => { - self.reg.isr.modify(|_, w| w.alrbf().clear_bit()); + self.reg.isr().modify(|_, w| w.alrbf().clear_bit()); exti.unpend(ExtiEvent::RTC_ALARM); } Event::Wakeup => { - self.reg.isr.modify(|_, w| w.wutf().clear_bit()); + self.reg.isr().modify(|_, w| w.wutf().clear_bit()); exti.unpend(ExtiEvent::RTC_WAKEUP); } Event::Timestamp => { - self.reg.isr.modify(|_, w| w.tsf().clear_bit()); + self.reg.isr().modify(|_, w| w.tsf().clear_bit()); exti.unpend(ExtiEvent::RTC_OTHER); } } @@ -779,7 +790,7 @@ impl Rtc { // unsafe: Only we can use these bits let rcc = unsafe { &*RCC::ptr() }; - rcc.bdcr + rcc.bdcr() .modify(|_, w| w.lsecsson().security_off().lseon().off()); // We're allowed to change this once after the LSE fails diff --git a/src/sai/i2s.rs b/src/sai/i2s.rs index d06735a5..08586e69 100644 --- a/src/sai/i2s.rs +++ b/src/sai/i2s.rs @@ -665,7 +665,7 @@ fn i2s_config_channel( let mode_bits = (mode as u8) | (config.dir as u8); unsafe { - audio_ch.cr1.modify(|_, w| { + audio_ch.cr1().modify(|_, w| { w.mode() .bits(mode_bits) .prtcfg() @@ -687,7 +687,7 @@ fn i2s_config_channel( .osr() .bit(config.oversampling) }); - audio_ch.cr2.modify(|_, w| { + audio_ch.cr2().modify(|_, w| { w.fth() .quarter1() .tris() @@ -703,7 +703,7 @@ fn i2s_config_channel( .comp() .bits(config.companding as u8) }); - audio_ch.frcr.modify(|_, w| { + audio_ch.frcr().modify(|_, w| { w.frl() .bits(frame_size - 1) .fsall() @@ -715,7 +715,7 @@ fn i2s_config_channel( .fsoff() .bit(config.frame_sync_before) }); - audio_ch.slotr.modify(|_, w| { + audio_ch.slotr().modify(|_, w| { w.fboff() .bits(config.first_bit_offset) .slotsz() @@ -729,20 +729,20 @@ fn i2s_config_channel( } fn enable_ch(audio_ch: &CH) { - unsafe { audio_ch.clrfr.write(|w| w.bits(CLEAR_ALL_FLAGS_BITS)) }; - audio_ch.cr2.modify(|_, w| w.fflush().flush()); - audio_ch.cr1.modify(|_, w| w.saien().enabled()); + unsafe { audio_ch.clrfr().write(|w| w.bits(CLEAR_ALL_FLAGS_BITS)) }; + audio_ch.cr2().modify(|_, w| w.fflush().flush()); + audio_ch.cr1().modify(|_, w| w.saien().enabled()); } fn disable_ch(audio_ch: &CH) { - audio_ch.cr1.modify(|_, w| w.saien().disabled()); - while audio_ch.cr1.read().saien().bit_is_set() {} + audio_ch.cr1().modify(|_, w| w.saien().disabled()); + while audio_ch.cr1().read().saien().bit_is_set() {} } fn read(audio_ch: &CH) -> nb::Result<(u32, u32), I2SError> { - match audio_ch.sr.read().flvl().variant() { - Some(sr::FLVL_A::Empty) => Err(nb::Error::WouldBlock), - _ => Ok((audio_ch.dr.read().bits(), audio_ch.dr.read().bits())), + match audio_ch.sr().read().flvl().variant() { + Some(sr::FLVLR::Empty) => Err(nb::Error::WouldBlock), + _ => Ok((audio_ch.dr().read().bits(), audio_ch.dr().read().bits())), } } @@ -753,13 +753,13 @@ fn send( ) -> nb::Result<(), I2SError> { // The FIFO is 8 words long. A write consists of 2 words, in stereo mode. // Therefore you need to wait for 3/4s to ensure 2 words are available for writing. - match audio_ch.sr.read().flvl().variant() { - Some(sr::FLVL_A::Full) => Err(nb::Error::WouldBlock), - Some(sr::FLVL_A::Quarter4) => Err(nb::Error::WouldBlock), + match audio_ch.sr().read().flvl().variant() { + Some(sr::FLVLR::Full) => Err(nb::Error::WouldBlock), + Some(sr::FLVLR::Quarter4) => Err(nb::Error::WouldBlock), _ => { unsafe { - audio_ch.dr.write(|w| w.bits(left_word)); - audio_ch.dr.write(|w| w.bits(right_word)); + audio_ch.dr().write(|w| w.bits(left_word)); + audio_ch.dr().write(|w| w.bits(right_word)); } Ok(()) } diff --git a/src/sai/mod.rs b/src/sai/mod.rs index 7bef8f7d..9dcb9940 100644 --- a/src/sai/mod.rs +++ b/src/sai/mod.rs @@ -201,7 +201,7 @@ macro_rules! sai_hal { fn master_channel(&self, func: F) -> T where F: FnOnce(&CH) -> T, { - func(&self.rb.ch[self.master_channel as usize]) + func(&self.rb.ch(self.master_channel as usize)) } /// Access to the current slave channel, if set @@ -209,76 +209,76 @@ macro_rules! sai_hal { where F: FnOnce(&CH) -> T, { match self.slave_channel { - Some(channel) => Some(func(&self.rb.ch[channel as usize])), + Some(channel) => Some(func(&self.rb.ch(channel as usize))), None => None } } /// Start listening for `event` on a given `channel` pub fn listen(&mut self, channel: SaiChannel, event: Event) { - let ch = &self.rb.ch[channel as usize]; + let ch = &self.rb.ch(channel as usize); match event { - Event::Overdue => ch.im.modify(|_, w| w.ovrudrie().set_bit()), - Event::Muted => ch.im.modify(|_, w| w.mutedetie().set_bit()), - Event::WrongClock => ch.im.modify(|_, w| w.wckcfgie().set_bit()), - Event::Data => ch.im.modify(|_, w| w.freqie().set_bit()), - Event::AnticipatedFrameSync => ch.im.modify(|_, w| w.afsdetie().set_bit()), - Event::LateFrameSync => ch.im.modify(|_, w| w.lfsdetie().set_bit()), - } + Event::Overdue => ch.im().modify(|_, w| w.ovrudrie().set_bit()), + Event::Muted => ch.im().modify(|_, w| w.mutedetie().set_bit()), + Event::WrongClock => ch.im().modify(|_, w| w.wckcfgie().set_bit()), + Event::Data => ch.im().modify(|_, w| w.freqie().set_bit()), + Event::AnticipatedFrameSync => ch.im().modify(|_, w| w.afsdetie().set_bit()), + Event::LateFrameSync => ch.im().modify(|_, w| w.lfsdetie().set_bit()), + }; } /// Stop listening for `event` on a given `channel` pub fn unlisten(&mut self, channel: SaiChannel, event: Event) { - let ch = &self.rb.ch[channel as usize]; + let ch = &self.rb.ch(channel as usize); match event { - Event::Overdue => ch.im.modify(|_, w| w.ovrudrie().clear_bit()), - Event::Muted => ch.im.modify(|_, w| w.mutedetie().clear_bit()), - Event::WrongClock => ch.im.modify(|_, w| w.wckcfgie().clear_bit()), - Event::Data => ch.im.modify(|_, w| w.freqie().clear_bit()), - Event::AnticipatedFrameSync => ch.im.modify(|_, w| w.afsdetie().clear_bit()), - Event::LateFrameSync => ch.im.modify(|_, w| w.lfsdetie().clear_bit()), - } - let _ = ch.im.read(); - let _ = ch.im.read(); // Delay 2 peripheral clocks + Event::Overdue => ch.im().modify(|_, w| w.ovrudrie().clear_bit()), + Event::Muted => ch.im().modify(|_, w| w.mutedetie().clear_bit()), + Event::WrongClock => ch.im().modify(|_, w| w.wckcfgie().clear_bit()), + Event::Data => ch.im().modify(|_, w| w.freqie().clear_bit()), + Event::AnticipatedFrameSync => ch.im().modify(|_, w| w.afsdetie().clear_bit()), + Event::LateFrameSync => ch.im().modify(|_, w| w.lfsdetie().clear_bit()), + }; + let _ = ch.im().read(); + let _ = ch.im().read(); // Delay 2 peripheral clocks } /// Clears interrupt flag `event` on the `channel` /// /// Note: Event::Data is accepted but does nothing as that flag is cleared by reading/writing data pub fn clear_irq(&mut self, channel: SaiChannel, event: Event) { - let ch = &self.rb.ch[channel as usize]; + let ch = &self.rb.ch(channel as usize); match event { - Event::Overdue => ch.clrfr.write(|w| w.covrudr().set_bit()), - Event::Muted => ch.clrfr.write(|w| w.cmutedet().set_bit()), - Event::WrongClock => ch.clrfr.write(|w| w.cwckcfg().set_bit()), - Event::Data => (), // Cleared by reading/writing data - Event::AnticipatedFrameSync => ch.clrfr.write(|w| w.cafsdet().set_bit()), - Event::LateFrameSync => ch.clrfr.write(|w| w.clfsdet().set_bit()), - } - let _ = ch.sr.read(); - let _ = ch.sr.read(); // Delay 2 peripheral clocks + Event::Overdue => ch.clrfr().write(|w| w.covrudr().set_bit()), + Event::Muted => ch.clrfr().write(|w| w.cmutedet().set_bit()), + Event::WrongClock => ch.clrfr().write(|w| w.cwckcfg().set_bit()), + Event::Data => 0, // Cleared by reading/writing data + Event::AnticipatedFrameSync => ch.clrfr().write(|w| w.cafsdet().set_bit()), + Event::LateFrameSync => ch.clrfr().write(|w| w.clfsdet().set_bit()), + }; + let _ = ch.sr().read(); + let _ = ch.sr().read(); // Delay 2 peripheral clocks } /// Clears all interrupts on the `channel` pub fn clear_all_irq(&mut self, channel: SaiChannel) { - let ch = &self.rb.ch[channel as usize]; + let ch = &self.rb.ch(channel as usize); unsafe { - ch.clrfr.write(|w| w.bits(CLEAR_ALL_FLAGS_BITS)); + ch.clrfr().write(|w| w.bits(CLEAR_ALL_FLAGS_BITS)); } - let _ = ch.sr.read(); - let _ = ch.sr.read(); // Delay 2 peripheral clocks + let _ = ch.sr().read(); + let _ = ch.sr().read(); // Delay 2 peripheral clocks } /// Mute `channel`, this is checked at the start of each frame /// Meaningful only in Tx mode pub fn mute(&mut self, channel: SaiChannel) { - self.rb.ch[channel as usize].cr2.modify(|_, w| w.mute().enabled()); + self.rb.ch(channel as usize).cr2().modify(|_, w| w.mute().enabled()); } /// Unmute `channel`, this is checked at the start of each frame /// Meaningful only in Tx mode pub fn unmute(&mut self, channel: SaiChannel) { - self.rb.ch[channel as usize].cr2.modify(|_, w| w.mute().disabled()); + self.rb.ch(channel as usize).cr2().modify(|_, w| w.mute().disabled()); } /// Used to operate the audio block(s) with an external SAI for synchronization @@ -288,21 +288,21 @@ macro_rules! sai_hal { /// e.g. for SAI1 1-3 are valid and 0 is invalid pub fn set_sync_input(&mut self, selection: u8) { assert!(selection < 0b1_00); - unsafe { self.rb.gcr.modify(|_, w| w.syncout().bits(selection)) }; + unsafe { self.rb.gcr().modify(|_, w| w.syncout().bits(selection)) }; } /// Synchronization output for other SAI blocks pub fn set_sync_output(&mut self, channel: Option) { match channel { - Some(SaiChannel::ChannelA) => unsafe { &self.rb.gcr.modify(|_, w| w.syncout().bits(0b01) ) }, - Some(SaiChannel::ChannelB) => unsafe { &self.rb.gcr.modify(|_, w| w.syncout().bits(0b10) ) }, - None => unsafe { &self.rb.gcr.modify(|_, w| w.syncout().bits(0b00) ) }, + Some(SaiChannel::ChannelA) => unsafe { &self.rb.gcr().modify(|_, w| w.syncout().bits(0b01) ) }, + Some(SaiChannel::ChannelB) => unsafe { &self.rb.gcr().modify(|_, w| w.syncout().bits(0b10) ) }, + None => unsafe { &self.rb.gcr().modify(|_, w| w.syncout().bits(0b00) ) }, }; } /// Enable DMA for the SAI peripheral. pub fn enable_dma(&mut self, channel: SaiChannel) { - self.rb.ch[channel as usize].cr1.modify(|_, w| w.dmaen().enabled()); + self.rb.ch(channel as usize).cr1().modify(|_, w| w.dmaen().enabled()); } /// Releases the SAI peripheral @@ -311,23 +311,23 @@ macro_rules! sai_hal { // Master: Clear SAIEN self.master_channel(|ch| { - ch.cr1.modify(|_, w| w.saien().disabled()) + ch.cr1().modify(|_, w| w.saien().disabled()) }); // Master: Wait for SAI to clear at the end of the // frame while self.master_channel(|ch| { - ch.cr1.read().saien().bit_is_set() + ch.cr1().read().saien().bit_is_set() }) {} // Slave: Clear SAIEN self.slave_channel(|ch| { - ch.cr1.modify(|_, w| w.saien().disabled()) + ch.cr1().modify(|_, w| w.saien().disabled()) }); // Slave: Wait for SAI to clear while self.slave_channel(|ch| { - ch.cr1.read().saien().bit_is_set() + ch.cr1().read().saien().bit_is_set() }).unwrap_or(false) {} diff --git a/src/sai/pdm.rs b/src/sai/pdm.rs index 0c3bb55f..e37e5d93 100644 --- a/src/sai/pdm.rs +++ b/src/sai/pdm.rs @@ -202,20 +202,20 @@ macro_rules! hal { pub fn read_data(&mut self) -> nb::Result { while self.interface.invalid_countdown > 0 { // Check for words to read - if self.rb.cha().sr.read().freq().bit_is_clear() { + if self.rb.cha().sr().read().freq().bit_is_clear() { return Err(nb::Error::WouldBlock); } - let _ = self.rb.cha().dr.read(); // Flush + let _ = self.rb.cha().dr().read(); // Flush self.interface.invalid_countdown -= 1; } // Check for words to read - if self.rb.cha().sr.read().freq().bit_is_clear() { + if self.rb.cha().sr().read().freq().bit_is_clear() { return Err(nb::Error::WouldBlock); } - Ok(self.rb.cha().dr.read().bits() & 0xFFFF) + Ok(self.rb.cha().dr().read().bits() & 0xFFFF) } /// Initialise SAI in PDM mode @@ -269,7 +269,7 @@ macro_rules! hal { let audio_ch_a = &s.rb.cha(); unsafe { - audio_ch_a.cr1.modify(|_, w| { + audio_ch_a.cr1().modify(|_, w| { w.mode() .master_rx() // Master receiver .prtcfg() @@ -288,7 +288,7 @@ macro_rules! hal { .bits(kernel_clock_divider - 1) }); - audio_ch_a.frcr.modify(|_, w| { + audio_ch_a.frcr().modify(|_, w| { w.fsoff() .clear_bit() .fspol() @@ -301,7 +301,7 @@ macro_rules! hal { .bits(frl) }); - audio_ch_a.slotr.modify(|_, w| { + audio_ch_a.slotr().modify(|_, w| { w.fboff() .bits(0) // No offset on slot .slotsz() @@ -314,26 +314,26 @@ macro_rules! hal { // PDM Control Register if PINS::ENABLE_BITSTREAM_CLOCK_1 { - s.rb.pdmcr.modify(|_, w| { + s.rb.pdmcr().modify(|_, w| { w.cken1().set_bit() // CKEN1 }); } if PINS::ENABLE_BITSTREAM_CLOCK_2 { - s.rb.pdmcr.modify(|_, w| { + s.rb.pdmcr().modify(|_, w| { w.cken2().set_bit() // CKEN2 }); } if PINS::ENABLE_BITSTREAM_CLOCK_3 { - s.rb.pdmcr.modify(|_, w| { + s.rb.pdmcr().modify(|_, w| { w.cken3().set_bit() // CKEN3 }); } if PINS::ENABLE_BITSTREAM_CLOCK_4 { - s.rb.pdmcr.modify(|_, w| { + s.rb.pdmcr().modify(|_, w| { w.cken4().set_bit() // CKEN4 }); } - s.rb.pdmcr.modify(|_, w| { + s.rb.pdmcr().modify(|_, w| { w.micnbr() .bits(micnbr) // 2, 4, 6 or 8 microphones .pdmen() @@ -342,7 +342,7 @@ macro_rules! hal { } // Enable SAI_A - audio_ch_a.cr1.modify(|_, w| w.saien().enabled()); + audio_ch_a.cr1().modify(|_, w| w.saien().enabled()); // SAI s diff --git a/src/sdmmc.rs b/src/sdmmc.rs index 87dd4515..3c32b677 100644 --- a/src/sdmmc.rs +++ b/src/sdmmc.rs @@ -496,12 +496,12 @@ macro_rules! sdmmc { self.clock = new_clock; // CPSMACT and DPSMACT must be 0 to set CLKDIV - while self.sdmmc.star.read().dpsmact().bit_is_set() - || self.sdmmc.star.read().cpsmact().bit_is_set() + while self.sdmmc.star().read().dpsmact().bit_is_set() + || self.sdmmc.star().read().cpsmact().bit_is_set() {} self.sdmmc - .clkcr + .clkcr() .modify(|_, w| unsafe { w.clkdiv().bits(clkdiv) }); Ok(()) @@ -542,7 +542,7 @@ macro_rules! sdmmc { .expect("SDMMC too slow. Cannot be generated from ker_ck"); // Configure clock - sdmmc.clkcr.write(|w| unsafe { + sdmmc.clkcr().write(|w| unsafe { w.widbus() .bits(0) // 1-bit wide bus .clkdiv() @@ -558,7 +558,7 @@ macro_rules! sdmmc { // Power off, writen 00: Clock to the card is stopped; // D[7:0], CMD, and CK are driven high. sdmmc - .power + .power() .modify(|_, w| unsafe { w.pwrctrl().bits(PowerCtrl::Off as u8) }); Sdmmc { @@ -578,7 +578,7 @@ macro_rules! sdmmc { fn power_card(&mut self, state : PowerCtrl) { self.sdmmc - .power + .power() .modify(|_, w| unsafe { w.pwrctrl().bits(state as u8) }); } @@ -609,7 +609,7 @@ macro_rules! sdmmc { assert!(block_size <= 14, "Block size up to 2^14 bytes"); // Block Size must be greater than 0 ( != 1 byte) in DDR mode - let ddr = self.sdmmc.clkcr.read().ddr().bit_is_set(); + let ddr = self.sdmmc.clkcr().read().ddr().bit_is_set(); assert!( !ddr || block_size != 0, "Block size must be >= 1, or >= 2 in DDR mode" @@ -621,20 +621,20 @@ macro_rules! sdmmc { }; // Command AND Data state machines must be idle - while self.sdmmc.star.read().dpsmact().bit_is_set() - || self.sdmmc.star.read().cpsmact().bit_is_set() + while self.sdmmc.star().read().dpsmact().bit_is_set() + || self.sdmmc.star().read().cpsmact().bit_is_set() {} // Data timeout, in bus cycles self.sdmmc - .dtimer + .dtimer() .write(|w| unsafe { w.datatime().bits(5_000_000) }); // Data length, in bytes self.sdmmc - .dlenr + .dlenr() .write(|w| unsafe { w.datalength().bits(length_bytes) }); // Transfer - self.sdmmc.dctrl.write(|w| unsafe { + self.sdmmc.dctrl().write(|w| unsafe { w.dblocksize() .bits(block_size) // 2^n bytes block size .dtdir() @@ -665,7 +665,7 @@ macro_rules! sdmmc { let mut i = 0; let mut status; while { - status = self.sdmmc.star.read(); + status = self.sdmmc.star().read(); !(status.rxoverr().bit() || status.dcrcfail().bit() || status.dtimeout().bit() @@ -673,7 +673,7 @@ macro_rules! sdmmc { } { if status.rxfifohf().bit() { for _ in 0..8 { - let bytes = self.sdmmc.fifor.read().bits().to_le_bytes(); + let bytes = self.sdmmc.fifor().read().bits().to_le_bytes(); buffer[i..i + 4].copy_from_slice(&bytes); i += 4; } @@ -715,7 +715,7 @@ macro_rules! sdmmc { let mut i = 0; let mut status; while { - status = self.sdmmc.star.read(); + status = self.sdmmc.star().read(); !(status.rxoverr().bit() || status.dcrcfail().bit() || status.dtimeout().bit() @@ -723,7 +723,7 @@ macro_rules! sdmmc { } { if status.rxfifohf().bit() { for _ in 0..8 { - let bytes = self.sdmmc.fifor.read().bits().to_le_bytes(); + let bytes = self.sdmmc.fifor().read().bits().to_le_bytes(); buffer[i..i + 4].copy_from_slice(&bytes); i += 4; } @@ -760,7 +760,7 @@ macro_rules! sdmmc { let mut i = 0; let mut status; while { - status = self.sdmmc.star.read(); + status = self.sdmmc.star().read(); !(status.txunderr().bit() || status.dcrcfail().bit() || status.dtimeout().bit() @@ -771,7 +771,7 @@ macro_rules! sdmmc { let mut wb = [0u8; 4]; wb.copy_from_slice(&buffer[i..i + 4]); let word = u32::from_le_bytes(wb); - self.sdmmc.fifor.write(|w| unsafe { w.bits(word) }); + self.sdmmc.fifor().write(|w| unsafe { w.bits(word) }); i += 4; } } @@ -837,7 +837,7 @@ macro_rules! sdmmc { let mut i = 0; let mut status; while { - status = self.sdmmc.star.read(); + status = self.sdmmc.star().read(); !(status.txunderr().bit() || status.dcrcfail().bit() || status.dtimeout().bit() @@ -848,7 +848,7 @@ macro_rules! sdmmc { let mut wb = [0u8; 4]; wb.copy_from_slice(&buffer[i..i + 4]); let word = u32::from_le_bytes(wb); - self.sdmmc.fifor.write(|w| unsafe { w.bits(word) }); + self.sdmmc.fifor().write(|w| unsafe { w.bits(word) }); i += 4; } } @@ -863,7 +863,7 @@ macro_rules! sdmmc { let mut status; while { - status = self.sdmmc.star.read(); + status = self.sdmmc.star().read(); !(status.txunderr().bit() || status.dcrcfail().bit() || status.dtimeout().bit() @@ -893,7 +893,7 @@ macro_rules! sdmmc { // CMD13 self.cmd(common_cmd::card_status(self.card_rca, false))?; - let r1 = self.sdmmc.resp1r.read().bits(); + let r1 = self.sdmmc.resp1r().read().bits(); Ok(CardStatus::from(r1)) } @@ -920,7 +920,7 @@ macro_rules! sdmmc { /// Clear "static flags" in interrupt clear register fn clear_static_interrupt_flags(&self) { - self.sdmmc.icr.modify(|_, w| { + self.sdmmc.icr().modify(|_, w| { w.dcrcfailc() .set_bit() .dtimeoutc() @@ -947,7 +947,7 @@ macro_rules! sdmmc { /// Send command to card fn cmd(&self, cmd: Cmd) -> Result<(), Error> { // Clear interrupts - self.sdmmc.icr.modify(|_, w| { + self.sdmmc.icr().modify(|_, w| { w.ccrcfailc() // CRC FAIL .set_bit() .ctimeoutc() // TIMEOUT @@ -973,11 +973,11 @@ macro_rules! sdmmc { }); // CP state machine must be idle - while self.sdmmc.star.read().cpsmact().bit_is_set() {} + while self.sdmmc.star().read().cpsmact().bit_is_set() {} // Command arg self.sdmmc - .argr + .argr() .write(|w| unsafe { w.cmdarg().bits(cmd.arg) }); // Determine what kind of response the CPSM should wait for @@ -992,7 +992,7 @@ macro_rules! sdmmc { let cpsm_stop_transmission = (cmd.cmd == 12); // Command index and start CP State Machine - self.sdmmc.cmdr.write(|w| unsafe { + self.sdmmc.cmdr().write(|w| unsafe { w.waitint() .clear_bit() .waitresp() // No / Short / Long @@ -1011,7 +1011,7 @@ macro_rules! sdmmc { if cmd.response_len() == ResponseLen::Zero { // Wait for CMDSENT or a timeout while { - status = self.sdmmc.star.read(); + status = self.sdmmc.star().read(); !(status.ctimeout().bit() || status.cmdsent().bit()) && timeout > 0 } { @@ -1020,7 +1020,7 @@ macro_rules! sdmmc { } else { // Wait for CMDREND or CCRCFAIL or a timeout while { - status = self.sdmmc.star.read(); + status = self.sdmmc.star().read(); !(status.ctimeout().bit() || status.cmdrend().bit() || status.ccrcfail().bit()) @@ -1056,7 +1056,7 @@ macro_rules! sdmmc { // Check if cards supports CMD8 (with pattern) self.cmd(sd_cmd::send_if_cond(1, 0xAA))?; - let cic = CIC::from(self.sdmmc.resp1r.read().bits()); + let cic = CIC::from(self.sdmmc.resp1r().read().bits()); let mut card = if cic.pattern() == 0xAA { // Card echoed back the pattern. Must be at least v2 @@ -1077,7 +1077,7 @@ macro_rules! sdmmc { Err(Error::Crc) => (), Err(err) => return Err(err), } - let ocr = OCR::from(self.sdmmc.resp1r.read().bits()); + let ocr = OCR::from(self.sdmmc.resp1r().read().bits()); if !ocr.is_busy() { // Power up done break ocr; @@ -1094,22 +1094,22 @@ macro_rules! sdmmc { // Get CID self.cmd(common_cmd::all_send_cid())?; // CMD2 - let cid = ((self.sdmmc.resp1r.read().bits() as u128) << 96) - | ((self.sdmmc.resp2r.read().bits() as u128) << 64) - | ((self.sdmmc.resp3r.read().bits() as u128) << 32) - | self.sdmmc.resp4r.read().bits() as u128; + let cid = ((self.sdmmc.resp1r().read().bits() as u128) << 96) + | ((self.sdmmc.resp2r().read().bits() as u128) << 64) + | ((self.sdmmc.resp3r().read().bits() as u128) << 32) + | self.sdmmc.resp4r().read().bits() as u128; card.cid = cid.into(); // Get RCA self.cmd(sd_cmd::send_relative_address())?; - card.rca = RCA::from(self.sdmmc.resp1r.read().bits()); + card.rca = RCA::from(self.sdmmc.resp1r().read().bits()); // Get CSD self.cmd(common_cmd::send_csd(card.rca.address()))?; - let csd = ((self.sdmmc.resp1r.read().bits() as u128) << 96) - | ((self.sdmmc.resp2r.read().bits() as u128) << 64) - | ((self.sdmmc.resp3r.read().bits() as u128) << 32) - | self.sdmmc.resp4r.read().bits() as u128; + let csd = ((self.sdmmc.resp1r().read().bits() as u128) << 96) + | ((self.sdmmc.resp2r().read().bits() as u128) << 64) + | ((self.sdmmc.resp3r().read().bits() as u128) << 32) + | self.sdmmc.resp4r().read().bits() as u128; card.csd = csd.into(); // Select and get RCA @@ -1130,10 +1130,10 @@ macro_rules! sdmmc { self.app_cmd(sd_cmd::cmd6(acmd_arg))?; // ACMD6: Bus Width // CPSMACT and DPSMACT must be 0 to set WIDBUS - while self.sdmmc.star.read().dpsmact().bit_is_set() - || self.sdmmc.star.read().cpsmact().bit_is_set() + while self.sdmmc.star().read().dpsmact().bit_is_set() + || self.sdmmc.star().read().cpsmact().bit_is_set() {} - self.sdmmc.clkcr.modify(|_, w| unsafe { + self.sdmmc.clkcr().modify(|_, w| unsafe { w.widbus().bits(match width { Buswidth::One => 0, Buswidth::Four => 1, @@ -1186,7 +1186,7 @@ macro_rules! sdmmc { let mut idx = 0; let mut sta_reg; while { - sta_reg = self.sdmmc.star.read(); + sta_reg = self.sdmmc.star().read(); !(sta_reg.rxoverr().bit() || sta_reg.dcrcfail().bit() || sta_reg.dtimeout().bit() @@ -1195,7 +1195,7 @@ macro_rules! sdmmc { if sta_reg.rxfifohf().bit() { for _ in 0..8 { status[15-idx] = u32::from_be( - self.sdmmc.fifor.read().bits()); + self.sdmmc.fifor().read().bits()); idx += 1; } @@ -1227,7 +1227,7 @@ macro_rules! sdmmc { let mut i = 0; let mut status; while { - status = self.sdmmc.star.read(); + status = self.sdmmc.star().read(); !(status.rxoverr().bit() || status.dcrcfail().bit() @@ -1236,7 +1236,7 @@ macro_rules! sdmmc { } { if status.rxfifoe().bit_is_clear() { // FIFO not empty - scr[i] = self.sdmmc.fifor.read().bits(); + scr[i] = self.sdmmc.fifor().read().bits(); i += 1; } @@ -1280,7 +1280,7 @@ macro_rules! sdmmc { let mut idx = 0; let mut sta_reg; while { - sta_reg = self.sdmmc.star.read(); + sta_reg = self.sdmmc.star().read(); !(sta_reg.rxoverr().bit() || sta_reg.dcrcfail().bit() || sta_reg.dtimeout().bit() @@ -1288,7 +1288,7 @@ macro_rules! sdmmc { } { if sta_reg.rxfifohf().bit() { for _ in 0..8 { - status[idx] = self.sdmmc.fifor.read().bits(); + status[idx] = self.sdmmc.fifor().read().bits(); idx += 1; } } @@ -1393,7 +1393,7 @@ macro_rules! sdmmc { let mut idx = 0; let mut sta_reg; while { - sta_reg = self.sdmmc.star.read(); + sta_reg = self.sdmmc.star().read(); !(sta_reg.rxoverr().bit() || sta_reg.dcrcfail().bit() || sta_reg.dtimeout().bit() @@ -1402,7 +1402,7 @@ macro_rules! sdmmc { if sta_reg.rxfifohf().bit() { for _ in 0..8 { buffer[idx] = u32::from_be( - self.sdmmc.fifor.read().bits()); + self.sdmmc.fifor().read().bits()); idx += 1; } @@ -1443,7 +1443,7 @@ macro_rules! sdmmc { Err(Error::Crc) => (), Err(err) => return Err(err), }; - let ocr = OCR::from(self.sdmmc.resp1r.read().bits()); + let ocr = OCR::from(self.sdmmc.resp1r().read().bits()); if !ocr.is_busy() { break ocr; } @@ -1452,10 +1452,10 @@ macro_rules! sdmmc { // CMD2: Get CID self.cmd(common_cmd::all_send_cid())?; let mut cid = [0; 4]; - cid[3] = self.sdmmc.resp1r.read().bits(); - cid[2] = self.sdmmc.resp2r.read().bits(); - cid[1] = self.sdmmc.resp3r.read().bits(); - cid[0] = self.sdmmc.resp4r.read().bits(); + cid[3] = self.sdmmc.resp1r().read().bits(); + cid[2] = self.sdmmc.resp2r().read().bits(); + cid[1] = self.sdmmc.resp3r().read().bits(); + cid[0] = self.sdmmc.resp4r().read().bits(); let cid = CID::from(cid); // CMD3: Assign address @@ -1466,10 +1466,10 @@ macro_rules! sdmmc { self.cmd(common_cmd::send_csd(self.card_rca))?; let mut csd = [0; 4]; - csd[3] = self.sdmmc.resp1r.read().bits(); - csd[2] = self.sdmmc.resp2r.read().bits(); - csd[1] = self.sdmmc.resp3r.read().bits(); - csd[0] = self.sdmmc.resp4r.read().bits(); + csd[3] = self.sdmmc.resp1r().read().bits(); + csd[2] = self.sdmmc.resp2r().read().bits(); + csd[1] = self.sdmmc.resp3r().read().bits(); + csd[0] = self.sdmmc.resp4r().read().bits(); let csd = CSD::from(csd); // CMD7: Place card in the transfer state @@ -1546,12 +1546,12 @@ macro_rules! sdmmc { while !self.card_ready()? {} // CPSMACT and DPSMACT must be 0 to set WIDBUS and DDR - while self.sdmmc.star.read().dpsmact().bit_is_set() - || self.sdmmc.star.read().cpsmact().bit_is_set() + while self.sdmmc.star().read().dpsmact().bit_is_set() + || self.sdmmc.star().read().cpsmact().bit_is_set() {} // Set WIDBUS - self.sdmmc.clkcr.modify(|_, w| unsafe { + self.sdmmc.clkcr().modify(|_, w| unsafe { w.widbus().bits(match width { Buswidth::One => 0, Buswidth::Four => 1, @@ -1567,7 +1567,7 @@ macro_rules! sdmmc { // Check the achieved clkdiv in DDR mode if matches!(signaling, EmmcSignaling::DDR52) && - self.sdmmc.clkcr.read().clkdiv().bits() == 0 { + self.sdmmc.clkcr().read().clkdiv().bits() == 0 { return Err(Error::InvalidConfiguration); } diff --git a/src/serial.rs b/src/serial.rs index 2eee59e2..f5642d65 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -17,22 +17,20 @@ use embedded_hal::prelude::*; use embedded_hal::serial; use nb::block; -use stm32::usart1::cr2::{ - CLKEN_A, CPHA_A, CPOL_A, LBCL_A, MSBFIRST_A, RXINV_A, TXINV_A, -}; -use stm32::usart1::cr3::HDSEL_A; +use stm32::usart1::cr2::{CLKEN, CPHA, CPOL, LBCL, MSBFIRST, RXINV, TXINV}; +use stm32::usart1::cr3::HDSEL; use crate::gpio::{self, Alternate}; use crate::rcc::{rec, CoreClocks, ResetEnable}; use crate::stm32; #[cfg(feature = "rm0455")] -use crate::stm32::rcc::cdccip2r::{USART16910SEL_A, USART234578SEL_A}; +use crate::stm32::rcc::cdccip2r::{USART16910SEL, USART234578SEL}; #[cfg(feature = "rm0468")] -use crate::stm32::rcc::d2ccip2r::{USART16910SEL_A, USART234578SEL_A}; +use crate::stm32::rcc::d2ccip2r::{USART16910SEL, USART234578SEL}; #[cfg(any(feature = "rm0433", feature = "rm0399"))] -use crate::stm32::rcc::d2ccip2r::{USART16SEL_A, USART234578SEL_A}; +use crate::stm32::rcc::d2ccip2r::{USART16SEL, USART234578SEL}; -use crate::stm32::usart1::cr1::{M0_A as M0, PCE_A as PCE, PS_A as PS}; +use crate::stm32::usart1::cr1::{M0, PCE, PS}; use crate::stm32::{UART4, UART5, UART7, UART8}; #[cfg(any(feature = "rm0455", feature = "rm0468"))] use crate::stm32::{UART9, USART10}; @@ -605,7 +603,7 @@ macro_rules! usart { let ker_ck = Self::kernel_clk_unwrap(clocks); let mut serial = Serial { usart, ker_ck }; let config = config.into(); - serial.usart.cr1.reset(); + serial.usart.cr1().reset(); // If synchronous mode is supported, check that it is not // enabled alongside half duplex mode @@ -623,12 +621,12 @@ macro_rules! usart { /// /// The serial port must be disabled when called. fn configure(&mut self, config: &config::Config $(, $synchronous: bool)?) { - use crate::stm32::usart1::cr2::STOP_A as STOP; + use crate::stm32::usart1::cr2::STOP as STOP; use self::config::*; // Prescaler not used for now let usart_ker_ck_presc = self.ker_ck; - self.usart.presc.reset(); + self.usart.presc().reset(); // Calculate baudrate divisor let usartdiv = usart_ker_ck_presc / config.baudrate; @@ -636,11 +634,12 @@ macro_rules! usart { // 16 times oversampling, OVER8 = 0 let brr = usartdiv as u16; - self.usart.brr.write(|w| { w.brr().bits(brr) }); + //NOTE(unsafe) Only valid bit patterns written, checked above + self.usart.brr().write(|w| unsafe { w.brr().bits(brr) }); // Reset registers to disable advanced USART features - self.usart.cr2.reset(); - self.usart.cr3.reset(); + self.usart.cr2().reset(); + self.usart.cr3().reset(); // RXFIFO threshold let fifo_threshold_bits = match config.rxfifothreshold { @@ -652,7 +651,7 @@ macro_rules! usart { FifoThreshold::Full => 5, }; unsafe { - self.usart.cr3.modify(|_, w| w.rxftcfg().bits(fifo_threshold_bits)); + self.usart.cr3().modify(|_, w| w.rxftcfg().bits(fifo_threshold_bits)); } // TXFIFO threashold @@ -665,20 +664,20 @@ macro_rules! usart { FifoThreshold::Full => 5, }; unsafe { - self.usart.cr3.modify(|_, w| w.txftcfg().bits(fifo_threshold_bits)); + self.usart.cr3().modify(|_, w| w.txftcfg().bits(fifo_threshold_bits)); } // Configure half-duplex mode - self.usart.cr3.modify(|_, w| { + self.usart.cr3().modify(|_, w| { w.hdsel().variant(if config.halfduplex { - HDSEL_A::Selected + HDSEL::Selected } else { - HDSEL_A::NotSelected + HDSEL::NotSelected }) }); // Configure serial mode - self.usart.cr2.write(|w| { + self.usart.cr2().write(|w| { w.stop().variant(match config.stopbits { StopBits::Stop0p5 => STOP::Stop0p5, StopBits::Stop1 => STOP::Stop1, @@ -687,47 +686,47 @@ macro_rules! usart { }); w.msbfirst().variant(match config.bitorder { - BitOrder::LsbFirst => MSBFIRST_A::Lsb, - BitOrder::MsbFirst => MSBFIRST_A::Msb, + BitOrder::LsbFirst => MSBFIRST::Lsb, + BitOrder::MsbFirst => MSBFIRST::Msb, }); w.swap().bit(config.swaptxrx); w.rxinv().variant(if config.invertrx { - RXINV_A::Inverted + RXINV::Inverted } else { - RXINV_A::Standard + RXINV::Standard }); w.txinv().variant(if config.inverttx { - TXINV_A::Inverted + TXINV::Inverted } else { - TXINV_A::Standard + TXINV::Standard }); // If synchronous mode is not supported, these bits are // reserved and must be kept at reset value $( w.lbcl().variant(if config.lastbitclockpulse { - LBCL_A::Output + LBCL::Output } else { - LBCL_A::NotOutput + LBCL::NotOutput }); w.clken().variant(if $synchronous { - CLKEN_A::Enabled + CLKEN::Enabled } else { - CLKEN_A::Disabled + CLKEN::Disabled }); w.cpol().variant(match config.clockpolarity { - ClockPolarity::IdleHigh =>CPOL_A::High, - ClockPolarity::IdleLow =>CPOL_A::Low + ClockPolarity::IdleHigh =>CPOL::High, + ClockPolarity::IdleLow =>CPOL::Low }); w.cpha().variant(match config.clockphase { - ClockPhase::First => CPHA_A::First, - ClockPhase::Second => CPHA_A::Second + ClockPhase::First => CPHA::First, + ClockPhase::Second => CPHA::Second }); )? @@ -736,7 +735,7 @@ macro_rules! usart { // Enable transmission and receiving and configure frame // Retain enabled events - self.usart.cr1.modify(|_, w| { + self.usart.cr1().modify(|_, w| { w.fifoen() .set_bit() // FIFO mode enabled .over8() @@ -777,7 +776,7 @@ macro_rules! usart { panic!("Cannot reconfigure serial while DMA enabled"); } - self.usart.cr1.modify(|_, w| w.ue().disabled()); + self.usart.cr1().modify(|_, w| w.ue().disabled()); let config = config.into(); self.configure(&config $(, $synchronous )?); @@ -785,76 +784,76 @@ macro_rules! usart { /// Enables the Rx DMA stream. pub fn enable_dma_rx(&mut self) { - self.usart.cr3.modify(|_, w| w.dmar().set_bit()); + self.usart.cr3().modify(|_, w| w.dmar().set_bit()); } /// Disables the Rx DMA stream. pub fn disable_dma_rx(&mut self) { - self.usart.cr3.modify(|_, w| w.dmar().clear_bit()); + self.usart.cr3().modify(|_, w| w.dmar().clear_bit()); } /// Returns `true` if the Rx DMA stream is enabled. pub fn dma_rx_enabled(&self) -> bool { - self.usart.cr3.read().dmar().bit_is_set() + self.usart.cr3().read().dmar().bit_is_set() } /// Enables the Tx DMA stream. pub fn enable_dma_tx(&mut self) { - self.usart.cr3.modify(|_, w| w.dmat().set_bit()); + self.usart.cr3().modify(|_, w| w.dmat().set_bit()); } /// Disables the Tx DMA stream. pub fn disable_dma_tx(&mut self) { - self.usart.cr3.modify(|_, w| w.dmat().clear_bit()); + self.usart.cr3().modify(|_, w| w.dmat().clear_bit()); } /// Returns `true` if the Tx DMA stream is enabled. pub fn dma_tx_enabled(&self) -> bool { - self.usart.cr3.read().dmat().bit_is_set() + self.usart.cr3().read().dmat().bit_is_set() } /// Starts listening for an interrupt event pub fn listen(&mut self, event: Event) { match event { Event::Rxne => { - self.usart.cr1.modify(|_, w| w.rxneie().enabled()) + self.usart.cr1().modify(|_, w| w.rxneie().enabled()) }, Event::Txe => { - self.usart.cr1.modify(|_, w| w.txeie().enabled()) + self.usart.cr1().modify(|_, w| w.txeie().enabled()) }, Event::Idle => { - self.usart.cr1.modify(|_, w| w.idleie().enabled()) + self.usart.cr1().modify(|_, w| w.idleie().enabled()) }, Event::Txftie => { - self.usart.cr3.modify(|_, w| w.txftie().set_bit()) + self.usart.cr3().modify(|_, w| w.txftie().set_bit()) }, Event::Rxftie => { - self.usart.cr3.modify(|_, w| w.rxftie().set_bit()) + self.usart.cr3().modify(|_, w| w.rxftie().set_bit()) }, - } + }; } /// Stop listening for an interrupt event pub fn unlisten(&mut self, event: Event) { match event { Event::Rxne => { - self.usart.cr1.modify(|_, w| w.rxneie().disabled()) + self.usart.cr1().modify(|_, w| w.rxneie().disabled()) }, Event::Txe => { - self.usart.cr1.modify(|_, w| w.txeie().disabled()) + self.usart.cr1().modify(|_, w| w.txeie().disabled()) }, Event::Idle => { - self.usart.cr1.modify(|_, w| w.idleie().disabled()) + self.usart.cr1().modify(|_, w| w.idleie().disabled()) }, Event::Txftie => { - self.usart.cr3.modify(|_, w| w.txftie().clear_bit()) + self.usart.cr3().modify(|_, w| w.txftie().clear_bit()) }, Event::Rxftie => { - self.usart.cr3.modify(|_, w| w.rxftie().clear_bit()) + self.usart.cr3().modify(|_, w| w.rxftie().clear_bit()) }, - } - let _ = self.usart.cr1.read(); - let _ = self.usart.cr1.read(); // Delay 2 peripheral clocks + }; + let _ = self.usart.cr1().read(); + let _ = self.usart.cr1().read(); // Delay 2 peripheral clocks } /// Return true if the line idle status is set @@ -862,14 +861,14 @@ macro_rules! usart { /// The line idle status bit is set when the peripheral detects the receive line is idle. /// The bit is cleared by software, by calling `clear_idle()`. pub fn is_idle(&self) -> bool { - unsafe { (*$USARTX::ptr()).isr.read().idle().bit_is_set() } + unsafe { (*$USARTX::ptr()).isr().read().idle().bit_is_set() } } /// Clear the line idle status bit pub fn clear_idle(&mut self) { - unsafe { (*$USARTX::ptr()).icr.write(|w| w.idlecf().set_bit()) } - let _ = self.usart.isr.read(); - let _ = self.usart.isr.read(); // Delay 2 peripheral clocks + unsafe { (*$USARTX::ptr()).icr().write(|w| w.idlecf().set_bit()); } + let _ = self.usart.isr().read(); + let _ = self.usart.isr().read(); // Delay 2 peripheral clocks } /// Return true if the line busy status is set @@ -877,17 +876,17 @@ macro_rules! usart { /// The busy status bit is set when there is communication active on the receive line, /// and reset at the end of reception. pub fn is_busy(&self) -> bool { - unsafe { (*$USARTX::ptr()).isr.read().busy().bit_is_set() } + unsafe { (*$USARTX::ptr()).isr().read().busy().bit_is_set() } } /// Return true if the tx register is empty (and can accept data) pub fn is_txe(&self) -> bool { - unsafe { (*$USARTX::ptr()).isr.read().txe().bit_is_set() } + unsafe { (*$USARTX::ptr()).isr().read().txe().bit_is_set() } } /// Return true if the rx register is not empty (and can be read) pub fn is_rxne(&self) -> bool { - unsafe { (*$USARTX::ptr()).isr.read().rxne().bit_is_set() } + unsafe { (*$USARTX::ptr()).isr().read().rxne().bit_is_set() } } /// Splits the [`Serial`] struct into transmit ([`Tx`]) and receive ([`Rx`]) parts which can be used @@ -917,7 +916,7 @@ macro_rules! usart { /// Releases the USART peripheral pub fn release(self) -> $USARTX { // Wait until both TXFIFO and shift register are empty - while self.usart.isr.read().tc().bit_is_clear() {} + while self.usart.isr().read().tc().bit_is_clear() {} self.usart } @@ -981,24 +980,24 @@ macro_rules! usart { fn read(&mut self) -> nb::Result { // NOTE(unsafe) atomic read with no side effects - let isr = unsafe { (*$USARTX::ptr()).isr.read() }; + let isr = unsafe { (*$USARTX::ptr()).isr().read() }; Err(if isr.pe().bit_is_set() { - unsafe { (*$USARTX::ptr()).icr.write(|w| w.pecf().clear() );}; + unsafe { (*$USARTX::ptr()).icr().write(|w| w.pecf().clear() );}; nb::Error::Other(Error::Parity) } else if isr.fe().bit_is_set() { - unsafe { (*$USARTX::ptr()).icr.write(|w| w.fecf().clear() );}; + unsafe { (*$USARTX::ptr()).icr().write(|w| w.fecf().clear() );}; nb::Error::Other(Error::Framing) } else if isr.nf().bit_is_set() { - unsafe { (*$USARTX::ptr()).icr.write(|w| w.ncf().clear() );}; + unsafe { (*$USARTX::ptr()).icr().write(|w| w.ncf().clear() );}; nb::Error::Other(Error::Noise) } else if isr.ore().bit_is_set() { - unsafe { (*$USARTX::ptr()).icr.write(|w| w.orecf().clear() );}; + unsafe { (*$USARTX::ptr()).icr().write(|w| w.orecf().clear() );}; nb::Error::Other(Error::Overrun) } else if isr.rxne().bit_is_set() { // NOTE(read_volatile) see `write_volatile` below return Ok(unsafe { - ptr::read_volatile(&(*$USARTX::ptr()).rdr as *const _ as *const _) + ptr::read_volatile(&(*$USARTX::ptr()).rdr() as *const _ as *const _) }); } else { nb::Error::WouldBlock @@ -1010,13 +1009,13 @@ macro_rules! usart { /// Start listening for `Rxne` event pub fn listen(&mut self) { // unsafe: rxneie bit accessed by Rx part only - unsafe { &*$USARTX::ptr() }.cr1.modify(|_, w| w.rxneie().enabled()); + unsafe { &*$USARTX::ptr() }.cr1().modify(|_, w| w.rxneie().enabled()); } /// Stop listening for `Rxne` event pub fn unlisten(&mut self) { // unsafe: rxneie bit accessed by Rx part only - let cr1 = &unsafe { &*$USARTX::ptr() }.cr1; + let cr1 = &unsafe { &*$USARTX::ptr() }.cr1(); cr1.modify(|_, w| w.rxneie().disabled()); let _ = cr1.read(); let _ = cr1.read(); // Delay 2 peripheral clocks @@ -1025,13 +1024,13 @@ macro_rules! usart { /// Enables the Rx DMA stream. pub fn enable_dma_rx(&mut self) { // unsafe: dmar bit accessed by Rx part only - unsafe { &*$USARTX::ptr() }.cr3.modify(|_, w| w.dmar().set_bit()); + unsafe { &*$USARTX::ptr() }.cr3().modify(|_, w| w.dmar().set_bit()); } /// Disables the Rx DMA stream. pub fn disable_dma_rx(&mut self) { // unsafe: dmar bit accessed by Rx part only - unsafe { &*$USARTX::ptr() }.cr3.modify(|_, w| w.dmar().clear_bit()); + unsafe { &*$USARTX::ptr() }.cr3().modify(|_, w| w.dmar().clear_bit()); } /// Return true if the line idle status is set @@ -1039,15 +1038,15 @@ macro_rules! usart { /// The line idle status bit is set when the peripheral detects the receive line is idle. /// The bit is cleared by software, by calling `clear_idle()`. pub fn is_idle(&self) -> bool { - unsafe { (*$USARTX::ptr()).isr.read().idle().bit_is_set() } + unsafe { (*$USARTX::ptr()).isr().read().idle().bit_is_set() } } /// Clear the line idle status bit pub fn clear_idle(&mut self) { let usart = unsafe { &*$USARTX::ptr() }; - usart.icr.write(|w| w.idlecf().set_bit()); - let _ = usart.isr.read(); - let _ = usart.isr.read(); // Delay 2 peripheral clocks + usart.icr().write(|w| w.idlecf().set_bit()); + let _ = usart.isr().read(); + let _ = usart.isr().read(); // Delay 2 peripheral clocks } /// Return true if the line busy status is set @@ -1055,12 +1054,12 @@ macro_rules! usart { /// The busy status bit is set when there is communication active on the receive line, /// and reset at the end of reception. pub fn is_busy(&self) -> bool { - unsafe { (*$USARTX::ptr()).isr.read().busy().bit_is_set() } + unsafe { (*$USARTX::ptr()).isr().read().busy().bit_is_set() } } /// Return true if the rx register is not empty (and can be read) pub fn is_rxne(&self) -> bool { - unsafe { (*$USARTX::ptr()).isr.read().rxne().bit_is_set() } + unsafe { (*$USARTX::ptr()).isr().read().rxne().bit_is_set() } } } @@ -1097,7 +1096,7 @@ macro_rules! usart { fn flush(&mut self) -> nb::Result<(), Self::Error> { // NOTE(unsafe) atomic read with no side effects - let isr = unsafe { (*$USARTX::ptr()).isr.read() }; + let isr = unsafe { (*$USARTX::ptr()).isr().read() }; if isr.tc().bit_is_set() { Ok(()) @@ -1108,14 +1107,14 @@ macro_rules! usart { fn write(&mut self, byte: u8) -> nb::Result<(), Self::Error> { // NOTE(unsafe) atomic read with no side effects - let isr = unsafe { (*$USARTX::ptr()).isr.read() }; + let isr = unsafe { (*$USARTX::ptr()).isr().read() }; if isr.txe().bit_is_set() { // NOTE(unsafe) atomic write to stateless register // NOTE(write_volatile) 8-bit write that's not // possible through the svd2rust API unsafe { - let tdr = &(*$USARTX::ptr()).tdr as *const _ as *const UnsafeCell; + let tdr = (*$USARTX::ptr()).tdr().as_ptr() as *const UnsafeCell; ptr::write_volatile(UnsafeCell::raw_get(tdr), byte) } @@ -1130,13 +1129,13 @@ macro_rules! usart { /// Start listening for `Txe` event pub fn listen(&mut self) { // unsafe: txeie bit accessed by Tx part only - unsafe { &*$USARTX::ptr() }.cr1.modify(|_, w| w.txeie().enabled()); + unsafe { &*$USARTX::ptr() }.cr1().modify(|_, w| w.txeie().enabled()); } /// Stop listening for `Txe` event pub fn unlisten(&mut self) { // unsafe: txeie bit accessed by Tx part only - let cr1 = &unsafe { &*$USARTX::ptr() }.cr1; + let cr1 = &unsafe { &*$USARTX::ptr() }.cr1(); cr1.modify(|_, w| w.txeie().disabled()); let _ = cr1.read(); let _ = cr1.read(); // Delay 2 peripheral clocks @@ -1145,18 +1144,18 @@ macro_rules! usart { /// Enables the Tx DMA stream. pub fn enable_dma_tx(&mut self) { // unsafe: dmat bit accessed by Tx part only - unsafe { &*$USARTX::ptr() }.cr3.modify(|_, w| w.dmat().set_bit()); + unsafe { &*$USARTX::ptr() }.cr3().modify(|_, w| w.dmat().set_bit()); } /// Disables the Tx DMA stream. pub fn disable_dma_tx(&mut self) { // unsafe: dmat bit accessed by Tx part only - unsafe { &*$USARTX::ptr() }.cr3.modify(|_, w| w.dmat().clear_bit()); + unsafe { &*$USARTX::ptr() }.cr3().modify(|_, w| w.dmat().clear_bit()); } /// Return true if the tx register is empty (and can accept data) pub fn is_txe(& self) -> bool { - unsafe { (*$USARTX::ptr()).isr.read().txe().bit_is_set() } + unsafe { (*$USARTX::ptr()).isr().read().txe().bit_is_set() } } } )+ @@ -1172,7 +1171,7 @@ macro_rules! usart_sel { #[doc=$doc] pub fn kernel_clk(clocks: &CoreClocks) -> Option { // unsafe: read only - let ccip = unsafe { (*stm32::RCC::ptr()).$ccip.read() }; + let ccip = unsafe { (*stm32::RCC::ptr()).$ccip().read() }; match ccip.$sel().variant() { Some($SEL::$PCLK) => Some(clocks.$pclk()), @@ -1192,7 +1191,7 @@ macro_rules! usart_sel { /// Panics if the kernel clock is not running pub fn kernel_clk_unwrap(clocks: &CoreClocks) -> Hertz { // unsafe: read only - let ccip = unsafe { (*stm32::RCC::ptr()).$ccip.read() }; + let ccip = unsafe { (*stm32::RCC::ptr()).$ccip().read() }; match ccip.$sel().variant() { Some($SEL::$PCLK) => clocks.$pclk(), @@ -1244,14 +1243,14 @@ usart! { #[cfg(any(feature = "rm0433", feature = "rm0399"))] usart_sel! { - d2ccip2r, USART16SEL_A, usart16sel, RccPclk2, pclk2; + d2ccip2r, USART16SEL, usart16sel, RccPclk2, pclk2; USART1: "USART1", USART6: "USART6", } #[cfg(feature = "rm0455")] usart_sel! { - cdccip2r, USART16910SEL_A, usart16910sel, RccPclk2, pclk2; + cdccip2r, USART16910SEL, usart16910sel, RccPclk2, pclk2; USART1: "USART1", USART6: "USART6", @@ -1261,7 +1260,7 @@ usart_sel! { } #[cfg(feature = "rm0468")] usart_sel! { - d2ccip2r, USART16910SEL_A, usart16910sel, RccPclk2, pclk2; + d2ccip2r, USART16910SEL, usart16910sel, RccPclk2, pclk2; USART1: "USART1", USART6: "USART6", @@ -1272,7 +1271,7 @@ usart_sel! { #[cfg(not(feature = "rm0455"))] usart_sel! { - d2ccip2r, USART234578SEL_A, usart234578sel, RccPclk1, pclk1; + d2ccip2r, USART234578SEL, usart234578sel, RccPclk1, pclk1; USART2: "USART2", USART3: "USART3", @@ -1284,7 +1283,7 @@ usart_sel! { } #[cfg(feature = "rm0455")] usart_sel! { - cdccip2r, USART234578SEL_A, usart234578sel, RccPclk1, pclk1; + cdccip2r, USART234578SEL, usart234578sel, RccPclk1, pclk1; USART2: "USART2", USART3: "USART3", diff --git a/src/spi.rs b/src/spi.rs index 4e86cf58..ed65c780 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -78,9 +78,7 @@ use crate::stm32; use crate::stm32::rcc::{cdccip1r as ccip1r, srdccipr}; #[cfg(not(feature = "rm0455"))] use crate::stm32::rcc::{d2ccip1r as ccip1r, d3ccipr as srdccipr}; -use crate::stm32::spi1::{ - cfg1::MBR_A as MBR, cfg2::COMM_A as COMM, cfg2::SSIOP_A as SSIOP, -}; +use crate::stm32::spi1::{cfg1::MBR, cfg2::COMM, cfg2::SSIOP}; use crate::stm32::{SPI1, SPI2, SPI3, SPI4, SPI5, SPI6}; use crate::time::Hertz; @@ -493,7 +491,7 @@ pins! { macro_rules! check_status_error { ($spi:expr; $( {$flag:ident, $variant:ident, $blk:block} ),*) => {{ - let sr = $spi.sr.read(); + let sr = $spi.sr().read(); return Err(if sr.ovr().is_overrun() { nb::Error::Other(Error::Overrun) @@ -672,19 +670,22 @@ pub trait HalSpi: Sized { macro_rules! spi { (DSIZE, $spi:ident, u8) => { - $spi.cfg1.modify(|_, w| { + //NOTE(unsafe) 7 is a valid bit patterns + $spi.cfg1().modify(|_, w| unsafe { w.dsize() .bits(8 - 1) // 8 bit words }); }; (DSIZE, $spi:ident, u16) => { - $spi.cfg1.modify(|_, w| { + //NOTE(unsafe) 15 is a valid bit pattern + $spi.cfg1().modify(|_, w| unsafe { w.dsize() .bits(16 - 1) // 16 bit words }); }; (DSIZE, $spi:ident, u32) => { - $spi.cfg1.modify(|_, w| { + //NOTE(unsafe) 31 is a valid bit pattern + $spi.cfg1().modify(|_, w| unsafe { w.dsize() .bits(32 - 1) // 32 bit words }); @@ -710,7 +711,7 @@ macro_rules! spi { let _ = prec.enable(); // drop, can be recreated by free method // Disable SS output - spi.cfg2.write(|w| w.ssoe().disabled()); + spi.cfg2().write(|w| w.ssoe().disabled()); let config: Config = config.into(); @@ -726,14 +727,14 @@ macro_rules! spi { 65..=128 => MBR::Div128, _ => MBR::Div256, }; - spi.cfg1.modify(|_, w| { + spi.cfg1().modify(|_, w| { w.mbr() .variant(mbr) // master baud rate }); spi!(DSIZE, spi, $TY); // modify CFG1 for DSIZE // ssi: select slave = master mode - spi.cr1.write(|w| w.ssi().slave_not_selected()); + spi.cr1().write(|w| w.ssi().slave_not_selected()); // Calculate the CS->transaction cycle delay bits. let (assertion_delay, inter_word_delay) = { @@ -775,7 +776,8 @@ macro_rules! spi { // mstr: master configuration // lsbfrst: MSB first // comm: full-duplex - spi.cfg2.write(|w| { + //NOTE(unsafe) Only valid bit patterns written, checked above + spi.cfg2().write(|w| unsafe { w.cpha() .bit(config.mode.phase == Phase::CaptureOnSecondTransition) @@ -805,10 +807,13 @@ macro_rules! spi { // Reset to default (might have been set if previously used by a frame transaction) // So that is 1 when it's a frame transaction and 0 when in another mode - spi.cr2.write(|w| w.tsize().bits(matches!(config.hardware_cs.mode, HardwareCSMode::FrameTransaction) as u16)); + //NOTE(unsafe) Only valid bit patterns written + spi.cr2().write(|w| unsafe { + w.tsize().bits(matches!(config.hardware_cs.mode, HardwareCSMode::FrameTransaction) as u16) + }); // spe: enable the SPI bus - spi.cr1.write(|w| w.ssi().slave_not_selected().spe().enabled()); + spi.cr1().write(|w| w.ssi().slave_not_selected().spe().enabled()); Spi { spi, hardware_cs_mode: config.hardware_cs.mode, _word: PhantomData, _ed: PhantomData } } @@ -817,15 +822,15 @@ macro_rules! spi { impl Spi<$SPIX, Ed, $TY> { /// internally disable the SPI without changing its type-state fn internal_disable(&mut self) { - self.spi.cr1.modify(|_, w| w.csusp().requested()); - while self.spi.sr.read().eot().is_completed() {} - self.spi.cr1.write(|w| w.ssi().slave_not_selected().spe().disabled()); + self.spi.cr1().modify(|_, w| w.csusp().requested()); + while self.spi.sr().read().eot().is_completed() {} + self.spi.cr1().write(|w| w.ssi().slave_not_selected().spe().disabled()); } /// internally enable the SPI without changing its type-state fn internal_enable(&mut self) { self.clear_modf(); // SPE cannot be set when MODF is set - self.spi.cr1.write(|w| w.ssi().slave_not_selected().spe().enabled()); + self.spi.cr1().write(|w| w.ssi().slave_not_selected().spe().enabled()); } } @@ -854,21 +859,22 @@ macro_rules! spi { return Err(Error::InvalidCall); } - if self.spi.cr1.read().cstart().is_started() { + if self.spi.cr1().read().cstart().is_started() { return Err(Error::TransactionAlreadyStarted); } // We can only set tsize when spi is disabled - self.spi.cr1.modify(|_, w| w.csusp().requested()); - while self.spi.sr.read().eot().is_completed() {} - self.spi.cr1.write(|w| w.ssi().slave_not_selected().spe().disabled()); + self.spi.cr1().modify(|_, w| w.csusp().requested()); + while self.spi.sr().read().eot().is_completed() {} + self.spi.cr1().write(|w| w.ssi().slave_not_selected().spe().disabled()); // Set the frame size - self.spi.cr2.write(|w| w.tsize().bits(words.get())); + //NOTE(unsafe) Only valid bit patterns are written + self.spi.cr2().write(|w| unsafe { w.tsize().bits(words.get())}); // Re-enable self.clear_modf(); // SPE cannot be set when MODF is set - self.spi.cr1.write(|w| w.ssi().slave_not_selected().spe().enabled()); + self.spi.cr1().write(|w| w.ssi().slave_not_selected().spe().enabled()); Ok(()) } @@ -878,10 +884,10 @@ macro_rules! spi { return Err(Error::InvalidCall); } - self.spi.cr1.modify(|_, w| w.csusp().requested()); - while(self.spi.cr1.read().cstart().is_started()) {} + self.spi.cr1().modify(|_, w| w.csusp().requested()); + while(self.spi.cr1().read().cstart().is_started()) {} - self.spi.ifcr.write(|w| w.txtfc().clear().eotc().clear()); + self.spi.ifcr().write(|w| w.txtfc().clear().eotc().clear()); Ok(()) } @@ -902,19 +908,19 @@ macro_rules! spi { } fn enable_dma_rx(&mut self) { - self.spi.cfg1.modify(|_,w| w.rxdmaen().enabled()); + self.spi.cfg1().modify(|_,w| w.rxdmaen().enabled()); } fn disable_dma_rx(&mut self) { - self.spi.cfg1.modify(|_,w| w.rxdmaen().disabled()); + self.spi.cfg1().modify(|_,w| w.rxdmaen().disabled()); } fn enable_dma_tx(&mut self) { - self.spi.cfg1.modify(|_,w| w.txdmaen().enabled()); + self.spi.cfg1().modify(|_,w| w.txdmaen().enabled()); } fn disable_dma_tx(&mut self) { - self.spi.cfg1.modify(|_,w| w.txdmaen().disabled()); + self.spi.cfg1().modify(|_,w| w.txdmaen().disabled()); } fn free(self) -> ($SPIX, rec::$Rec) { @@ -943,11 +949,11 @@ macro_rules! spi { /// - Error fn listen(&mut self, event: Event) { match event { - Event::Rxp => self.spi.ier.modify(|_, w| + Event::Rxp => self.spi.ier().modify(|_, w| w.rxpie().not_masked()), - Event::Txp => self.spi.ier.modify(|_, w| + Event::Txp => self.spi.ier().modify(|_, w| w.txpie().not_masked()), - Event::Error => self.spi.ier.modify(|_, w| { + Event::Error => self.spi.ier().modify(|_, w| { w.udrie() // Underrun .not_masked() .ovrie() // Overrun @@ -957,7 +963,7 @@ macro_rules! spi { .modfie() // Mode fault .not_masked() }), - } + }; } /// Disable interrupts for the given `event`: @@ -967,13 +973,13 @@ macro_rules! spi { fn unlisten(&mut self, event: Event) { match event { Event::Rxp => { - self.spi.ier.modify(|_, w| w.rxpie().masked()); + self.spi.ier().modify(|_, w| w.rxpie().masked()); } Event::Txp => { - self.spi.ier.modify(|_, w| w.txpie().masked()); + self.spi.ier().modify(|_, w| w.txpie().masked()); } Event::Error => { - self.spi.ier.modify(|_, w| { + self.spi.ier().modify(|_, w| { w.udrie() // Underrun .masked() .ovrie() // Overrun @@ -982,45 +988,45 @@ macro_rules! spi { .masked() .modfie() // Mode fault .masked() - }) + }); } } - let _ = self.spi.ier.read(); - let _ = self.spi.ier.read(); // Delay 2 peripheral clocks + let _ = self.spi.ier().read(); + let _ = self.spi.ier().read(); // Delay 2 peripheral clocks } /// Return `true` if the TXP flag is set, i.e. new /// data to transmit can be written to the SPI. fn is_txp(&self) -> bool { - self.spi.sr.read().txp().is_not_full() + self.spi.sr().read().txp().is_not_full() } /// Return `true` if the RXP flag is set, i.e. new /// data has been received and can be read from the /// SPI. fn is_rxp(&self) -> bool { - self.spi.sr.read().rxp().is_not_empty() + self.spi.sr().read().rxp().is_not_empty() } /// Return `true` if the MODF flag is set, i.e. the /// SPI has experienced a mode fault fn is_modf(&self) -> bool { - self.spi.sr.read().modf().is_fault() + self.spi.sr().read().modf().is_fault() } /// Return `true` if the OVR flag is set, i.e. new /// data has been received while the receive data /// register was already filled. fn is_ovr(&self) -> bool { - self.spi.sr.read().ovr().is_overrun() + self.spi.sr().read().ovr().is_overrun() } /// Clears the MODF flag, which indicates that a /// mode fault has occurred. fn clear_modf(&mut self) { - self.spi.ifcr.write(|w| w.modfc().clear()); - let _ = self.spi.sr.read(); - let _ = self.spi.sr.read(); // Delay 2 peripheral clocks + self.spi.ifcr().write(|w| w.modfc().clear()); + let _ = self.spi.sr().read(); + let _ = self.spi.sr().read(); // Delay 2 peripheral clocks } } @@ -1069,7 +1075,7 @@ macro_rules! spi { // NOTE(read_volatile) read only 1 word return Ok(unsafe { ptr::read_volatile( - &self.spi.rxdr as *const _ as *const $TY, + &self.spi.rxdr() as *const _ as *const $TY, ) }); } @@ -1083,7 +1089,7 @@ macro_rules! spi { { // NOTE(write_volatile) see note above unsafe { - let txdr = &self.spi.txdr as *const _ as *const UnsafeCell<$TY>; + let txdr = self.spi.txdr().as_ptr() as *const UnsafeCell<$TY>; ptr::write_volatile( UnsafeCell::raw_get(txdr), word, @@ -1091,7 +1097,7 @@ macro_rules! spi { } // write CSTART to start a transaction in // master mode - self.spi.cr1.modify(|_, w| w.cstart().started()); + self.spi.cr1().modify(|_, w| w.cstart().started()); return Ok(()); } @@ -1113,20 +1119,20 @@ macro_rules! spi { { // NOTE(write_volatile/read_volatile) write/read only 1 word unsafe { - let txdr = &self.spi.txdr as *const _ as *const UnsafeCell<$TY>; + let txdr = self.spi.txdr().as_ptr() as *const UnsafeCell<$TY>; ptr::write_volatile( UnsafeCell::raw_get(txdr), word, ); return Ok(ptr::read_volatile( - &self.spi.rxdr as *const _ as *const $TY, + &self.spi.rxdr() as *const _ as *const $TY, )); } } }, { // else if sr.txc().is_completed() { txc, is_completed, { - let sr = self.spi.sr.read(); // Read SR again on a subsequent PCLK cycle + let sr = self.spi.sr().read(); // Read SR again on a subsequent PCLK cycle if sr.txc().is_completed() && !sr.rxp().is_not_empty() { // The Tx FIFO completed, but no words were @@ -1151,14 +1157,14 @@ macro_rules! spi { // NOTE(read_volatile) read only 1 word return Ok(unsafe { ptr::read_volatile( - &self.spi.rxdr as *const _ as *const $TY, + &self.spi.rxdr() as *const _ as *const $TY, ) }); } }, { // else if sr.txc().is_completed() txc, is_completed, { - let sr = self.spi.sr.read(); // Read SR again on a subsequent PCLK cycle + let sr = self.spi.sr().read(); // Read SR again on a subsequent PCLK cycle if sr.txc().is_completed() && !sr.rxp().is_not_empty() { // The Tx FIFO completed, but no words were @@ -1318,17 +1324,17 @@ macro_rules! spi123sel { /// for SPI1, SPI2, SPI3 pub fn kernel_clk(clocks: &CoreClocks) -> Option { #[cfg(not(feature = "rm0455"))] - let ccip1r = unsafe { (*stm32::RCC::ptr()).d2ccip1r.read() }; + let ccip1r = unsafe { (*stm32::RCC::ptr()).d2ccip1r().read() }; #[cfg(feature = "rm0455")] - let ccip1r = unsafe { (*stm32::RCC::ptr()).cdccip1r.read() }; + let ccip1r = unsafe { (*stm32::RCC::ptr()).cdccip1r().read() }; match ccip1r.spi123sel().variant() { - Some(ccip1r::SPI123SEL_A::Pll1Q) => clocks.pll1_q_ck(), - Some(ccip1r::SPI123SEL_A::Pll2P) => clocks.pll2_p_ck(), - Some(ccip1r::SPI123SEL_A::Pll3P) => clocks.pll3_p_ck(), + Some(ccip1r::SAI1SEL::Pll1Q) => clocks.pll1_q_ck(), + Some(ccip1r::SAI1SEL::Pll2P) => clocks.pll2_p_ck(), + Some(ccip1r::SAI1SEL::Pll3P) => clocks.pll3_p_ck(), // Need a method of specifying pin clock - Some(ccip1r::SPI123SEL_A::I2sCkin) => unimplemented!(), - Some(ccip1r::SPI123SEL_A::Per) => clocks.per_ck(), + Some(ccip1r::SAI1SEL::I2sCkin) => unimplemented!(), + Some(ccip1r::SAI1SEL::Per) => clocks.per_ck(), _ => unreachable!(), } } @@ -1340,23 +1346,23 @@ macro_rules! spi123sel { /// Panics if the kernel clock is not running pub fn kernel_clk_unwrap(clocks: &CoreClocks) -> Hertz { #[cfg(not(feature = "rm0455"))] - let ccip1r = unsafe { (*stm32::RCC::ptr()).d2ccip1r.read() }; + let ccip1r = unsafe { (*stm32::RCC::ptr()).d2ccip1r().read() }; #[cfg(feature = "rm0455")] - let ccip1r = unsafe { (*stm32::RCC::ptr()).cdccip1r.read() }; + let ccip1r = unsafe { (*stm32::RCC::ptr()).cdccip1r().read() }; match ccip1r.spi123sel().variant() { - Some(ccip1r::SPI123SEL_A::Pll1Q) => { + Some(ccip1r::SAI1SEL::Pll1Q) => { clocks.pll1_q_ck().expect("SPI123: PLL1_Q must be enabled") } - Some(ccip1r::SPI123SEL_A::Pll2P) => { + Some(ccip1r::SAI1SEL::Pll2P) => { clocks.pll2_p_ck().expect("SPI123: PLL2_P must be enabled") } - Some(ccip1r::SPI123SEL_A::Pll3P) => { + Some(ccip1r::SAI1SEL::Pll3P) => { clocks.pll3_p_ck().expect("SPI123: PLL3_P must be enabled") } // Need a method of specifying pin clock - Some(ccip1r::SPI123SEL_A::I2sCkin) => unimplemented!(), - Some(ccip1r::SPI123SEL_A::Per) => { + Some(ccip1r::SAI1SEL::I2sCkin) => unimplemented!(), + Some(ccip1r::SAI1SEL::Per) => { clocks.per_ck().expect("SPI123: PER clock must be enabled") } _ => unreachable!(), @@ -1374,17 +1380,17 @@ macro_rules! spi45sel { /// for SPI4, SPI5 pub fn kernel_clk(clocks: &CoreClocks) -> Option { #[cfg(not(feature = "rm0455"))] - let ccip1r = unsafe { (*stm32::RCC::ptr()).d2ccip1r.read() }; + let ccip1r = unsafe { (*stm32::RCC::ptr()).d2ccip1r().read() }; #[cfg(feature = "rm0455")] - let ccip1r = unsafe { (*stm32::RCC::ptr()).cdccip1r.read() }; + let ccip1r = unsafe { (*stm32::RCC::ptr()).cdccip1r().read() }; match ccip1r.spi45sel().variant() { - Some(ccip1r::SPI45SEL_A::Apb) => Some(clocks.pclk2()), - Some(ccip1r::SPI45SEL_A::Pll2Q) => clocks.pll2_q_ck(), - Some(ccip1r::SPI45SEL_A::Pll3Q) => clocks.pll3_q_ck(), - Some(ccip1r::SPI45SEL_A::HsiKer) => clocks.hsi_ck(), - Some(ccip1r::SPI45SEL_A::CsiKer) => clocks.csi_ck(), - Some(ccip1r::SPI45SEL_A::Hse) => clocks.hse_ck(), + Some(ccip1r::SPI45SEL::Apb) => Some(clocks.pclk2()), + Some(ccip1r::SPI45SEL::Pll2Q) => clocks.pll2_q_ck(), + Some(ccip1r::SPI45SEL::Pll3Q) => clocks.pll3_q_ck(), + Some(ccip1r::SPI45SEL::HsiKer) => clocks.hsi_ck(), + Some(ccip1r::SPI45SEL::CsiKer) => clocks.csi_ck(), + Some(ccip1r::SPI45SEL::Hse) => clocks.hse_ck(), _ => unreachable!(), } } @@ -1396,25 +1402,25 @@ macro_rules! spi45sel { /// Panics if the kernel clock is not running pub fn kernel_clk_unwrap(clocks: &CoreClocks) -> Hertz { #[cfg(not(feature = "rm0455"))] - let ccip1r = unsafe { (*stm32::RCC::ptr()).d2ccip1r.read() }; + let ccip1r = unsafe { (*stm32::RCC::ptr()).d2ccip1r().read() }; #[cfg(feature = "rm0455")] - let ccip1r = unsafe { (*stm32::RCC::ptr()).cdccip1r.read() }; + let ccip1r = unsafe { (*stm32::RCC::ptr()).cdccip1r().read() }; match ccip1r.spi45sel().variant() { - Some(ccip1r::SPI45SEL_A::Apb) => clocks.pclk2(), - Some(ccip1r::SPI45SEL_A::Pll2Q) => { + Some(ccip1r::SPI45SEL::Apb) => clocks.pclk2(), + Some(ccip1r::SPI45SEL::Pll2Q) => { clocks.pll2_q_ck().expect("SPI45: PLL2_Q must be enabled") } - Some(ccip1r::SPI45SEL_A::Pll3Q) => { + Some(ccip1r::SPI45SEL::Pll3Q) => { clocks.pll3_q_ck().expect("SPI45: PLL3_Q must be enabled") } - Some(ccip1r::SPI45SEL_A::HsiKer) => { + Some(ccip1r::SPI45SEL::HsiKer) => { clocks.hsi_ck().expect("SPI45: HSI clock must be enabled") } - Some(ccip1r::SPI45SEL_A::CsiKer) => { + Some(ccip1r::SPI45SEL::CsiKer) => { clocks.csi_ck().expect("SPI45: CSI clock must be enabled") } - Some(ccip1r::SPI45SEL_A::Hse) => { + Some(ccip1r::SPI45SEL::Hse) => { clocks.hse_ck().expect("SPI45: HSE clock must be enabled") } _ => unreachable!(), @@ -1432,17 +1438,17 @@ macro_rules! spi6sel { /// for SPI6 pub fn kernel_clk(clocks: &CoreClocks) -> Option { #[cfg(not(feature = "rm0455"))] - let srdccipr = unsafe { (*stm32::RCC::ptr()).d3ccipr.read() }; + let srdccipr = unsafe { (*stm32::RCC::ptr()).d3ccipr().read() }; #[cfg(feature = "rm0455")] - let srdccipr = unsafe { (*stm32::RCC::ptr()).srdccipr.read() }; + let srdccipr = unsafe { (*stm32::RCC::ptr()).srdccipr().read() }; match srdccipr.spi6sel().variant() { - Some(srdccipr::SPI6SEL_A::RccPclk4) => Some(clocks.pclk4()), - Some(srdccipr::SPI6SEL_A::Pll2Q) => clocks.pll2_q_ck(), - Some(srdccipr::SPI6SEL_A::Pll3Q) => clocks.pll3_q_ck(), - Some(srdccipr::SPI6SEL_A::HsiKer) => clocks.hsi_ck(), - Some(srdccipr::SPI6SEL_A::CsiKer) => clocks.csi_ck(), - Some(srdccipr::SPI6SEL_A::Hse) => clocks.hse_ck(), + Some(srdccipr::SPI6SEL::RccPclk4) => Some(clocks.pclk4()), + Some(srdccipr::SPI6SEL::Pll2Q) => clocks.pll2_q_ck(), + Some(srdccipr::SPI6SEL::Pll3Q) => clocks.pll3_q_ck(), + Some(srdccipr::SPI6SEL::HsiKer) => clocks.hsi_ck(), + Some(srdccipr::SPI6SEL::CsiKer) => clocks.csi_ck(), + Some(srdccipr::SPI6SEL::Hse) => clocks.hse_ck(), _ => unreachable!(), } } @@ -1450,25 +1456,25 @@ macro_rules! spi6sel { /// for SPI6 pub fn kernel_clk_unwrap(clocks: &CoreClocks) -> Hertz { #[cfg(not(feature = "rm0455"))] - let srdccipr = unsafe { (*stm32::RCC::ptr()).d3ccipr.read() }; + let srdccipr = unsafe { (*stm32::RCC::ptr()).d3ccipr().read() }; #[cfg(feature = "rm0455")] - let srdccipr = unsafe { (*stm32::RCC::ptr()).srdccipr.read() }; + let srdccipr = unsafe { (*stm32::RCC::ptr()).srdccipr().read() }; match srdccipr.spi6sel().variant() { - Some(srdccipr::SPI6SEL_A::RccPclk4) => clocks.pclk4(), - Some(srdccipr::SPI6SEL_A::Pll2Q) => { + Some(srdccipr::SPI6SEL::RccPclk4) => clocks.pclk4(), + Some(srdccipr::SPI6SEL::Pll2Q) => { clocks.pll2_q_ck().expect("SPI6: PLL2_Q must be enabled") } - Some(srdccipr::SPI6SEL_A::Pll3Q) => { + Some(srdccipr::SPI6SEL::Pll3Q) => { clocks.pll3_q_ck().expect("SPI6: PLL3_Q must be enabled") } - Some(srdccipr::SPI6SEL_A::HsiKer) => { + Some(srdccipr::SPI6SEL::HsiKer) => { clocks.hsi_ck().expect("SPI6: HSI clock must be enabled") } - Some(srdccipr::SPI6SEL_A::CsiKer) => { + Some(srdccipr::SPI6SEL::CsiKer) => { clocks.csi_ck().expect("SPI6: CSI clock must be enabled") } - Some(srdccipr::SPI6SEL_A::Hse) => { + Some(srdccipr::SPI6SEL::Hse) => { clocks.hse_ck().expect("SPI6: HSE clock must be enabled") } _ => unreachable!(), diff --git a/src/system_watchdog.rs b/src/system_watchdog.rs index aec8eee0..b3aee3cb 100644 --- a/src/system_watchdog.rs +++ b/src/system_watchdog.rs @@ -56,9 +56,9 @@ impl SystemWindowWatchdog { pub fn new(wwdg: WWDG, ccdr: &Ccdr) -> Self { // enable the peripheral inside the APB3 #[cfg(not(feature = "rm0455"))] - ccdr.rb.apb3enr.modify(|_, w| w.wwdg1en().set_bit()); + ccdr.rb.apb3enr().modify(|_, w| w.wwdg1en().set_bit()); #[cfg(feature = "rm0455")] - ccdr.rb.apb3enr.modify(|_, w| w.wwdgen().set_bit()); + ccdr.rb.apb3enr().modify(|_, w| w.wwdgen().set_bit()); SystemWindowWatchdog { wwdg, @@ -76,7 +76,7 @@ impl SystemWindowWatchdog { // which would immediately call the interrupt. assert!(self.down_counter != 0); // Set the ewi bit - self.wwdg.cfr.modify(|_, w| w.ewi().enable()); + self.wwdg.cfr().modify(|_, w| w.ewi().enable()); } } } @@ -91,7 +91,7 @@ impl SystemWindowWatchdog { /// Returns `true` if `event` is pending pub fn is_pending(&self, event: Event) -> bool { match event { - Event::EarlyWakeup => self.wwdg.sr.read().ewif().is_pending(), + Event::EarlyWakeup => self.wwdg.sr().read().ewif().is_pending(), } } @@ -99,7 +99,7 @@ impl SystemWindowWatchdog { pub fn unpend(&mut self, event: Event) { match event { Event::EarlyWakeup => { - self.wwdg.sr.write(|w| w.ewif().finished()); + self.wwdg.sr().write(|w| w.ewif().finished()); } } } @@ -121,7 +121,10 @@ impl Watchdog for SystemWindowWatchdog { fn feed(&mut self) { // if this value is 0 it is assumed that the watchdog has not yet been started assert!(self.down_counter != 0); - self.wwdg.cr.modify(|_, w| w.t().bits(self.down_counter)); + //NOTE(unsafe) Only valid bit patterns written, checked on start + self.wwdg + .cr() + .modify(|_, w| unsafe { w.t().bits(self.down_counter) }); } } @@ -160,13 +163,24 @@ impl WatchdogEnable for SystemWindowWatchdog { self.down_counter = u8(t).unwrap() | (1 << 6); // write the config values, matching the set timeout the most - self.wwdg.cfr.modify(|_, w| w.wdgtb().bits(wdgtb)); - self.wwdg.cfr.modify(|_, w| w.w().bits(self.down_counter)); - self.wwdg.cr.modify(|_, w| w.t().bits(self.down_counter)); + //NOTE(unsafe) Only valid bit patterns written + self.wwdg + .cfr() + .modify(|_, w| unsafe { w.wdgtb().bits(wdgtb) }); + + //NOTE(unsafe) Only valid bit patterns written, checked above + self.wwdg + .cfr() + .modify(|_, w| unsafe { w.w().bits(self.down_counter) }); + + //NOTE(unsafe) Only valid bit patterns written, checked above + self.wwdg + .cr() + .modify(|_, w| unsafe { w.t().bits(self.down_counter) }); // For some reason, setting the t value makes the early wakeup pending. // That's bad behaviour, so lets turn it off again. self.unpend(Event::EarlyWakeup); // enable the watchdog - self.wwdg.cr.modify(|_, w| w.wdga().set_bit()); + self.wwdg.cr().modify(|_, w| w.wdga().set_bit()); } } diff --git a/src/timer.rs b/src/timer.rs index dfa73429..67eb6921 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -70,17 +70,17 @@ impl GetClk for LPTIM1 { fn get_clk(clocks: &CoreClocks) -> Option { // unsafe: read only #[cfg(not(feature = "rm0455"))] - let ccip2r = &unsafe { &*stm32::RCC::ptr() }.d2ccip2r; + let ccip2r = &unsafe { &*stm32::RCC::ptr() }.d2ccip2r(); #[cfg(feature = "rm0455")] - let ccip2r = &unsafe { &*stm32::RCC::ptr() }.cdccip2r; + let ccip2r = &unsafe { &*stm32::RCC::ptr() }.cdccip2r(); match ccip2r.read().lptim1sel().variant() { - Some(ccip2r::LPTIM1SEL_A::RccPclk1) => Some(clocks.pclk1()), - Some(ccip2r::LPTIM1SEL_A::Pll2P) => clocks.pll2_p_ck(), - Some(ccip2r::LPTIM1SEL_A::Pll3R) => clocks.pll3_r_ck(), - Some(ccip2r::LPTIM1SEL_A::Lse) => unimplemented!(), - Some(ccip2r::LPTIM1SEL_A::Lsi) => clocks.lsi_ck(), - Some(ccip2r::LPTIM1SEL_A::Per) => clocks.per_ck(), + Some(ccip2r::LPTIM1SEL::RccPclk1) => Some(clocks.pclk1()), + Some(ccip2r::LPTIM1SEL::Pll2P) => clocks.pll2_p_ck(), + Some(ccip2r::LPTIM1SEL::Pll3R) => clocks.pll3_r_ck(), + Some(ccip2r::LPTIM1SEL::Lse) => unimplemented!(), + Some(ccip2r::LPTIM1SEL::Lsi) => clocks.lsi_ck(), + Some(ccip2r::LPTIM1SEL::Per) => clocks.per_ck(), _ => unreachable!(), } } @@ -92,17 +92,17 @@ impl GetClk for LPTIM2 { fn get_clk(clocks: &CoreClocks) -> Option { // unsafe: read only #[cfg(not(feature = "rm0455"))] - let srdccipr = &unsafe { &*stm32::RCC::ptr() }.d3ccipr; + let srdccipr = &unsafe { &*stm32::RCC::ptr() }.d3ccipr(); #[cfg(feature = "rm0455")] - let srdccipr = &unsafe { &*stm32::RCC::ptr() }.srdccipr; + let srdccipr = &unsafe { &*stm32::RCC::ptr() }.srdccipr(); match srdccipr.read().lptim2sel().variant() { - Some(srdccipr::LPTIM2SEL_A::RccPclk4) => Some(clocks.pclk4()), - Some(srdccipr::LPTIM2SEL_A::Pll2P) => clocks.pll2_p_ck(), - Some(srdccipr::LPTIM2SEL_A::Pll3R) => clocks.pll3_r_ck(), - Some(srdccipr::LPTIM2SEL_A::Lse) => unimplemented!(), - Some(srdccipr::LPTIM2SEL_A::Lsi) => clocks.lsi_ck(), - Some(srdccipr::LPTIM2SEL_A::Per) => clocks.per_ck(), + Some(srdccipr::LPTIM2SEL::RccPclk4) => Some(clocks.pclk4()), + Some(srdccipr::LPTIM2SEL::Pll2P) => clocks.pll2_p_ck(), + Some(srdccipr::LPTIM2SEL::Pll3R) => clocks.pll3_r_ck(), + Some(srdccipr::LPTIM2SEL::Lse) => unimplemented!(), + Some(srdccipr::LPTIM2SEL::Lsi) => clocks.lsi_ck(), + Some(srdccipr::LPTIM2SEL::Per) => clocks.per_ck(), _ => unreachable!(), } } @@ -114,7 +114,7 @@ impl GetClk for LPTIM3 { /// Current kernel clock fn get_clk(clocks: &CoreClocks) -> Option { // unsafe: read only - let srdccipr = &unsafe { &*stm32::RCC::ptr() }.srdccipr; + let srdccipr = &unsafe { &*stm32::RCC::ptr() }.srdccipr(); match srdccipr.read().lptim3sel().bits() { 0 => Some(clocks.pclk4()), @@ -137,15 +137,15 @@ macro_rules! impl_clk_lptim345 { /// Current kernel clock fn get_clk(clocks: &CoreClocks) -> Option { // unsafe: read only - let d3ccipr = &unsafe { &*stm32::RCC::ptr() }.d3ccipr; + let d3ccipr = &unsafe { &*stm32::RCC::ptr() }.d3ccipr(); match d3ccipr.read().lptim345sel().variant() { - Some(srdccipr::LPTIM345SEL_A::RccPclk4) => Some(clocks.pclk4()), - Some(srdccipr::LPTIM345SEL_A::Pll2P) => clocks.pll2_p_ck(), - Some(srdccipr::LPTIM345SEL_A::Pll3R) => clocks.pll3_r_ck(), - Some(srdccipr::LPTIM345SEL_A::Lse) => unimplemented!(), - Some(srdccipr::LPTIM345SEL_A::Lsi) => clocks.lsi_ck(), - Some(srdccipr::LPTIM345SEL_A::Per) => clocks.per_ck(), + Some(srdccipr::LPTIM2SEL::RccPclk4) => Some(clocks.pclk4()), + Some(srdccipr::LPTIM2SEL::Pll2P) => clocks.pll2_p_ck(), + Some(srdccipr::LPTIM2SEL::Pll3R) => clocks.pll3_r_ck(), + Some(srdccipr::LPTIM2SEL::Lse) => unimplemented!(), + Some(srdccipr::LPTIM2SEL::Lsi) => clocks.lsi_ck(), + Some(srdccipr::LPTIM2SEL::Per) => clocks.per_ck(), _ => unreachable!(), } } @@ -438,9 +438,10 @@ macro_rules! hal { /// ``` fn set_timeout_ticks(&mut self, ticks: u32) { let (psc, arr) = calculate_timeout_ticks_register_values(ticks); - self.tim.psc.write(|w| w.psc().bits(psc)); + //NOTE(unsafe) All bit patterns are valid + self.tim.psc().write(|w| unsafe { w.psc().bits(psc) }); #[allow(unused_unsafe)] // method is safe for some timers - self.tim.arr.write(|w| unsafe { w.bits(u32(arr)) }); + self.tim.arr().write(|w| unsafe { w.bits(u32(arr)) }); } /// Configures the timer to count up at the given frequency @@ -452,11 +453,12 @@ macro_rules! hal { let div = self.clk / frequency.raw(); let psc = u16(div - 1).unwrap(); - self.tim.psc.write(|w| w.psc().bits(psc)); + //NOTE(unsafe) All bit patterns are valid + self.tim.psc().write(|w| unsafe { w.psc().bits(psc) }); let counter_max = u32(<$cntType>::MAX); #[allow(unused_unsafe)] // method is safe for some timers - self.tim.arr.write(|w| unsafe { w.bits(counter_max) }); + self.tim.arr().write(|w| unsafe { w.bits(counter_max) }); } /// Applies frequency/timeout changes immediately @@ -465,32 +467,32 @@ macro_rules! hal { /// value when its counter overflows. This function causes /// those changes to happen immediately. Also clears the counter. pub fn apply_freq(&mut self) { - self.tim.egr.write(|w| w.ug().set_bit()); + self.tim.egr().write(|w| w.ug().set_bit()); } /// Pauses the TIM peripheral pub fn pause(&mut self) { - self.tim.cr1.modify(|_, w| w.cen().clear_bit()); + self.tim.cr1().modify(|_, w| w.cen().clear_bit()); } /// Resume (unpause) the TIM peripheral pub fn resume(&mut self) { - self.tim.cr1.modify(|_, w| w.cen().set_bit()); + self.tim.cr1().modify(|_, w| w.cen().set_bit()); } /// Set Update Request Source to counter overflow/underflow only pub fn urs_counter_only(&mut self) { - self.tim.cr1.modify(|_, w| w.urs().counter_only()); + self.tim.cr1().modify(|_, w| w.urs().counter_only()); } /// Reset the counter of the TIM peripheral pub fn reset_counter(&mut self) { - self.tim.cnt.reset(); + self.tim.cnt().reset(); } /// Read the counter of the TIM peripheral pub fn counter(&self) -> u32 { - self.tim.cnt.read().cnt().bits().into() + self.tim.cnt().read().cnt().bits().into() } /// Start listening for `event` @@ -498,7 +500,7 @@ macro_rules! hal { match event { Event::TimeOut => { // Enable update event interrupt - self.tim.dier.write(|w| w.uie().set_bit()); + self.tim.dier().write(|w| w.uie().set_bit()); } } } @@ -508,26 +510,26 @@ macro_rules! hal { match event { Event::TimeOut => { // Disable update event interrupt - self.tim.dier.write(|w| w.uie().clear_bit()); - let _ = self.tim.dier.read(); - let _ = self.tim.dier.read(); // Delay 2 peripheral clocks + self.tim.dier().write(|w| w.uie().clear_bit()); + let _ = self.tim.dier().read(); + let _ = self.tim.dier().read(); // Delay 2 peripheral clocks } } } /// Check if Update Interrupt flag is cleared pub fn is_irq_clear(&mut self) -> bool { - self.tim.sr.read().uif().bit_is_clear() + self.tim.sr().read().uif().bit_is_clear() } /// Clears interrupt flag pub fn clear_irq(&mut self) { - self.tim.sr.modify(|_, w| { + self.tim.sr().modify(|_, w| { // Clears timeout event w.uif().clear_bit() }); - let _ = self.tim.sr.read(); - let _ = self.tim.sr.read(); // Delay 2 peripheral clocks + let _ = self.tim.sr().read(); + let _ = self.tim.sr().read(); // Delay 2 peripheral clocks } /// Releases the TIM peripheral @@ -620,7 +622,7 @@ macro_rules! lptim_hal { self.reset_counter(); // Disable counter - self.tim.cr.write(|w| w.enable().disabled()); + self.tim.cr().write(|w| w.enable().disabled()); // Set prescale and ARR self.priv_set_freq(timeout.into()); // side effect: enables counter @@ -629,12 +631,12 @@ macro_rules! lptim_hal { self.clear_irq(); // Start counter - self.tim.cr.write(|w| w.enable().enabled()); - self.tim.cr.write(|w| w.cntstrt().set_bit().enable().enabled()); + self.tim.cr().write(|w| w.enable().enabled()); + self.tim.cr().write(|w| w.cntstrt().set_bit().enable().enabled()); } fn wait(&mut self) -> nb::Result<(), Void> { - if self.tim.isr.read().arrm().bit_is_clear() { + if self.tim.isr().read().arrm().bit_is_clear() { Err(nb::Error::WouldBlock) } else { self.clear_irq(); @@ -675,7 +677,7 @@ macro_rules! lptim_hal { timer.reset_counter(); // Disable counter - timer.tim.cr.write(|w| w.enable().disabled()); + timer.tim.cr().write(|w| w.enable().disabled()); // Set tick frequency timer.priv_set_tick_freq(frequency); @@ -684,8 +686,8 @@ macro_rules! lptim_hal { timer.clear_irq(); // Start counter - timer.tim.cr.write(|w| w.enable().enabled()); - timer.tim.cr.write(|w| w.cntstrt().set_bit().enable().enabled()); + timer.tim.cr().write(|w| w.enable().enabled()); + timer.tim.cr().write(|w| w.cntstrt().set_bit().enable().enabled()); timer } @@ -719,15 +721,15 @@ macro_rules! lptim_hal { fn reset_counter(&mut self) { // Counter Reset - self.tim.cr.write(|w| w.countrst().set_bit().enable().enabled()); - let _ = self.tim.cr.read(); - let _ = self.tim.cr.read(); // Delay 2 peripheral clocks + self.tim.cr().write(|w| w.countrst().set_bit().enable().enabled()); + let _ = self.tim.cr().read(); + let _ = self.tim.cr().read(); // Delay 2 peripheral clocks } /// Disables the LPTIM peripheral fn pause(self) -> Self::Disabled { // Disable the entire timer - self.tim.cr.write(|w| w.enable().disabled()); + self.tim.cr().write(|w| w.enable().disabled()); Self::Disabled { clk: self.clk, @@ -745,7 +747,7 @@ macro_rules! lptim_hal { self.priv_set_freq(timeout); // side effect: enables counter // Disable timer - self.tim.cr.write(|w| w.enable().disabled()); + self.tim.cr().write(|w| w.enable().disabled()); } fn set_tick_freq(&mut self, frequency: Hertz) @@ -753,14 +755,14 @@ macro_rules! lptim_hal { self.priv_set_tick_freq(frequency); // side effect: enables counter // Disable timer - self.tim.cr.write(|w| w.enable().disabled()); + self.tim.cr().write(|w| w.enable().disabled()); } fn listen(&mut self, event: Event) { match event { Event::TimeOut => { // Enable autoreload match interrupt - self.tim.ier.modify(|_, w| w.arrmie().set_bit()); + self.tim.ier().modify(|_, w| w.arrmie().set_bit()); } } } @@ -769,9 +771,9 @@ macro_rules! lptim_hal { match event { Event::TimeOut => { // Disable autoreload match interrupt - self.tim.ier.modify(|_, w| w.arrmie().clear_bit()); - let _ = self.tim.ier.read(); - let _ = self.tim.ier.read(); // Delay 2 peripheral clocks + self.tim.ier().modify(|_, w| w.arrmie().clear_bit()); + let _ = self.tim.ier().read(); + let _ = self.tim.ier().read(); // Delay 2 peripheral clocks } } } @@ -779,8 +781,8 @@ macro_rules! lptim_hal { /// Enables the LPTIM, and starts counting fn resume(self) -> Self::Enabled { // Enable and start counting - self.tim.cr.write(|w| w.enable().enabled()); - self.tim.cr.write(|w| w.cntstrt().set_bit().enable().enabled()); + self.tim.cr().write(|w| w.enable().enabled()); + self.tim.cr().write(|w| w.cntstrt().set_bit().enable().enabled()); Self::Enabled { clk: self.clk, @@ -805,14 +807,14 @@ macro_rules! lptim_hal { // Calculate prescaler let (prescale, prescale_div) = match ticks / (1 << 16) { - 0 => ($timXpac::cfgr::PRESC_A::Div1, 1), - 1 => ($timXpac::cfgr::PRESC_A::Div2, 2), - 2..=3 => ($timXpac::cfgr::PRESC_A::Div4, 4), - 4..=7 => ($timXpac::cfgr::PRESC_A::Div8, 8), - 8..=15 => ($timXpac::cfgr::PRESC_A::Div16, 16), - 16..=31 => ($timXpac::cfgr::PRESC_A::Div32, 32), - 32..=63 => ($timXpac::cfgr::PRESC_A::Div64, 64), - _ => ($timXpac::cfgr::PRESC_A::Div128, 128), + 0 => ($timXpac::cfgr::PRESC::Div1, 1), + 1 => ($timXpac::cfgr::PRESC::Div2, 2), + 2..=3 => ($timXpac::cfgr::PRESC::Div4, 4), + 4..=7 => ($timXpac::cfgr::PRESC::Div8, 8), + 8..=15 => ($timXpac::cfgr::PRESC::Div16, 16), + 16..=31 => ($timXpac::cfgr::PRESC::Div32, 32), + 32..=63 => ($timXpac::cfgr::PRESC::Div64, 64), + _ => ($timXpac::cfgr::PRESC::Div128, 128), }; // Calcuate reload @@ -821,15 +823,16 @@ macro_rules! lptim_hal { assert!(arr > 0); // Write CFGR: LPTIM must be disabled - self.tim.cfgr.modify(|_, w| w.presc().variant(prescale)); + self.tim.cfgr().modify(|_, w| w.presc().variant(prescale)); // Enable - self.tim.cr.write(|w| w.enable().enabled()); + self.tim.cr().write(|w| w.enable().enabled()); // Write ARR: LPTIM must be enabled - self.tim.arr.write(|w| w.arr().bits(arr as u16)); - while self.tim.isr.read().arrok().bit_is_clear() {} - self.tim.icr.write(|w| w.arrokcf().clear()); + //NOTE(unsafe) All bit patterns are valid + self.tim.arr().write(|w| unsafe { w.arr().bits(arr as u16) }); + while self.tim.isr().read().arrok().bit_is_clear() {} + self.tim.icr().write(|w| w.arrokcf().clear()); } /// Private method to configure the timer to count up at the @@ -846,28 +849,29 @@ macro_rules! lptim_hal { "LPTIM input clock is too slow to achieve this frequency"); let (prescale, _prescale_div) = match ticks { - 0..=1 => ($timXpac::cfgr::PRESC_A::Div1, 1), - 2 => ($timXpac::cfgr::PRESC_A::Div2, 2), - 3..=4 => ($timXpac::cfgr::PRESC_A::Div4, 4), - 5..=8 => ($timXpac::cfgr::PRESC_A::Div8, 8), - 9..=16 => ($timXpac::cfgr::PRESC_A::Div16, 16), - 17..=32 => ($timXpac::cfgr::PRESC_A::Div32, 32), - 33..=64 => ($timXpac::cfgr::PRESC_A::Div64, 64), - _ => ($timXpac::cfgr::PRESC_A::Div128, 128), + 0..=1 => ($timXpac::cfgr::PRESC::Div1, 1), + 2 => ($timXpac::cfgr::PRESC::Div2, 2), + 3..=4 => ($timXpac::cfgr::PRESC::Div4, 4), + 5..=8 => ($timXpac::cfgr::PRESC::Div8, 8), + 9..=16 => ($timXpac::cfgr::PRESC::Div16, 16), + 17..=32 => ($timXpac::cfgr::PRESC::Div32, 32), + 33..=64 => ($timXpac::cfgr::PRESC::Div64, 64), + _ => ($timXpac::cfgr::PRESC::Div128, 128), }; // Write CFGR: LPTIM must be disabled - self.tim.cfgr.modify(|_, w| w.presc().variant(prescale)); + self.tim.cfgr().modify(|_, w| w.presc().variant(prescale)); // Enable - self.tim.cr.write(|w| w.enable().enabled()); + self.tim.cr().write(|w| w.enable().enabled()); // Set ARR = max // Write ARR: LPTIM must be enabled - self.tim.arr.write(|w| w.arr().bits(0xFFFF as u16)); - while self.tim.isr.read().arrok().bit_is_clear() {} - self.tim.icr.write(|w| w.arrokcf().clear()); + //NOTE(unsafe) 0xFFFF is a valid bit pattern + self.tim.arr().write(|w| unsafe { w.arr().bits(0xFFFF as u16) }); + while self.tim.isr().read().arrok().bit_is_clear() {} + self.tim.icr().write(|w| w.arrokcf().clear()); } } @@ -878,10 +882,10 @@ macro_rules! lptim_hal { fn counter(&self) -> u16 { loop { // Read once - let count1 = self.tim.cnt.read().cnt().bits(); + let count1 = self.tim.cnt().read().cnt().bits(); // Read twice - see RM0433 Rev 7. 43.4.14 - let count2 = self.tim.cnt.read().cnt().bits(); + let count2 = self.tim.cnt().read().cnt().bits(); if count1 == count2 { return count2; } } @@ -889,13 +893,13 @@ macro_rules! lptim_hal { fn clear_irq(&mut self) { // Clear autoreload match event - self.tim.icr.write(|w| w.arrmcf().set_bit()); - while self.tim.isr.read().arrm().bit_is_set() {} + self.tim.icr().write(|w| w.arrmcf().set_bit()); + while self.tim.isr().read().arrm().bit_is_set() {} } fn free(self) -> (Self::Timer, Self::Rec) { // Disable timer - self.tim.cr.write(|w| w.enable().disabled()); + self.tim.cr().write(|w| w.enable().disabled()); (self.tim, rec::$Rec { _marker: PhantomData }) } diff --git a/src/usb_hs.rs b/src/usb_hs.rs index e0aa7983..6b726a3b 100644 --- a/src/usb_hs.rs +++ b/src/usb_hs.rs @@ -129,14 +129,14 @@ macro_rules! usb_peripheral { cortex_m::interrupt::free(|_| { // USB Regulator in BYPASS mode - pwr.cr3.modify(|_, w| w.usb33den().set_bit()); + pwr.cr3().modify(|_, w| w.usb33den().set_bit()); // Enable USB peripheral - rcc.ahb1enr.modify(|_, w| w.$en().set_bit()); + rcc.ahb1enr().modify(|_, w| w.$en().set_bit()); // Reset USB peripheral - rcc.ahb1rstr.modify(|_, w| w.$rst().set_bit()); - rcc.ahb1rstr.modify(|_, w| w.$rst().clear_bit()); + rcc.ahb1rstr().modify(|_, w| w.$rst().set_bit()); + rcc.ahb1rstr().modify(|_, w| w.$rst().clear_bit()); }); } @@ -305,14 +305,14 @@ unsafe impl UsbPeripheral for USB1_ULPI { cortex_m::interrupt::free(|_| { // Enable USB peripheral - rcc.ahb1enr.modify(|_, w| w.usb1otgen().enabled()); + rcc.ahb1enr().modify(|_, w| w.usb1otgen().enabled()); // Enable ULPI Clock - rcc.ahb1enr.modify(|_, w| w.usb1ulpien().enabled()); + rcc.ahb1enr().modify(|_, w| w.usb1ulpien().enabled()); // Reset USB peripheral - rcc.ahb1rstr.modify(|_, w| w.usb1otgrst().set_bit()); - rcc.ahb1rstr.modify(|_, w| w.usb1otgrst().clear_bit()); + rcc.ahb1rstr().modify(|_, w| w.usb1otgrst().set_bit()); + rcc.ahb1rstr().modify(|_, w| w.usb1otgrst().clear_bit()); }); } diff --git a/src/xspi/mod.rs b/src/xspi/mod.rs index 31115a2f..142bfd32 100644 --- a/src/xspi/mod.rs +++ b/src/xspi/mod.rs @@ -447,13 +447,13 @@ mod common { #[cfg(any(feature = "rm0433", feature = "rm0399"))] macro_rules! fmode_reg { ($e:expr) => { - $e.rb.ccr + $e.rb.ccr() }; } #[cfg(any(feature = "rm0455", feature = "rm0468"))] macro_rules! fmode_reg { ($e:expr) => { - $e.rb.cr + $e.rb.cr() }; } @@ -487,7 +487,7 @@ mod common { /// Check if the XSPI peripheral is currently busy with a /// transaction pub fn is_busy(&self) -> Result<(), XspiError> { - if self.rb.sr.read().busy().bit_is_set() { + if self.rb.sr().read().busy().bit_is_set() { Err(XspiError::Busy) } else { Ok(()) @@ -496,7 +496,7 @@ mod common { /// Enable interrupts for the given `event` pub fn listen(&mut self, event: Event) { - self.rb.cr.modify(|_, w| match event { + self.rb.cr().modify(|_, w| match event { Event::FIFOThreashold => w.ftie().set_bit(), Event::Complete => w.tcie().set_bit(), Event::Error => w.teie().set_bit(), @@ -505,13 +505,13 @@ mod common { /// Disable interrupts for the given `event` pub fn unlisten(&mut self, event: Event) { - self.rb.cr.modify(|_, w| match event { + self.rb.cr().modify(|_, w| match event { Event::FIFOThreashold => w.ftie().clear_bit(), Event::Complete => w.tcie().clear_bit(), Event::Error => w.teie().clear_bit(), }); - let _ = self.rb.cr.read(); - let _ = self.rb.cr.read(); // Delay 2 peripheral clocks + let _ = self.rb.cr().read(); + let _ = self.rb.cr().read(); // Delay 2 peripheral clocks } pub fn kernel_clk_unwrap(clocks: &CoreClocks) -> Hertz { @@ -521,24 +521,24 @@ mod common { use stm32::rcc::cdccipr as ccipr; #[cfg(not(feature = "rm0455"))] - let ccipr = unsafe { (*stm32::RCC::ptr()).d1ccipr.read() }; + let ccipr = unsafe { (*stm32::RCC::ptr()).d1ccipr().read() }; #[cfg(feature = "rm0455")] - let ccipr = unsafe { (*stm32::RCC::ptr()).cdccipr.read() }; + let ccipr = unsafe { (*stm32::RCC::ptr()).cdccipr().read() }; match ccipr.$ccip().variant() { - ccipr::[< $ccip:upper _A >]::RccHclk3 => clocks.hclk(), - ccipr::[< $ccip:upper _A >]::Pll1Q => { + ccipr::FMCSEL::RccHclk3 => clocks.hclk(), + ccipr::FMCSEL::Pll1Q => { clocks.pll1_q_ck().expect( concat!(stringify!($peripheral), ": PLL1_Q must be enabled") ) } - ccipr::[< $ccip:upper _A >]::Pll2R + ccipr::FMCSEL::Pll2R => { clocks.pll2_r_ck().expect( concat!(stringify!($peripheral), ": PLL2_R must be enabled") ) } - ccipr::[< $ccip:upper _A >]::Per => { + ccipr::FMCSEL::Per => { clocks.per_ck().expect( concat!(stringify!($peripheral), ": PER clock must be enabled") ) @@ -577,7 +577,7 @@ mod common { /// Sets the interface to 8-bit address and data only using the /// current operational mode (number of bits). fn set_mode_address_data_only(&mut self) { - self.rb.ccr.modify(|_, w| unsafe { + self.rb.ccr().modify(|_, w| unsafe { w.imode() // NO instruction phase .bits(0) .admode() // address phase @@ -611,7 +611,7 @@ mod common { //writing to ccr will trigger the start of a transaction if there is no address or //data rm0433 pg 894, so we do it all in one go - self.rb.ccr.modify(|_, w| unsafe { + self.rb.ccr().modify(|_, w| unsafe { #[cfg(any(feature = "rm0433", feature = "rm0399"))] let w = { let ir = instruction.bits_u8().unwrap(); @@ -637,18 +637,18 @@ mod common { #[cfg(any(feature = "rm0455", feature = "rm0468"))] { - self.rb.tcr.write(|w| unsafe { w.dcyc().bits(dummy_cycles) }); - self.rb.cr.modify(|_, w| unsafe { w.fmode().bits(fmode) }); + self.rb.tcr().write(|w| unsafe { w.dcyc().bits(dummy_cycles) }); + self.rb.cr().modify(|_, w| unsafe { w.fmode().bits(fmode) }); } // Write alternate-bytes - self.rb.abr.write(|w| unsafe { + self.rb.abr().write(|w| unsafe { w.alternate().bits(alternate_bytes.bits()) }); #[cfg(any(feature = "rm0455", feature = "rm0468"))] if instruction != XspiWord::None { - self.rb.ir.write(|w| unsafe { + self.rb.ir().write(|w| unsafe { w.instruction().bits(instruction.bits()) }); } @@ -657,7 +657,7 @@ mod common { // Write the address. The transaction starts on the next write // to DATA, unless there is no DATA phase configured, in which // case it starts here. - self.rb.ar.write(|w| unsafe { w.address().bits(address.bits()) }); + self.rb.ar().write(|w| unsafe { w.address().bits(address.bits()) }); } } @@ -681,11 +681,11 @@ mod common { self.set_mode_address_data_only(); // Clear the transfer complete flag. - self.rb.fcr.write(|w| w.ctcf().set_bit()); + self.rb.fcr().write(|w| w.ctcf().set_bit()); // Write the length self.rb - .dlr + .dlr() .write(|w| unsafe { w.dl().bits(length as u32 - 1) }); // Configure the mode to indirect write. @@ -694,7 +694,7 @@ mod common { // Write the address. The transaction starts on the next write // to DATA, unless there is no DATA phase configured, in which // case it starts here. - self.rb.ar.write(|w| unsafe { w.address().bits(addr) }); + self.rb.ar().write(|w| unsafe { w.address().bits(addr) }); Ok(()) } @@ -724,14 +724,14 @@ mod common { // Write data to the FIFO in a byte-wise manner. unsafe { for byte in data { - let dr = &self.rb.dr as *const _ as *const UnsafeCell; + let dr = self.rb.dr().as_ptr() as *const UnsafeCell; ptr::write_volatile(UnsafeCell::raw_get(dr), *byte); } } // Wait for the transaction to complete - while self.rb.sr.read().tcf().bit_is_clear() {} + while self.rb.sr().read().tcf().bit_is_clear() {} // Wait for the peripheral to indicate it is no longer busy. while self.is_busy().is_err() {} @@ -762,12 +762,12 @@ mod common { self.is_busy()?; // Clear the transfer complete flag. - self.rb.fcr.write(|w| w.ctcf().set_bit()); + self.rb.fcr().write(|w| w.ctcf().set_bit()); // Data length if length > 0 { self.rb - .dlr + .dlr() .write(|w| unsafe { w.dl().bits(length as u32 - 1) }); } @@ -808,14 +808,14 @@ mod common { // Transaction starts here unsafe { for byte in data { - let dr = &self.rb.dr as *const _ as *const UnsafeCell; + let dr = self.rb.dr().as_ptr() as *const UnsafeCell; ptr::write_volatile(UnsafeCell::raw_get(dr), *byte); } } // Wait for the transaction to complete - while self.rb.sr.read().tcf().bit_is_clear() {} + while self.rb.sr().read().tcf().bit_is_clear() {} // Wait for the peripheral to indicate it is no longer busy. while self.is_busy().is_err() {} @@ -843,18 +843,18 @@ mod common { self.set_mode_address_data_only(); // Clear the transfer complete flag. - self.rb.fcr.write(|w| w.ctcf().set_bit()); + self.rb.fcr().write(|w| w.ctcf().set_bit()); // Write the length that should be read. self.rb - .dlr + .dlr() .write(|w| unsafe { w.dl().bits(length as u32 - 1) }); // Configure the mode to indirect read. fmode_reg!(self).modify(|_, w| unsafe { w.fmode().bits(0b01) }); // Write the address to force the read to start. - self.rb.ar.write(|w| unsafe { w.address().bits(addr) }); + self.rb.ar().write(|w| unsafe { w.address().bits(addr) }); Ok(()) } @@ -883,10 +883,10 @@ mod common { self.begin_read(addr as u32, dest.len())?; // Wait for the transaction to complete - while self.rb.sr.read().tcf().bit_is_clear() {} + while self.rb.sr().read().tcf().bit_is_clear() {} // Check for underflow on the FIFO. - if (self.rb.sr.read().flevel().bits() as usize) < dest.len() { + if (self.rb.sr().read().flevel().bits() as usize) < dest.len() { return Err(XspiError::Underflow); } @@ -894,7 +894,7 @@ mod common { unsafe { for location in dest { *location = - ptr::read_volatile(&self.rb.dr as *const _ as *const u8); + ptr::read_volatile(&self.rb.dr() as *const _ as *const u8); } } @@ -940,11 +940,11 @@ mod common { self.is_busy()?; // Clear the transfer complete flag. - self.rb.fcr.write(|w| w.ctcf().set_bit()); + self.rb.fcr().write(|w| w.ctcf().set_bit()); // Write the length that should be read. self.rb - .dlr + .dlr() .write(|w| unsafe { w.dl().bits(length as u32 - 1) }); // Setup extended mode. Read operations always have a data phase. @@ -987,10 +987,10 @@ mod common { alternate_bytes, dummy_cycles, dest.len())?; // Wait for the transaction to complete - while self.rb.sr.read().tcf().bit_is_clear() {} + while self.rb.sr().read().tcf().bit_is_clear() {} // Check for underflow on the FIFO. - if (self.rb.sr.read().flevel().bits() as usize) < dest.len() { + if (self.rb.sr().read().flevel().bits() as usize) < dest.len() { return Err(XspiError::Underflow); } @@ -998,7 +998,7 @@ mod common { unsafe { for location in dest { *location = - ptr::read_volatile(&self.rb.dr as *const _ as *const u8); + ptr::read_volatile(&self.rb.dr() as *const _ as *const u8); } } diff --git a/src/xspi/octospi.rs b/src/xspi/octospi.rs index dc50d0df..57ab50c4 100644 --- a/src/xspi/octospi.rs +++ b/src/xspi/octospi.rs @@ -419,16 +419,16 @@ macro_rules! octospi_impl { prec.enable(); // Disable OCTOSPI before configuring it. - regs.cr.write(|w| w.en().clear_bit()); + regs.cr().write(|w| w.en().clear_bit()); let spi_kernel_ck = Self::kernel_clk_unwrap(clocks).raw(); - while regs.sr.read().busy().bit_is_set() {} + while regs.sr().read().busy().bit_is_set() {} let config: Config = config.into(); // Clear all pending flags. - regs.fcr.write(|w| { + regs.fcr().write(|w| { w.ctof() .set_bit() .csmf() @@ -440,14 +440,14 @@ macro_rules! octospi_impl { }); // Configure the communication method for OCTOSPI. - regs.cr.write(|w| unsafe { + regs.cr().write(|w| unsafe { w.fmode() .bits(0) // indirect mode .fthres() .bits(config.fifo_threshold - 1) }); - regs.dcr1.write(|w| unsafe { + regs.dcr1().write(|w| unsafe { w.mtyp() .bits(2) // standard mode // Configure the FSIZE to maximum. It appears that even when addressing @@ -457,7 +457,7 @@ macro_rules! octospi_impl { }); // Communications configuration register - regs.ccr.write(|w| unsafe { + regs.ccr().write(|w| unsafe { w.dmode() .bits(config.modes.data.reg_value()) .admode() @@ -486,7 +486,7 @@ macro_rules! octospi_impl { // more information // // SSHIFT must not be set in DDR mode. - regs.tcr.write(|w| unsafe { + regs.tcr().write(|w| unsafe { w.sshift() .bit(config.sampling_edge == SamplingEdge::Falling) .dcyc() @@ -494,7 +494,7 @@ macro_rules! octospi_impl { }); // Enable the peripheral - regs.cr.modify(|_, w| w.en().set_bit()); + regs.cr().modify(|_, w| w.en().set_bit()); Octospi { rb: regs, @@ -514,7 +514,7 @@ macro_rules! octospi_impl { prec.enable().reset(); // Disable OCTOSPI before configuring it. - regs.cr.write(|w| w.en().clear_bit()); + regs.cr().write(|w| w.en().clear_bit()); let spi_kernel_ck = Self::kernel_clk_unwrap(clocks).raw(); @@ -532,10 +532,10 @@ macro_rules! octospi_impl { let period_ns = 1e9 * (divisor as f32) / (spi_kernel_ck as f32); let period_ns = period_ns as u32; // floor - while regs.sr.read().busy().bit_is_set() {} + while regs.sr().read().busy().bit_is_set() {} // Clear all pending flags. - regs.fcr.write(|w| { + regs.fcr().write(|w| { w.ctof() .set_bit() .csmf() @@ -547,14 +547,14 @@ macro_rules! octospi_impl { }); // Configure the communication method for OCTOSPI - regs.cr.write(|w| unsafe { + regs.cr().write(|w| unsafe { w.fmode() .bits(3) // Memory-mapped .fthres() .bits(4 - 1) // TODO? }); - regs.dcr1.write(|w| unsafe { + regs.dcr1().write(|w| unsafe { w.mtyp() .bits(4) // Hyperbus memory mode .devsize() @@ -571,7 +571,7 @@ macro_rules! octospi_impl { // the memory. These are separate dies on some parts (thus // separate transactions may be required) and has a very minimal // performance penalty if not. - regs.dcr3.write(|w| unsafe { + regs.dcr3().write(|w| unsafe { w.csbound().bits(hyperbus.size_order - 1) }); // Release nCS for refresh @@ -584,7 +584,7 @@ macro_rules! octospi_impl { .write(|w| unsafe { w.refresh().bits(refresh_cycles) }); // 8-wide, DDR - regs.ccr.write(|w| unsafe { + regs.ccr().write(|w| unsafe { w.dqse() .set_bit() // DQS enable .ddtr() @@ -599,7 +599,7 @@ macro_rules! octospi_impl { .bits(4) // 8-wide }); // 8-wide, DDR - regs.wccr.write(|w| unsafe { + regs.wccr().write(|w| unsafe { w.dqse() .set_bit() // DQS enable .ddtr() @@ -614,12 +614,12 @@ macro_rules! octospi_impl { .bits(4) // 8-wide }); // TCR - regs.tcr.write(|w| { + regs.tcr().write(|w| { w.dhqc().set_bit() // Delay hold quarter cycle }); // Hyperbus - regs.hlcr.modify(|_, w| unsafe { + regs.hlcr().modify(|_, w| unsafe { w.trwr() .bits(hyperbus.read_write_recovery) .tacc() @@ -670,18 +670,18 @@ macro_rules! octospi_impl { /// pointer to the memory pub fn init(self) -> *mut u32 { // Enable the peripheral - self.rb.cr.modify(|_, w| w.en().set_bit()); + self.rb.cr().modify(|_, w| w.en().set_bit()); // Wait for the peripheral to indicate it is no longer busy - while self.rb.sr.read().busy().bit_is_set() {} + while self.rb.sr().read().busy().bit_is_set() {} // Transition to memory-mapped mode - self.rb.cr.modify(|_, w| unsafe { + self.rb.cr().modify(|_, w| unsafe { w.fmode().bits(3) // Memory mapped }); // Wait for the peripheral to indicate it is no longer busy - while self.rb.sr.read().busy().bit_is_set() {} + while self.rb.sr().read().busy().bit_is_set() {} // Mapped to memory $memaddr as *mut u32 diff --git a/src/xspi/qspi.rs b/src/xspi/qspi.rs index 6f48b6f4..008f0b67 100644 --- a/src/xspi/qspi.rs +++ b/src/xspi/qspi.rs @@ -240,11 +240,11 @@ impl Qspi { return Err(QspiError::Busy); }; - self.rb.cr.modify(|_, w| w.dfm().clear_bit()); + self.rb.cr().modify(|_, w| w.dfm().clear_bit()); match bank { - BankSelect::One => self.rb.cr.modify(|_, w| w.fsel().clear_bit()), - BankSelect::Two => self.rb.cr.modify(|_, w| w.fsel().set_bit()), - } + BankSelect::One => self.rb.cr().modify(|_, w| w.fsel().clear_bit()), + BankSelect::Two => self.rb.cr().modify(|_, w| w.fsel().set_bit()), + }; Ok(()) } @@ -261,20 +261,20 @@ impl Qspi { prec.enable(); // Disable QUADSPI before configuring it. - regs.cr.write(|w| w.en().clear_bit()); + regs.cr().write(|w| w.en().clear_bit()); let spi_kernel_ck = Self::kernel_clk_unwrap(clocks).raw(); - while regs.sr.read().busy().bit_is_set() {} + while regs.sr().read().busy().bit_is_set() {} let config: Config = config.into(); // Configure the FSIZE to maximum. It appears that even when addressing is not used, the // flash size violation may still trigger. - regs.dcr.write(|w| unsafe { w.fsize().bits(0x1F) }); + regs.dcr().write(|w| unsafe { w.fsize().bits(0x1F) }); // Clear all pending flags. - regs.fcr.write(|w| { + regs.fcr().write(|w| { w.ctof() .set_bit() .csmf() @@ -286,7 +286,7 @@ impl Qspi { }); // Configure the communication method for QSPI. - regs.ccr.write(|w| unsafe { + regs.ccr().write(|w| unsafe { w.fmode() .bits(0) // indirect mode .dmode() @@ -317,7 +317,7 @@ impl Qspi { // more information // // SSHIFT must not be set in DDR mode. - regs.cr.write(|w| unsafe { + regs.cr().write(|w| unsafe { w.prescaler() .bits(divisor as u8) .sshift() @@ -327,13 +327,13 @@ impl Qspi { }); match bank { - Bank::One => regs.cr.modify(|_, w| w.fsel().clear_bit()), - Bank::Two => regs.cr.modify(|_, w| w.fsel().set_bit()), - Bank::Dual => regs.cr.modify(|_, w| w.dfm().set_bit()), - } + Bank::One => regs.cr().modify(|_, w| w.fsel().clear_bit()), + Bank::Two => regs.cr().modify(|_, w| w.fsel().set_bit()), + Bank::Dual => regs.cr().modify(|_, w| w.dfm().set_bit()), + }; // Enable ther peripheral - regs.cr.modify(|_, w| w.en().set_bit()); + regs.cr().modify(|_, w| w.en().set_bit()); Qspi { rb: regs, From 01a70dc5dcf8fce9eb3ed11e751f47cf12be2b19 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Fri, 6 Dec 2024 15:36:05 +0100 Subject: [PATCH 02/15] Attempt to add support for HRTIM to rcc --- src/rcc/rec.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/rcc/rec.rs b/src/rcc/rec.rs index 7b70096c..2ff49ba2 100644 --- a/src/rcc/rec.rs +++ b/src/rcc/rec.rs @@ -649,7 +649,8 @@ peripheral_reset_and_enable_control! { #[cfg(all())] APB2, "Advanced Peripheral Bus 2 (APB2) peripherals" => [ - Tim1, Tim8, Tim15, Tim16, Tim17, Hrtim + Tim1, Tim8, Tim15, Tim16, Tim17, + Hrtim [kernel clk: Hrtim HRTIM cfg "HRTIM"] ]; #[cfg(not(feature = "rm0455"))] APB2, "" => [ From cbe92132ced9acd3d1f291d34e40ea82de261c50 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Sat, 14 Dec 2024 01:39:33 +0100 Subject: [PATCH 03/15] Fix errors for stm32h747cm7 --- src/dsi.rs | 14 +++++++------- src/exti.rs | 18 +++++++++--------- src/gpio/exti.rs | 4 ++-- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/dsi.rs b/src/dsi.rs index 03df1d1b..3cfc3ec1 100644 --- a/src/dsi.rs +++ b/src/dsi.rs @@ -202,11 +202,11 @@ impl DsiHost { ); // Configure the number of active data lanes - dsi.pconfr + dsi.pconfr() .modify(|_, w| unsafe { w.nl().bits(dsi_config.lane_count as u8) }); // 0b00 - 1 lanes, 0b01 - 2 lanes // Set TX escape clock division factor - dsi.ccr + dsi.ccr() .modify(|_, w| unsafe { w.txeckdiv().bits(pll_config.eckdiv) }); // Set the bit period in high speed mode @@ -232,7 +232,7 @@ impl DsiHost { f_pix_khz, uix4 ); - dsi.wpcr0 + dsi.wpcr0() .modify(|_, w| unsafe { w.uix4().bits(uix4 as u8) }); // debug!("f_phy={}, uix4=override=8", f_phy); // dsi.wpcr0().modify(|_, w| unsafe { w.uix4().bits(8) }); @@ -395,12 +395,12 @@ impl DsiHost { }); // Tearing effect acknowledge request - dsi.cmcr().modify(|_, w| w.teare().set_bit()) + dsi.cmcr().modify(|_, w| w.teare().set_bit()); } } // Select virtual channel for the LTDC interface traffic - dsi.lvcidr + dsi.lvcidr() .modify(|_, w| unsafe { w.vcid().bits(dsi_config.channel as u8) }); // Polarity @@ -636,8 +636,8 @@ impl DsiHostCtrlIo for DsiHost { ) -> Result<(), Error> { // println!("DSI read: {:x?}", kind); if buf.len() > 2 && buf.len() <= 65_535 { - self().write(DsiWriteCommand::SetMaximumReturnPacketSize( - buf.len() as u16, + self.write(DsiWriteCommand::SetMaximumReturnPacketSize( + buf.len() as u16 ))?; } else if buf.len() > 65_535 { return Err(Error::BufferIsToBig); diff --git a/src/exti.rs b/src/exti.rs index 0cdeebbd..2f6e4b4b 100644 --- a/src/exti.rs +++ b/src/exti.rs @@ -137,31 +137,31 @@ macro_rules! reg_for_cpu { #[cfg(all(feature = "rm0399", feature = "cm7"))] macro_rules! reg_for_cpu { ($self:ident, imr1) => { - $self.c1imr1 + $self.c1imr1() }; ($self:ident, imr2) => { - $self.c1imr2 + $self.c1imr2() }; ($self:ident, imr3) => { - $self.c1imr3 + $self.c1imr3() }; ($self:ident, emr1) => { - $self.c1emr1 + $self.c1emr1() }; ($self:ident, emr2) => { - $self.c1emr2 + $self.c1emr2() }; ($self:ident, emr3) => { - $self.c1emr3 + $self.c1emr3() }; ($self:ident, pr1) => { - $self.c1pr1 + $self.c1pr1() }; ($self:ident, pr2) => { - $self.c1pr2 + $self.c1pr2() }; ($self:ident, pr3) => { - $self.c1pr3 + $self.c1pr3() }; } diff --git a/src/gpio/exti.rs b/src/gpio/exti.rs index fb64ba47..28bff5b4 100644 --- a/src/gpio/exti.rs +++ b/src/gpio/exti.rs @@ -98,7 +98,7 @@ where #[cfg(not(feature = "rm0399"))] let imr1 = &exti.cpuimr1(); #[cfg(all(feature = "rm0399", feature = "cm7"))] - let imr1 = &exti.c1imr1; + let imr1 = &exti.c1imr1(); #[cfg(all(feature = "rm0399", feature = "cm4"))] let imr1 = &exti.c2imr1; @@ -142,7 +142,7 @@ where #[cfg(not(feature = "rm0399"))] let pr1 = &(*EXTI::ptr()).cpupr1(); #[cfg(all(feature = "rm0399", feature = "cm7"))] - let pr1 = &(*EXTI::ptr()).c1pr1; + let pr1 = &(*EXTI::ptr()).c1pr1(); #[cfg(all(feature = "rm0399", feature = "cm4"))] let pr1 = &(*EXTI::ptr()).c2pr1; From d75020859416d1966cf5ab301a94a2a7d4710c10 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Sat, 14 Dec 2024 15:16:04 +0100 Subject: [PATCH 04/15] Use stm32h7-staging --- Cargo.toml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 4ca12586..5a494a13 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -32,8 +32,7 @@ embedded-hal = { version = "0.2.6", features = ["unproven"] } embedded-dma = "0.2.0" cortex-m = { version = "^0.7.7", features = ["critical-section-single-core"] } defmt = { version = ">=0.2.0,<0.4", optional = true } -#stm32h7 = { version = "^0.15.1", default-features = false } -stm32h7 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies", default-features = false } +stm32h7 = { version = "0.16.0", package = "stm32h7-staging", default-features = false } void = { version = "1.0.2", default-features = false } cast = { version = "0.3.0", default-features = false } nb = "1.0.0" From 91964c167c3924b049b4be879feafba499bdc2a3 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Mon, 16 Dec 2024 21:23:47 +0100 Subject: [PATCH 05/15] Fix some clippy warnings --- src/dma/bdma.rs | 4 ++-- src/dma/dma.rs | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/dma/bdma.rs b/src/dma/bdma.rs index f01501c3..72632772 100644 --- a/src/dma/bdma.rs +++ b/src/dma/bdma.rs @@ -265,11 +265,11 @@ trait InstanceStream { impl StreamX { unsafe fn stream() -> &'static BDMAStream { - &(*I::ptr()).ch(S as usize) + (*I::ptr()).ch(S as usize) } unsafe fn dmamux_ccr() -> &'static pac::dmamux2::CCR { let dmamux = &*I::mux_ptr(); - &dmamux.ccr(S as usize + I::DMA_MUX_STREAM_OFFSET) + dmamux.ccr(S as usize + I::DMA_MUX_STREAM_OFFSET) } } diff --git a/src/dma/dma.rs b/src/dma/dma.rs index 1cd433a9..cd65ebea 100644 --- a/src/dma/dma.rs +++ b/src/dma/dma.rs @@ -342,11 +342,11 @@ trait InstanceStream { impl StreamX { unsafe fn stream() -> &'static pac::dma1::ST { - &(*I::ptr()).st(S as usize) + (*I::ptr()).st(S as usize) } unsafe fn dmamux_ccr() -> &'static pac::dmamux1::CCR { let dmamux = &*I::mux_ptr(); - &dmamux.ccr(S as usize + I::DMA_MUX_STREAM_OFFSET) + dmamux.ccr(S as usize + I::DMA_MUX_STREAM_OFFSET) } #[inline(always)] From 3362409da9ba5a64e20ba81a406261e8a9079de0 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Mon, 16 Dec 2024 21:29:02 +0100 Subject: [PATCH 06/15] Update examples for new pac --- examples/i2c4_bdma.rs | 4 ++-- examples/rtic_low_power.rs | 4 ++-- examples/sai_dma_passthru.rs | 2 +- examples/spi-dma-rtic.rs | 6 +++--- examples/spi-dma.rs | 6 +++--- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/examples/i2c4_bdma.rs b/examples/i2c4_bdma.rs index 50e596ec..ea2cec7f 100644 --- a/examples/i2c4_bdma.rs +++ b/examples/i2c4_bdma.rs @@ -37,9 +37,9 @@ fn main() -> ! { // Run D3 / SRD domain #[cfg(not(feature = "rm0455"))] - dp.PWR.cpucr.modify(|_, w| w.run_d3().set_bit()); + dp.PWR.cpucr().modify(|_, w| w.run_d3().set_bit()); #[cfg(feature = "rm0455")] - dp.PWR.cpucr.modify(|_, w| w.run_srd().set_bit()); + dp.PWR.cpucr().modify(|_, w| w.run_srd().set_bit()); let pwr = dp.PWR.constrain(); let pwrcfg = example_power!(pwr).freeze(); diff --git a/examples/rtic_low_power.rs b/examples/rtic_low_power.rs index ef2823b4..c861a411 100644 --- a/examples/rtic_low_power.rs +++ b/examples/rtic_low_power.rs @@ -57,9 +57,9 @@ mod app { // Run D3 / SRD domain #[cfg(not(feature = "rm0455"))] - ctx.device.PWR.cpucr.modify(|_, w| w.run_d3().set_bit()); + ctx.device.PWR.cpucr().modify(|_, w| w.run_d3().set_bit()); #[cfg(feature = "rm0455")] // 7b3/7a3/7b0 parts - ctx.device.PWR.cpucr.modify(|_, w| w.run_srd().set_bit()); + ctx.device.PWR.cpucr().modify(|_, w| w.run_srd().set_bit()); let pwr = ctx.device.PWR.constrain(); let vos = example_power!(pwr).freeze(); diff --git a/examples/sai_dma_passthru.rs b/examples/sai_dma_passthru.rs index c4d2952b..94cf3880 100644 --- a/examples/sai_dma_passthru.rs +++ b/examples/sai_dma_passthru.rs @@ -194,7 +194,7 @@ fn main() -> ! { // wait until sai1's fifo starts to receive data info!("sai1 fifo waiting to receive data"); - while sai1_rb.cha().sr.read().flvl().is_empty() {} + while sai1_rb.cha().sr().read().flvl().is_empty() {} info!("audio started"); sai1.enable(); diff --git a/examples/spi-dma-rtic.rs b/examples/spi-dma-rtic.rs index 47f243e6..dceedda2 100644 --- a/examples/spi-dma-rtic.rs +++ b/examples/spi-dma-rtic.rs @@ -147,7 +147,7 @@ mod app { transfer.pause(|spi| { // At this point, the DMA transfer is done, but the data is still in the SPI output // FIFO. Wait for it to complete before disabling CS. - while spi.inner().sr.read().txc().bit_is_clear() {} + while spi.inner().sr().read().txc().bit_is_clear() {} cs.set_high(); }); }); @@ -163,8 +163,8 @@ mod app { // Enable TX DMA support, enable the SPI peripheral, and start the transaction. spi.enable_dma_tx(); - spi.inner_mut().cr1.modify(|_, w| w.spe().enabled()); - spi.inner_mut().cr1.modify(|_, w| w.cstart().started()); + spi.inner_mut().cr1().modify(|_, w| w.spe().enabled()); + spi.inner_mut().cr1().modify(|_, w| w.cstart().started()); // The transaction immediately begins as the TX FIFO is now being filled by DMA. }); diff --git a/examples/spi-dma.rs b/examples/spi-dma.rs index 40f17dea..4120a5f0 100644 --- a/examples/spi-dma.rs +++ b/examples/spi-dma.rs @@ -131,11 +131,11 @@ fn main() -> ! { // Enable the SPI by setting the SPE bit spi.inner_mut() - .cr1 + .cr1() .write(|w| w.ssi().slave_not_selected().spe().enabled()); // write CSTART to start a transaction in master mode - spi.inner_mut().cr1.modify(|_, w| w.cstart().started()); + spi.inner_mut().cr1().modify(|_, w| w.cstart().started()); }); // Wait for transfer to complete @@ -171,7 +171,7 @@ fn main() -> ! { transfer.pause(|spi| { // At this point, the DMA transfer is done, but the data is still in the // SPI output FIFO. Wait for it to complete - while spi.inner().sr.read().txc().bit_is_clear() {} + while spi.inner().sr().read().txc().bit_is_clear() {} }); info!("Chunked transfer complete!"); From 32d9305dabfeeadacccfbdb151ba2c736f1bc239 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Mon, 16 Dec 2024 21:29:27 +0100 Subject: [PATCH 07/15] Enable feature critical-section --- Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Cargo.toml b/Cargo.toml index 5a494a13..0374ed9a 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -32,7 +32,7 @@ embedded-hal = { version = "0.2.6", features = ["unproven"] } embedded-dma = "0.2.0" cortex-m = { version = "^0.7.7", features = ["critical-section-single-core"] } defmt = { version = ">=0.2.0,<0.4", optional = true } -stm32h7 = { version = "0.16.0", package = "stm32h7-staging", default-features = false } +stm32h7 = { version = "0.16.0", package = "stm32h7-staging", features = ["critical-section"], default-features = false } void = { version = "1.0.2", default-features = false } cast = { version = "0.3.0", default-features = false } nb = "1.0.0" From b939a69337f2ad416c922797af0c8a0596d13e99 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Mon, 16 Dec 2024 21:56:40 +0100 Subject: [PATCH 08/15] Fix errors for rm455 --- src/rcc/backup.rs | 6 +++--- src/rcc/mod.rs | 10 +++++----- src/rcc/rec.rs | 16 +++++++--------- src/rcc/reset_reason.rs | 16 ++++++++-------- src/xspi/octospi.rs | 6 +++--- 5 files changed, 26 insertions(+), 28 deletions(-) diff --git a/src/rcc/backup.rs b/src/rcc/backup.rs index 221569c0..2b6c4ec1 100644 --- a/src/rcc/backup.rs +++ b/src/rcc/backup.rs @@ -96,7 +96,7 @@ mod rtc { fn reset(self) -> Self { // unsafe: Owned exclusive access to this bitfield interrupt::free(|_| { - let bdcr = unsafe { &(*RCC::ptr()).bdcr() }; + let bdcr = unsafe { (*RCC::ptr()).bdcr() }; #[cfg(not(feature = "rm0455"))] bdcr.modify(|_, w| w.bdrst().set_bit()); @@ -104,9 +104,9 @@ mod rtc { bdcr.modify(|_, w| w.bdrst().clear_bit()); #[cfg(feature = "rm0455")] - bdcr().modify(|_, w| w.vswrst().set_bit()); + bdcr.modify(|_, w| w.vswrst().set_bit()); #[cfg(feature = "rm0455")] - bdcr().modify(|_, w| w.vswrst().set_bit()); + bdcr.modify(|_, w| w.vswrst().set_bit()); }); self } diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index 38fc9a16..a4b8d542 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -1016,16 +1016,16 @@ impl Rcc { let cdcfgr1 = rcc.cdcfgr1().read(); debug!( "CDCFGR1 register: CDCPRE={:?} HPRE={:?} CDPPRE={:?}", - cdcfgr1.cdcpre().variant().unwrap(), - cdcfgr1.hpre().variant().unwrap(), - cdcfgr1.cdppre().variant().unwrap(), + cdcfgr1.cdcpre().variant(), + cdcfgr1.hpre().variant(), + cdcfgr1.cdppre().variant(), ); let cdcfgr2 = rcc.cdcfgr2().read(); debug!( "CDCFGR2 register: CDPPRE1={:?} CDPPRE1={:?}", - cdcfgr2.cdppre1().variant().unwrap(), - cdcfgr2.cdppre2().variant().unwrap(), + cdcfgr2.cdppre1().variant(), + cdcfgr2.cdppre2().variant(), ); let srdcfgr = rcc.srdcfgr().read(); diff --git a/src/rcc/rec.rs b/src/rcc/rec.rs index 2ff49ba2..db5ff099 100644 --- a/src/rcc/rec.rs +++ b/src/rcc/rec.rs @@ -507,7 +507,7 @@ peripheral_reset_and_enable_control! { AHB1, "" => [ Crc, Usb1Otg [group clk: Usb USB cdccip2 "USB"], - Adc12 [group clk: Adc(Variant) ADC12 srdccip "ADC"] + Adc12 [group clk: Adc(Variant) ADC srdccip "ADC"] ]; @@ -649,8 +649,7 @@ peripheral_reset_and_enable_control! { #[cfg(all())] APB2, "Advanced Peripheral Bus 2 (APB2) peripherals" => [ - Tim1, Tim8, Tim15, Tim16, Tim17, - Hrtim [kernel clk: Hrtim HRTIM cfg "HRTIM"] + Tim1, Tim8, Tim15, Tim16, Tim17 ]; #[cfg(not(feature = "rm0455"))] APB2, "" => [ @@ -660,7 +659,8 @@ peripheral_reset_and_enable_control! { Spi1 [group clk: Spi123(Variant) SAI1 d2ccip1 "SPI1/2/3"], Spi4 [group clk: Spi45(Variant) SPI45 d2ccip1 "SPI4/5"], - Spi5 [group clk: Spi45] + Spi5 [group clk: Spi45], + Hrtim [kernel clk: Hrtim HRTIM cfg "HRTIM"] ]; #[cfg(any(feature = "rm0433", feature = "rm0399"))] APB2, "" => [ @@ -675,16 +675,16 @@ peripheral_reset_and_enable_control! { Dfsdm1 [kernel clk: Dfsdm1 DFSDM1 cdccip1 "DFSDM1"], Sai1 [kernel clk: Sai1(Variant) SAI1 cdccip1 "SAI1"], - Sai2 [kernel clk_a: Sai2A(Variant) SAI1 cdccip1 + Sai2 [kernel clk_a: Sai2A(Variant) SAI2A cdccip1 "Sub-Block A of SAI2"] - [kernel clk_b: Sai2B(Variant) SAI1 cdccip1 + [kernel clk_b: Sai2B(Variant) SAI2A cdccip1 "Sub-Block B of SAI2"], Spi1 [group clk: Spi123(Variant) SAI1 cdccip1 "SPI1/2/3"], Spi4 [group clk: Spi45(Variant) SPI45 cdccip1 "SPI4/5"], Spi5 [group clk: Spi45], - Usart1 [group clk: Usart16910(Variant) USART16 cdccip2 "USART1/6/9/10"], + Usart1 [group clk: Usart16910(Variant) USART16910 cdccip2 "USART1/6/9/10"], Usart6 [group clk: Usart16910], Uart9 [group clk: Usart16910], Usart10 [group clk: Usart16910] @@ -697,14 +697,12 @@ peripheral_reset_and_enable_control! { Usart10 [group clk: Usart16910] ]; - #[cfg(all())] APB3, "Advanced Peripheral Bus 3 (APB3) peripherals" => [ Ltdc [fixed clk: "pll3_r_ck"], #[cfg(any(feature = "rm0399"))] Dsi ]; - #[cfg(all())] APB4, "Advanced Peripheral Bus 4 (APB4) peripherals" => [ (Auto) Vref, diff --git a/src/rcc/reset_reason.rs b/src/rcc/reset_reason.rs index aa4c7b3d..3556e1e0 100644 --- a/src/rcc/reset_reason.rs +++ b/src/rcc/reset_reason.rs @@ -65,14 +65,14 @@ pub fn get_reset_reason(rcc: &mut crate::stm32::RCC) -> ResetReason { #[cfg(feature = "rm0455")] // See RM0455 Rev 6 Section 8.4.4 Reset source identification match ( - reset_reason.lpwrrstf().is_reset_occourred(), - reset_reason.wwdgrstf().is_reset_occourred(), - reset_reason.iwdgrstf().is_reset_occourred(), - reset_reason.sftrstf().is_reset_occourred(), - reset_reason.porrstf().is_reset_occourred(), - reset_reason.pinrstf().is_reset_occourred(), - reset_reason.borrstf().is_reset_occourred(), - reset_reason.cdrstf().is_reset_occourred(), + reset_reason.lpwrrstf().is_reset_occurred(), + reset_reason.wwdgrstf().is_reset_occurred(), + reset_reason.iwdgrstf().is_reset_occurred(), + reset_reason.sftrstf().is_reset_occurred(), + reset_reason.porrstf().is_reset_occurred(), + reset_reason.pinrstf().is_reset_occurred(), + reset_reason.borrstf().is_reset_occurred(), + reset_reason.cdrstf().is_reset_occurred(), ) { (false, false, false, false, true, true, true, true) => { ResetReason::PowerOnReset diff --git a/src/xspi/octospi.rs b/src/xspi/octospi.rs index 57ab50c4..b5d2c0e3 100644 --- a/src/xspi/octospi.rs +++ b/src/xspi/octospi.rs @@ -475,7 +475,7 @@ macro_rules! octospi_impl { divisor @ 1..=256 => divisor - 1, _ => panic!("Invalid OCTOSPI frequency requested"), }; - regs.dcr2 + regs.dcr2() .write(|w| unsafe { w.prescaler().bits(divisor as u8) }); // Note that we default to setting SSHIFT (sampling on the falling @@ -564,7 +564,7 @@ macro_rules! octospi_impl { }); // Prescaler - regs.dcr2 + regs.dcr2() .write(|w| unsafe { w.prescaler().bits(divisor - 1) }); // CS boundary. We actually use this feature to ensure the // transcation is re-started when crossing between each half of @@ -580,7 +580,7 @@ macro_rules! octospi_impl { (1000 * hyperbus.refresh_interval.ticks() as u32); (interval_ns + period_ns - 1) / period_ns }; - regs.dcr4 + regs.dcr4() .write(|w| unsafe { w.refresh().bits(refresh_cycles) }); // 8-wide, DDR From 6a8f1111dd170340bff9a45cd4e65a78a199d7b0 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Mon, 16 Dec 2024 22:08:04 +0100 Subject: [PATCH 09/15] Move hrtim behind rm0433 and rm0399 --- src/rcc/rec.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/rcc/rec.rs b/src/rcc/rec.rs index db5ff099..2b5ebf9b 100644 --- a/src/rcc/rec.rs +++ b/src/rcc/rec.rs @@ -659,8 +659,7 @@ peripheral_reset_and_enable_control! { Spi1 [group clk: Spi123(Variant) SAI1 d2ccip1 "SPI1/2/3"], Spi4 [group clk: Spi45(Variant) SPI45 d2ccip1 "SPI4/5"], - Spi5 [group clk: Spi45], - Hrtim [kernel clk: Hrtim HRTIM cfg "HRTIM"] + Spi5 [group clk: Spi45] ]; #[cfg(any(feature = "rm0433", feature = "rm0399"))] APB2, "" => [ @@ -668,7 +667,8 @@ peripheral_reset_and_enable_control! { Sai3 [group clk: Sai23], Usart1 [group clk: Usart16(Variant) USART16 d2ccip2 "USART1/6"], - Usart6 [group clk: Usart16] + Usart6 [group clk: Usart16], + Hrtim [kernel clk: Hrtim HRTIM cfg "HRTIM"] ]; #[cfg(feature = "rm0455")] APB2, "" => [ From dbe27a0afea26151e199d92407a3bdf6de424d3b Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Mon, 16 Dec 2024 22:21:51 +0100 Subject: [PATCH 10/15] Update examples for new pac --- examples/display-dsi-command-teartest-stm32h747i-disco.rs | 4 ++-- examples/display-dsi-video-stm32h747i-disco.rs | 4 ++-- examples/display-dsi-video-teartest-stm32h747i-disco.rs | 4 ++-- examples/ethernet-rtic-stm32h747i-disco.rs | 2 +- examples/ethernet-stm32h747i-disco.rs | 2 +- examples/i2c4_bdma.rs | 4 +++- examples/rtic_low_power.rs | 4 +++- 7 files changed, 14 insertions(+), 10 deletions(-) diff --git a/examples/display-dsi-command-teartest-stm32h747i-disco.rs b/examples/display-dsi-command-teartest-stm32h747i-disco.rs index e14907da..9ce9a39d 100644 --- a/examples/display-dsi-command-teartest-stm32h747i-disco.rs +++ b/examples/display-dsi-command-teartest-stm32h747i-disco.rs @@ -34,7 +34,7 @@ use cortex_m_rt::{entry, exception}; use crate::utilities_display::display_target::BufferedDisplay; use stm32h7xx_hal::gpio::Speed; use stm32h7xx_hal::ltdc; -use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL_A; +use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL; use stm32h7xx_hal::{prelude::*, stm32}; use embedded_display_controller::DisplayController; @@ -186,7 +186,7 @@ fn main() -> ! { gpioh.ph5 // SDNWE }; - let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL_A::Pll2R); + let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL::Pll2R); // TODO: incorrect for disco! let sdram_chip = stm32_fmc::devices::is42s32800g_6::Is42s32800g {}; let mut sdram = dp.FMC.sdram( diff --git a/examples/display-dsi-video-stm32h747i-disco.rs b/examples/display-dsi-video-stm32h747i-disco.rs index e27fc9b4..829d6e0b 100644 --- a/examples/display-dsi-video-stm32h747i-disco.rs +++ b/examples/display-dsi-video-stm32h747i-disco.rs @@ -29,7 +29,7 @@ use cortex_m_rt::{entry, exception}; use crate::utilities_display::display_target::BufferedDisplay; use stm32h7xx_hal::gpio::Speed; use stm32h7xx_hal::ltdc; -use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL_A; +use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL; use stm32h7xx_hal::{prelude::*, rtc, stm32}; use embedded_display_controller::DisplayController; @@ -188,7 +188,7 @@ fn main() -> ! { gpioh.ph5 // SDNWE }; - let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL_A::Pll2R); + let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL::Pll2R); // TODO: incorrect for disco! let sdram_chip = stm32_fmc::devices::is42s32800g_6::Is42s32800g {}; let mut sdram = dp.FMC.sdram( diff --git a/examples/display-dsi-video-teartest-stm32h747i-disco.rs b/examples/display-dsi-video-teartest-stm32h747i-disco.rs index 4b95ac8c..00c0da00 100644 --- a/examples/display-dsi-video-teartest-stm32h747i-disco.rs +++ b/examples/display-dsi-video-teartest-stm32h747i-disco.rs @@ -33,7 +33,7 @@ use cortex_m_rt::{entry, exception}; use crate::utilities_display::display_target::BufferedDisplay; use stm32h7xx_hal::gpio::Speed; use stm32h7xx_hal::ltdc; -use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL_A; +use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL; use stm32h7xx_hal::{prelude::*, stm32}; use embedded_display_controller::DisplayController; @@ -185,7 +185,7 @@ fn main() -> ! { gpioh.ph5 // SDNWE }; - let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL_A::Pll2R); + let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL::Pll2R); // TODO: incorrect for disco! let sdram_chip = stm32_fmc::devices::is42s32800g_6::Is42s32800g {}; let mut sdram = dp.FMC.sdram( diff --git a/examples/ethernet-rtic-stm32h747i-disco.rs b/examples/ethernet-rtic-stm32h747i-disco.rs index 43cdc6a3..47c91cdb 100644 --- a/examples/ethernet-rtic-stm32h747i-disco.rs +++ b/examples/ethernet-rtic-stm32h747i-disco.rs @@ -127,7 +127,7 @@ mod app { let pwrcfg = pwr.smps().freeze(); // Link the SRAM3 power state to CPU1 - ctx.device.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit()); + ctx.device.RCC.ahb2enr().modify(|_, w| w.sram3en().set_bit()); // Initialise clocks... let rcc = ctx.device.RCC.constrain(); diff --git a/examples/ethernet-stm32h747i-disco.rs b/examples/ethernet-stm32h747i-disco.rs index 7fd027bc..9b4b1968 100644 --- a/examples/ethernet-stm32h747i-disco.rs +++ b/examples/ethernet-stm32h747i-disco.rs @@ -46,7 +46,7 @@ fn main() -> ! { // Link the SRAM3 power state to CPU1 info!("Setup RCC... "); - dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit()); + dp.RCC.ahb2enr().modify(|_, w| w.sram3en().set_bit()); // Initialise clocks... let rcc = dp.RCC.constrain(); diff --git a/examples/i2c4_bdma.rs b/examples/i2c4_bdma.rs index ea2cec7f..ba77fc88 100644 --- a/examples/i2c4_bdma.rs +++ b/examples/i2c4_bdma.rs @@ -36,8 +36,10 @@ fn main() -> ! { let dp = pac::Peripherals::take().expect("Cannot take peripherals"); // Run D3 / SRD domain - #[cfg(not(feature = "rm0455"))] + #[cfg(not(any(feature = "rm0455", feature = "rm0399")))] dp.PWR.cpucr().modify(|_, w| w.run_d3().set_bit()); + #[cfg(feature = "rm0399")] + dp.PWR.cpu1cr().modify(|_, w| w.run_d3().set_bit()); #[cfg(feature = "rm0455")] dp.PWR.cpucr().modify(|_, w| w.run_srd().set_bit()); diff --git a/examples/rtic_low_power.rs b/examples/rtic_low_power.rs index c861a411..46a09cbf 100644 --- a/examples/rtic_low_power.rs +++ b/examples/rtic_low_power.rs @@ -56,8 +56,10 @@ mod app { let mut syscfg = ctx.device.SYSCFG; // Run D3 / SRD domain - #[cfg(not(feature = "rm0455"))] + #[cfg(not(any(feature = "rm0455", feature = "rm0399")))] ctx.device.PWR.cpucr().modify(|_, w| w.run_d3().set_bit()); + #[cfg(feature = "rm0399")] + ctx.device.PWR.cpu1cr().modify(|_, w| w.run_d3().set_bit()); #[cfg(feature = "rm0455")] // 7b3/7a3/7b0 parts ctx.device.PWR.cpucr().modify(|_, w| w.run_srd().set_bit()); From 5bbd4090b4282f2a136d9966b805d3d0c95203e8 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Mon, 16 Dec 2024 22:22:40 +0100 Subject: [PATCH 11/15] fmt --- examples/ethernet-rtic-stm32h747i-disco.rs | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/examples/ethernet-rtic-stm32h747i-disco.rs b/examples/ethernet-rtic-stm32h747i-disco.rs index 47c91cdb..eee7d75c 100644 --- a/examples/ethernet-rtic-stm32h747i-disco.rs +++ b/examples/ethernet-rtic-stm32h747i-disco.rs @@ -127,7 +127,10 @@ mod app { let pwrcfg = pwr.smps().freeze(); // Link the SRAM3 power state to CPU1 - ctx.device.RCC.ahb2enr().modify(|_, w| w.sram3en().set_bit()); + ctx.device + .RCC + .ahb2enr() + .modify(|_, w| w.sram3en().set_bit()); // Initialise clocks... let rcc = ctx.device.RCC.constrain(); From 18d6873f14ea4de0cd070d75894c471ce840a766 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Mon, 16 Dec 2024 22:28:20 +0100 Subject: [PATCH 12/15] Update examples for new pac --- examples/ethernet-nucleo-h743zi2.rs | 2 +- examples/qspi_mdma.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/ethernet-nucleo-h743zi2.rs b/examples/ethernet-nucleo-h743zi2.rs index 787ca35c..a4915b98 100644 --- a/examples/ethernet-nucleo-h743zi2.rs +++ b/examples/ethernet-nucleo-h743zi2.rs @@ -69,7 +69,7 @@ fn main() -> ! { // Initialise SRAM3 info!("Setup RCC... "); - dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit()); + dp.RCC.ahb2enr().modify(|_, w| w.sram3en().set_bit()); // Initialise clocks... let rcc = dp.RCC.constrain(); diff --git a/examples/qspi_mdma.rs b/examples/qspi_mdma.rs index a7dd6dd4..79cad15d 100644 --- a/examples/qspi_mdma.rs +++ b/examples/qspi_mdma.rs @@ -71,7 +71,7 @@ fn main() -> ! { qspi.configure_mode(QspiMode::FourBit).unwrap(); // Disable address phase qspi.inner_mut() - .ccr + .ccr() .modify(|_, w| unsafe { w.admode().bits(0) }); // Source buffer in TCM From cf5a479a322fe16bbef0f49f4311ded1e7f2b2d3 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Mon, 16 Dec 2024 22:59:02 +0100 Subject: [PATCH 13/15] Update test for new pac --- src/rcc/pll.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/rcc/pll.rs b/src/rcc/pll.rs index 028e7c79..de6f651e 100644 --- a/src/rcc/pll.rs +++ b/src/rcc/pll.rs @@ -439,6 +439,10 @@ mod tests { pllcfgr: MockPllCfgr {}, } } + + pub fn pllcfgr(&self) -> &MockPllCfgr { + &self.pllcfgr + } } #[test] From d230335b0eaf7fd7c350302811a91d3627f5fdec Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Tue, 17 Dec 2024 22:06:51 +0100 Subject: [PATCH 14/15] Use set instead of bits --- examples/qspi_mdma.rs | 4 +-- src/adc.rs | 64 ++++++++++++++++-------------------- src/crc.rs | 29 +++++----------- src/dma/bdma.rs | 4 +-- src/dma/dma.rs | 10 +++--- src/gpio.rs | 24 +++++++------- src/gpio/convert.rs | 62 +++++++++++++++------------------- src/gpio/erased.rs | 12 +++---- src/gpio/partially_erased.rs | 10 +++--- src/i2c.rs | 47 +++++++++++--------------- src/independent_watchdog.rs | 23 +++++-------- src/ltdc.rs | 47 ++++++++++++-------------- src/pwm.rs | 23 +++++-------- src/qei.rs | 3 +- src/rcc/mod.rs | 35 ++++++++++---------- src/rcc/pll.rs | 14 +++----- src/rtc.rs | 46 ++++++++++++-------------- src/sai/i2s.rs | 2 +- src/serial.rs | 3 +- src/spi.rs | 30 +++++++---------- src/system_watchdog.rs | 25 ++++---------- src/timer.rs | 14 ++++---- src/xspi/mod.rs | 6 ++-- src/xspi/qspi.rs | 18 +++++----- 24 files changed, 230 insertions(+), 325 deletions(-) diff --git a/examples/qspi_mdma.rs b/examples/qspi_mdma.rs index 79cad15d..42773f92 100644 --- a/examples/qspi_mdma.rs +++ b/examples/qspi_mdma.rs @@ -70,9 +70,7 @@ fn main() -> ! { ); qspi.configure_mode(QspiMode::FourBit).unwrap(); // Disable address phase - qspi.inner_mut() - .ccr() - .modify(|_, w| unsafe { w.admode().bits(0) }); + qspi.inner_mut().ccr().modify(|_, w| w.admode().set(0)); // Source buffer in TCM let mut source_buffer: [u8; 80] = [0x4A; 80]; diff --git a/src/adc.rs b/src/adc.rs index 09026474..e75861e5 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -767,33 +767,31 @@ macro_rules! adc_hal { fn set_chan_smp(&mut self, chan: u8) { let t = self.get_sample_time().into(); if chan <= 9 { - //NOTE(unsafe) Only valid bit patterns written - self.rb.smpr1().modify(|_, w| unsafe { match chan { - 0 => w.smp0().bits(t), - 1 => w.smp1().bits(t), - 2 => w.smp2().bits(t), - 3 => w.smp3().bits(t), - 4 => w.smp4().bits(t), - 5 => w.smp5().bits(t), - 6 => w.smp6().bits(t), - 7 => w.smp7().bits(t), - 8 => w.smp8().bits(t), - 9 => w.smp9().bits(t), + self.rb.smpr1().modify(|_, w| { match chan { + 0 => w.smp0().set(t), + 1 => w.smp1().set(t), + 2 => w.smp2().set(t), + 3 => w.smp3().set(t), + 4 => w.smp4().set(t), + 5 => w.smp5().set(t), + 6 => w.smp6().set(t), + 7 => w.smp7().set(t), + 8 => w.smp8().set(t), + 9 => w.smp9().set(t), _ => unreachable!(), }}); } else { - //NOTE(unsafe) Only valid bit patterns written - self.rb.smpr2().modify(|_, w| unsafe { match chan { - 10 => w.smp10().bits(t), - 11 => w.smp11().bits(t), - 12 => w.smp12().bits(t), - 13 => w.smp13().bits(t), - 14 => w.smp14().bits(t), - 15 => w.smp15().bits(t), - 16 => w.smp16().bits(t), - 17 => w.smp17().bits(t), - 18 => w.smp18().bits(t), - 19 => w.smp19().bits(t), + self.rb.smpr2().modify(|_, w| { match chan { + 10 => w.smp10().set(t), + 11 => w.smp11().set(t), + 12 => w.smp12().set(t), + 13 => w.smp13().set(t), + 14 => w.smp14().set(t), + 15 => w.smp15().set(t), + 16 => w.smp16().set(t), + 17 => w.smp17().set(t), + 18 => w.smp18().set(t), + 19 => w.smp19().set(t), _ => unreachable!(), }}); } @@ -805,16 +803,14 @@ macro_rules! adc_hal { // Set LSHIFT[3:0] //NOTE(unsafe) Only valid bit patterns written - unsafe { - self.rb.cfgr2().modify(|_, w| w.lshift().bits(self.get_lshift().value())); - } + self.rb.cfgr2().modify(|_, w| w.lshift().set(self.get_lshift().value())); // Select channel (with preselection, refer to RM0433 Rev 7 - Chapter 25.4.12) self.rb.pcsel().modify(|r, w| unsafe { w.pcsel().bits(r.pcsel().bits() | (1 << chan)) }); self.set_chan_smp(chan); self.rb.sqr1().modify(|_, w| unsafe { w.sq1().bits(chan) - .l().bits(0) + .l().set(0) }); self.current_channel = Some(chan); @@ -854,14 +850,10 @@ macro_rules! adc_hal { // Set resolution self.rb.cfgr().modify(|_, w| unsafe { w.res().bits(self.get_resolution().into()) }); - - //NOTE(unsafe) Only valid bit patterns written - unsafe { - self.rb.cfgr().modify(|_, w| w.dmngt().bits(match mode { - AdcDmaMode::OneShot => 0b01, - AdcDmaMode::Circular => 0b11, - })); - } + self.rb.cfgr().modify(|_, w| w.dmngt().set(match mode { + AdcDmaMode::OneShot => 0b01, + AdcDmaMode::Circular => 0b11, + })); // Set continuous mode self.rb.cfgr().modify(|_, w| w.cont().set_bit().discen().clear_bit() ); diff --git a/src/crc.rs b/src/crc.rs index bf688600..b6253235 100644 --- a/src/crc.rs +++ b/src/crc.rs @@ -38,24 +38,18 @@ impl Crc { // manual says unit must be reset (or DR read) before change of polynomial // (technically only in case of ongoing calculation, but DR is buffered) //NOTE(unsafe) Only valid bit patterns are written - self.reg.cr().modify(|_, w| unsafe { + self.reg.cr().modify(|_, w| { w.polysize() - .bits(config.poly.polysize()) + .set(config.poly.polysize()) .rev_in() - .bits(config.get_reverse_input()) + .set(config.get_reverse_input()) .rev_out() .bit(config.reverse_output) .reset() .set_bit() }); - //NOTE(unsafe) All bit patterns are valid - self.reg - .pol() - .write(|w| unsafe { w.pol().bits(config.poly.pol()) }); - //NOTE(unsafe) All bit patterns are valid - self.reg - .init() - .write(|w| unsafe { w.init().bits(config.initial) }); + self.reg.pol().write(|w| w.pol().set(config.poly.pol())); + self.reg.init().write(|w| w.init().set(config.initial)); // writing to INIT sets DR to its value } @@ -67,23 +61,18 @@ impl Crc { let mut words = data.chunks_exact(4); for word in words.by_ref() { let word = u32::from_be_bytes(word.try_into().unwrap()); - //NOTE(unsafe) All bit patterns are valid - self.reg.dr().write(|w| unsafe { w.dr().bits(word) }); + self.reg.dr().write(|w| w.dr().set(word)); } // there will be at most 3 bytes remaining, so 1 half-word and 1 byte let mut half_word = words.remainder().chunks_exact(2); if let Some(half_word) = half_word.next() { let half_word = u16::from_be_bytes(half_word.try_into().unwrap()); - //NOTE(unsafe) All bit patterns are valid - self.reg - .dr16() - .write(|w| unsafe { w.dr16().bits(half_word) }); + self.reg.dr16().write(|w| w.dr16().set(half_word)); } if let Some(byte) = half_word.remainder().first() { - //NOTE(unsafe) All bit patterns are valid - self.reg.dr8().write(|w| unsafe { w.dr8().bits(*byte) }); + self.reg.dr8().write(|w| w.dr8().set(*byte)); } } @@ -136,7 +125,7 @@ impl Crc { /// The IDR is not involved with CRC calculation. pub fn set_idr(&mut self, value: u32) { //NOTE(unsafe) All bit patterns are valid - self.reg.idr().write(|w| unsafe { w.idr().bits(value) }); + self.reg.idr().write(|w| w.idr().set(value)); } /// Get the current value of the independent data register. diff --git a/src/dma/bdma.rs b/src/dma/bdma.rs index 72632772..695da7c3 100644 --- a/src/dma/bdma.rs +++ b/src/dma/bdma.rs @@ -357,7 +357,7 @@ where unsafe { Self::stream() .cr() - .modify(|_, w| w.pl().bits(priority.bits())); + .modify(|_, w| w.pl().set(priority.bits())); } } @@ -466,7 +466,7 @@ where //NOTE(unsafe) We only access the registers that belongs to the StreamX //NOTE(unsafe) All bit patterns are valid for ndt unsafe { - Self::stream().ndtr().write(|w| w.ndt().bits(value)); + Self::stream().ndtr().write(|w| w.ndt().set(value)); } } #[inline(always)] diff --git a/src/dma/dma.rs b/src/dma/dma.rs index cd65ebea..2140ca9c 100644 --- a/src/dma/dma.rs +++ b/src/dma/dma.rs @@ -356,7 +356,7 @@ impl StreamX { unsafe { Self::stream() .fcr() - .modify(|_, w| w.fth().bits(fifo_threshold.bits())); + .modify(|_, w| w.fth().set(fifo_threshold.bits())); } } @@ -376,7 +376,7 @@ impl StreamX { unsafe { Self::stream() .cr() - .modify(|_, w| w.mburst().bits(memory_burst.bits())); + .modify(|_, w| w.mburst().set(memory_burst.bits())); } } @@ -387,7 +387,7 @@ impl StreamX { unsafe { Self::stream() .cr() - .modify(|_, w| w.pburst().bits(peripheral_burst.bits())); + .modify(|_, w| w.pburst().set(peripheral_burst.bits())); } } @@ -518,7 +518,7 @@ where unsafe { Self::stream() .cr() - .modify(|_, w| w.pl().bits(priority.bits())); + .modify(|_, w| w.pl().set(priority.bits())); } } @@ -645,7 +645,7 @@ where //NOTE(unsafe) We only access the registers that belongs to the StreamX //NOTE(unsafe) All bit pattern for ndt are valid unsafe { - Self::stream().ndtr().write(|w| w.ndt().bits(value)); + Self::stream().ndtr().write(|w| w.ndt().set(value)); } } diff --git a/src/gpio.rs b/src/gpio.rs index 4ae7a173..f47620f2 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -317,11 +317,9 @@ where let offset = 2 * { N }; unsafe { - (*Gpio::

::ptr()).ospeedr().modify(|r, w| { - w.bits( - (r.bits() & !(0b11 << offset)) | ((speed as u32) << offset), - ) - }); + (*Gpio::

::ptr()) + .ospeedr() + .modify(|_, w| w.ospeedr(offset).set(speed as u8)); } } @@ -339,11 +337,11 @@ where /// Set the internal pull-up and pull-down resistor pub fn set_internal_resistor(&mut self, resistor: Pull) { let offset = 2 * { N }; - let value = resistor as u32; + let value = resistor as u8; unsafe { - (*Gpio::

::ptr()).pupdr().modify(|r, w| { - w.bits((r.bits() & !(0b11 << offset)) | (value << offset)) - }); + (*Gpio::

::ptr()) + .pupdr() + .modify(|_, w| w.pupdr(offset).bits(value)); } } @@ -428,25 +426,25 @@ impl Pin { fn _set_high(&mut self) { // NOTE(unsafe) atomic write to a stateless register unsafe { - (*Gpio::

::ptr()).bsrr().write(|w| w.bits(1 << N)); + (*Gpio::

::ptr()).bsrr().write(|w| w.bs(N).set_bit()); } } #[inline(always)] fn _set_low(&mut self) { // NOTE(unsafe) atomic write to a stateless register unsafe { - (*Gpio::

::ptr()).bsrr().write(|w| w.bits(1 << (16 + N))); + (*Gpio::

::ptr()).bsrr().write(|w| w.br(N).set_bit()); } } #[inline(always)] fn _is_set_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*Gpio::

::ptr()).odr().read().bits() & (1 << N) == 0 } + unsafe { (*Gpio::

::ptr()).odr().read().odr(N).is_low() } } #[inline(always)] fn _is_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*Gpio::

::ptr()).idr().read().bits() & (1 << N) == 0 } + unsafe { (*Gpio::

::ptr()).idr().read().idr(N).is_low() } } } diff --git a/src/gpio/convert.rs b/src/gpio/convert.rs index ca1ed9c6..56885959 100644 --- a/src/gpio/convert.rs +++ b/src/gpio/convert.rs @@ -259,9 +259,9 @@ impl Pin { unsafe { if MODE::OTYPER != M::OTYPER { if let Some(otyper) = M::OTYPER { - (*Gpio::

::ptr()).otyper().modify(|r, w| { - w.bits(r.bits() & !(0b1 << N) | (otyper << N)) - }); + (*Gpio::

::ptr()) + .otyper() + .modify(|_, w| w.ot(N).bit(otyper)); } } @@ -269,30 +269,22 @@ impl Pin { if let Some(afr) = M::AFR { if N < 8 { let offset2 = 4 * { N }; - (*Gpio::

::ptr()).afrl().modify(|r, w| { - w.bits( - (r.bits() & !(0b1111 << offset2)) - | (afr << offset2), - ) - }); + (*Gpio::

::ptr()) + .afrl() + .modify(|_, w| w.afr(offset2).set(afr)); } else { let offset2 = 4 * { N - 8 }; - (*Gpio::

::ptr()).afrh().modify(|r, w| { - w.bits( - (r.bits() & !(0b1111 << offset2)) - | (afr << offset2), - ) - }); + (*Gpio::

::ptr()) + .afrh() + .modify(|_, w| w.afr(offset2).set(afr)); } } } if MODE::MODER != M::MODER { - (*Gpio::

::ptr()).moder().modify(|r, w| { - w.bits( - (r.bits() & !(0b11 << offset)) | (M::MODER << offset), - ) - }); + (*Gpio::

::ptr()) + .moder() + .modify(|_, w| w.moder(offset).set(M::MODER)); } } } @@ -435,43 +427,43 @@ pub trait PinMode: crate::Sealed { // They are not part of public API. #[doc(hidden)] - const MODER: u32 = u32::MAX; + const MODER: u8 = u8::MAX; #[doc(hidden)] - const OTYPER: Option = None; + const OTYPER: Option = None; #[doc(hidden)] - const AFR: Option = None; + const AFR: Option = None; } impl crate::Sealed for Input {} impl PinMode for Input { - const MODER: u32 = 0b00; + const MODER: u8 = 0b00; } impl crate::Sealed for Analog {} impl PinMode for Analog { - const MODER: u32 = 0b11; + const MODER: u8 = 0b11; } impl crate::Sealed for Output {} impl PinMode for Output { - const MODER: u32 = 0b01; - const OTYPER: Option = Some(0b1); + const MODER: u8 = 0b01; + const OTYPER: Option = Some(true); } impl PinMode for Output { - const MODER: u32 = 0b01; - const OTYPER: Option = Some(0b0); + const MODER: u8 = 0b01; + const OTYPER: Option = Some(false); } impl crate::Sealed for Alternate {} impl PinMode for Alternate { - const MODER: u32 = 0b10; - const OTYPER: Option = Some(0b1); - const AFR: Option = Some(A as _); + const MODER: u8 = 0b10; + const OTYPER: Option = Some(true); + const AFR: Option = Some(A as _); } impl PinMode for Alternate { - const MODER: u32 = 0b10; - const OTYPER: Option = Some(0b0); - const AFR: Option = Some(A as _); + const MODER: u8 = 0b10; + const OTYPER: Option = Some(false); + const AFR: Option = Some(A as _); } diff --git a/src/gpio/erased.rs b/src/gpio/erased.rs index 00e9f2e9..b402b9bb 100644 --- a/src/gpio/erased.rs +++ b/src/gpio/erased.rs @@ -82,18 +82,14 @@ impl ErasedPin> { #[inline(always)] pub fn set_high(&mut self) { // NOTE(unsafe) atomic write to a stateless register - unsafe { self.block().bsrr().write(|w| w.bits(1 << self.pin_id())) }; + self.block().bsrr().write(|w| w.bs(self.pin_id()).set_bit()); } /// Drives the pin low #[inline(always)] pub fn set_low(&mut self) { // NOTE(unsafe) atomic write to a stateless register - unsafe { - self.block() - .bsrr() - .write(|w| w.bits(1 << (self.pin_id() + 16))) - }; + self.block().bsrr().write(|w| w.br(self.pin_id()).set_bit()); } /// Is the pin in drive high or low mode? @@ -124,7 +120,7 @@ impl ErasedPin> { /// Is the pin in drive low mode? #[inline(always)] pub fn is_set_low(&self) -> bool { - self.block().odr().read().bits() & (1 << self.pin_id()) == 0 + self.block().odr().read().odr(self.pin_id()).is_low() } /// Toggle pin output @@ -151,6 +147,6 @@ where /// Is the input pin low? #[inline(always)] pub fn is_low(&self) -> bool { - self.block().idr().read().bits() & (1 << self.pin_id()) == 0 + self.block().idr().read().idr(self.pin_id()).is_low() } } diff --git a/src/gpio/partially_erased.rs b/src/gpio/partially_erased.rs index f88bbb3b..6eecb5d6 100644 --- a/src/gpio/partially_erased.rs +++ b/src/gpio/partially_erased.rs @@ -63,7 +63,7 @@ impl PartiallyErasedPin> { pub fn set_high(&mut self) { // NOTE(unsafe) atomic write to a stateless register unsafe { - (*Gpio::

::ptr()).bsrr().write(|w| w.bits(1 << self.i)); + (*Gpio::

::ptr()).bsrr().write(|w| w.bs(self.i).set_bit()); } } @@ -72,9 +72,7 @@ impl PartiallyErasedPin> { pub fn set_low(&mut self) { // NOTE(unsafe) atomic write to a stateless register unsafe { - (*Gpio::

::ptr()) - .bsrr() - .write(|w| w.bits(1 << (self.i + 16))); + (*Gpio::

::ptr()).bsrr().write(|w| w.br(self.i).set_bit()); } } @@ -107,7 +105,7 @@ impl PartiallyErasedPin> { #[inline(always)] pub fn is_set_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*Gpio::

::ptr()).odr().read().bits() & (1 << self.i) == 0 } + unsafe { (*Gpio::

::ptr()).odr().read().odr(self.i).is_low() } } /// Toggle pin output @@ -135,7 +133,7 @@ where #[inline(always)] pub fn is_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*Gpio::

::ptr()).idr().read().bits() & (1 << self.i) == 0 } + unsafe { (*Gpio::

::ptr()).idr().read().idr(self.i).is_low() } } } diff --git a/src/i2c.rs b/src/i2c.rs index c1f24aa2..bdced3bf 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -112,10 +112,7 @@ macro_rules! flush_txdr { ($i2c:expr) => { // If a pending TXIS flag is set, write dummy data to TXDR if $i2c.isr().read().txis().bit_is_set() { - unsafe { - //NOTE(unsafe) 0 is a valid bit pattern - $i2c.txdr().write(|w| w.txdata().bits(0)); - } + $i2c.txdr().write(|w| w.txdata().set(0)); } // If TXDR is not flagged as empty, write 1 to flush it @@ -304,18 +301,18 @@ macro_rules! i2c { // Configure timing let (presc_reg, scll, sclh, sdadel, scldel) = i2c_timing!(i2c_clk, freq); - //NOTE(unsafe) Only valid bit patterns written, checked by i2c_timing - i2c.timingr().write(|w| unsafe { + + i2c.timingr().write(|w| { w.presc() - .bits(presc_reg) + .set(presc_reg) .scll() - .bits(scll) + .set(scll) .sclh() - .bits(sclh) + .set(sclh) .sdadel() - .bits(sdadel) + .set(sdadel) .scldel() - .bits(scldel) + .set(scldel) }); // Enable the peripheral @@ -431,13 +428,13 @@ macro_rules! i2c { // `buffer`. The START bit can be set even if the bus // is BUSY or I2C is in slave mode. //NOTE(unsafe) Only valid bit patterns written - self.i2c.cr2().write(|w| unsafe { + self.i2c.cr2().write(|w| { w.sadd() - .bits((addr << 1 | 0) as u16) + .set((addr << 1 | 0) as u16) .rd_wrn() .read() .nbytes() - .bits(length as u8) + .set(length as u8) .start() .set_bit() .autoend() @@ -464,16 +461,16 @@ macro_rules! i2c { // START bit can be set even if the bus is BUSY or // I2C is in slave mode. //NOTE(unsafe) Only valid bit patterns written - self.i2c.cr2().write(|w| unsafe { + self.i2c.cr2().write(|w| { w.start() .set_bit() .sadd() - .bits(u16(addr << 1 | 0)) + .set(u16(addr << 1 | 0)) .add10().clear_bit() .rd_wrn() .write() .nbytes() - .bits(length as u8) + .set(length as u8) .autoend() .bit(stop == Stop::Automatic) }); @@ -493,14 +490,14 @@ macro_rules! i2c { assert!(length < 256 && length > 0); //NOTE(unsafe) Only valid bit patterns written - self.i2c.cr2().write(|w| unsafe { + self.i2c.cr2().write(|w| { w.sadd() - .bits(u16(addr << 1 | 1)) + .set(u16(addr << 1 | 1)) .add10().clear_bit() .rd_wrn() .read() .nbytes() - .bits(length as u8) + .set(length as u8) .start() .set_bit() .autoend() @@ -584,10 +581,7 @@ macro_rules! i2c { busy_wait!(self.i2c, txis, is_empty); // Put byte on the wire - //NOTE(unsafe) All bit bit patterns are valid - unsafe { - self.i2c.txdr().write(|w| w.txdata().bits(*byte)); - } + self.i2c.txdr().write(|w| w.txdata().set(*byte)); } // Wait until the write finishes @@ -627,10 +621,7 @@ macro_rules! i2c { busy_wait!(self.i2c, txis, is_empty); // Put byte on the wire - //NOTE(unsafe) All bit patterns are valid - unsafe { - self.i2c.txdr().write(|w| w.txdata().bits(*byte)); - } + self.i2c.txdr().write(|w| w.txdata().set(*byte)); } // Wait until the write finishes before beginning to read. diff --git a/src/independent_watchdog.rs b/src/independent_watchdog.rs index 864c67f1..18eb38c2 100644 --- a/src/independent_watchdog.rs +++ b/src/independent_watchdog.rs @@ -119,12 +119,9 @@ impl IndependentWatchdog { cortex_m::asm::nop(); } - //NOTE(unsafe) 0xFFF is a valid bit patterns for w.win() - unsafe { - self.iwdg - .winr() - .write(|w| w.win().bits(Self::MAX_COUNTER_VALUE as u16)); - } + self.iwdg + .winr() + .write(|w| w.win().set(Self::MAX_COUNTER_VALUE as u16)); // Calculate the counter values let reload_value = max_window_time.to_millis() @@ -138,10 +135,8 @@ impl IndependentWatchdog { while self.iwdg.sr().read().rvu().bit_is_set() { cortex_m::asm::nop(); } - //NOTE(unsafe) Only valid bit patterns written, values are checked above for maximum value - unsafe { - self.iwdg.rlr().write(|w| w.rl().bits(reload_value as u16)); - } + + self.iwdg.rlr().write(|w| w.rl().set(reload_value as u16)); self.feed(); // Enable register access @@ -153,11 +148,9 @@ impl IndependentWatchdog { } // TODO: There is nothing preventing this from underflowing right? - unsafe { - self.iwdg - .winr() - .write(|w| w.win().bits((reload_value - window_value) as u16)); - } + self.iwdg + .winr() + .write(|w| w.win().set((reload_value - window_value) as u16)); // Wait until everything is set while self.iwdg.sr().read().bits() != 0 { diff --git a/src/ltdc.rs b/src/ltdc.rs index 2269b2a1..b788ac2e 100644 --- a/src/ltdc.rs +++ b/src/ltdc.rs @@ -142,21 +142,16 @@ impl DisplayController for Ltdc { }); // Set synchronization pulse width - // TODO: The h_sync and v_sync values are not checked - self.ltdc.sscr().modify(|_, w| unsafe { - w.vsh() - .bits(config.v_sync - 1) - .hsw() - .bits(config.h_sync - 1) + self.ltdc.sscr().modify(|_, w| { + w.vsh().set(config.v_sync - 1).hsw().set(config.h_sync - 1) }); // Set accumulated back porch - // TODO: The values are not checked - self.ltdc.bpcr().modify(|_, w| unsafe { + self.ltdc.bpcr().modify(|_, w| { w.avbp() - .bits(config.v_sync + config.v_back_porch - 1) + .set(config.v_sync + config.v_back_porch - 1) .ahbp() - .bits(config.h_sync + config.h_back_porch - 1) + .set(config.h_sync + config.h_back_porch - 1) }); // Set accumulated active width @@ -164,9 +159,9 @@ impl DisplayController for Ltdc { config.v_sync + config.v_back_porch + config.active_height - 1; let aa_width = config.h_sync + config.h_back_porch + config.active_width - 1; - self.ltdc.awcr().modify(|_, w| unsafe { - w.aah().bits(aa_height).aaw().bits(aa_width) - }); + self.ltdc + .awcr() + .modify(|_, w| w.aah().set(aa_height).aaw().set(aa_width)); // Set total width and height let total_height: u16 = config.v_sync @@ -179,9 +174,9 @@ impl DisplayController for Ltdc { + config.active_width + config.h_front_porch - 1; - // TODO: total_width is not checked - self.ltdc.twcr().modify(|_, w| unsafe { - w.totalh().bits(total_height).totalw().bits(total_width) + + self.ltdc.twcr().modify(|_, w| { + w.totalh().set(total_height).totalw().set(total_width) }); // Set the background color value @@ -256,7 +251,7 @@ macro_rules! impl_layer { let h_win_stop = self.window_x1 + ltdc.bpcr().read().ahbp().bits(); layer.whpcr().modify(|_, w| { - w.whstpos().bits(h_win_start).whsppos().bits(h_win_stop) + w.whstpos().set(h_win_start).whsppos().set(h_win_stop) }); // Configure the vertical start and stop position @@ -265,19 +260,19 @@ macro_rules! impl_layer { let v_win_stop = self.window_y1 + ltdc.bpcr().read().avbp().bits(); layer.wvpcr().modify(|_, w| { - w.wvstpos().bits(v_win_start).wvsppos().bits(v_win_stop) + w.wvstpos().set(v_win_start).wvsppos().set(v_win_stop) }); } // Set the pixel format - layer.pfcr().modify(|_, w| w.pf().bits(pixel_format as u8)); + layer.pfcr().modify(|_, w| w.pf().set(pixel_format as u8)); // Set the default color value layer.dccr().reset(); // Transparent black // Set the global constant alpha value let alpha = 0xFF; - layer.cacr().modify(|_, w| w.consta().bits(alpha)); + layer.cacr().modify(|_, w| w.consta().set(alpha)); // Set the blending factors let blending_factor1 = @@ -291,7 +286,7 @@ macro_rules! impl_layer { // Set frame buffer layer .cfbar() - .modify(|_, w| w.cfbadd().bits(start_ptr as u32)); + .modify(|_, w| w.cfbadd().set(start_ptr as u32)); // Calculate framebuffer pitch in bytes self.bytes_per_pixel = match pixel_format { @@ -307,13 +302,13 @@ macro_rules! impl_layer { // Framebuffer pitch and line length layer.cfblr().modify(|_, w| { w.cfbp() - .bits(width * self.bytes_per_pixel) + .set(width * self.bytes_per_pixel) .cfbll() - .bits(width * self.bytes_per_pixel + 7) + .set(width * self.bytes_per_pixel + 7) }); // Framebuffer line number - layer.cfblnr().modify(|_, w| w.cfblnbr().bits(height)); + layer.cfblnr().modify(|_, w| w.cfblnbr().set(height)); // Enable LTDC_Layer by setting LEN bit layer.cr().modify(|_, w| w.len().set_bit()); @@ -346,7 +341,7 @@ macro_rules! impl_layer { ); // Modify CFBP - self.layer.cfblr().modify(|_, w| w.cfbp().bits(pitch_bytes)); + self.layer.cfblr().modify(|_, w| w.cfbp().set(pitch_bytes)); // Immediate reload (*LTDC::ptr()).srcr().write(|w| w.imr().set_bit()); @@ -365,7 +360,7 @@ macro_rules! impl_layer { // Set the new frame buffer address self.layer .cfbar() - .modify(|_, w| w.cfbadd().bits(start_ptr as u32)); + .modify(|_, w| w.cfbadd().set(start_ptr as u32)); // Configure a shadow reload for the next blanking period (*LTDC::ptr()).srcr().write(|w| w.vbr().set_bit()); diff --git a/src/pwm.rs b/src/pwm.rs index aac3930a..1515ac14 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -1142,12 +1142,10 @@ macro_rules! tim_hal { }; // Write prescale - //NOTE(unsafe) Only valid bit patterns written, checked by calculate_frequency_{16,32}bit - tim.psc().write(|w| unsafe { w.psc().bits(prescale as u16) }); + tim.psc().write(|w| w.psc().set(prescale as u16)); // Write period - //NOTE(unsafe) Only valid bit patterns written, checked by calculate_frequency_{16,32}bit - tim.arr().write(|w| unsafe { w.arr().bits(period as $typ) }); + tim.arr().write(|w| w.arr().set(period as $typ)); // BDTR: Advanced-control timers $( @@ -1210,12 +1208,10 @@ macro_rules! tim_hal { }; // Write prescaler - //NOTE(unsafe) Only valid bit patterns written, checked by calculate_frequency_{16,32}bit - tim.psc().write(|w| unsafe { w.psc().bits(prescaler as u16) }); + tim.psc().write(|w| w.psc().set(prescaler as u16)); // Write period - //NOTE(unsafe) Only valid bit patterns written, checked by calculate_frequency_{16,32}bit - tim.arr().write(|w| unsafe { w.arr().bits(period as $typ) }); + tim.arr().write(|w| w.arr().set(period as $typ)); $( let (dtg, ckd) = calculate_deadtime(self.base_freq, self.deadtime); @@ -1255,7 +1251,7 @@ macro_rules! tim_hal { // BK2E = 1 -> break is enabled // BK2P = 0 for active low, 1 for active high // Safety: bkf is set to a constant value (1) that is a valid value for the field per the reference manual - unsafe { tim.$bdtr().write(|w| w.dtg().bits(dtg).bk2f().bits(1).aoe().clear_bit().bk2e().set_bit().bk2p().bit(bkp).moe().$moe_set()); } + unsafe { tim.$bdtr().write(|w| w.dtg().set(dtg).bk2f().bits(1).aoe().clear_bit().bk2e().set_bit().bk2p().bit(bkp).moe().$moe_set()); } // AF1: // BKINE = 1 -> break input enabled @@ -1501,8 +1497,7 @@ macro_rules! tim_pin_hal { fn set_duty(&mut self, duty: Self::Duty) { let tim = unsafe { &*<$TIMX>::ptr() }; - //NOTE(unsafe) All bit patterns are valid - tim.ccr($CH as usize).write(|w| unsafe { w.ccr().bits(duty) }); + tim.ccr($CH as usize).write(|w| { w.ccr().set(duty) }); } } @@ -1754,8 +1749,7 @@ macro_rules! lptim_hal { tim.cr().modify(|_, w| w.enable().enabled()); // Write ARR: LPTIM must be enabled - //NOTE(unsafe) All bit patterns are valid - tim.arr().write(|w| unsafe { w.arr().bits(arr as u16) }); + tim.arr().write(|w| { w.arr().set(arr as u16) }); while !tim.isr().read().arrok().is_set() {} tim.icr().write(|w| w.arrokcf().clear()); @@ -1802,8 +1796,7 @@ macro_rules! lptim_hal { fn set_duty(&mut self, duty: u16) { let tim = unsafe { &*<$TIMX>::ptr() }; - //NOTE(unsafe) All bit patterns are valid - tim.cmp().write(|w| unsafe { w.cmp().bits(duty) }); + tim.cmp().write(|w| { w.cmp().set(duty) }); while !tim.isr().read().cmpok().is_set() {} tim.icr().write(|w| w.cmpokcf().clear()); } diff --git a/src/qei.rs b/src/qei.rs index ad08ee43..f3cf8e8d 100644 --- a/src/qei.rs +++ b/src/qei.rs @@ -183,8 +183,7 @@ macro_rules! tim_hal { }); // configure as quadrature encoder - //NOTE(unsafe) 3 is a valid bit patterns for w.sms() - tim.smcr().write(|w| unsafe { w.sms().bits(3) }); + tim.smcr().write(|w| w.sms().set(3)); #[allow(unused_unsafe)] // method is safe for some timers tim.arr().write(|w| unsafe { w.bits(u32::MAX) }); diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index a4b8d542..e5c26d15 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -835,16 +835,15 @@ impl Rcc { // // It is highly recommended to configure these bits only after // reset, before enabling the external oscillators and the PLLs. - //NOTE(unsafe) Only valid bit patterns written - rcc.cfgr().modify(|_, w| unsafe { + rcc.cfgr().modify(|_, w| { w.mco1() .variant(self.config.mco1.source) .mco1pre() - .bits(mco_1_pre) + .set(mco_1_pre) .mco2() .variant(self.config.mco2.source) .mco2pre() - .bits(mco_2_pre) + .set(mco_2_pre) }); // HSE @@ -892,20 +891,20 @@ impl Rcc { // Core Prescaler / AHB Prescaler / APB3 Prescaler #[cfg(not(feature = "rm0455"))] - rcc.d1cfgr().modify(|_, w| unsafe { + rcc.d1cfgr().modify(|_, w| { w.d1cpre() - .bits(d1cpre_bits) + .set(d1cpre_bits) .d1ppre() // D1 contains APB3 - .bits(ppre3_bits) + .set(ppre3_bits) .hpre() .variant(hpre_bits) }); #[cfg(feature = "rm0455")] - rcc.cdcfgr1().modify(|_, w| unsafe { + rcc.cdcfgr1().modify(|_, w| { w.cdcpre() - .bits(d1cpre_bits) + .set(d1cpre_bits) .cdppre() // D1/CD contains APB3 - .bits(ppre3_bits) + .set(ppre3_bits) .hpre() .variant(hpre_bits) }); @@ -918,25 +917,25 @@ impl Rcc { // APB1 / APB2 Prescaler #[cfg(not(feature = "rm0455"))] - rcc.d2cfgr().modify(|_, w| unsafe { + rcc.d2cfgr().modify(|_, w| { w.d2ppre1() // D2 contains APB1 - .bits(ppre1_bits) + .set(ppre1_bits) .d2ppre2() // D2 also contains APB2 - .bits(ppre2_bits) + .set(ppre2_bits) }); #[cfg(feature = "rm0455")] - rcc.cdcfgr2().modify(|_, w| unsafe { + rcc.cdcfgr2().modify(|_, w| { w.cdppre1() // D2/CD contains APB1 - .bits(ppre1_bits) + .set(ppre1_bits) .cdppre2() // D2/CD also contains APB2 - .bits(ppre2_bits) + .set(ppre2_bits) }); // APB4 Prescaler #[cfg(not(feature = "rm0455"))] - rcc.d3cfgr().modify(|_, w| unsafe { + rcc.d3cfgr().modify(|_, w| { w.d3ppre() // D3 contains APB4 - .bits(ppre4_bits) + .set(ppre4_bits) }); #[cfg(feature = "rm0455")] rcc.srdcfgr().modify(|_, w| unsafe { diff --git a/src/rcc/pll.rs b/src/rcc/pll.rs index de6f651e..b2de907d 100644 --- a/src/rcc/pll.rs +++ b/src/rcc/pll.rs @@ -226,9 +226,8 @@ macro_rules! pll_setup { let pll_x_n = vco_ck_target / ref_x_ck; // Write dividers - //NOTE(unsafe) Only valid bit patterns written, checked by vco_setup - rcc.pllckselr().modify(|_, w| unsafe { - w.$divmX().bits(pll_x_m as u8) // ref prescaler + rcc.pllckselr().modify(|_, w| { + w.$divmX().set(pll_x_m as u8) // ref prescaler }); // unsafe as not all values are permitted: see RM0433 assert!(pll_x_n >= 4); @@ -242,9 +241,8 @@ macro_rules! pll_setup { // Calculate FRACN let pll_x_fracn = calc_fracn(ref_x_ck as f32, pll_x_n as f32, pll_x as f32, output as f32); //RCC_PLL1FRACR - //NOTE(unsafe) Only valid bit patterns written, checked by calc_fracn - rcc.$pllXfracr().modify(|_, w| unsafe { - w.$fracnx().bits(pll_x_fracn) + rcc.$pllXfracr().modify(|_, w| { + w.$fracnx().set(pll_x_fracn) }); // Enable FRACN rcc.pllcfgr().modify(|_, w| { @@ -261,9 +259,7 @@ macro_rules! pll_setup { //RCC_PLL1FRACR // TODO: This cant be right, calc_fracn only checks that pll_x_fracn <= the max value, // since we have now incremented it by 1, that check does no longer hold? - rcc.$pllXfracr().modify(|_, w| unsafe { - w.$fracnx().bits(pll_x_fracn) - }); + rcc.$pllXfracr().modify(|_, w| w.$fracnx().set(pll_x_fracn)); // Enable FRACN rcc.pllcfgr().modify(|_, w| { w.$pllXfracen().set_() diff --git a/src/rtc.rs b/src/rtc.rs index 492c845b..6a8fb707 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -169,9 +169,7 @@ impl Rtc { RtcClock::Hse { divider } => { // Set HSE divider assert!(divider < 64, "HSE Divider larger than 63"); - //NOTE(unsafe) Value is checked above - rcc.cfgr() - .modify(|_, w| unsafe { w.rtcpre().bits(divider) }); + rcc.cfgr().modify(|_, w| w.rtcpre().set(divider)); clocks.hse_ck().map(|x| x / u32(divider)) } @@ -233,11 +231,11 @@ impl Rtc { ); //NOTE(unsafe) Only valid bit patterns are writte, values are checked above - rtc.prer().write(|w| unsafe { + rtc.prer().write(|w| { w.prediv_s() - .bits(u16(s_pre - 1).unwrap()) + .set(u16(s_pre - 1).unwrap()) .prediv_a() - .bits(u8(a_pre - 1).unwrap()) + .set(u8(a_pre - 1).unwrap()) }); // Exit initialization mode @@ -262,9 +260,7 @@ impl Rtc { /// Panics if `reg` is greater than 31. pub fn write_backup_reg(&mut self, reg: u8, value: u32) { //NOTE(unsafe) All bit patterns are valid - self.reg - .bkpr(reg as usize) - .write(|w| unsafe { w.bkp().bits(value) }); + self.reg.bkpr(reg as usize).write(|w| w.bkp().set(value)); } /// Sets the date and time of the RTC @@ -291,21 +287,21 @@ impl Rtc { let su = second % 10; //NOTE(unsafe) Only valid bit patterns are written - self.reg.tr().write(|w| unsafe { + self.reg.tr().write(|w| { w.pm() .clear_bit() .ht() - .bits(ht) + .set(ht) .hu() - .bits(hu) + .set(hu) .mnt() - .bits(mnt) + .set(mnt) .mnu() - .bits(mnu) + .set(mnu) .st() - .bits(st) + .set(st) .su() - .bits(su) + .set(su) }); let year = date_time.year(); @@ -325,19 +321,19 @@ impl Rtc { self.reg.dr().write(|w| unsafe { w.yt() - .bits(yt) + .set(yt) .yu() - .bits(yu) + .set(yu) .wdu() .bits(wdu) .mt() .bit(mt) .mu() - .bits(mu) + .set(mu) .dt() - .bits(dt) + .set(dt) .du() - .bits(du) + .set(du) }); // Exit initialization mode @@ -579,16 +575,16 @@ impl Rtc { .modify(|_, w| unsafe { w.wucksel().bits(0b110) }); let interval = u16(interval - (1 << 16) - 1) .expect("Interval was too large for wakeup timer"); - //NOTE(unsafe) Value is checked before being written - self.reg.wutr().write(|w| unsafe { w.wut().bits(interval) }); + + self.reg.wutr().write(|w| w.wut().set(interval)); } else { self.reg .cr() .modify(|_, w| unsafe { w.wucksel().bits(0b100) }); let interval = u16(interval - 1) .expect("Interval was too large for wakeup timer"); - //NOTE(unsafe) Value is checked before being written - self.reg.wutr().write(|w| unsafe { w.wut().bits(interval) }); + + self.reg.wutr().write(|w| w.wut().set(interval)); } self.reg.cr().modify(|_, w| w.wute().set_bit()); diff --git a/src/sai/i2s.rs b/src/sai/i2s.rs index 08586e69..913b044f 100644 --- a/src/sai/i2s.rs +++ b/src/sai/i2s.rs @@ -667,7 +667,7 @@ fn i2s_config_channel( unsafe { audio_ch.cr1().modify(|_, w| { w.mode() - .bits(mode_bits) + .set(mode_bits) .prtcfg() .free() .ds() diff --git a/src/serial.rs b/src/serial.rs index f5642d65..1c3224de 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -634,8 +634,7 @@ macro_rules! usart { // 16 times oversampling, OVER8 = 0 let brr = usartdiv as u16; - //NOTE(unsafe) Only valid bit patterns written, checked above - self.usart.brr().write(|w| unsafe { w.brr().bits(brr) }); + self.usart.brr().write(|w| w.brr().set(brr)); // Reset registers to disable advanced USART features self.usart.cr2().reset(); diff --git a/src/spi.rs b/src/spi.rs index ed65c780..613c0bc0 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -670,24 +670,21 @@ pub trait HalSpi: Sized { macro_rules! spi { (DSIZE, $spi:ident, u8) => { - //NOTE(unsafe) 7 is a valid bit patterns - $spi.cfg1().modify(|_, w| unsafe { + $spi.cfg1().modify(|_, w| { w.dsize() - .bits(8 - 1) // 8 bit words + .set(8 - 1) // 8 bit words }); }; (DSIZE, $spi:ident, u16) => { - //NOTE(unsafe) 15 is a valid bit pattern - $spi.cfg1().modify(|_, w| unsafe { + $spi.cfg1().modify(|_, w| { w.dsize() - .bits(16 - 1) // 16 bit words + .set(16 - 1) // 16 bit words }); }; (DSIZE, $spi:ident, u32) => { - //NOTE(unsafe) 31 is a valid bit pattern - $spi.cfg1().modify(|_, w| unsafe { + $spi.cfg1().modify(|_, w| { w.dsize() - .bits(32 - 1) // 32 bit words + .set(32 - 1) // 32 bit words }); }; ($($SPIX:ident: ($spiX:ident, $Rec:ident, $pclkX:ident) @@ -776,8 +773,7 @@ macro_rules! spi { // mstr: master configuration // lsbfrst: MSB first // comm: full-duplex - //NOTE(unsafe) Only valid bit patterns written, checked above - spi.cfg2().write(|w| unsafe { + spi.cfg2().write(|w| { w.cpha() .bit(config.mode.phase == Phase::CaptureOnSecondTransition) @@ -794,9 +790,9 @@ macro_rules! spi { .ssoe() .bit(config.hardware_cs.enabled() == true) .mssi() - .bits(assertion_delay) + .set(assertion_delay) .midi() - .bits(inter_word_delay) + .set(inter_word_delay) .ioswp() .bit(config.swap_miso_mosi == true) .comm() @@ -807,9 +803,8 @@ macro_rules! spi { // Reset to default (might have been set if previously used by a frame transaction) // So that is 1 when it's a frame transaction and 0 when in another mode - //NOTE(unsafe) Only valid bit patterns written - spi.cr2().write(|w| unsafe { - w.tsize().bits(matches!(config.hardware_cs.mode, HardwareCSMode::FrameTransaction) as u16) + spi.cr2().write(|w| { + w.tsize().set(matches!(config.hardware_cs.mode, HardwareCSMode::FrameTransaction) as u16) }); // spe: enable the SPI bus @@ -869,8 +864,7 @@ macro_rules! spi { self.spi.cr1().write(|w| w.ssi().slave_not_selected().spe().disabled()); // Set the frame size - //NOTE(unsafe) Only valid bit patterns are written - self.spi.cr2().write(|w| unsafe { w.tsize().bits(words.get())}); + self.spi.cr2().write(|w| w.tsize().set(words.get())); // Re-enable self.clear_modf(); // SPE cannot be set when MODF is set diff --git a/src/system_watchdog.rs b/src/system_watchdog.rs index b3aee3cb..a568d0fb 100644 --- a/src/system_watchdog.rs +++ b/src/system_watchdog.rs @@ -121,10 +121,8 @@ impl Watchdog for SystemWindowWatchdog { fn feed(&mut self) { // if this value is 0 it is assumed that the watchdog has not yet been started assert!(self.down_counter != 0); - //NOTE(unsafe) Only valid bit patterns written, checked on start - self.wwdg - .cr() - .modify(|_, w| unsafe { w.t().bits(self.down_counter) }); + + self.wwdg.cr().modify(|_, w| w.t().set(self.down_counter)); } } @@ -163,20 +161,11 @@ impl WatchdogEnable for SystemWindowWatchdog { self.down_counter = u8(t).unwrap() | (1 << 6); // write the config values, matching the set timeout the most - //NOTE(unsafe) Only valid bit patterns written - self.wwdg - .cfr() - .modify(|_, w| unsafe { w.wdgtb().bits(wdgtb) }); - - //NOTE(unsafe) Only valid bit patterns written, checked above - self.wwdg - .cfr() - .modify(|_, w| unsafe { w.w().bits(self.down_counter) }); - - //NOTE(unsafe) Only valid bit patterns written, checked above - self.wwdg - .cr() - .modify(|_, w| unsafe { w.t().bits(self.down_counter) }); + self.wwdg.cfr().modify(|_, w| w.wdgtb().set(wdgtb)); + + self.wwdg.cfr().modify(|_, w| w.w().set(self.down_counter)); + + self.wwdg.cr().modify(|_, w| w.t().set(self.down_counter)); // For some reason, setting the t value makes the early wakeup pending. // That's bad behaviour, so lets turn it off again. self.unpend(Event::EarlyWakeup); diff --git a/src/timer.rs b/src/timer.rs index 67eb6921..766fab2c 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -116,7 +116,7 @@ impl GetClk for LPTIM3 { // unsafe: read only let srdccipr = &unsafe { &*stm32::RCC::ptr() }.srdccipr(); - match srdccipr.read().lptim3sel().bits() { + match srdccipr.read().lptim3sel().set() { 0 => Some(clocks.pclk4()), 1 => clocks.pll2_p_ck(), 2 => clocks.pll3_r_ck(), @@ -439,8 +439,7 @@ macro_rules! hal { fn set_timeout_ticks(&mut self, ticks: u32) { let (psc, arr) = calculate_timeout_ticks_register_values(ticks); //NOTE(unsafe) All bit patterns are valid - self.tim.psc().write(|w| unsafe { w.psc().bits(psc) }); - #[allow(unused_unsafe)] // method is safe for some timers + self.tim.psc().write(|w| w.psc().set(psc)); self.tim.arr().write(|w| unsafe { w.bits(u32(arr)) }); } @@ -454,10 +453,10 @@ macro_rules! hal { let psc = u16(div - 1).unwrap(); //NOTE(unsafe) All bit patterns are valid - self.tim.psc().write(|w| unsafe { w.psc().bits(psc) }); + self.tim.psc().write(|w| w.psc().set(psc)); let counter_max = u32(<$cntType>::MAX); - #[allow(unused_unsafe)] // method is safe for some timers + //NOTE(unsafe) All bit patterns are valid self.tim.arr().write(|w| unsafe { w.bits(counter_max) }); } @@ -830,7 +829,7 @@ macro_rules! lptim_hal { // Write ARR: LPTIM must be enabled //NOTE(unsafe) All bit patterns are valid - self.tim.arr().write(|w| unsafe { w.arr().bits(arr as u16) }); + self.tim.arr().write(|w| w.arr().set(arr as u16)); while self.tim.isr().read().arrok().bit_is_clear() {} self.tim.icr().write(|w| w.arrokcf().clear()); } @@ -868,8 +867,7 @@ macro_rules! lptim_hal { // Set ARR = max // Write ARR: LPTIM must be enabled - //NOTE(unsafe) 0xFFFF is a valid bit pattern - self.tim.arr().write(|w| unsafe { w.arr().bits(0xFFFF as u16) }); + self.tim.arr().write(|w| w.arr().set(0xFFFF as u16)); while self.tim.isr().read().arrok().bit_is_clear() {} self.tim.icr().write(|w| w.arrokcf().clear()); } diff --git a/src/xspi/mod.rs b/src/xspi/mod.rs index 142bfd32..427f37a2 100644 --- a/src/xspi/mod.rs +++ b/src/xspi/mod.rs @@ -615,7 +615,7 @@ mod common { #[cfg(any(feature = "rm0433", feature = "rm0399"))] let w = { let ir = instruction.bits_u8().unwrap(); - w.dcyc().bits(dummy_cycles).instruction().bits(ir).fmode().bits(fmode) + w.dcyc().set(dummy_cycles).instruction().set(ir).fmode().set(fmode) }; #[cfg(any(feature = "rm0455", feature = "rm0468"))] @@ -694,7 +694,7 @@ mod common { // Write the address. The transaction starts on the next write // to DATA, unless there is no DATA phase configured, in which // case it starts here. - self.rb.ar().write(|w| unsafe { w.address().bits(addr) }); + self.rb.ar().write(|w| unsafe { w.address().bits(addr)}); Ok(()) } @@ -945,7 +945,7 @@ mod common { // Write the length that should be read. self.rb .dlr() - .write(|w| unsafe { w.dl().bits(length as u32 - 1) }); + .write(|w| unsafe { w.dl().bits(length as u32 - 1)}); // Setup extended mode. Read operations always have a data phase. // Transaction starts here diff --git a/src/xspi/qspi.rs b/src/xspi/qspi.rs index 008f0b67..c7a96922 100644 --- a/src/xspi/qspi.rs +++ b/src/xspi/qspi.rs @@ -271,7 +271,7 @@ impl Qspi { // Configure the FSIZE to maximum. It appears that even when addressing is not used, the // flash size violation may still trigger. - regs.dcr().write(|w| unsafe { w.fsize().bits(0x1F) }); + regs.dcr().write(|w| w.fsize().set(0x1F)); // Clear all pending flags. regs.fcr().write(|w| { @@ -286,19 +286,19 @@ impl Qspi { }); // Configure the communication method for QSPI. - regs.ccr().write(|w| unsafe { + regs.ccr().write(|w| { w.fmode() - .bits(0) // indirect mode + .set(0) // indirect mode .dmode() - .bits(config.modes.data.reg_value()) + .set(config.modes.data.reg_value()) .admode() - .bits(config.modes.address.reg_value()) + .set(config.modes.address.reg_value()) .adsize() - .bits(0) // Eight-bit address + .set(0) // Eight-bit address .imode() - .bits(0) // No instruction phase + .set(0) // No instruction phase .dcyc() - .bits(config.dummy_cycles) + .set(config.dummy_cycles) }); let spi_frequency = config.frequency.raw(); @@ -319,7 +319,7 @@ impl Qspi { // SSHIFT must not be set in DDR mode. regs.cr().write(|w| unsafe { w.prescaler() - .bits(divisor as u8) + .set(divisor as u8) .sshift() .bit(config.sampling_edge == SamplingEdge::Falling) .fthres() From c45373c00c1dcdf8332bb7eb5b9e61e66005e8e2 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Tue, 17 Dec 2024 23:10:48 +0100 Subject: [PATCH 15/15] Clean up --- src/crc.rs | 2 -- src/dma/bdma.rs | 2 -- src/dma/dma.rs | 5 ----- src/rcc/rec.rs | 2 -- src/rtc.rs | 3 --- src/system_watchdog.rs | 2 -- src/timer.rs | 3 +-- 7 files changed, 1 insertion(+), 18 deletions(-) diff --git a/src/crc.rs b/src/crc.rs index b6253235..867e1168 100644 --- a/src/crc.rs +++ b/src/crc.rs @@ -37,7 +37,6 @@ impl Crc { // manual says unit must be reset (or DR read) before change of polynomial // (technically only in case of ongoing calculation, but DR is buffered) - //NOTE(unsafe) Only valid bit patterns are written self.reg.cr().modify(|_, w| { w.polysize() .set(config.poly.polysize()) @@ -124,7 +123,6 @@ impl Crc { /// /// The IDR is not involved with CRC calculation. pub fn set_idr(&mut self, value: u32) { - //NOTE(unsafe) All bit patterns are valid self.reg.idr().write(|w| w.idr().set(value)); } diff --git a/src/dma/bdma.rs b/src/dma/bdma.rs index 695da7c3..a0e40df3 100644 --- a/src/dma/bdma.rs +++ b/src/dma/bdma.rs @@ -353,7 +353,6 @@ where #[inline(always)] fn set_priority(&mut self, priority: config::Priority) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) We only write valid bit patterns unsafe { Self::stream() .cr() @@ -464,7 +463,6 @@ where #[inline(always)] fn set_number_of_transfers(&mut self, value: u16) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) All bit patterns are valid for ndt unsafe { Self::stream().ndtr().write(|w| w.ndt().set(value)); } diff --git a/src/dma/dma.rs b/src/dma/dma.rs index 2140ca9c..a37224fb 100644 --- a/src/dma/dma.rs +++ b/src/dma/dma.rs @@ -352,7 +352,6 @@ impl StreamX { #[inline(always)] fn set_fifo_threshold(&mut self, fifo_threshold: config::FifoThreshold) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) We only write valid bit patterns unsafe { Self::stream() .fcr() @@ -372,7 +371,6 @@ impl StreamX { #[inline(always)] fn set_memory_burst(&mut self, memory_burst: config::BurstMode) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) We only write valid bit patterns unsafe { Self::stream() .cr() @@ -383,7 +381,6 @@ impl StreamX { #[inline(always)] fn set_peripheral_burst(&mut self, peripheral_burst: config::BurstMode) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) We only write valid bit patterns unsafe { Self::stream() .cr() @@ -514,7 +511,6 @@ where #[inline(always)] fn set_priority(&mut self, priority: config::Priority) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) We only write valid bit patterns unsafe { Self::stream() .cr() @@ -643,7 +639,6 @@ where #[inline(always)] fn set_number_of_transfers(&mut self, value: u16) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) All bit pattern for ndt are valid unsafe { Self::stream().ndtr().write(|w| w.ndt().set(value)); } diff --git a/src/rcc/rec.rs b/src/rcc/rec.rs index 2b5ebf9b..9de147de 100644 --- a/src/rcc/rec.rs +++ b/src/rcc/rec.rs @@ -76,8 +76,6 @@ use super::Rcc; use crate::stm32::{rcc, RCC}; use cortex_m::interrupt; -//const X: stm32h7::stm32h743v::rcc::d1ccipr::FMCSEL = (); - /// A trait for Resetting, Enabling and Disabling a single peripheral pub trait ResetEnable { /// Enable this peripheral diff --git a/src/rtc.rs b/src/rtc.rs index 6a8fb707..70ca8d39 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -230,7 +230,6 @@ impl Rtc { "Invalid RTC prescaler value" ); - //NOTE(unsafe) Only valid bit patterns are writte, values are checked above rtc.prer().write(|w| { w.prediv_s() .set(u16(s_pre - 1).unwrap()) @@ -259,7 +258,6 @@ impl Rtc { /// /// Panics if `reg` is greater than 31. pub fn write_backup_reg(&mut self, reg: u8, value: u32) { - //NOTE(unsafe) All bit patterns are valid self.reg.bkpr(reg as usize).write(|w| w.bkp().set(value)); } @@ -286,7 +284,6 @@ impl Rtc { let st = second / 10; let su = second % 10; - //NOTE(unsafe) Only valid bit patterns are written self.reg.tr().write(|w| { w.pm() .clear_bit() diff --git a/src/system_watchdog.rs b/src/system_watchdog.rs index a568d0fb..170d037e 100644 --- a/src/system_watchdog.rs +++ b/src/system_watchdog.rs @@ -162,9 +162,7 @@ impl WatchdogEnable for SystemWindowWatchdog { // write the config values, matching the set timeout the most self.wwdg.cfr().modify(|_, w| w.wdgtb().set(wdgtb)); - self.wwdg.cfr().modify(|_, w| w.w().set(self.down_counter)); - self.wwdg.cr().modify(|_, w| w.t().set(self.down_counter)); // For some reason, setting the t value makes the early wakeup pending. // That's bad behaviour, so lets turn it off again. diff --git a/src/timer.rs b/src/timer.rs index 766fab2c..6bfdfd2e 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -116,7 +116,7 @@ impl GetClk for LPTIM3 { // unsafe: read only let srdccipr = &unsafe { &*stm32::RCC::ptr() }.srdccipr(); - match srdccipr.read().lptim3sel().set() { + match srdccipr.read().lptim3sel().bits() { 0 => Some(clocks.pclk4()), 1 => clocks.pll2_p_ck(), 2 => clocks.pll3_r_ck(), @@ -452,7 +452,6 @@ macro_rules! hal { let div = self.clk / frequency.raw(); let psc = u16(div - 1).unwrap(); - //NOTE(unsafe) All bit patterns are valid self.tim.psc().write(|w| w.psc().set(psc)); let counter_max = u32(<$cntType>::MAX);