Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Explore defining verilog and HW modules or subsets of IP cores #20

Open
strangemonad opened this issue Nov 30, 2017 · 0 comments
Open

Explore defining verilog and HW modules or subsets of IP cores #20

strangemonad opened this issue Nov 30, 2017 · 0 comments

Comments

@strangemonad
Copy link
Owner

strangemonad commented Nov 30, 2017 •
edited
Loading

Can this bridge beyond pure software into hw implementations

e.g what could it mean to define things usable by chisel, verilog etc.
@strangemonad strangemonad changed the title Can this bridge beyond software into hw implementations Explore defining verilog and HW modules or subsets of IP cores Dec 29, 2017
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@strangemonad