Is it possible to skip using asap 7 calibre deck to perform synthesis? #726
Replies: 74 comments
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Hi,
Thanks! |
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Hi,
With chipyard, the macro compiler is using Thanks. |
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Yes, the macro compiler is using Barstools. So, in the asap7 case, its sram compiler puts one of the collateral ( sram_generator-output.json) that points to all of these files
. As long as you have this resulting JSON file and the memories inside match the ones in vlsi/generated-src/{Design_name}/{Design_name}.top.mems.v, you are good to go. Not all tech plugins utilize the sram_generator-rundir.
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Hi,
...
set_db syn_generic_effort high
set_db syn_map_effort high
set_db syn_opt_effort extreme
...
syn_opt
syn_opt -inc
...*Note: This still ends up with better timing even it is not met. Maybe in the flow, it can add an option on effort strategy. I think It will also fail on post-synthesis simulation too. But I run |
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Hi, Waxpple: Could you please tell me what your linux server version and VCS version is? I have some problem in Best, |
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Hi, Yes, here is my environment set up. OS: Redhat Enterprise Linux 7.9 I think the EDA tool is not very compatible with the Debian-based Linux system. |
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Thanks a lot. Yes, There are some many problems need to fix. I will try it on another RHEL6.10 linux server. |
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Perhaps a dumb question, but did you adjust the clock constraints ( For your simulation, are you running timing-annotated simulation or only post-synthesis functional simulation? If it's timing-annotated, it would make sense that it doesn't pass. If not, then I might look at that line in the
This would be a welcome contribution in hammer-synopsys-plugins! This should use the
VCS 2021.09 should be compatible with RHEL7 (we use that here), but not RHEL6 (due to outdated GNU C libraries). |
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Update on the ASAP7 Calibre decks. I sent an email to the ASAP7 project leader asking for help, and he replied that the Calibre deck is pulled off from the site for now. |
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Did he give any reason why? This is quite important for people wanting to use the PDK... Anyways, I think I might actually implement the |
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I'd love for you to review the VCS parallelism PR: ucb-bar/hammer-synopsys-plugins#23 (I can't add you as a reviewer directly). |
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Yes, there are some issues/concerns with files being distributed on GitHub.
Sure! I can run simulation under If I turn the dramsim off, the result is still the same. /home/ethan/Downloads/chipyard/vlsi/build/chipyard.TestHarness.SmallBoomConfig-ChipTop/sim-rtl-rundir/simv +permissive +dramsim +dramsim_ini_dir=/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +permissive-off /home/ethan/Downloads/chipyard/riscv-tools-install/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09_Full64; Runtime version S-2021.09_Full64; Apr 2 03:41 2022
[UART] UART0 is here (stdin/stdout).
== Loading device model file '/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini' ==
== Loading system model file '/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/system.ini' ==
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 4096MB | 1 Ranks | 16 Devices per rank
DRAMSim2 Clock Frequency =666666666Hz, CPU Clock Frequency=100000000Hz
Fatal: "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/chipyard.TestHarness.SmallBoomConfig.top.v", 191091: TestDriver.testHarness.chiptop.system.tile_prci_domain.tile_reset_domain.boom_tile.frontend.icache: at time 2913500000 fs
$finish called from file "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/chipyard.TestHarness.SmallBoomConfig.top.v", line 191091.
$finish at simulation time 29135000
V C S S i m u l a t i o n R e p o r t
Time: 2913500000 fs
CPU Time: 1.340 seconds; Data structure size: 14.0Mb
Sat Apr 2 03:41:41 2022The top Verilog file `ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (~(_T_9 <= 3'h1 | ~s1_valid) & ~reset) begin
$fatal; // @[icache.scala 206:9]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_9 <= 3'h1 | ~s1_valid)) begin
$fwrite(32'h80000002,
"Assertion failed\n at icache.scala:206 assert(PopCount(s1_tag_hit) <= 1.U || !s1_valid)\n"); // @[icache.scala 206:9]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
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Weird. The whole point of requesting the decks was that it was not distributed on Github along with the rest of the PDK.
Not quite. There is a difference between running RTL simulation in I haven't seen this particular issue before, and it looks like it has something to do with your ICache, not the simulated DRAM (hence why turning off DRAMSim didn't make a difference). Are you able to pull up the waveforms of both simulations to compare those wires ( |
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Oh also, I just noticed that you used the
After your tests, maybe also try pulling the branch of Hammer again? I hardcoded the sizes now. You will need to wipe/regenerate the SRAMs. |
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I tried busywait/mutex/serial, and the results are identical.
Got it. |
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#changing the sim-inputs.yml file manually sim.inputs:
top_module: ChipTop
input_files:
- "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/chipyard.TestHarness.SmallBoomConfig.harness.v"
- "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/chipyard.TestHarness.SmallBoomConfig.harness.mems.v"
input_files_meta: 'append'
timescale: '1ns/10ps'
options:
- "-notice"
- "-line"
- "+lint=all,noVCDE,noONGS,noUI"
- "-error=PCWM-L"
- "-error=noZMMCM"
- "-timescale=1ns/10ps"
- "-quiet"
- "-q"
- "+rad"
- "+vcs+lic+wait"
- "+vc+list"
- "-f"
- "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/sim_files.common.f"
- "-sverilog"
- "+systemverilogext+.sv+.svi+.svh+.svt"
- "-assert"
- "svaext"
- "+libext+.sv"
- "+v2k"
- "+verilog2001ext+.v95+.vt+.vp"
- "+libext+.v"
- "-debug_pp"
- "+incdir+/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig"
- "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/chipyard.TestHarness.SmallBoomConfig.top.v"
- "/home/ethan/Downloads/chipyard/sims/vcs/generated-src/chipyard.TestHarness.SmallBoomConfig/chipyard.TestHarness.SmallBoomConfig.top.mems.v"
options_meta: 'append'
defines:
- "VCS"
- "CLOCK_PERIOD=1.0"
- "RESET_DELAY=777.7"
- "PRINTF_COND=TestDriver.printf_cond"
- "STOP_COND=!TestDriver.reset"
- "MODEL=TestHarness"
- "RANDOMIZE_MEM_INIT"
- "RANDOMIZE_REG_INIT"
- "RANDOMIZE_GARBAGE_ASSIGN"
- "RANDOMIZE_INVALID_ASSIGN"
defines_meta: 'append'
compiler_cc_opts:
- "-O3"
- "-std=c++11"
- "-I/home/ethan/Downloads/chipyard/riscv-tools-install/include"
- "-I/home/ethan/Downloads/chipyard/tools/DRAMSim2"
- "-I/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig"
compiler_cc_opts_meta: 'append'
compiler_ld_opts:
- "-L/home/ethan/Downloads/chipyard/riscv-tools-install/lib"
- "-Wl,-rpath,/home/ethan/Downloads/chipyard/riscv-tools-install/lib"
- "-L/home/ethan/Downloads/chipyard/vlsi"
- "-L/home/ethan/Downloads/chipyard/tools/DRAMSim2"
- "-lfesvr"
- "-ldramsim"
compiler_ld_opts_meta: 'append'
execution_flags_prepend: ['+permissive']
execution_flags_append: ['+permissive-off']
execution_flags:
- "+dramsim"
- "+dramsim_ini_dir=/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini"
- "+max-cycles=10000000"
execution_flags_meta: 'append'
benchmarks: ['/home/ethan/Downloads/chipyard/riscv-tools-install/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add']
tb_dut: 'TestDriver.testHarness.chiptop'
I use the command: ./example-vlsi \
-e /home/ethan/Downloads/chipyard/vlsi/env.yml \
-p /home/ethan/Downloads/chipyard/vlsi/example-tools.yml \
-p /home/ethan/Downloads/chipyard/vlsi/example-asap7.yml \
-p /home/ethan/Downloads/chipyard/vlsi/build/chipyard.TestHarness.SmallBoomConfig-ChipTop/sram_generator-output.json \
-p /home/ethan/Downloads/chipyard/vlsi/build/chipyard.TestHarness.SmallBoomConfig-ChipTop/sim-debug-inputs.yml \
-p /home/ethan/Downloads/chipyard/vlsi/build/chipyard.TestHarness.SmallBoomConfig-ChipTop/sim-inputs.yml \
--sim_rundir /home/ethan/Downloads/chipyard/vlsi/build/chipyard.TestHarness.SmallBoomConfig-ChipTop/sim-rtl-rundir \
--obj_dir /home/ethan/Downloads/chipyard/vlsi/build/chipyard.TestHarness.SmallBoomConfig-ChipTop sim | tee log_file/vcs.log \If I changed the |
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One question, why do we use blocking in SRAM instead of using non-blocking? import os, tempfile, subprocess, math
from hammer_vlsi import MMMCCorner, MMMCCornerType, HammerTool, HammerToolStep, HammerSRAMGeneratorTool, SRAMParameters
from hammer_vlsi.units import VoltageValue, TemperatureValue
from hammer_tech import Library, ExtraLibrary
from typing import NamedTuple, Dict, Any, List
from abc import ABCMeta, abstractmethod
class ASAP7SRAMGenerator(HammerSRAMGeneratorTool):
def tool_config_prefix(self) -> str:
return "sram_generator.asap7"
def version_number(self, version: str) -> int:
return 0
# Run generator for a single sram and corner
def generate_sram(self, params: SRAMParameters, corner: MMMCCorner) -> ExtraLibrary:
tech_cache_dir = os.path.abspath(self.technology.cache_dir)
base_dir=os.path.join(self.tool_dir, "memories")
if params.family == "1RW" or params.family == "2RW":
fam_code = params.family
else:
self.logger.error("ASAP7 SRAM cache does not support family:{f}".format(f=params.family))
#TODO: this is really an abuse of the corner stuff
#TODO: when we have matching corners remove real_corner and symlink junk
if corner.type == MMMCCornerType.Setup:
speed_name = "slow"
elif corner.type == MMMCCornerType.Hold:
speed_name = "fast"
elif corner.type == MMMCCornerType.Extra:
speed_name = "typical"
corner_str = "PVT_{volt}V_{temp}C".format(
volt = str(corner.voltage.value_in_units("V")).replace(".","P"),
temp = str(int(corner.temp.value_in_units("C"))).replace(".","P"))
sram_name = "SRAM{fc}{d}x{w}".format(
fc=fam_code,
d=params.depth,
w=params.width)
# Generate Verilog file from template
verilog_path ="{t}/{n}.v".format(t=tech_cache_dir,n=sram_name)
with open(verilog_path, 'w') as f:
if params.family == "1RW":
f.write("""
`timescale 1ns/100fs
module {NAME} (A,CE,WEB,OEB,CSB,I,O);
input CE;
input WEB;
input OEB;
input CSB;
input [{NUMADDR}-1:0] A;
input [{WORDLENGTH}-1:0] I;
output [{WORDLENGTH}-1:0] O;
reg [{WORDLENGTH}-1:0] memory[{NUMWORDS}-1:0];
reg [{WORDLENGTH}-1:0] data_out;
wire [{WORDLENGTH}-1:0] O;
wire RE;
wire WE;
and u1 (RE, ~CSB, ~OEB);
and u2 (WE, ~CSB, ~WEB);
// Initialization for simulation
integer i;
initial begin
for (i = 0; i < {NUMWORDS}; i = i + 1) begin
memory[i] = {{{RAND_WIDTH}{{$urandom_range(2**{WORDLENGTH}-1)}}}}[{WORDLENGTH}-1:0];
end
data_out = {{{RAND_WIDTH}{{$urandom_range(2**{WORDLENGTH}-1)}}}}[{WORDLENGTH}-1:0];
end
always @ (posedge CE) begin
if (RE)
data_out <= memory[A];
if (WE)
memory[A] <= I;
end
assign O = data_out;
endmodule
""".format(NUMADDR=math.ceil(math.log2(params.depth)), NUMWORDS=params.depth, WORDLENGTH=params.width, NAME=sram_name, RAND_WIDTH=math.ceil(params.width/32)))
else:
f.write("""
`timescale 1ns/100fs
module {NAME} (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
input CE1;
input CE2;
input WEB1;
input WEB2;
input OEB1;
input OEB2;
input CSB1;
input CSB2;
input [{NUMADDR}-1:0] A1;
input [{NUMADDR}-1:0] A2;
input [{WORDLENGTH}-1:0] I1;
input [{WORDLENGTH}-1:0] I2;
output [{WORDLENGTH}-1:0] O1;
output [{WORDLENGTH}-1:0] O2;
reg [{WORDLENGTH}-1:0] memory[{NUMWORDS}-1:0];
reg [{WORDLENGTH}-1:0] data_out1;
reg [{WORDLENGTH}-1:0] data_out2;
wire [{WORDLENGTH}-1:0] O1;
wire [{WORDLENGTH}-1:0] O2;
wire RE1;
wire RE2;
wire WE1;
wire WE2;
and u1 (RE1, ~CSB1, ~OEB1);
and u2 (RE2, ~CSB2, ~OEB2);
and u3 (WE1, ~CSB1, ~WEB1);
and u4 (WE2, ~CSB2, ~WEB2);
// Initialization for simulation
integer i;
initial begin
for (i = 0; i < {NUMWORDS}; i = i + 1) begin
memory[i] = {{{RAND_WIDTH}{{$urandom_range(2**{WORDLENGTH}-1)}}}}[{WORDLENGTH}-1:0];
end
data_out1 = {{{RAND_WIDTH}{{$urandom_range(2**{WORDLENGTH}-1)}}}}[{WORDLENGTH}-1:0];
data_out2 = {{{RAND_WIDTH}{{$urandom_range(2**{WORDLENGTH}-1)}}}}[{WORDLENGTH}-1:0];
end
always @ (posedge CE1) begin
if (RE1)
data_out1 <= memory[A1];
if (WE1)
memory[A1] <= I1;
end
always @ (posedge CE2) begin
if (RE2)
data_out2 <= memory[A2];
if (WE2)
memory[A2] <= I2;
end
assign O1 = data_out1;
assign O2 = data_out2;
endmodule
""".format(NUMADDR=math.ceil(math.log2(params.depth)), NUMWORDS=params.depth, WORDLENGTH=params.width, NAME=sram_name, RAND_WIDTH=math.ceil(params.width/32)))
#lib_path ="{t}/{n}_{c}.lib".format(t=tech_cache_dir,n=sram_name,c=corner_str)
#if not os.path.exists(lib_path):
# os.symlink("{b}/lib/{n}_lib/{n}_{c}.lib".format(b=base_dir,n=sram_name,c=corner_str), "{t}/{n}_{c}.lib".format(t=tech_cache_dir,n=sram_name,c=corner_str))
lib = ExtraLibrary(prefix=None, library=Library(
name=sram_name,
nldm_liberty_file="{b}/lib/{n}_lib/{n}_{c}.lib".format(b=base_dir,n=sram_name,c=corner_str),
lef_file="{b}/lef/{n}_x4.lef".format(b=base_dir,n=sram_name),
gds_file="{b}/gds/{n}_x4.gds".format(b=base_dir,n=sram_name),
#verilog_sim="{b}/behavioral/sram_behav_models.v".format(b=base_dir),
verilog_sim=verilog_path,
corner = {'nmos': speed_name, 'pmos': speed_name, 'temperature': str(corner.temp.value_in_units("C")) +" C"},
supplies = {'VDD': str(corner.voltage.value_in_units("V")) + " V", 'GND': "0 V" },
provides = [{'lib_type': "sram", 'vt': params.vt}])) # type: ExtraLibrary
return lib
tool=ASAP7SRAMGeneratorresult Executing subprocess: /home/ethan/Downloads/chipyard/vlsi/build/chipyard.TestHarness.SmallBoomConfig-ChipTop/sim-rtl-rundir/simv +permissive -fgp=num_threads:1 +verbose +vcdplusfile=/home/ethan/Downloads/chipyard/vlsi/output/chipyard.TestHarness.SmallBoomConfig/rv64ui-p-add.vpd +dramsim +dramsim_ini_dir=/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +permissive-off /home/ethan/Downloads/chipyard/riscv-tools-install/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09_Full64; Runtime version S-2021.09_Full64; Apr 18 03:55 2022
Warning : License for product VCSMXRunTime_Net(774) will expire within 27 days, on: 14-may-2022.
If you would like to temporarily disable this message, set
the VCS_LIC_EXPIRE_WARNING environment variable to the number of days
before expiration that you want this message to start (the minimum is 0).
Warning : License for product VCSRuntime_Net(724) will expire within 27 days, on: 14-may-2022.
If you would like to temporarily disable this message, set
the VCS_LIC_EXPIRE_WARNING environment variable to the number of days
before expiration that you want this message to start (the minimum is 0).
[UART] UART0 is here (stdin/stdout).
testing $random 86561c0c seed 1
VCD+ Writer S-2021.09_Full64 Copyright (c) 1991-2021 by Synopsys Inc.
== Loading device model file '/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini' ==
== Loading system model file '/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/system.ini' ==
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 4096MB | 1 Ranks | 16 Devices per rank
DRAMSim2 Clock Frequency =666666666Hz, CPU Clock Frequency=100000000Hz
*** PASSED *** Completed after 11513 simulation cycles
$finish called from file "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/TestDriver.v", line 158.
$finish at simulation time 115125000
V C S S i m u l a t i o n R e p o r t
Time: 11512500000 fs
CPU Time: 7.790 seconds; Data structure size: 5.4Mb
Mon Apr 18 03:55:09 2022
{
"vlsi.builtins.is_complete": false,
"sim.outputs.waveforms": [],
"sim.outputs.saifs": [
"/home/ethan/Downloads/chipyard/vlsi/build/chipyard.TestHarness.SmallBoomConfig-ChipTop/sim-rtl-rundir/rv64ui-p-add/ucli.saif"
]
}
Executing subprocess: /home/ethan/Downloads/chipyard/vlsi/build/chipyard.TestHarness.SmallBoomConfig-ChipTop/sim-rtl-rundir/simv +permissive -fgp=num_threads:1 +verbose +vcdplusfile=/home/ethan/Downloads/chipyard/vlsi/output/chipyard.TestHarness.SmallBoomConfig/dhrystone.vpd +dramsim +dramsim_ini_dir=/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +permissive-off /home/ethan/Downloads/chipyard/riscv-tools-install/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09_Full64; Runtime version S-2021.09_Full64; Apr 18 03:59 2022
Warning : License for product VCSMXRunTime_Net(774) will expire within 27 days, on: 14-may-2022.
If you would like to temporarily disable this message, set
the VCS_LIC_EXPIRE_WARNING environment variable to the number of days
before expiration that you want this message to start (the minimum is 0).
Warning : License for product VCSRuntime_Net(724) will expire within 27 days, on: 14-may-2022.
If you would like to temporarily disable this message, set
the VCS_LIC_EXPIRE_WARNING environment variable to the number of days
before expiration that you want this message to start (the minimum is 0).
[UART] UART0 is here (stdin/stdout).
testing $random 86561c0c seed 1
VCD+ Writer S-2021.09_Full64 Copyright (c) 1991-2021 by Synopsys Inc.
== Loading device model file '/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini' ==
== Loading system model file '/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/system.ini' ==
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 4096MB | 1 Ranks | 16 Devices per rank
DRAMSim2 Clock Frequency =666666666Hz, CPU Clock Frequency=100000000Hz
Microseconds for one run through Dhrystone: 419
Dhrystones per Second: 2382
mcycle = 210008
minstret = 196029
*** PASSED *** Completed after 312526 simulation cycles
$finish called from file "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/TestDriver.v", line 158.
$finish at simulation time 3125255000
V C S S i m u l a t i o n R e p o r t
Time: 312525500000 fs
CPU Time: 402.870 seconds; Data structure size: 5.4Mb
Mon Apr 18 04:02:49 2022
{
"vlsi.builtins.is_complete": false,
"sim.outputs.waveforms": [],
"sim.outputs.saifs": [
"/home/ethan/Downloads/chipyard/vlsi/build/chipyard.TestHarness.SmallBoomConfig-ChipTop/sim-rtl-rundir/dhrystone.riscv/ucli.saif"
]
}
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Oh my, I don't know how I completely overlooked this. Of course, it has to be non-blocking in the section synchronous with CE! I will fix that and make a PR. Also, it's interesting how the FGP barely makes a difference, and even gets worse with high theread count. |
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Yes, the performance of FGP is not very linear along with the number of threads. I also fix the lint warning by |
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I'm not sure I see how this works? What's |
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Great, thanks! So with these fixes, I hope we finally resolved all the issues with using VCS FGP? |
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I hope so! I will run some tests this week and see if there is any issue. |
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I encounter this problem when I do sim-syn simultaion. could you please tell me how can I fix this? |
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I just remove the -fgp flag. I have not came up with any fix yet. |
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I run into errors on simulation with fgp, and my workstation is same as yours: |
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Hi,
I want to ask a few questions about using hammer with the chipyard.
make buildfileneeds the deck file.*I use
.eduinstead of.edu.twemail to request the Calibre deck and still no response yet.make buildfileundervlsi/. It will say that it cannot compile the memory.For now, I just want to synthesize the design and calculate its netlist simulation performance.
Thank you.
Best regards,
Waxpple
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All reactions