Casting to logic of specified bit length

[anantajit]

I'm trying to cast var s: logic<5> into var x: logic<32>.

However, when I use the syntax x = s as 32, Veryl generates a syntax error.

For now, I'm using the following workaround:

local width: u32 = 5;
...
assign x = s as width

Is there a more elegant way to achieve this?

[dalance]

Cast to built-in types is not supported now, and discussed on #499.
Or more simplified and specialized syntax for bit width conversion may be useful.