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mir-gen-ppc64.c
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mir-gen-ppc64.c
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/* This file is a part of MIR project.
Copyright (C) 2020-2024 Vladimir Makarov <[email protected]>.
*/
#include "mir-ppc64.h"
#include <limits.h>
/* We don't use TOC. So r2 is not necessary for the generated code. */
static void fancy_abort (int code) {
if (!code) abort ();
}
#undef gen_assert
#define gen_assert(c) fancy_abort (c)
#define TARGET_EXPAND_ADDO
#define TARGET_EXPAND_ADDOS
#define TARGET_EXPAND_UADDO
#define TARGET_EXPAND_UADDOS
#define TARGET_EXPAND_MULO
#define TARGET_EXPAND_MULOS
#define TARGET_EXPAND_UMULO
#define TARGET_EXPAND_UMULOS
static const MIR_reg_t LINK_HARD_REG = LR_HARD_REG;
static inline MIR_reg_t target_nth_loc (MIR_reg_t loc, MIR_type_t type MIR_UNUSED, int n) {
return loc + n;
}
static inline int target_call_used_hard_reg_p (MIR_reg_t hard_reg, MIR_type_t type MIR_UNUSED) {
assert (hard_reg <= MAX_HARD_REG);
return ((R0_HARD_REG <= hard_reg && hard_reg <= R13_HARD_REG)
|| (F0_HARD_REG <= hard_reg && hard_reg <= F13_HARD_REG));
}
static MIR_reg_t target_get_stack_slot_base_reg (gen_ctx_t gen_ctx MIR_UNUSED) {
return FP_HARD_REG;
}
/* Stack layout (r1(sp) refers to the last reserved stack slot
address) from higher address to lower address memory:
+-> Back chain BE LE
| Floating point register save area optional optional
| General register save area optional optional
| VRSAVE save word (32-bits) 0 NA
| Alignment padding (4 or 12 bytes)
| Vector register save area (quadword aligned) we don't have it
| Local variable space optional optional
| Parameter save area (for callees) (SP + 48) (SP + 32) optional
| TOC save area (SP + 40) (SP + 24)
| link editor doubleword (we don't use it) (SP + 32) NA
| compiler doubleword (we don't use it) (SP + 24) NA
| LR save area (used by callee) (SP + 16) (SP + 16)
| CR save area (SP + 8) (SP + 8)
SP,R31->+-- Back chain (SP + 0) (SP + 0)
Alloca area (after that new 48 or 32 bytes header should be created with new values)
Originally SP(r1) and FP (r31) are the same but r1 can be changed by alloca */
/* ppc64 has 3-ops insns */
static const MIR_insn_code_t target_io_dup_op_insn_codes[] = {MIR_INSN_BOUND};
static MIR_insn_code_t get_ext_code (MIR_type_t type) {
switch (type) {
case MIR_T_I8: return MIR_EXT8;
case MIR_T_U8: return MIR_UEXT8;
case MIR_T_I16: return MIR_EXT16;
case MIR_T_U16: return MIR_UEXT16;
case MIR_T_I32: return MIR_EXT32;
case MIR_T_U32: return MIR_UEXT32;
default: return MIR_INVALID_INSN;
}
}
struct insn_pattern_info {
int start, num;
};
typedef struct insn_pattern_info insn_pattern_info_t;
DEF_VARR (insn_pattern_info_t);
enum branch_type { BRCOND, JUMP, LADDR, BCTR };
struct label_ref {
int abs_addr_p;
enum branch_type branch_type;
size_t label_val_disp;
union {
MIR_label_t label;
void *jump_addr; /* absolute addr for BBV */
} u;
};
typedef struct label_ref label_ref_t;
DEF_VARR (label_ref_t);
struct target_ctx {
unsigned char alloca_p, block_arg_func_p, leaf_p, switch_p, laddr_p, short_bb_branch_p;
size_t param_save_area_size;
MIR_insn_t temp_jump;
const char *temp_jump_replacement;
VARR (int) * pattern_indexes;
VARR (insn_pattern_info_t) * insn_pattern_info;
VARR (uint8_t) * result_code;
VARR (label_ref_t) * label_refs;
VARR (uint64_t) * abs_address_locs;
VARR (MIR_code_reloc_t) * relocs;
};
#define alloca_p gen_ctx->target_ctx->alloca_p
#define block_arg_func_p gen_ctx->target_ctx->block_arg_func_p
#define leaf_p gen_ctx->target_ctx->leaf_p
#define switch_p gen_ctx->target_ctx->switch_p
#define laddr_p gen_ctx->target_ctx->laddr_p
#define short_bb_branch_p gen_ctx->target_ctx->short_bb_branch_p
#define param_save_area_size gen_ctx->target_ctx->param_save_area_size
#define temp_jump gen_ctx->target_ctx->temp_jump
#define temp_jump_replacement gen_ctx->target_ctx->temp_jump_replacement
#define pattern_indexes gen_ctx->target_ctx->pattern_indexes
#define insn_pattern_info gen_ctx->target_ctx->insn_pattern_info
#define result_code gen_ctx->target_ctx->result_code
#define label_refs gen_ctx->target_ctx->label_refs
#define abs_address_locs gen_ctx->target_ctx->abs_address_locs
#define relocs gen_ctx->target_ctx->relocs
static void gen_mov (gen_ctx_t gen_ctx, MIR_insn_t anchor, MIR_insn_code_t code, MIR_op_t dst_op,
MIR_op_t src_op) {
gen_add_insn_before (gen_ctx, anchor, MIR_new_insn (gen_ctx->ctx, code, dst_op, src_op));
}
static void mir_blk_mov (uint64_t *to, uint64_t *from, uint64_t nwords) {
for (; nwords > 0; nwords--) *to++ = *from++;
}
static const char *BLK_MOV = "mir.blk_mov";
static const char *BLK_MOV_P = "mir.blk_mov.p";
static void gen_blk_mov (gen_ctx_t gen_ctx, MIR_insn_t anchor, size_t to_disp,
MIR_reg_t to_base_hard_reg, size_t from_disp, MIR_reg_t from_base_reg,
size_t qwords, int save_regs) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_func_t func = curr_func_item->u.func;
MIR_item_t proto_item, func_import_item;
MIR_insn_t new_insn;
MIR_op_t ops[5], freg_op, treg_op, treg_op2, treg_op3;
treg_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
if (qwords <= 16) {
for (; qwords > 0; qwords--, to_disp += 8, from_disp += 8) {
gen_mov (gen_ctx, anchor, MIR_MOV, treg_op,
_MIR_new_var_mem_op (ctx, MIR_T_I64, from_disp, from_base_reg, MIR_NON_VAR, 1));
gen_mov (gen_ctx, anchor, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_I64, to_disp, to_base_hard_reg, MIR_NON_VAR, 1),
treg_op);
}
return;
}
treg_op2 = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
treg_op3 = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
/* Save arg regs: */
if (save_regs > 0) gen_mov (gen_ctx, anchor, MIR_MOV, treg_op, _MIR_new_var_op (ctx, 3));
if (save_regs > 1) gen_mov (gen_ctx, anchor, MIR_MOV, treg_op2, _MIR_new_var_op (ctx, 4));
if (save_regs > 2) gen_mov (gen_ctx, anchor, MIR_MOV, treg_op3, _MIR_new_var_op (ctx, 5));
/* call blk move: */
proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, BLK_MOV_P, 0, NULL, 3, MIR_T_I64,
"to", MIR_T_I64, "from", MIR_T_I64, "nwords");
func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, BLK_MOV, mir_blk_mov);
freg_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
new_insn = MIR_new_insn (ctx, MIR_MOV, freg_op, MIR_new_ref_op (ctx, func_import_item));
gen_add_insn_before (gen_ctx, anchor, new_insn);
gen_add_insn_before (gen_ctx, anchor,
MIR_new_insn (gen_ctx->ctx, MIR_ADD, _MIR_new_var_op (ctx, 3),
_MIR_new_var_op (ctx, to_base_hard_reg),
MIR_new_int_op (ctx, to_disp)));
gen_add_insn_before (gen_ctx, anchor,
MIR_new_insn (gen_ctx->ctx, MIR_ADD, _MIR_new_var_op (ctx, 4),
_MIR_new_var_op (ctx, from_base_reg),
MIR_new_int_op (ctx, from_disp)));
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_var_op (ctx, 5), MIR_new_int_op (ctx, qwords));
ops[0] = MIR_new_ref_op (ctx, proto_item);
ops[1] = freg_op;
ops[2] = _MIR_new_var_op (ctx, 3);
ops[3] = _MIR_new_var_op (ctx, 4);
ops[4] = _MIR_new_var_op (ctx, 5);
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, 5, ops);
gen_add_insn_before (gen_ctx, anchor, new_insn);
/* Restore arg regs: */
if (save_regs > 0) gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_var_op (ctx, 3), treg_op);
if (save_regs > 1) gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_var_op (ctx, 4), treg_op2);
if (save_regs > 2) gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_var_op (ctx, 5), treg_op3);
}
static void machinize_call (gen_ctx_t gen_ctx, MIR_insn_t call_insn) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_func_t func = curr_func_item->u.func;
MIR_proto_t proto = call_insn->ops[0].u.ref->u.proto;
int vararg_p = proto->vararg_p;
size_t qwords, disp, nargs, nops = MIR_insn_nops (ctx, call_insn), start = proto->nres + 2;
size_t mem_size = 0, n_iregs = 0, n_fregs = 0;
MIR_type_t type, mem_type;
MIR_op_mode_t mode;
MIR_var_t *arg_vars = NULL;
MIR_reg_t ret_reg;
MIR_op_t arg_op, temp_op, arg_reg_op, ret_reg_op, mem_op;
MIR_insn_code_t new_insn_code, ext_code;
MIR_insn_t new_insn, ext_insn;
if (call_insn->code == MIR_INLINE) call_insn->code = MIR_CALL;
if (proto->args == NULL) {
nargs = 0;
} else {
gen_assert (nops >= VARR_LENGTH (MIR_var_t, proto->args)
&& (vararg_p || nops - start == VARR_LENGTH (MIR_var_t, proto->args)));
nargs = VARR_LENGTH (MIR_var_t, proto->args);
arg_vars = VARR_ADDR (MIR_var_t, proto->args);
}
if (call_insn->ops[1].mode != MIR_OP_VAR) {
// ??? to optimize (can be immediate operand for func call)
temp_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
new_insn = MIR_new_insn (ctx, MIR_MOV, temp_op, call_insn->ops[1]);
call_insn->ops[1] = temp_op;
gen_add_insn_before (gen_ctx, call_insn, new_insn);
}
for (size_t i = start; i < nops; i++) {
arg_op = call_insn->ops[i];
gen_assert (arg_op.mode == MIR_OP_VAR
|| (arg_op.mode == MIR_OP_VAR_MEM && MIR_all_blk_type_p (arg_op.u.mem.type)));
if (i - start < nargs) {
type = arg_vars[i - start].type;
} else if (call_insn->ops[i].mode == MIR_OP_VAR_MEM) {
type = arg_op.u.mem.type;
gen_assert (MIR_all_blk_type_p (type));
} else {
mode = call_insn->ops[i].value_mode; // ??? smaller ints
gen_assert (mode == MIR_OP_INT || mode == MIR_OP_UINT || mode == MIR_OP_FLOAT
|| mode == MIR_OP_DOUBLE || mode == MIR_OP_LDOUBLE);
if (mode == MIR_OP_FLOAT)
(*MIR_get_error_func (ctx)) (MIR_call_op_error,
"passing float variadic arg (should be passed as double)");
type = mode == MIR_OP_DOUBLE ? MIR_T_D : mode == MIR_OP_LDOUBLE ? MIR_T_LD : MIR_T_I64;
}
ext_insn = NULL;
if ((ext_code = get_ext_code (type)) != MIR_INVALID_INSN) { /* extend arg if necessary */
temp_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
ext_insn = MIR_new_insn (ctx, ext_code, temp_op, arg_op);
call_insn->ops[i] = arg_op = temp_op;
}
mem_type = type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD ? type : MIR_T_I64; // ???
if ((type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD) && n_fregs < 13) {
/* put arguments to argument hard regs */
if (ext_insn != NULL) gen_add_insn_before (gen_ctx, call_insn, ext_insn);
arg_reg_op = _MIR_new_var_op (ctx, F1_HARD_REG + n_fregs);
gen_mov (gen_ctx, call_insn,
type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV
: MIR_LDMOV, // ???
arg_reg_op, arg_op);
call_insn->ops[i] = arg_reg_op;
if (vararg_p) { // ??? dead insns
if (n_iregs >= 8 || (type == MIR_T_LD && n_iregs == 7)) { /* store in memory too */
mem_op = _MIR_new_var_mem_op (ctx, mem_type, mem_size + PPC64_STACK_HEADER_SIZE,
SP_HARD_REG, MIR_NON_VAR, 1);
gen_assert (n_fregs < 12);
gen_mov (gen_ctx, call_insn, type == MIR_T_LD ? MIR_LDMOV : MIR_DMOV, mem_op, arg_reg_op);
}
if (n_iregs < 8) { /* load into gp reg too */
mem_op = _MIR_new_var_mem_op (ctx, mem_type, -16, SP_HARD_REG, MIR_NON_VAR, 1);
gen_mov (gen_ctx, call_insn, type == MIR_T_LD ? MIR_LDMOV : MIR_DMOV, mem_op, arg_reg_op);
mem_type = mem_type == MIR_T_F ? MIR_T_I32 : MIR_T_I64; // ???
mem_op = _MIR_new_var_mem_op (ctx, mem_type, -16, SP_HARD_REG, MIR_NON_VAR, 1);
arg_reg_op = _MIR_new_var_op (ctx, R3_HARD_REG + n_iregs);
gen_mov (gen_ctx, call_insn, MIR_MOV, arg_reg_op, mem_op);
call_insn->ops[i] = arg_reg_op; /* keep it alive */
if (type == MIR_T_LD && n_iregs + 1 < 8) {
mem_op = _MIR_new_var_mem_op (ctx, mem_type, -8, SP_HARD_REG, MIR_NON_VAR, 1);
gen_mov (gen_ctx, call_insn, MIR_MOV, _MIR_new_var_op (ctx, R3_HARD_REG + n_iregs + 1),
mem_op);
}
}
}
n_fregs += type == MIR_T_LD ? 2 : 1;
} else if (MIR_blk_type_p (type)) {
gen_assert (arg_op.mode == MIR_OP_VAR_MEM && arg_op.u.mem.disp >= 0
&& arg_op.u.mem.index == MIR_NON_VAR);
qwords = (arg_op.u.mem.disp + 7) / 8;
for (disp = 0; qwords > 0 && n_iregs < 8; qwords--, n_iregs++, mem_size += 8, disp += 8) {
arg_reg_op = _MIR_new_var_op (ctx, R3_HARD_REG + n_iregs);
gen_mov (gen_ctx, call_insn, MIR_MOV, arg_reg_op,
_MIR_new_var_mem_op (ctx, MIR_T_I64, disp, arg_op.u.mem.base, MIR_NON_VAR, 1));
setup_call_hard_reg_args (gen_ctx, call_insn, R3_HARD_REG + n_iregs);
}
if (qwords > 0)
gen_blk_mov (gen_ctx, call_insn, mem_size + PPC64_STACK_HEADER_SIZE, SP_HARD_REG, disp,
arg_op.u.mem.base, qwords, n_iregs);
mem_size += qwords * 8;
n_iregs += qwords;
continue;
} else if (type != MIR_T_F && type != MIR_T_D && type != MIR_T_LD && n_iregs < 8) {
if (ext_insn != NULL) gen_add_insn_before (gen_ctx, call_insn, ext_insn);
arg_reg_op = _MIR_new_var_op (ctx, R3_HARD_REG + n_iregs);
if (type != MIR_T_RBLK) {
gen_mov (gen_ctx, call_insn, MIR_MOV, arg_reg_op, arg_op);
} else {
assert (arg_op.mode == MIR_OP_VAR_MEM);
gen_mov (gen_ctx, call_insn, MIR_MOV, arg_reg_op, _MIR_new_var_op (ctx, arg_op.u.mem.base));
arg_reg_op = _MIR_new_var_mem_op (ctx, MIR_T_RBLK, arg_op.u.mem.disp, R3_HARD_REG + n_iregs,
MIR_NON_VAR, 1);
}
call_insn->ops[i] = arg_reg_op;
} else { /* put arguments on the stack */
if (ext_insn != NULL) gen_add_insn_before (gen_ctx, call_insn, ext_insn);
new_insn_code = (type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV
: type == MIR_T_LD ? MIR_LDMOV
: MIR_MOV);
mem_op = _MIR_new_var_mem_op (ctx, mem_type, mem_size + PPC64_STACK_HEADER_SIZE, SP_HARD_REG,
MIR_NON_VAR, 1);
if (type != MIR_T_RBLK) {
gen_mov (gen_ctx, call_insn, new_insn_code, mem_op, arg_op);
} else {
assert (arg_op.mode == MIR_OP_VAR_MEM);
gen_mov (gen_ctx, call_insn, new_insn_code, mem_op,
_MIR_new_var_op (ctx, arg_op.u.mem.base));
}
call_insn->ops[i] = mem_op;
}
mem_size += type == MIR_T_LD ? 16 : 8;
n_iregs += type == MIR_T_LD ? 2 : 1;
}
if (vararg_p && mem_size < 64) mem_size = 64; /* to save all arg gprs */
if (param_save_area_size < mem_size) param_save_area_size = mem_size;
n_iregs = n_fregs = 0;
for (size_t i = 0; i < proto->nres; i++) {
ret_reg_op = call_insn->ops[i + 2];
gen_assert (ret_reg_op.mode == MIR_OP_VAR);
type = proto->res_types[i];
if (((type == MIR_T_F || type == MIR_T_D) && n_fregs < 4)
|| (type == MIR_T_LD && n_fregs < 3)) {
new_insn_code = type == MIR_T_F ? MIR_FMOV : type == MIR_T_D ? MIR_DMOV : MIR_LDMOV;
ret_reg = F1_HARD_REG + n_fregs++;
} else if (n_iregs < 8) {
new_insn_code = MIR_MOV;
ret_reg = R3_HARD_REG + n_iregs++;
} else {
(*MIR_get_error_func (ctx)) (MIR_ret_error,
"ppc64 can not handle this combination of return values");
}
new_insn = MIR_new_insn (ctx, new_insn_code, ret_reg_op, _MIR_new_var_op (ctx, ret_reg));
MIR_insert_insn_after (ctx, curr_func_item, call_insn, new_insn);
call_insn->ops[i + 2] = new_insn->ops[1];
if ((ext_code = get_ext_code (type)) != MIR_INVALID_INSN) {
MIR_insert_insn_after (ctx, curr_func_item, new_insn,
MIR_new_insn (ctx, ext_code, ret_reg_op, ret_reg_op));
new_insn = DLIST_NEXT (MIR_insn_t, new_insn);
}
create_new_bb_insns (gen_ctx, call_insn, DLIST_NEXT (MIR_insn_t, new_insn), call_insn);
}
}
static long double mir_i2ld (int64_t i) { return i; }
static const char *I2LD = "mir.i2ld";
static const char *I2LD_P = "mir.i2ld.p";
static long double mir_ui2ld (uint64_t i) { return i; }
static const char *UI2LD = "mir.ui2ld";
static const char *UI2LD_P = "mir.ui2ld.p";
static long double mir_f2ld (float f) { return f; }
static const char *F2LD = "mir.f2ld";
static const char *F2LD_P = "mir.f2ld.p";
static long double mir_d2ld (double d) { return d; }
static const char *D2LD = "mir.d2ld";
static const char *D2LD_P = "mir.d2ld.p";
static int64_t mir_ld2i (long double ld) { return ld; }
static const char *LD2I = "mir.ld2i";
static const char *LD2I_P = "mir.ld2i.p";
static float mir_ld2f (long double ld) { return ld; }
static const char *LD2F = "mir.ld2f";
static const char *LD2F_P = "mir.ld2f.p";
static double mir_ld2d (long double ld) { return ld; }
static const char *LD2D = "mir.ld2d";
static const char *LD2D_P = "mir.ld2d.p";
static long double mir_ldadd (long double d1, long double d2) { return d1 + d2; }
static const char *LDADD = "mir.ldadd";
static const char *LDADD_P = "mir.ldadd.p";
static long double mir_ldsub (long double d1, long double d2) { return d1 - d2; }
static const char *LDSUB = "mir.ldsub";
static const char *LDSUB_P = "mir.ldsub.p";
static long double mir_ldmul (long double d1, long double d2) { return d1 * d2; }
static const char *LDMUL = "mir.ldmul";
static const char *LDMUL_P = "mir.ldmul.p";
static long double mir_lddiv (long double d1, long double d2) { return d1 / d2; }
static const char *LDDIV = "mir.lddiv";
static const char *LDDIV_P = "mir.lddiv.p";
static long double mir_ldneg (long double d) { return -d; }
static const char *LDNEG = "mir.ldneg";
static const char *LDNEG_P = "mir.ldneg.p";
static const char *VA_ARG_P = "mir.va_arg.p";
static const char *VA_ARG = "mir.va_arg";
static const char *VA_BLOCK_ARG_P = "mir.va_block_arg.p";
static const char *VA_BLOCK_ARG = "mir.va_block_arg";
static int64_t mir_ldeq (long double d1, long double d2) { return d1 == d2; }
static const char *LDEQ = "mir.ldeq";
static const char *LDEQ_P = "mir.ldeq.p";
static int64_t mir_ldne (long double d1, long double d2) { return d1 != d2; }
static const char *LDNE = "mir.ldne";
static const char *LDNE_P = "mir.ldne.p";
static int64_t mir_ldlt (long double d1, long double d2) { return d1 < d2; }
static const char *LDLT = "mir.ldlt";
static const char *LDLT_P = "mir.ldlt.p";
static int64_t mir_ldge (long double d1, long double d2) { return d1 >= d2; }
static const char *LDGE = "mir.ldge";
static const char *LDGE_P = "mir.ldge.p";
static int64_t mir_ldgt (long double d1, long double d2) { return d1 > d2; }
static const char *LDGT = "mir.ldgt";
static const char *LDGT_P = "mir.ldgt.p";
static int64_t mir_ldle (long double d1, long double d2) { return d1 <= d2; }
static const char *LDLE = "mir.ldle";
static const char *LDLE_P = "mir.ldle.p";
static int get_builtin (gen_ctx_t gen_ctx, MIR_insn_code_t code, MIR_item_t *proto_item,
MIR_item_t *func_import_item) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_type_t res_type;
*func_import_item = *proto_item = NULL; /* to remove uninitialized warning */
switch (code) {
case MIR_I2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, I2LD_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, I2LD, mir_i2ld);
return 1;
case MIR_UI2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, UI2LD_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, UI2LD, mir_ui2ld);
return 1;
case MIR_F2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, F2LD_P, 1, &res_type, 1, MIR_T_F, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, F2LD, mir_f2ld);
return 1;
case MIR_D2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, D2LD_P, 1, &res_type, 1, MIR_T_D, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, D2LD, mir_d2ld);
return 1;
case MIR_LD2I:
res_type = MIR_T_I64;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2I_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2I, mir_ld2i);
return 1;
case MIR_LD2F:
res_type = MIR_T_F;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2F_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2F, mir_ld2f);
return 1;
case MIR_LD2D:
res_type = MIR_T_D;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2D_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2D, mir_ld2d);
return 1;
case MIR_LDADD:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDADD_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDADD, mir_ldadd);
return 2;
case MIR_LDSUB:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDSUB_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDSUB, mir_ldsub);
return 2;
case MIR_LDMUL:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDMUL_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDMUL, mir_ldmul);
return 2;
case MIR_LDDIV:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDDIV_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDDIV, mir_lddiv);
return 2;
case MIR_LDNEG:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LDNEG_P, 1, &res_type, 1, MIR_T_LD, "d");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDNEG, mir_ldneg);
return 1;
case MIR_LDEQ:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDEQ_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDEQ, mir_ldeq);
return 2;
case MIR_LDNE:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDNE_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDNE, mir_ldne);
return 2;
case MIR_LDLT:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDLT_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDLT, mir_ldlt);
return 2;
case MIR_LDGE:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDGE_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDGE, mir_ldge);
return 2;
case MIR_LDGT:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDGT_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDGT, mir_ldgt);
return 2;
case MIR_LDLE:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDLE_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDLE, mir_ldle);
return 2;
case MIR_VA_ARG:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, VA_ARG_P, 1, &res_type, 2,
MIR_T_I64, "va", MIR_T_I64, "type");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, VA_ARG, va_arg_builtin);
return 2;
case MIR_VA_BLOCK_ARG:
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, VA_BLOCK_ARG_P, 0, NULL, 4, MIR_T_I64,
"res", MIR_T_I64, "va", MIR_T_I64, "size", MIR_T_I64, "ncase");
*func_import_item
= _MIR_builtin_func (ctx, curr_func_item->module, VA_BLOCK_ARG, va_block_arg_builtin);
return 4;
default: return 0;
}
}
static MIR_disp_t target_get_stack_slot_offset (gen_ctx_t gen_ctx, MIR_type_t type MIR_UNUSED,
MIR_reg_t slot) {
/* slot is 0, 1, ... */
return ((MIR_disp_t) slot * 8 + PPC64_STACK_HEADER_SIZE + param_save_area_size);
}
static void set_prev_sp_op (gen_ctx_t gen_ctx, MIR_insn_t anchor, MIR_op_t *prev_sp_op) {
if (!block_arg_func_p) {
/* don't use r11 as we can have spilled param<-mem in param set up which needs r11 as a temp */
block_arg_func_p = TRUE;
*prev_sp_op = _MIR_new_var_op (gen_ctx->ctx, R12_HARD_REG);
gen_mov (gen_ctx, anchor, MIR_MOV, *prev_sp_op,
_MIR_new_var_mem_op (gen_ctx->ctx, MIR_T_I64, 0, SP_HARD_REG, MIR_NON_VAR, 1));
}
}
static int target_valid_mem_offset_p (gen_ctx_t gen_ctx MIR_UNUSED, MIR_type_t type MIR_UNUSED,
MIR_disp_t offset MIR_UNUSED) {
return TRUE;
}
static void target_machinize (gen_ctx_t gen_ctx) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_func_t func;
MIR_type_t type, res_type;
MIR_insn_code_t code, new_insn_code;
MIR_insn_t insn, next_insn, new_insn, anchor;
MIR_reg_t ret_reg;
MIR_op_t ret_reg_op, arg_reg_op, prev_sp_op, temp_op, arg_var_op;
size_t i, int_arg_num, fp_arg_num, disp, var_args_start, qwords, offset;
assert (curr_func_item->item_type == MIR_func_item);
func = curr_func_item->u.func;
block_arg_func_p = FALSE;
param_save_area_size = 0;
anchor = DLIST_HEAD (MIR_insn_t, func->insns);
if (func->vararg_p)
set_prev_sp_op (gen_ctx, anchor, &prev_sp_op); /* arg can be taken from memory */
disp = PPC64_STACK_HEADER_SIZE; /* param area start in the caller frame */
for (i = int_arg_num = fp_arg_num = 0; i < func->nargs; i++) {
/* Argument extensions is already done in simplify */
/* Prologue: generate arg_var = hard_reg|stack mem ... */
type = VARR_GET (MIR_var_t, func->vars, i).type;
arg_var_op = _MIR_new_var_op (ctx, i + MAX_HARD_REG + 1);
if ((type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD) && fp_arg_num < 13) {
if (type == MIR_T_LD && fp_arg_num == 12) { /* dmov f14,disp(r1) -> lfd f14,disp(r1): */
set_prev_sp_op (gen_ctx, anchor, &prev_sp_op);
arg_reg_op = _MIR_new_var_op (ctx, F14_HARD_REG);
gen_mov (gen_ctx, anchor, MIR_DMOV, arg_reg_op,
_MIR_new_var_mem_op (ctx, MIR_T_D, disp + 8, R12_HARD_REG, MIR_NON_VAR, 1));
}
arg_reg_op = _MIR_new_var_op (ctx, F1_HARD_REG + fp_arg_num);
gen_mov (gen_ctx, anchor,
type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV
: MIR_LDMOV,
arg_var_op, arg_reg_op); /* (f|d|ld|)mov arg, arg_hard_reg */
fp_arg_num += type == MIR_T_LD ? 2 : 1;
} else if (type == MIR_T_F || type == MIR_T_D
|| type == MIR_T_LD) { /* (f|d|ld|)mov arg, arg_memory */
set_prev_sp_op (gen_ctx, anchor, &prev_sp_op);
gen_mov (gen_ctx, anchor,
type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV
: MIR_LDMOV,
arg_var_op, _MIR_new_var_mem_op (ctx, type, disp, R12_HARD_REG, MIR_NON_VAR, 1));
} else if (MIR_blk_type_p (type)) {
qwords = (VARR_GET (MIR_var_t, func->vars, i).size + 7) / 8;
offset = int_arg_num < 8 ? PPC64_STACK_HEADER_SIZE + int_arg_num * 8 : disp;
set_prev_sp_op (gen_ctx, anchor, &prev_sp_op);
for (; qwords > 0 && int_arg_num < 8; qwords--, int_arg_num++, disp += 8) {
if (!func->vararg_p)
gen_mov (gen_ctx, anchor, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_I64, PPC64_STACK_HEADER_SIZE + int_arg_num * 8,
R12_HARD_REG, MIR_NON_VAR, 1),
_MIR_new_var_op (ctx, R3_HARD_REG + int_arg_num));
}
gen_add_insn_before (gen_ctx, anchor,
MIR_new_insn (ctx, MIR_ADD, arg_var_op,
_MIR_new_var_op (ctx, R12_HARD_REG),
MIR_new_int_op (ctx, offset)));
disp += qwords * 8;
int_arg_num += qwords;
continue;
} else if (int_arg_num < 8) { /* mov arg, arg_hard_reg */
arg_reg_op = _MIR_new_var_op (ctx, R3_HARD_REG + int_arg_num);
gen_mov (gen_ctx, anchor, MIR_MOV, arg_var_op, arg_reg_op);
} else { /* mov arg, arg_memory */
set_prev_sp_op (gen_ctx, anchor, &prev_sp_op);
gen_mov (gen_ctx, anchor, MIR_MOV, arg_var_op,
_MIR_new_var_mem_op (ctx, MIR_T_I64, disp, R12_HARD_REG, MIR_NON_VAR, 1));
}
disp += type == MIR_T_LD ? 16 : 8;
int_arg_num += type == MIR_T_LD ? 2 : 1;
}
var_args_start = disp;
switch_p = laddr_p = alloca_p = FALSE;
leaf_p = TRUE;
for (insn = DLIST_HEAD (MIR_insn_t, func->insns); insn != NULL; insn = next_insn) {
MIR_item_t proto_item, func_import_item;
int nargs;
next_insn = DLIST_NEXT (MIR_insn_t, insn);
code = insn->code;
if (code == MIR_LDBEQ || code == MIR_LDBNE || code == MIR_LDBLT || code == MIR_LDBGE
|| code == MIR_LDBGT || code == MIR_LDBLE) { /* split to cmp and branch */
temp_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
code = (code == MIR_LDBEQ ? MIR_LDEQ
: code == MIR_LDBNE ? MIR_LDNE
: code == MIR_LDBLT ? MIR_LDLT
: code == MIR_LDBGE ? MIR_LDGE
: code == MIR_LDBGT ? MIR_LDGT
: MIR_LDLE);
new_insn = MIR_new_insn (ctx, code, temp_op, insn->ops[1], insn->ops[2]);
gen_add_insn_before (gen_ctx, insn, new_insn);
next_insn = MIR_new_insn (ctx, MIR_BT, insn->ops[0], temp_op);
gen_add_insn_after (gen_ctx, new_insn, next_insn);
gen_delete_insn (gen_ctx, insn);
insn = new_insn;
}
if ((nargs = get_builtin (gen_ctx, code, &proto_item, &func_import_item)) > 0) {
if (code == MIR_VA_ARG || code == MIR_VA_BLOCK_ARG) {
/* Use a builtin func call:
mov func_reg, func ref; [mov reg3, type;] call proto, func_reg, res_reg, va_reg,
reg3 */
MIR_op_t ops[6], func_reg_op, reg_op3;
MIR_op_t res_reg_op = insn->ops[0], va_reg_op = insn->ops[1], op3 = insn->ops[2];
assert (res_reg_op.mode == MIR_OP_VAR && va_reg_op.mode == MIR_OP_VAR
&& op3.mode == (code == MIR_VA_ARG ? MIR_OP_VAR_MEM : MIR_OP_VAR));
func_reg_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
reg_op3 = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
next_insn = new_insn
= MIR_new_insn (ctx, MIR_MOV, func_reg_op, MIR_new_ref_op (ctx, func_import_item));
gen_add_insn_before (gen_ctx, insn, new_insn);
if (code == MIR_VA_ARG) {
new_insn
= MIR_new_insn (ctx, MIR_MOV, reg_op3, MIR_new_int_op (ctx, (int64_t) op3.u.mem.type));
op3 = reg_op3;
gen_add_insn_before (gen_ctx, insn, new_insn);
}
ops[0] = MIR_new_ref_op (ctx, proto_item);
ops[1] = func_reg_op;
ops[2] = res_reg_op;
ops[3] = va_reg_op;
ops[4] = op3;
if (code == MIR_VA_BLOCK_ARG) ops[5] = insn->ops[3];
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, code == MIR_VA_ARG ? 5 : 6, ops);
gen_add_insn_before (gen_ctx, insn, new_insn);
gen_delete_insn (gen_ctx, insn);
} else { /* Use builtin: mov freg, func ref; call proto, freg, res_reg, op_reg[, op_reg2] */
MIR_op_t freg_op, res_reg_op = insn->ops[0], op_reg_op = insn->ops[1], ops[5];
assert (res_reg_op.mode == MIR_OP_VAR && op_reg_op.mode == MIR_OP_VAR);
freg_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
next_insn = new_insn
= MIR_new_insn (ctx, MIR_MOV, freg_op, MIR_new_ref_op (ctx, func_import_item));
gen_add_insn_before (gen_ctx, insn, new_insn);
ops[0] = MIR_new_ref_op (ctx, proto_item);
ops[1] = freg_op;
ops[2] = res_reg_op;
ops[3] = op_reg_op;
if (nargs == 2) ops[4] = insn->ops[2];
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, nargs + 3, ops);
gen_add_insn_before (gen_ctx, insn, new_insn);
gen_delete_insn (gen_ctx, insn);
}
} else if (code == MIR_VA_START) {
MIR_op_t treg_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
MIR_op_t treg_op2 = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
MIR_op_t va_op = insn->ops[0];
MIR_reg_t va_reg;
assert (func->vararg_p && va_op.mode == MIR_OP_VAR);
va_reg = va_op.u.reg;
/* Insns can be non-simplified as soon as they match a machine insn. */
/* treg = mem64[r1]; treg = treg + var_args_start; mem64[va_reg] = treg */
gen_mov (gen_ctx, insn, MIR_MOV, treg_op,
_MIR_new_var_mem_op (ctx, MIR_T_I64, 0, R1_HARD_REG, MIR_NON_VAR, 1));
gen_mov (gen_ctx, insn, MIR_MOV, treg_op2, MIR_new_int_op (ctx, var_args_start));
/* don't use immediate in ADD as treg_op can become r0: */
new_insn = MIR_new_insn (ctx, MIR_ADD, treg_op, treg_op, treg_op2);
gen_add_insn_before (gen_ctx, insn, new_insn);
gen_mov (gen_ctx, insn, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_I64, 0, va_reg, MIR_NON_VAR, 1), treg_op);
gen_delete_insn (gen_ctx, insn);
} else if (code == MIR_VA_END) { /* do nothing */
gen_delete_insn (gen_ctx, insn);
} else if (MIR_call_code_p (code)) {
machinize_call (gen_ctx, insn);
leaf_p = FALSE;
} else if (code == MIR_ALLOCA) {
alloca_p = TRUE;
} else if (code == MIR_SWITCH) {
switch_p = TRUE;
} else if (code == MIR_LADDR) {
laddr_p = TRUE;
} else if (code == MIR_RET) {
/* In simplify we already transformed code for one return insn
and added extension insn (if any). */
uint32_t n_gpregs = 0, n_fregs = 0;
assert (func->nres == MIR_insn_nops (ctx, insn));
for (i = 0; i < func->nres; i++) {
assert (insn->ops[i].mode == MIR_OP_VAR);
res_type = func->res_types[i];
if (((res_type == MIR_T_F || res_type == MIR_T_D) && n_fregs < 4)
|| (res_type == MIR_T_LD && n_fregs < 3)) {
new_insn_code = res_type == MIR_T_F ? MIR_FMOV
: res_type == MIR_T_D ? MIR_DMOV
: MIR_LDMOV;
ret_reg = F1_HARD_REG + n_fregs++;
} else if (n_gpregs < 8) {
new_insn_code = MIR_MOV;
ret_reg = R3_HARD_REG + n_gpregs++;
} else {
(*MIR_get_error_func (ctx)) (MIR_ret_error,
"ppc64 can not handle this combination of return values");
}
ret_reg_op = _MIR_new_var_op (ctx, ret_reg);
gen_mov (gen_ctx, insn, new_insn_code, ret_reg_op, insn->ops[i]);
insn->ops[i] = ret_reg_op;
}
}
}
}
static void isave (gen_ctx_t gen_ctx, MIR_insn_t anchor, int disp, MIR_reg_t hard_reg) {
gen_mov (gen_ctx, anchor, MIR_MOV,
_MIR_new_var_mem_op (gen_ctx->ctx, MIR_T_I64, disp, R1_HARD_REG, MIR_NON_VAR, 1),
_MIR_new_var_op (gen_ctx->ctx, hard_reg));
}
static void fsave (gen_ctx_t gen_ctx, MIR_insn_t anchor, int disp, MIR_reg_t hard_reg) {
gen_mov (gen_ctx, anchor, MIR_DMOV,
_MIR_new_var_mem_op (gen_ctx->ctx, MIR_T_D, disp, R1_HARD_REG, MIR_NON_VAR, 1),
_MIR_new_var_op (gen_ctx->ctx, hard_reg));
}
static void target_make_prolog_epilog (gen_ctx_t gen_ctx, bitmap_t used_hard_regs,
size_t stack_slots_num) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_func_t func;
MIR_insn_t anchor, new_insn;
MIR_op_t sp_reg_op, fp_reg_op, r0_reg_op, lr_reg_op;
int64_t start_save_regs_offset;
size_t i, n, frame_size, saved_iregs_num, saved_fregs_num;
assert (curr_func_item->item_type == MIR_func_item);
func = curr_func_item->u.func;
anchor = DLIST_HEAD (MIR_insn_t, func->insns);
if (func->vararg_p) {
for (i = 0; i < 8; i++)
isave (gen_ctx, anchor, PPC64_STACK_HEADER_SIZE + i * 8, i + R3_HARD_REG);
}
for (i = saved_iregs_num = saved_fregs_num = 0; i <= MAX_HARD_REG; i++)
if (!target_call_used_hard_reg_p (i, MIR_T_UNDEF) && bitmap_bit_p (used_hard_regs, i)) {
if (i < F0_HARD_REG)
saved_iregs_num++;
else
saved_fregs_num++;
}
if (leaf_p && !alloca_p && !switch_p && !laddr_p /* switch and laddr changes LR */
&& saved_iregs_num == 0 && saved_fregs_num == 0 && stack_slots_num == 0)
return;
saved_iregs_num++; /* for fp (R31) ??? only alloca_p */
r0_reg_op = _MIR_new_var_op (ctx, R0_HARD_REG);
lr_reg_op = _MIR_new_var_op (ctx, LR_HARD_REG);
sp_reg_op = _MIR_new_var_op (ctx, R1_HARD_REG);
fp_reg_op = _MIR_new_var_op (ctx, R31_HARD_REG);
/* Prologue: */
frame_size = param_save_area_size + PPC64_STACK_HEADER_SIZE + stack_slots_num * 8;
start_save_regs_offset = frame_size;
frame_size += (saved_iregs_num + saved_fregs_num) * 8;
if (frame_size % 16 != 0) frame_size = (frame_size + 15) / 16 * 16;
if (!func->jret_p) {
gen_mov (gen_ctx, anchor, MIR_MOV, r0_reg_op, lr_reg_op); /* r0 = lr */
gen_mov (gen_ctx, anchor, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_I64, 16, R1_HARD_REG, MIR_NON_VAR, 1),
r0_reg_op); /* mem[r1] = r0 */
}
gen_mov (gen_ctx, anchor, MIR_MOV, r0_reg_op, sp_reg_op);
new_insn = MIR_new_insn (ctx, MIR_ADD, sp_reg_op, sp_reg_op, MIR_new_int_op (ctx, -frame_size));
gen_add_insn_before (gen_ctx, anchor, new_insn); /* r1 -= frame_size */
gen_mov (gen_ctx, anchor, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_I64, 0, R1_HARD_REG, MIR_NON_VAR, 1),
r0_reg_op); /* mem[r1] = r0 */
gen_mov (gen_ctx, anchor, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_I64, PPC64_TOC_OFFSET, R1_HARD_REG, MIR_NON_VAR, 1),
_MIR_new_var_op (ctx, R2_HARD_REG)); /* mem[r1+toc_off] = r2 */
for (n = i = 0; i <= MAX_HARD_REG; i++)
if (!target_call_used_hard_reg_p (i, MIR_T_UNDEF) && bitmap_bit_p (used_hard_regs, i)) {
if (i < F0_HARD_REG)
isave (gen_ctx, anchor, start_save_regs_offset + (n++) * 8, i);
else
fsave (gen_ctx, anchor, start_save_regs_offset + (n++) * 8, i);
}
isave (gen_ctx, anchor, start_save_regs_offset + n * 8, R31_HARD_REG); /* save R31 */
gen_mov (gen_ctx, anchor, MIR_MOV, fp_reg_op, sp_reg_op); /* r31 = r1 */
/* Epilogue: */
for (anchor = DLIST_TAIL (MIR_insn_t, func->insns); anchor != NULL;
anchor = DLIST_PREV (MIR_insn_t, anchor))
if (anchor->code == MIR_RET || anchor->code == MIR_JRET) break;
if (anchor == NULL) return;
/* Restoring hard registers: */
for (i = n = 0; i <= MAX_HARD_REG; i++)
if (!target_call_used_hard_reg_p (i, MIR_T_UNDEF) && bitmap_bit_p (used_hard_regs, i)) {
if (i < F0_HARD_REG) {
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_var_op (ctx, i),
_MIR_new_var_mem_op (ctx, MIR_T_I64, start_save_regs_offset + (n++) * 8,
FP_HARD_REG, MIR_NON_VAR, 1));
} else {
gen_mov (gen_ctx, anchor, MIR_DMOV, _MIR_new_var_op (ctx, i),
_MIR_new_var_mem_op (ctx, MIR_T_D, start_save_regs_offset + (n++) * 8, FP_HARD_REG,
MIR_NON_VAR, 1));
}
}
/* Restore sp, fp, lr */
new_insn = MIR_new_insn (ctx, MIR_ADD, sp_reg_op, fp_reg_op, MIR_new_int_op (ctx, frame_size));
gen_add_insn_before (gen_ctx, anchor, new_insn); /* sp = fp + frame_size */
gen_mov (gen_ctx, anchor, MIR_MOV, fp_reg_op,
_MIR_new_var_mem_op (ctx, MIR_T_I64, start_save_regs_offset + n * 8, FP_HARD_REG,
MIR_NON_VAR, 1)); /* restore fp */
if (!func->jret_p) {
gen_mov (gen_ctx, anchor, MIR_MOV, r0_reg_op,
_MIR_new_var_mem_op (ctx, MIR_T_I64, 16, R1_HARD_REG, MIR_NON_VAR,
1)); /* r0 = 16(sp) */
gen_mov (gen_ctx, anchor, MIR_MOV, lr_reg_op, r0_reg_op); /* lr = r0 */
}
}
struct pattern {
MIR_insn_code_t code;
/* Pattern elements:
blank - ignore
X - match everything
$ - finish successfully matching
r - register but LR
R - r but R0
h<one or two decimal digits> - hard register with given number
memory with signed 16-bit disp and optional non-R0 base:
m[0-2] - int (signed or unsigned) memory of size 8,16,32,64-bits
ms[0-2] - signed int type memory of size 8,16,32,64-bits
mu[0-2] - unsigned int type memory of size 8,16,32,64-bits
memory with non-R0 base and index:
M[0-3] - int (signed or unsigned) type memory of size 8,16,32,64-bits
Ms[0-2] - signed int type memory of size 8,16,32,64-bits
Mu[0-2] - unsigned int type memory of size 8,16,32,64-bits
mds - signed 32-bit memory with scaled by 4 signed 16-bit disp and optional non-R0 base:
Mds - 64-bit memory with scaled by 4 signed 16-bit disp and optional non-R0 base:
i - 16 bit signed immediate
I - 16 bit signed immediate shift left by 16
u - 16 bit unsigned immediate
U - 16 bit unsigned immediate shift left by 16
x - 64 bit unsigned immediate whose high 32-bit part is described by pattern 0*1*
z - 32-bit unsigned immediate
zs - 32-bit unsigned immediate with zero 0-th bit
Z - any integer immediate
Zs - 48-bit unsigned immediate with zero 0-th bit
Sh - 6-bit unsigned shift
sh - 5-bit unsigned shift
ia - roundup (i, 16) as 16 bit signed integer
memory with signed 16-bit disp and optional non-R0 base:
mf - memory of float
md - memory of double
mld - memory of long double where disp + 8 is also in 16-bit range and non-R0 base reg
mld0 - as previous bit with R0 base reg
mds - signed 32-bit memory with scaled by 4 signed 16-bit disp and option non-R0 base:
memory with non-R0 base and index:
Mf - memory of float
Md - memory of double
L - reference or label as the 1st or 2nd op which can be present by signed 24-bit pc word
offset
Remember we have no float or (long) double immediate at this stage. They were removed during
simplification. */
const char *pattern;
/* Bit addressing: 0..31
Replacement elements:
blank - ignore
; - insn separation
o<number> - opcode [0..5], <number> is decimal
O<number> - opcode [21..30], <number> is decimal
P<number> - opcode [26..30], <number> is decimal
(r|n)t[0-2] - put n-th operand register into rd field [6..10]
(r|n)s[0-2] - put n-th operand register into rs field [6..10] -- source
(r|n)a[0-2] - put n-th operand register into rn field [11..15]
(r|n)b[0-2] - put n-th operand register into rm field [16..20]
rc[0-2] - put n-th operand register into rc field [21..25]
n above means operand reg+1
Ra[0-2] - put n-th operand register (which is not R0) into rn field [11..15]
h(t,s,a,b)<dec digits> - hardware register with given number in rt,ra,rb field
sr<number> - special reg with given number [11..15]
m = operand is (8-,16-,32-,64-bit) mem with base (0 reg means 0) and signed 16-bit disp
M = operand is (8-,16-,32-,64-bit) mem with base (0 reg means 0) and index
mds = 32-bit scaled mem with base (0 reg means 0) and signed 16-bit disp scaled by 4
Mds = 64-bit scaled mem with base (0 reg means 0) and signed 16-bit disp scaled by 4
d<number> = field [30..31]
mt = 8-byte memory -16(r1)
i - 16 bit signed immediate - field [16..31]
I - 16 bit signed immediate shift left by 16 - field [16..31]
u - 16 bit unsigned immediate - field [16..31]
U - 16 bit unsigned immediate shift left by 16 - field [16..31]
z[0-3] - n-th 16 bytes of 64-bit immediate
x - mb for x immediate
sh<number> - field [16..20]
Sh<number> - field [16..20,30]
Mb<number> - field [21..26], and zero bits [27..28]
Me<number> - field [21..26], and one in bit [27..29]
Sh - Sh value: field [16..20,30]
sh - sh value: field [16..20]
Shr - 64 - Sh value: field [16..20,30]
shr - 32 - sh value: field [16..20]
mbSh - mb with value 64-Sh: field [21..26] and zero in bits [27..29]
mbsh - mb with value 32-sh: field [21..25]
meSh - mb with value 63-Sh: field [21..26] and 1 in bits [27..29]
mesh - mb with value 31-sh: field [26..30]
mb<number> - number in filed [21..25]
me<number> - number in filed [26..30]
ia - roundup (i, 16)
ih - PPC64_STACK_HEADER_SIZE + param_area_size