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HiSpeed support #5

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llysdal opened this issue Mar 5, 2021 · 0 comments
Open

HiSpeed support #5

llysdal opened this issue Mar 5, 2021 · 0 comments
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enhancement New feature or request

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@llysdal
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llysdal commented Mar 5, 2021 •
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My idea for this is that you can define HiSpeed inputs that are assigned to memory ranges (in the FPGA HiSpeed addressing space), and then those HiSpeed links can be connected to internal gates. A set of converter gates to convert from HiSpeed to Number and back.

HiSpeed links work weird however, and I'm not sure the current "type" system can handle it. Some devices have the HiSpeed link (at least the wire port dedicated to it) on the input, and others on the output.
Maybe some special new 'pseudo' type? In theory every gate has "HiSpeed", even if they don't implement WriteCell and ReadCell, so maybe it could be a special link between 2 gates? HiSpeed functionality is already pretty advanced, so it wouldn't matter too much if using it is slightly complex.

It should be noted that wirelinks already work (HiSpeed write and read gates), but 'legacy' HiSpeed gates use different input/output conventions.

Currently gates that exclusively have HiSpeed behaviour are 'banned'/hidden (String to Memory and the reverse)
@llysdal llysdal added the enhancement New feature or request label Mar 5, 2021
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