nucleo-h7s3l8 adc dma interrupt not working. callback not triggered.

[Sambsc19]

I am having an issue with adc dma on nucleo-h7s3l8. I am using zephyr branch:

https://github.com/Sambsc19/zephyr/tree/xip_h7s3_dma

and mcuboot branch:

https://github.com/Sambsc19/mcuboot/tree/xip_h7s3

I have updated working branch stm32h7rs.dtsi with changes from:

https://github.com/FRASTM/zephyr/tree/stm32h7rs_dma

I have verified the ADC working. I have verified MEM to MEM DMA working.

I have built 2 versions of app for testing peripheral to mem ADC DMA.

The app dma_p2m1 is not using CONFIG_ADC_STM32_DMA. the app dma_p2m2 is using CONFIG_ADC_STM32_DMA.

P2M1

from the logs it seems dest inc (80000). although with my block config i would expect (1)?

struct dma_block_config block_cfg = {
		.source_address = (uint32_t)&ADC1->DR,  /* ADC Data Register */
		.dest_address = (uint32_t)adc_buffer,
		.block_size = BUFFER_SIZE * sizeof(adc_buffer[0]),
		.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE,  /* No increment for source */
		.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT,    /* Increment by 1 for destination */
		.next_block = NULL                          /* Ensure no chaining */
	};

adc ISR is triggered
[00:00:00.502,000] adc_stm32: adc_stm32_isr: adc@40022000 ISR triggered.

I Do not see DMA callback being triggered.

I manually trigger DMA IRQ with NVIC_SetPendingIRQ(GPDMA1_Channel0_IRQn); and see callback execute.

Logs from dma_p2m1:

Booting MCUboot v2.1.0-rc1-123-g7261638c9197 ***
*** Using Zephyr OS build v3.7.0-5917-g03cad26291b5 ***
I: Starting bootloader
I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Boot source: none
I: Image index: 0, Swap type: none
I: Bootloader chainload address offset: 0x0
I: Jumping to the first image slot
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 0 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 1 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 2 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 3 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 4 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 5 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 6 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 7 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 8 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 9 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 10 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 11 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 12 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 13 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 14 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 15 connected and enabled.
[00:00:00.000,000] <dbg> os: setup_thread_stack: stack 0x24001940 for thread 0x240006e0: obj_size=2112 buf_start=0x24001980  buf_size 2048 stack_ptr=0x24002180
[00:00:00.000,000] <dbg> os: setup_thread_stack: stack 0x240017c0 for thread 0x24000660: obj_size=384 buf_start=0x24001800  buf_size 320 stack_ptr=0x24001940
[00:00:00.000,000] <dbg> os: setup_thread_stack: stack 0x24000c40 for thread 0x24000190: obj_size=832 buf_start=0x24000c80  buf_size 768 stack_ptr=0x24000f80
[00:00:00.000,000] <dbg> adc_stm32: adc_stm32_init: Initializing adc@40022000
*** Booting Zephyr OS build v3.7.0-5917-g03cad26291b5 ***
[00:00:00.001,000] <dbg> os: k_sched_unlock: scheduler unlocked (0x240006e0:0)
[00:00:00.001,000] <dbg> os: z_tick_sleep: thread 0x240006e0 for 5000 ticks
[00:00:00.501,000] <inf> main: Starting ADC with DMA sample application
[00:00:00.501,000] <dbg> main: main: DMA Config: src_addr_adj=2, dest_addr_adj=0, block_size=32
[00:00:00.501,000] <dbg> dma_stm32: dma_stm32_configure: Channel (0) src inc (0).
[00:00:00.501,000] <dbg> dma_stm32: dma_stm32_configure: Channel (0) dest inc (80000).
[00:00:00.501,000] <dbg> dma_stm32: dma_stm32_configure: Enabling DMA TC, HT, and error interrupts for channel 0
[00:00:00.502,000] <dbg> dma_stm32: dma_stm32_configure: Checking DMA IRQ flags for channel 0
[00:00:00.502,000] <dbg> dma_stm32: dma_stm32_configure: TC: 0, HT: 0, DTE: 0
[00:00:00.502,000] <dbg> adc_stm32: adc_stm32_channel_setup: Channel setup succeeded!
[00:00:00.502,000] <dbg> adc_stm32: adc_stm32_start_conversion: Starting conversion
[00:00:00.502,000] <dbg> adc_stm32: adc_stm32_isr: adc@40022000 ISR triggered.
[00:00:00.502,000] <inf> main: ADC sampling with DMA started...
[00:00:00.502,000] <inf> main: DMA Status: busy=1, pending_length=32
[00:00:00.502,000] <inf> main: Triggering DMA IRQ manually for testing...
[00:00:00.503,000] <dbg> dma_stm32: dma_stm32_irq_handler: DMA IRQ Handler called for channel 0
[00:00:00.503,000] <err> dma_stm32: Transfer Error.
[00:00:00.503,000] <inf> dma_stm32: tc: 0, ht: 0, dte: 0, ule: 0, use: 0
[00:00:00.503,000] <inf> main: DMA transfer completed with status: -5

P2M2

In the version I am using CONFIG_ADC_STM32_DMA. it seems dma adc config code is being executed correctly from adc_stm32.c but callback is not triggered.

Logs from dma_p2m2:

I: Bootloader chainload address offset: 0x0
I: Jumping to the first image slot
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 2 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 3 connected and enabled.
--- 2 messages dropped ---
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 4 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 5 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 6 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 7 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 8 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 9 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 10 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 11 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 12 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 13 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 14 connected and enabled.
[00:00:10.703,000] <dbg> dma_stm32: dma_stm32_config_irq_0: IRQ for DMA channel 15 connected and enabled.
[00:00:00.000,000] <dbg> os: setup_thread_stack: stack 0x24001980 for thread 0x24000730: obj_size=2112 buf_start=0x240019c0  buf_size 2048 stack_ptr=0x240021c0
[00:00:00.000,000] <dbg> os: setup_thread_stack: stack 0x24001800 for thread 0x240006b0: obj_size=384 buf_start=0x24001840  buf_size 320 stack_ptr=0x24001980
[00:00:00.000,000] <dbg> os: setup_thread_stack: stack 0x24000c80 for thread 0x240001e0: obj_size=832 buf_start=0x24000cc0  buf_size 768 stack_ptr=0x24000fc0
[00:00:00.000,000] <dbg> adc_stm32: adc_stm32_init: Initializing adc@40022000
*** Booting Zephyr OS build v3.7.0-5918-g76896516efca ***
[00:00:00.001,000] <dbg> os: k_sched_unlock: scheduler unlocked (0x24000730:0)
[00:00:00.001,000] <inf> adc_dma_sample: Starting ADC DMA sample application
[00:00:00.001,000] <dbg> adc_stm32: adc_stm32_channel_setup: Channel setup succeeded!
[00:00:00.001,000] <dbg> dma_stm32: dma_stm32_configure: Channel (0) src inc (0).
[00:00:00.001,000] <dbg> dma_stm32: dma_stm32_configure: Channel (0) dest inc (80000).
[00:00:00.001,000] <dbg> dma_stm32: dma_stm32_configure: Enabling DMA TC, HT, and error interrupts for channel 0
[00:00:00.001,000] <dbg> dma_stm32: dma_stm32_configure: Checking DMA IRQ flags for channel 0
[00:00:00.001,000] <dbg> dma_stm32: dma_stm32_configure: TC: 0, HT: 0, DTE: 0
[00:00:00.002,000] <dbg> adc_stm32: adc_stm32_dma_start: DMA started
[00:00:00.002,000] <dbg> adc_stm32: adc_stm32_start_conversion: Starting conversion

I have attached both projects. I am now going to setup debugging to do memory analysis.

dma_p2m1.zip
dma_p2m2.zip

[Sambsc19]

I am missing the file target/stm32h7rx.cfg for debugging openocd if anyone could share it.

source [find interface/stlink-dap.cfg]
transport select "dapdirect_swd"

set WORKAREASIZE 0x8000
set CHIPNAME STM32H7S3XX
set BOARDNAME NUCLEO-H7S3L8

# Enable debug when in low power modes
set ENABLE_LOW_POWER 1

# Stop Watchdog counters when halt
set STOP_WATCHDOG 1

# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
# reset_config srst_only srst_nogate connect_assert_srst

#set CONNECT_UNDER_RESET 1
#set CORE_RESET 0

source [find target/stm32h7rx.cfg]


$_CHIPNAME.cpu0 configure -event gdb-attach {
        echo "Debugger attaching: halting execution"
        gdb_breakpoint_override hard
}

$_CHIPNAME.cpu0 configure -event gdb-detach {
        echo "Debugger detaching: resuming execution"
        resume
}

# Due to the use of connect_assert_srst, running gdb requires
# to reset halt just after openocd init.
rename init old_init
proc init {} {
        old_init
        reset halt
}

[Sambsc19]

I found a patch for openocd to include stm32h7rs chips:

https://review.openocd.org/c/openocd/+/8086

My OpenOCD repo with patch:

https://github.com/[Sambsc19/OpenOCD](https://github.com/Sambsc19/OpenOCD)

I have attached. the openocd.cfg for the board and the project itself.

using:

source [find interface/stlink-dap.cfg]
transport select "dapdirect_swd"

I have the following gdb logs:

[2024-12-15T20:21:49.235Z] SERVER CONSOLE DEBUG: onBackendConnect: gdb-server session connected. You can switch to "DEBUG CONSOLE" to see GDB interactions.
openocd.exe -c "gdb_port 50000" -c "tcl_port 50001" -c "telnet_port 50002" -s "C:\\Partition_Environments\\Pythons\\zephyrproject\\wsc\\dma_p2m2" -f "c:/Users/sambs/.vscode/extensions/marus25.cortex-debug-1.12.1/support/openocd-helpers.tcl" -f "C:/Partition_Environments/Pythons/zephyrproject/zephyr/boards/st/nucleo_h7s3l8/support/openocd.cfg" -c CDLiveWatchSetup
Open On-Chip Debugger 0.12.0 (2023-10-02) [https://github.com/sysprogs/openocd]
Licensed under GNU GPL v2
libusb1 09e75e98b4d9ea7909e8837b7a3f00dda4589dc3
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
CDLiveWatchSetup
init
c:/Users/sambs/.vscode/extensions/marus25.cortex-debug-1.12.1/support/openocd-helpers.tcl: Info: Setting gdb-max-connections for target 'STM32H7S3XX.ap0' to 2
c:/Users/sambs/.vscode/extensions/marus25.cortex-debug-1.12.1/support/openocd-helpers.tcl: Info: Setting gdb-max-connections for target 'STM32H7S3XX.cpu0' to 2
Info : Listening on port 50001 for tcl connections
Info : Listening on port 50002 for telnet connections
Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
Info : STLINK V3J15M6 (API v3) VID:PID 0483:3754
Info : Target voltage: 3.276800
Info : Unable to match requested speed 1800 kHz, using 1000 kHz
Info : Unable to match requested speed 1800 kHz, using 1000 kHz
Info : clock speed 1000 kHz
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x6ba02477
Info : [STM32H7S3XX.cpu0] Cortex-M7 r1p2 processor detected
Info : [STM32H7S3XX.cpu0] target has 8 breakpoints, 4 watchpoints
Error: Failed to read memory at 0x5c001004
Error executing event examine-end on target STM32H7S3XX.cpu0:
read_memory: failed to read memory
in procedure 'init'
Info : gdb port disabled
Info : starting gdb server for STM32H7S3XX.cpu0 on 50000
Info : Listening on port 50000 for gdb connections
Error: Failed to read memory at 0x5c001004
Error executing event examine-end on target STM32H7S3XX.cpu0:
embedded:startup.tcl:1187: Error: read_memory: failed to read memory
in procedure 'init' 
in procedure 'ocd_process_reset' 
in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 1187
[STM32H7S3XX.cpu0] halted due to debug-request, current mode: Thread 
xPSR: 0x01000000 pc: 0x08002438 msp: 0x24002200
Info : accepting 'gdb' connection on tcp/50000
Debugger attaching: halting execution
force hard breakpoints
Info : New GDB Connection: 1, Target STM32H7S3XX.cpu0, state: halted
Info : accepting 'gdb' connection on tcp/50000
Debugger attaching: halting execution
force hard breakpoints
Info : New GDB Connection: 2, Target STM32H7S3XX.cpu0, state: running
Warn : GDB connection 2 on target STM32H7S3XX.cpu0 not halted
Debugger detaching: resuming execution
Error: [STM32H7S3XX.cpu0] not halted
Error: [STM32H7S3XX.cpu0] context restore failed, aborting resume
Error executing event gdb-detach on target STM32H7S3XX.cpu0:

Info : dropped 'gdb' connection (error -400)
Error: [STM32H7S3XX.cpu0] not halted
Error: [STM32H7S3XX.cpu0] context restore failed, aborting resume
Info : target STM32H7S3XX.cpu0 was not halted when resume was requested
Debugger detaching: resuming execution
Info : dropped 'gdb' connection (error -400)
[2024-12-15T20:24:08.187Z] SERVER CONSOLE DEBUG: onBackendConnect: gdb-server session closed
GDB server session ended. This terminal will be reused, waiting for next session to start...

I believe I should be using:

source [find interface/stlink.cfg]
transport select hla_swd

as it is stlink-v3 but then I have the error:

Error : hla does not support multicore debugging
Error: The selected transport doesn't support this target

The stm32h7rs is not multicore like other h7's. I need to assert this somehow. Important to note the bootloader is at 0x08000000 and app is at 0x70000000.

[dma_p2m2.zip](https://github.com/user-attachments
openocd.zip
/files/18141947/dma_p2m2.zip)