Ziicfiss emulation

.cargo/config.toml

@@ -1,17 +1,19 @@
 [target.riscv64imac-unknown-none-elf]
 runner = """
 qemu-system-riscv64
+-cpu rv64,smstateen=true
 -machine virt
 -bios none
 -nographic
 -m 2G
--initrd vmlinux
--drive file=rootfs.img,format=raw,id=hd0,if=none
+-initrd vmlinux_debug
+-drive file=rootfs.ext2,format=raw,id=hd0,if=none
 -device virtio-blk-pci,drive=hd0,iommu_platform=true,disable-legacy=on
 -append root=/dev/vda,rw,console=ttyS0
 -device riscv-iommu-pci
 -kernel
 """
+
 # for debug
 # runner = "../../qemu/build/qemu-system-riscv64 -S -gdb tcp::10000 -d int,in_asm,cpu_reset,mmu,page,guest_errors -machine virt -bios none -nographic -m 2G -initrd vmlinux_debug -drive file=rootfs.img,format=raw,id=hd0,if=none -device virtio-blk-pci,drive=hd0,iommu_platform=true,disable-legacy=on -append root=/dev/vda,rw,console=ttyS0 -device riscv-iommu-pci -kernel"
 # memo: maintenance packet Qqemu.PhyMemMode:1
@@ -24,4 +26,3 @@ rustflags = [
 
 [build]
 target = "riscv64imac-unknown-none-elf"
-

.gitignore

@@ -21,3 +21,4 @@ Cargo.lock
 .gdb_history
 vmlinux
 vmlinux_debug
+rootfs.*

Cargo.toml

@@ -10,7 +10,7 @@ pedantic = "warn"
 elf = { version = "0.7.2", default-features = false }
 fdt = "0.1.5"
 linked_list_allocator = "0.10.5"
-raki = { version = "1.0.0" }
+raki = "1.2.0"
 riscv = "0.11.1"
 riscv-rt = "0.11.0"
 rustsbi = { version = "0.4.0-alpha.1", features = ["machine"] }

guest_image/README.md

@@ -1,15 +1,15 @@
 # Build guest image
 
 ## device tree
-```
+```sh
 $ ./build_dtb.sh create
 $ vim guest.dts # edit dts
 $ ./build_dtb.sh build
 # guest.dtb is created to repository root.
 ```
 
 ## Linux (with debug info)
-```
+```sh
 $ git clone https://github.com/torvalds/linux -b v6.9
 
 $ cd /path/to/this/repository
@@ -22,3 +22,23 @@ $ DEBUG_KERNEL [=y], DEBUG_INFO [=y], EFI [=n], RELOCATABLE [=n]
 $ make ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- -j$(nproc)
 $ mv vmlinux /path/to/linux/vmlinx_debug
 ```
+
+## Linux (For Zicfiss)
+See [https://lwn.net/Articles/992578/](https://lwn.net/Articles/992578/).
+```sh
+# Toolchain
+$ git clone [email protected]:sifive/riscv-gnu-toolchain.git -b cfi-dev
+$ riscv-gnu-toolchain/configure --prefix=<path-to-where-to-build> --with-arch=rv64gc_zicfilp_zicfiss --enable-linux --disable-gdb  --with-extra-multilib-test="rv64gc_zicfilp_zicfiss-lp64d:-static"
+$ make -j$(nproc)
+
+# Opensbi
+$ git clone [email protected]:deepak0414/opensbi.git -b v6_cfi_spec_split_opensbi
+$ make CROSS_COMPILE=<your riscv toolchain> -j$(nproc) PLATFORM=generic
+
+# Linux
+$ git clone https://github.com/torvalds/linux -b v6.12-rc1
+$ wget https://patchwork.kernel.org/series/896898/mbox/ --output-document riscv-control-flow-integrity-for-usermode.patch
+$ git am riscv-control-flow-integrity-for-usermode.patch 
+$ make ARCH=riscv CROSS_COMPILE=<path-to-cfi-riscv-gnu-toolchain>/build/bin/riscv64-unknown-linux-gnu- -j$(nproc) defconfig
+$ make ARCH=riscv CROSS_COMPILE=<path-to-cfi-riscv-gnu-toolchain>/build/bin/riscv64-unknown-linux-gnu- -j$(nproc)
+```

guest_image/guest.dts

@@ -47,10 +47,10 @@
 			riscv,cbop-block-size = <0x40>;
 			riscv,cboz-block-size = <0x40>;
 			riscv,cbom-block-size = <0x40>;
-			riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd\0zba\0zbb\0zbc\0zbs\0ssccptr\0sscounterenw\0sstc\0sstvala\0sstvecd\0svadu";
+			riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicfiss\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd\0zba\0zbb\0zbc\0zbs\0ssccptr\0sscounterenw\0sstc\0sstvala\0sstvecd\0svadu";
 			riscv,isa-base = "rv64i";
-			riscv,isa = "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_ssccptr_sscounterenw_sstc_sstvala_sstvecd_svadu";
-			mmu-type = "riscv,sv57";
+			riscv,isa = "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicfiss_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_ssccptr_sscounterenw_sstc_sstvala_sstvecd_svadu";
+			mmu-type = "riscv,sv39";
 
 			interrupt-controller {
 				#interrupt-cells = <0x01>;

src/emulate_extension.rs

@@ -0,0 +1,89 @@
+//! Extension emulation
+
+pub mod zicfiss;
+
+use crate::h_extension::csrs::vstvec;
+use crate::trap::hypervisor_supervisor::hstrap_exit;
+use crate::HYPERVISOR_DATA;
+
+use core::arch::asm;
+use raki::Instruction;
+use riscv::register::sstatus;
+
+/// Trait for extention emulation.
+pub trait EmulateExtension {
+    /// Emulate instruction
+    fn instruction(&mut self, inst: &Instruction);
+    /// Emulate CSR
+    fn csr(&mut self, inst: &Instruction);
+    /// Emulate CSR field that already exists.
+    fn csr_field(&mut self, inst: &Instruction, write_to_csr_value: u64, read_csr_value: &mut u64);
+}
+
+/// CSR data for CSRs emulation.
+pub struct CsrData(u64);
+
+impl CsrData {
+    /// Return raw data.
+    pub fn bits(&self) -> u64 {
+        self.0
+    }
+
+    /// Write data to CSR.
+    /// For CSRRW or CSRRWI
+    pub fn write(&mut self, data: u64) {
+        self.0 = data;
+    }
+
+    /// Set bit in CSR.
+    /// For CSRRS or CSRRSI
+    pub fn set(&mut self, mask: u64) {
+        self.0 |= mask;
+    }
+
+    /// Clear bit in CSR.
+    /// For CSRRC or CSRRCI
+    pub fn clear(&mut self, mask: u64) {
+        self.0 &= !mask;
+    }
+}
+
+/// Throw an VS-level exception.
+/// * `exception_num`: Exception number. (store to vscause)
+/// * `trap_value`: Trap value. (store to vstval)
+pub fn pseudo_vs_exception(exception_num: usize, trap_value: usize) -> ! {
+    unsafe {
+        let hypervisor_data = HYPERVISOR_DATA.lock();
+        let mut context = hypervisor_data.get().unwrap().guest().context;
+        asm!(
+            "csrw vsepc, {sepc}",
+            "csrw vscause, {cause}",
+            "csrw vstval, {tval}",
+            sepc = in(reg) context.sepc(),
+            cause = in(reg) exception_num,
+            tval = in(reg) trap_value,
+        );
+
+        let spp = sstatus::read().spp();
+        let vsstatus: usize;
+        asm!("csrr {status}, vsstatus", status = out(reg) vsstatus);
+        let sie = vsstatus >> 1 & 0x1;
+        asm!(
+            "csrw vsstatus, {status}",
+            status = in(reg) (vsstatus & !(1 << 8)) | (spp as usize) << 8
+        );
+        // disable interrupt
+        asm!(
+            "csrs vsstatus, {status}",
+            "csrci vsstatus, 0b10",
+            status = in(reg) sie << 5,
+        );
+        context.set_sstatus(context.sstatus() | 1 << 8);
+
+        context.set_sepc(vstvec::read().bits());
+
+        drop(hypervisor_data);
+
+        hstrap_exit();
+    }
+}