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Extending support for DII execution mode #24
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I have been able to run some DII/TestRIG tests against the
Unfortunately, it is not particularly robust, as might be expected from heretofore untested code. The much less structured |
That might be tricky... for all the wires that RVFI does define (including all CSRs...), I think it doesn't define shipping out the entire (GP) register file, just those in use by the current instruction. Of course, we can do anything we want, model-wise, to fake it, but it's just... another shortcoming of RVFI. |
I see - is the trace generation in sail tied to RVFI? I am hoping we can just dump everything and do a trace file comparison rather than relying on RVFI packets..
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AFAIK yes, there is no existing support for traces other than ad hoc textual printouts and RVFI. It's part of why I was looking at Nexus 5000 last week, because neither of those are very satisfactory answers. |
A better fix is 0c38f6b, which hackishly, but hopefully correctly, models these high selector values as raising illegal opcode traps, rather than crashing the simulator. :) |
The following features when in DII mode are needed in order to use the sail model in the design verification flow.
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