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Issues: CHERIoT-Platform/cheriot-sail
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Should misaligned non-cap memory accesses by enabled by default?
#92
opened Dec 23, 2024 by
resistor
v2? revisit RV C encodings?
maybe-v2
Tracking issues for possible changes for an ISAv2
#89
opened Nov 29, 2024 by
nwf
Tweak cincaddr so that it can replace cmove instruction
maybe-v2
Tracking issues for possible changes for an ISAv2
#88
opened Nov 29, 2024 by
rmn30
Revised encoding with fewer degenerate cases?
maybe-v2
Tracking issues for possible changes for an ISAv2
#69
opened Sep 13, 2024 by
nwf
Incorrect behaviour when registers greater than 15 used as destination in certain instructions
#67
opened Aug 15, 2024 by
rmn30
v2? Permuted capability encoding optimized for 33-bit busses
maybe-v2
Tracking issues for possible changes for an ISAv2
#46
opened Mar 19, 2024 by
nwf-msr
v2? cgp as SCR
maybe-v2
Tracking issues for possible changes for an ISAv2
#43
opened Feb 28, 2024 by
nwf-msr
v2? isentry support
maybe-v2
Tracking issues for possible changes for an ISAv2
#41
opened Feb 28, 2024 by
nwf-msr
CSub redundant?
maybe-v2
Tracking issues for possible changes for an ISAv2
#40
opened Feb 26, 2024 by
rmn30
Libraries accessing Read/Write data through caps stored within PCC
#39
opened Feb 23, 2024 by
vmurali
CSRs that can be accessed without
PERMIT_ACCESS_SYSTEM_REGISTERS should be specific to compartments
#22
opened Dec 20, 2023 by
vmurali
ProTip!
Follow long discussions with comments:>50.