Fix RISCV and CHERI soft-tlb non page-aligned #214
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The QEMU softtlb only caches (target) page sized ranges. In the case another size is probed, the TLB is filled in but marked as invalid. CHERI tag setting needs to acknowledge this case. RISCV also had a completely broken implementation that worked out if the PMP covered an entire page. It tried to mask with a number that was not a power of two, and masking was not appropriate in the first place even had the number been a power of two. It also ignored priority rules on PMP entry matching, and rules concerning PMP entry matching in M-Mode, and matching rules in non M-Mode where there are no PMP entries. A lot of these changes could go away if we merged with upstream. They fix the PMP issues, and offer a new probe that returns the struct that tagmem needs without the current ugly hack.
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This all looks sensible but maybe better to wait until an overdue upstream merge? |
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Sounds sensible. Upstream fixes the whole nonsense page alignment part. All we would have to keep are the tagmem fixes. |
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The QEMU softtlb only caches (target) page sized ranges. In the case another size is probed, the TLB is filled in but marked as invalid.
CHERI tag setting needs to acknowledge this case.
RISCV also had a completely broken implementation that worked out if the PMP covered an entire page. It tried to mask with a number that was not a power of two, and masking was not appropriate in the first place even had the number been a power of two.
It also ignored priority rules on PMP entry matching, and rules concerning PMP entry matching in M-Mode, and matching rules in non M-Mode where there are no PMP entries.
A lot of these changes could go away if we merged with upstream. They fix the PMP issues, and offer a new probe that returns the struct that tagmem needs without the current ugly hack.