Merge first two pull requests of 6.1 development

VERSION

@@ -1 +1 @@
-6.0.0
+6.0.50

accel/tcg/cpu-exec.c

@@ -166,10 +166,10 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
 
     qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc,
                            "Trace %d: %p [" TARGET_FMT_lx "/" TARGET_FMT_lx
-                           "/" TARGET_FMT_lx "/%#x/%#x] %s\n",
+                           "/" TARGET_FMT_lx "-" TARGET_FMT_lx "/%#x/%#x] %s\n",
                            cpu->cpu_index, itb->tc.ptr, itb->cs_base, itb->pc,
-                           itb->cs_top, itb->cheri_flags, itb->flags,
-                           lookup_symbol(itb->pc));
+                           itb->pcc_base, itb->pcc_top, itb->cheri_flags,
+                           itb->flags, lookup_symbol(itb->pc));
 
 #if defined(DEBUG_DISAS)
     if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
@@ -247,7 +247,7 @@ void cpu_exec_step_atomic(CPUState *cpu)
 {
     CPUArchState *env = (CPUArchState *)cpu->env_ptr;
     TranslationBlock *tb;
-    target_ulong cs_base, cs_top = 0, pc;
+    target_ulong cs_base, pcc_base = 0, pcc_top = 0, pc;
     uint32_t cheri_flags = 0;
     uint32_t flags;
     uint32_t cflags = (curr_cflags(cpu) & ~CF_PARALLEL) | 1;
@@ -259,13 +259,15 @@ void cpu_exec_step_atomic(CPUState *cpu)
         g_assert(!cpu->running);
         cpu->running = true;
 
-        cpu_get_tb_cpu_state_6(env, &pc, &cs_base, &cs_top, &cheri_flags, &flags);
-        tb = tb_lookup(cpu, pc, cs_base, cs_top, cheri_flags, flags, cflags);
+        cpu_get_tb_cpu_state_ext(env, &pc, &cs_base, &pcc_base, &pcc_top,
+                                 &cheri_flags, &flags);
+        tb = tb_lookup(cpu, pc, cs_base, pcc_base, pcc_top, cheri_flags, flags,
+                       cflags);
 
         if (tb == NULL) {
             mmap_lock();
-            tb = tb_gen_code(cpu, pc, cs_base, cs_top, cheri_flags, flags,
-                             cflags);
+            tb = tb_gen_code(cpu, pc, cs_base, pcc_base, pcc_top, cheri_flags,
+                             flags, cflags);
             mmap_unlock();
         }
 
@@ -303,7 +305,8 @@ void cpu_exec_step_atomic(CPUState *cpu)
 struct tb_desc {
     target_ulong pc;
     target_ulong cs_base;
-    target_ulong cs_top;
+    target_ulong pcc_base;
+    target_ulong pcc_top;
     CPUArchState *env;
     tb_page_addr_t phys_page1;
     uint32_t cheri_flags;
@@ -318,8 +321,9 @@ static bool tb_lookup_cmp(const void *p, const void *d)
     const struct tb_desc *desc = d;
 
     if (tb->pc == desc->pc && tb->page_addr[0] == desc->phys_page1 &&
-        tb->cs_base == desc->cs_base && tb->cs_top == desc->cs_top &&
-        tb->cheri_flags == desc->cheri_flags && tb->flags == desc->flags &&
+        tb->cs_base == desc->cs_base && tb->pcc_base == desc->pcc_base &&
+        tb->pcc_top == desc->pcc_top && tb->cheri_flags == desc->cheri_flags &&
+        tb->flags == desc->flags &&
         tb->trace_vcpu_dstate == desc->trace_vcpu_dstate &&
         tb_cflags(tb) == desc->cflags) {
         /* check next page if needed */
@@ -340,17 +344,18 @@ static bool tb_lookup_cmp(const void *p, const void *d)
 }
 
 TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
-                                   target_ulong cs_base, target_ulong cs_top,
-                                   uint32_t cheri_flags, uint32_t flags,
-                                   uint32_t cflags)
+                                   target_ulong cs_base, target_ulong pcc_base,
+                                   target_ulong pcc_top, uint32_t cheri_flags,
+                                   uint32_t flags, uint32_t cflags)
 {
     tb_page_addr_t phys_pc;
     struct tb_desc desc;
     uint32_t h;
 
     desc.env = (CPUArchState *)cpu->env_ptr;
     desc.cs_base = cs_base;
-    desc.cs_top = cs_top;
+    desc.pcc_base = pcc_base;
+    desc.pcc_top = pcc_top;
     desc.cheri_flags = cheri_flags;
     desc.flags = flags;
     desc.cflags = cflags;
@@ -425,16 +430,19 @@ static inline TranslationBlock *tb_find(CPUState *cpu,
 {
     CPUArchState *env = (CPUArchState *)cpu->env_ptr;
     TranslationBlock *tb;
-    target_ulong cs_base, cs_top = 0, pc;
+    target_ulong cs_base, pcc_base = 0, pcc_top = 0, pc;
     uint32_t cheri_flags = 0;
     uint32_t flags;
 
-    cpu_get_tb_cpu_state_6(env, &pc, &cs_base, &cs_top, &cheri_flags, &flags);
+    cpu_get_tb_cpu_state_ext(env, &pc, &cs_base, &pcc_base, &pcc_top,
+                             &cheri_flags, &flags);
 
-    tb = tb_lookup(cpu, pc, cs_base, cs_top, cheri_flags, flags, cflags);
+    tb = tb_lookup(cpu, pc, cs_base, pcc_base, pcc_top, cheri_flags, flags,
+                   cflags);
     if (tb == NULL) {
         mmap_lock();
-        tb = tb_gen_code(cpu, pc, cs_base, cs_top, cheri_flags, flags, cflags);
+        tb = tb_gen_code(cpu, pc, cs_base, pcc_base, pcc_top, cheri_flags,
+                         flags, cflags);
         mmap_unlock();
         /* We add the TB in the virtual pc hash table for the fast lookup */
         qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb);

accel/tcg/internal.h

@@ -12,8 +12,9 @@
 #include "exec/exec-all.h"
 
 TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc,
-                              target_ulong cs_base, target_ulong cs_top,
-                              uint32_t cheri_flags, uint32_t flags, int cflags);
+                              target_ulong cs_base, target_ulong pcc_base,
+                              target_ulong pcc_top, uint32_t cheri_flags,
+                              uint32_t flags, int cflags);
 
 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
 

accel/tcg/tcg-runtime.c

@@ -154,21 +154,23 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
 {
     CPUState *cpu = env_cpu(env);
     TranslationBlock *tb;
-    target_ulong cs_base, cs_top = 0, pc;
+    target_ulong cs_base, pcc_base = 0, pcc_top = 0, pc;
     uint32_t cheri_flags = 0;
     uint32_t flags;
 
-    cpu_get_tb_cpu_state_6(env, &pc, &cs_base, &cs_top, &cheri_flags, &flags);
+    cpu_get_tb_cpu_state_ext(env, &pc, &cs_base, &pcc_base, &pcc_top,
+                             &cheri_flags, &flags);
 
-    tb = tb_lookup(cpu, pc, cs_base, cs_top, cheri_flags, flags, curr_cflags(cpu));
+    tb = tb_lookup(cpu, pc, cs_base, pcc_base, pcc_top, cheri_flags, flags,
+                   curr_cflags(cpu));
     if (tb == NULL) {
         return tcg_code_gen_epilogue;
     }
     qemu_log_mask_and_addr(CPU_LOG_EXEC, pc,
                            "Chain %d: %p [" TARGET_FMT_lx "/" TARGET_FMT_lx
-                           "/" TARGET_FMT_lx "/%#x/%#x] %s\n",
-                           cpu->cpu_index, tb->tc.ptr, cs_base, pc, cs_top,
-                           cheri_flags, flags, lookup_symbol(pc));
+                           "/" TARGET_FMT_lx "-" TARGET_FMT_lx "/%#x/%#x] %s\n",
+                           cpu->cpu_index, tb->tc.ptr, cs_base, pc, pcc_base,
+                           pcc_top, cheri_flags, flags, lookup_symbol(pc));
     return tb->tc.ptr;
 }
 

accel/tcg/translate-all.c

@@ -1309,7 +1309,8 @@ static bool tb_cmp(const void *ap, const void *bp)
 
     return a->pc == b->pc &&
         a->cs_base == b->cs_base &&
-        a->cs_top == b->cs_top &&
+        a->pcc_base == b->pcc_base &&
+        a->pcc_top == b->pcc_top &&
         a->cheri_flags == b->cheri_flags &&
         a->flags == b->flags &&
         (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&
@@ -1844,8 +1845,9 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
 
 /* Called with mmap_lock held for user mode emulation.  */
 TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc,
-                              target_ulong cs_base, target_ulong cs_top,
-                              uint32_t cheri_flags, uint32_t flags, int cflags)
+                              target_ulong cs_base, target_ulong pcc_base,
+                              target_ulong pcc_top, uint32_t cheri_flags,
+                              uint32_t flags, int cflags)
 {
     CPUArchState *env = cpu->env_ptr;
     TranslationBlock *tb, *existing_tb;
@@ -1894,7 +1896,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc,
     tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf);
     tb->pc = pc;
     tb->cs_base = cs_base;
-    tb->cs_top = cs_top;
+    tb->pcc_base = pcc_base;
+    tb->pcc_top = pcc_top;
     tb->cheri_flags = cheri_flags;
     tb->flags = flags;
     tb->cflags = cflags;
@@ -2134,7 +2137,8 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
     TranslationBlock *current_tb = NULL;
     target_ulong current_pc = 0;
     target_ulong current_cs_base = 0;
-    target_ulong current_cs_top = 0;
+    target_ulong current_pcc_base = 0;
+    target_ulong current_pcc_top = 0;
     uint32_t current_cheri_flags = 0;
     uint32_t current_flags = 0;
 #endif /* TARGET_HAS_PRECISE_SMC */
@@ -2180,9 +2184,9 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
                  */
                 current_tb_modified = true;
                 cpu_restore_state_from_tb(cpu, current_tb, retaddr, true);
-                cpu_get_tb_cpu_state_6(env, &current_pc, &current_cs_base,
-                                     &current_cs_top, &current_cheri_flags,
-                                     &current_flags);
+                cpu_get_tb_cpu_state_ext(env, &current_pc, &current_cs_base,
+                                         &current_pcc_base, &current_pcc_top,
+                                         &current_cheri_flags, &current_flags);
             }
 #endif /* TARGET_HAS_PRECISE_SMC */
             tb_phys_invalidate__locked(tb);
@@ -2325,8 +2329,8 @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc)
     int current_tb_modified = 0;
     target_ulong current_pc = 0;
     target_ulong current_cs_base = 0;
-    target_ulong current_cs_top = 0;
-    target_ulong current_ds_base = 0;
+    target_ulong current_pcc_base = 0;
+    target_ulong current_pcc_top = 0;
     uint32_t current_cheri_flags = 0;
     uint32_t current_flags = 0;
 #endif
@@ -2360,9 +2364,9 @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc)
 
             current_tb_modified = 1;
             cpu_restore_state_from_tb(cpu, current_tb, pc, true);
-            cpu_get_tb_cpu_state_6(env, &current_pc, &current_cs_base,
-                                 &current_cs_top, &current_cheri_flags,
-                                 &current_flags);
+            cpu_get_tb_cpu_state_ext(env, &current_pc, &current_cs_base,
+                                     &current_pcc_base, &current_pcc_top,
+                                     &current_cheri_flags, &current_flags);
         }
 #endif /* TARGET_HAS_PRECISE_SMC */
         tb_phys_invalidate(tb, addr);
@@ -2396,12 +2400,13 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr)
         /* The exception probably happened in a helper.  The CPU state should
            have been saved before calling it. Fetch the PC from there.  */
         CPUArchState *env = cpu->env_ptr;
-        target_ulong pc, cs_base, cs_top = 0;
+        target_ulong pc, cs_base, pcc_base = 0, pcc_top = 0;
         uint32_t cheri_flags = 0;
         tb_page_addr_t addr;
         uint32_t flags;
 
-        cpu_get_tb_cpu_state_6(env, &pc, &cs_base, &cs_top, &cheri_flags, &flags);
+        cpu_get_tb_cpu_state_ext(env, &pc, &cs_base, &pcc_base, &pcc_top,
+                                 &cheri_flags, &flags);
         addr = get_page_addr_code(env, pc);
         if (addr != -1) {
             tb_invalidate_phys_range(addr, addr + 1);

accel/tcg/translator.c

@@ -58,8 +58,8 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
     db->max_insns = max_insns;
     db->singlestep_enabled = cpu->singlestep_enabled;
 #ifdef TARGET_CHERI
-    db->pcc_base = tb->cs_base;
-    db->pcc_top = tb->cs_top;
+    db->pcc_base = tb->pcc_base;
+    db->pcc_top = tb->pcc_top;
     cheri_debug_assert(db->pcc_base ==
                        cap_get_base(cheri_get_recent_pcc(cpu->env_ptr)));
     cheri_debug_assert(db->pcc_top ==

hw/arm/smmuv3.c

@@ -259,8 +259,9 @@ static void smmuv3_init_regs(SMMUv3State *s)
     s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
     s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
 
-   /* 4K and 64K granule support */
+    /* 4K, 16K and 64K granule support */
     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
+    s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1);
     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
 
@@ -503,7 +504,8 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
 
         tg = CD_TG(cd, i);
         tt->granule_sz = tg2granule(tg, i);
-        if ((tt->granule_sz != 12 && tt->granule_sz != 16) || CD_ENDI(cd)) {
+        if ((tt->granule_sz != 12 && tt->granule_sz != 14 &&
+             tt->granule_sz != 16) || CD_ENDI(cd)) {
             goto bad_cd;
         }
 

hw/arm/virt.c

@@ -2772,10 +2772,15 @@ static void machvirt_machine_init(void)
 }
 type_init(machvirt_machine_init);
 
+static void virt_machine_6_1_options(MachineClass *mc)
+{
+}
+DEFINE_VIRT_MACHINE_AS_LATEST(6, 1)
+
 static void virt_machine_6_0_options(MachineClass *mc)
 {
 }
-DEFINE_VIRT_MACHINE_AS_LATEST(6, 0)
+DEFINE_VIRT_MACHINE(6, 0)
 
 static void virt_machine_5_2_options(MachineClass *mc)
 {

hw/core/machine.c

@@ -36,6 +36,11 @@
 #include "hw/virtio/virtio.h"
 #include "hw/virtio/virtio-pci.h"
 
+GlobalProperty hw_compat_6_0[] = {
+    { "gpex-pcihost", "allow-unmapped-accesses", "false" },
+};
+const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0);
+
 GlobalProperty hw_compat_5_2[] = {
     { "ICH9-LPC", "smm-compat", "on"},
     { "PIIX4_PM", "smm-compat", "on"},

hw/i386/pc.c

@@ -96,6 +96,9 @@
 #include "trace.h"
 #include CONFIG_DEVICES
 
+GlobalProperty pc_compat_6_0[] = {};
+const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
+
 GlobalProperty pc_compat_5_2[] = {
     { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
 };

hw/i386/pc_piix.c

@@ -415,7 +415,7 @@ static void pc_i440fx_machine_options(MachineClass *m)
     machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
 }
 
-static void pc_i440fx_6_0_machine_options(MachineClass *m)
+static void pc_i440fx_6_1_machine_options(MachineClass *m)
 {
     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
     pc_i440fx_machine_options(m);
@@ -424,6 +424,18 @@ static void pc_i440fx_6_0_machine_options(MachineClass *m)
     pcmc->default_cpu_version = 1;
 }
 
+DEFINE_I440FX_MACHINE(v6_1, "pc-i440fx-6.1", NULL,
+                      pc_i440fx_6_1_machine_options);
+
+static void pc_i440fx_6_0_machine_options(MachineClass *m)
+{
+    pc_i440fx_6_1_machine_options(m);
+    m->alias = NULL;
+    m->is_default = false;
+    compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len);
+    compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len);
+}
+
 DEFINE_I440FX_MACHINE(v6_0, "pc-i440fx-6.0", NULL,
                       pc_i440fx_6_0_machine_options);
 

hw/i386/pc_q35.c

@@ -345,14 +345,25 @@ static void pc_q35_machine_options(MachineClass *m)
     m->max_cpus = 288;
 }
 
-static void pc_q35_6_0_machine_options(MachineClass *m)
+static void pc_q35_6_1_machine_options(MachineClass *m)
 {
     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
     pc_q35_machine_options(m);
     m->alias = "q35";
     pcmc->default_cpu_version = 1;
 }
 
+DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL,
+                   pc_q35_6_1_machine_options);
+
+static void pc_q35_6_0_machine_options(MachineClass *m)
+{
+    pc_q35_6_1_machine_options(m);
+    m->alias = NULL;
+    compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len);
+    compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len);
+}
+
 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL,
                    pc_q35_6_0_machine_options);