Fix the missing flow argument in TileLink/ToAXI4 (chipsalliance#3505)

`flow` must be explicitly passed to `Queue.irrevocable` to avoid
mismatching the arguments.

src/main/scala/tilelink/ToAXI4.scala

@@ -145,8 +145,8 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String
       val depth = if (combinational) 1 else 2
       val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params)))
       val out_w = Wire(chiselTypeOf(out.w))
-      out.w :<>= Queue.irrevocable(out_w, entries=depth, combinational)
-      val queue_arw = Queue.irrevocable(out_arw, entries=depth, combinational)
+      out.w :<>= Queue.irrevocable(out_w, entries=depth, flow=combinational)
+      val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational)
 
       // Fan out the ARW channel to AR and AW
       out.ar.bits := queue_arw.bits