[CODE SHARING] Ravil/sched inst #611
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…structure
- Copied scheduler from MatmulLoopPipeline (much could be consolidated)
- Enable register buffering (even though may increases register pressure)
- Enable num_stages=2+, including multi-buffering, and make `2` the default
- updated tutorial for new tuning default
- added lit tests
- Also move independent(from loop-carried buffer) `triton_gpu.local_store` as early as possible
- check for last atomic (sync?) - also check for other accesses to the source
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Implemented the insertion of the scheduling primitives to MLIR/LLVM