Kernel: New IO mapped Register API and a rework of the E1000 drivers #25521
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Hendiadyoin1
commented
Dec 1, 2024
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| UNMAP_AFTER_INIT void E1000NetworkAdapter::check_quirks() | ||
| { | ||
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| u16 device_id = device_identifier().hardware_id().device_id; | ||
| // The 82541xx and 82547GI/EI have a different EEPROM access method | ||
| switch (device_id) { | ||
| case 0x1019: // 82547EI-A0, 82547EI-A1, 82547EI-B0, 82547GI-B0 | ||
| case 0x101A: // 82547EI-B0 | ||
| case 0x1013: // 82541EI-A0, 82541EI-B0 | ||
| case 0x1018: // 82541EI-B0 | ||
| case 0x1076: // 82541GI-B1, 82541PI-C0 | ||
| case 0x1077: // 82541GI-B1 | ||
| case 0x1078: // 82541ER-C0 | ||
| m_is_82541xx_82547GI_EI.set(); | ||
| break; | ||
| default: | ||
| break; | ||
| } | ||
| } |
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Would be cool if someone who has this HW can check one of these...
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| // FIXME: Do this properly | ||
| // IPGT:= 10 (8/6 for the 82544GC/EI) - IPG Transmit Time (10 bit) | ||
| // The 82544GC/EI has a different value for IPGT depending if it is in IEEE 802.3 mode or 10/100/1000BASE-T mode | ||
| // IPGR1:= 8 - IPG Receive Time 1 (half duplex only) ~= 2/3 of IPGR2 (10 bit) | ||
| // IPGR2:= 6 (+6) - IPG Receive Time 2 (half duplex only) (10 bit) | ||
| // Recommendation are for "IEEE 802.3 minimum IPG value of 96-bit time" | ||
| // The magic value here has: | ||
| // 10, 8, 6 so it should be fine for now | ||
| m_registers.write<Register::TIPG>(0x0060200A); |
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I have no clue what half of this means....
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| // FIXME: This seems odd to me: | ||
| // We disable interrupts and then wait for and irq to happen... |
Kernel/Net/Intel/E1000Registers.h
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| // 17-31 Reserved | ||
| }; | ||
| AK_ENUM_BITWISE_OPERATORS(InterruptMask); | ||
| // FIXME: This should be the same as the interrupt cause, which is nicer? |
This also adds some quirk handling, and 64 bit DMA support, which where previously missing.
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Less defines, more type safety....