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dft: update docs, change starting ordinal to 0 instead of 1
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Signed-off-by: Mohamed Gaber <[email protected]>
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@donn
donn committed Dec 23, 2024
1 parent 3bc69bf commit 384887b
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42 changes: 40 additions & 2 deletions src/dft/README.md
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Expand Up @@ -77,13 +77,51 @@ preview_dft

### Insert DFT

Architect scan chains and connect them up in a way that minimises wirelength. As a result, this
should be run after placement, and after `scan_replace`.
Architect scan chains and connect them up in a way that minimises wirelength. As
a result, this should be run after placement, and after `scan_replace`.

```tcl
insert_dft
[-per_chain_enable]
[-scan_enable_name_pattern <string>]
[-scan_in_name_pattern <string>]
[-scan_out_name_pattern <string>]
```

#### Options

| Switch Name | Description |
| ---- | ---- |
| `-per_chain_enable` | Creates one enable signal per chain instead of reusing the same one for every chain. |
| `-scan_enable_name_pattern` | A format pattern with exactly one set of braces (`{}`) to use to find or create scan enable drivers. The braces will be replaced with the chain's ordinal number (starting at `0`) if `-per_chain_enable` is defined, otherwise, all will share `0`. If an un-escaped forward slash (`/`) is found, instead of searching for and/or creating a top-level port, an instance's pin will be searched for instead where the part of the string preceding the `/` is interpreted as the instance name and part succeeding it will be interpreted as the pin's name. |
| `-scan_in_name_pattern` | A format pattern with exactly one set of braces (`{}`) to use to find or create scan in drivers. The braces will be replaced with the chain's ordinal number (starting at `0`). If an un-escaped forward slash (`/`) is found, instead of searching for and/or creating a top-level port, an instance's pin will be searched for instead where the part of the string preceding the `/` is interpreted as the instance name and part succeeding it will be interpreted as the pin's name. |
| `-scan_out_name_pattern` | A format pattern with exactly one set of braces (`{}`) to use to find or create scan in loads. The braces will be replaced with the chain's ordinal number (starting at `0`). If an un-escaped forward slash (`/`) is found, instead of searching for and/or creating a top-level port, an instance's pin will be searched for instead where the part of the string preceding the `/` is interpreted as the instance name and part succeeding it will be interpreted as the pin's name. |

### Write Scan Chains

Writes a JSON file containing metadata about the current architected scan chain.

The JSON file is currently in this format:

```jsonc
{
"chain_0": {
"cells": [
"scanflop_0",
"scanflop_1",
"scanflop_2"
]
},
/* … other chains … */
}
```

…where the order of `.chain_name.cells` corresponds to the order of the elements
in the scan-chain.

```tcl
write_scan_chains
```

## Example scripts

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4 changes: 2 additions & 2 deletions src/dft/src/stitch/ScanStitch.cpp
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Expand Up @@ -29,8 +29,8 @@ void ScanStitch::Stitch(
return;
}

size_t enable_ordinal = 1;
size_t ordinal = 1;
size_t enable_ordinal = 0;
size_t ordinal = 0;
for (const std::unique_ptr<ScanChain>& scan_chain : scan_chains) {
Stitch(top_block_, *scan_chain, logger, ordinal, enable_ordinal);
ordinal += 1;
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30 changes: 15 additions & 15 deletions src/dft/test/max_chain_count_sky130.vok
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Expand Up @@ -11,8 +11,8 @@ module max_chain_count (clock,
output9,
port1,
set_b,
scan_enable_1,
scan_in_1);
scan_enable_0,
scan_in_0);
input clock;
output output1;
output output10;
Expand All @@ -26,68 +26,68 @@ module max_chain_count (clock,
output output9;
input port1;
input set_b;
input scan_enable_1;
input scan_in_1;
input scan_enable_0;
input scan_in_0;


sky130_fd_sc_hd__sdfsbp_1 ff1_clk1_rising (.D(port1),
.Q(output1),
.SCD(output2),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff2_clk1_rising (.D(port1),
.Q(output2),
.SCD(output3),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff3_clk1_rising (.D(port1),
.Q(output3),
.SCD(output4),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff4_clk1_rising (.D(port1),
.Q(output4),
.SCD(output5),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff5_clk1_rising (.D(port1),
.Q(output5),
.SCD(output6),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff6_clk1_rising (.D(port1),
.Q(output6),
.SCD(output7),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff7_clk1_rising (.D(port1),
.Q(output7),
.SCD(output8),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff8_clk1_rising (.D(port1),
.Q(output8),
.SCD(output9),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff9_clk1_rising (.D(port1),
.Q(output9),
.SCD(scan_in_1),
.SCE(scan_enable_1),
.SCD(scan_in_0),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff10_clk1_rising (.D(port1),
.Q(output10),
.SCD(output1),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
endmodule
4 changes: 2 additions & 2 deletions src/dft/test/one_cell_sky130.ok
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Expand Up @@ -53,8 +53,8 @@ Instance ff1
Path cells: sky130_fd_sc_hd__sdfsbp_1
Input pins:
D input port1
SCD input scan_in_1
SCE input scan_enable_1
SCD input scan_in_0
SCE input scan_enable_0
SET_B input set_b
CLK input clock
Output pins:
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12 changes: 6 additions & 6 deletions src/dft/test/one_cell_sky130.vok
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Original file line number Diff line number Diff line change
Expand Up @@ -2,20 +2,20 @@ module one_cell (clock,
output1,
port1,
set_b,
scan_enable_1,
scan_in_1);
scan_enable_0,
scan_in_0);
input clock;
output output1;
input port1;
input set_b;
input scan_enable_1;
input scan_in_1;
input scan_enable_0;
input scan_in_0;


sky130_fd_sc_hd__sdfsbp_1 ff1 (.D(port1),
.Q(output1),
.SCD(scan_in_1),
.SCE(scan_enable_1),
.SCD(scan_in_0),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
endmodule
30 changes: 15 additions & 15 deletions src/dft/test/place_sort_sky130.vok
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Original file line number Diff line number Diff line change
Expand Up @@ -11,8 +11,8 @@ module place_sort (clock,
output9,
port1,
set_b,
scan_enable_1,
scan_in_1);
scan_enable_0,
scan_in_0);
input clock;
output output1;
output output10;
Expand All @@ -26,68 +26,68 @@ module place_sort (clock,
output output9;
input port1;
input set_b;
input scan_enable_1;
input scan_in_1;
input scan_enable_0;
input scan_in_0;


sky130_fd_sc_hd__sdfsbp_1 ff1_clk1_rising (.D(port1),
.Q(output1),
.SCD(output5),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff2_clk1_rising (.D(port1),
.Q(output2),
.SCD(output8),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff3_clk1_rising (.D(port1),
.Q(output3),
.SCD(output4),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff4_clk1_rising (.D(port1),
.Q(output4),
.SCD(output9),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff5_clk1_rising (.D(port1),
.Q(output5),
.SCD(scan_in_1),
.SCE(scan_enable_1),
.SCD(scan_in_0),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff6_clk1_rising (.D(port1),
.Q(output6),
.SCD(output2),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff7_clk1_rising (.D(port1),
.Q(output7),
.SCD(output6),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff8_clk1_rising (.D(port1),
.Q(output8),
.SCD(output10),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff9_clk1_rising (.D(port1),
.Q(output9),
.SCD(output7),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
sky130_fd_sc_hd__sdfsbp_1 ff10_clk1_rising (.D(port1),
.Q(output10),
.SCD(output1),
.SCE(scan_enable_1),
.SCE(scan_enable_0),
.SET_B(set_b),
.CLK(clock));
endmodule
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