xen/arch/x86: Restore MTRRs earlier

There is over one minute boot delay with SLAUNCH on Intel platform. Restore MTRRs earlier, so that the delays is reduced. Signed-off-by: Michał Żygowski <[email protected]>
TrenchBoot · Aug 17, 2024 · 0623704 · 0623704
1 parent 0b53c6a
commit 0623704
Show file tree

Hide file tree

Showing 4 changed files with 16 additions and 18 deletions.
diff --git a/xen/arch/x86/e820.c b/xen/arch/x86/e820.c
@@ -457,9 +457,6 @@ static uint64_t __init mtrr_top_of_ram(void)
     rdmsrl(MSR_MTRRcap, mtrr_cap);
     rdmsrl(MSR_MTRRdefType, mtrr_def);
 
-    if ( slaunch_active && boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
-        txt_restore_mtrrs(e820_verbose);
-
     if ( e820_verbose )
         printk(" MTRR cap: %"PRIx64" type: %"PRIx64"\n", mtrr_cap, mtrr_def);
 

diff --git a/xen/arch/x86/include/asm/intel_txt.h b/xen/arch/x86/include/asm/intel_txt.h
@@ -324,6 +324,6 @@ static inline int is_in_pmr(struct txt_os_sinit_data *os_sinit, uint64_t base,
 
 extern void map_txt_mem_regions(void);
 extern void protect_txt_mem_regions(void);
-extern void txt_restore_mtrrs(bool e820_verbose);
+extern void txt_restore_mtrrs(void);
 
 #endif /* __ASSEMBLY__ */
diff --git a/xen/arch/x86/intel_txt.c b/xen/arch/x86/intel_txt.c
@@ -57,7 +57,7 @@ void __init protect_txt_mem_regions(void)
                  E820_RAM, E820_UNUSABLE);
 }
 
-void __init txt_restore_mtrrs(bool e820_verbose)
+void __init txt_restore_mtrrs(void)
 {
     struct txt_os_mle_data *os_mle;
     struct slr_table *slrt;
@@ -75,18 +75,16 @@ void __init txt_restore_mtrrs(bool e820_verbose)
     rdmsrl(MSR_MTRRcap, mtrr_cap);
     rdmsrl(MSR_MTRRdefType, mtrr_def);
 
-    if ( e820_verbose ) {
-        printk("MTRRs set previously for SINIT ACM:\n");
-        printk(" MTRR cap: %"PRIx64" type: %"PRIx64"\n", mtrr_cap, mtrr_def);
+    printk("MTRRs set previously for SINIT ACM:\n");
+    printk(" MTRR cap: %"PRIx64" type: %"PRIx64"\n", mtrr_cap, mtrr_def);
 
-        for ( i = 0; i < (uint8_t)mtrr_cap; i++ )
-        {
-            rdmsrl(MSR_IA32_MTRR_PHYSBASE(i), base);
-            rdmsrl(MSR_IA32_MTRR_PHYSMASK(i), mask);
+    for ( i = 0; i < (uint8_t)mtrr_cap; i++ )
+    {
+        rdmsrl(MSR_IA32_MTRR_PHYSBASE(i), base);
+        rdmsrl(MSR_IA32_MTRR_PHYSMASK(i), mask);
 
-            printk(" MTRR[%d]: base %"PRIx64" mask %"PRIx64"\n",
-                   i, base, mask);
-        }
+        printk(" MTRR[%d]: base %"PRIx64" mask %"PRIx64"\n",
+                i, base, mask);
     }
 
     slrt = __va(os_mle->slrt);
@@ -111,7 +109,4 @@ void __init txt_restore_mtrrs(bool e820_verbose)
         wrmsrl(MSR_IA32_MTRR_PHYSBASE(i), base);
         wrmsrl(MSR_IA32_MTRR_PHYSMASK(i), mask);
     }
-
-    if ( e820_verbose )
-        printk("Restored MTRRs:\n"); /* Printed by caller, mtrr_top_of_ram(). */
 }
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
@@ -55,6 +55,7 @@
 #include <asm/guest.h>
 #include <asm/microcode.h>
 #include <asm/pv/domain.h>
+#include <asm/intel_txt.h>
 #include <asm/slaunch.h>
 #include <asm/tpm.h>
 
@@ -1180,6 +1181,11 @@ void __init noreturn __start_xen(unsigned long mbi_p)
         tpm_measure_slrt();
 
         protect_slaunch_mem_regions();
+
+        /* Restore MTRRs as soon as possible, otherwise we might get a huge boot
+         * delay */
+        if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+            txt_restore_mtrrs();
     }
 
     /* Sanitise the raw E820 map to produce a final clean version. */