Need help following the Pre-implemented Modules tutorial

[garyfpga]

Hi,

I would like to do something very similar to the pre-implemented module tutorial. Basically I have a basic module which I would like to,

1. create a pblock
2. place and route a module within the pblock
3. duplicate the pblock multiple times (with placement and routing), and I might even wanna duplicated it to other SLR

Now I see this in the tutorial.
set_property HD.CLK_SRC BUFGCTRL_X0Y2 [get_ports clk]

My question is, is this necessary? And if it is necessary how do I select which BUFGCTRL to use? Should I just randomly pick one BUFGCTRL within the pblock?

Thanks

Gary

[clavin-xlnx]

Hi Gary,

To answer your first question, the HD.CLK_SRC is not required, but highly recommended as it will improve routing quality as it allows the router (in Vivado) to take into account the potential clock skew it might see when put in the full context of the design. Without it, Vivado will just not take into account the clock delay path when routing, so you will likely see a drop in final fmax for the design.

To choose the clock buffer, you may want to look to the final implementation of your design. If you can construct your design in a conventional manner (flat through Vivado), you could reuse the same BUFGCTRL that Vivado selects. Ultimately, it should be the clock buffer that is going to be used in the final implementation so that the router can route against the realistic timing numbers.

Hope that helps.

Chris

[garyfpga]

Hi Clavin,

Thank you for your reply. I just re-read the tutorial and saw that fixing the HD.CLK_SRC is only for provide a better clock skew estimation and hence it is not absolutely necessary.

Would you mind also enlighting me about the clock uncertainity in part two of the tutorial. I see this
Clock Uncertainty (applied before placement, then removed before routing)

What does this actually mean, does it mean before the placement we put a certain nanosecond of clock uncertainity in the placement pharse to guide the time driven placement. And when we finished routing, the timing is calculated by the precise physial design and the clock uncertainity is not used for calculation (which should be the correct way for timing analysis.

Thanks

Gary

[clavin-xlnx]

Hi Gary,

Clock uncertainty is a component of delay when calculating the maximum frequency of the clock period, more clock uncertainty means a slower clock frequency at which the circuit can run.

In the tutorial, we are artificially adding clock uncertainty to the timing calculation as a constraint on the design. This is done to help push the placement solution to find a better result. That is, the placer must try to globally reduce the critical paths by placing things together because it must account for the extra clock uncertainty added by the constraint. This often leads to results that can be better, however, adding too much can also make results worse. Ultimately, it is just a strategy used to find a variety of solutions for a given design in hopes that the placement and routing solution space is explored more thoroughly.

Chris