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Pull requests: Xilinx/RapidWright
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[DesignTools] updatePinsIsRouted() to return num unrouted sinks
#1131
opened Dec 24, 2024 by
eddieh-xlnx
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[DesignTools] foreachConnectedBELPin() to walk through Versal IMRs
#1129
opened Dec 24, 2024 by
eddieh-xlnx
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Test for SiteInst.isEmpty()
needs new release
Dependent on the next future release
#1128
opened Dec 19, 2024 by
clavin-xlnx
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Draft
Tests for Versal BEL flags and site unrouting
needs new release
Dependent on the next future release
#1125
opened Dec 16, 2024 by
clavin-xlnx
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[TestDesign] Add testPlaceCellPinMappings()
needs new release
Dependent on the next future release
#1122
opened Dec 5, 2024 by
eddieh-xlnx
•
Draft
Tile.getWireConnections() not consistent with Vivado
#1096
opened Nov 6, 2024 by
eddieh-xlnx
•
Draft
[DesignTools] makeBlackbox() to use phys netlist not logical
needs new release
Dependent on the next future release
#1044
opened Aug 7, 2024 by
eddieh-xlnx
•
Draft
[Interchange] Prototype multi-message support for logical and physical netlists
#1031
opened Jul 13, 2024 by
clavin-xlnx
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[RWRoute] Adjust wire base costs + cross SLR estimates
#1030
opened Jul 12, 2024 by
eddieh-xlnx
•
Draft
[DesignTools.deletePblock()]: utility to delete a pblock
#1020
opened Jun 30, 2024 by
Licheng-Guo
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[Interchange] Exports DeviceResources Routing (Wires and Nodes) Info in Multiple Messages
#1017
opened Jun 25, 2024 by
clavin-xlnx
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Adding shape support for DREAMPlaceFPGA inputs and Interchange Netlist
#1011
opened Jun 21, 2024 by
clavin-xlnx
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Node.getAllWiresInNode() returns empty list when Vivado doesn't
bug
#1002
opened Jun 12, 2024 by
eddieh-xlnx
•
Draft
[DeviceResourcesWriter] Output resource timings for US+
#1001
opened Jun 12, 2024 by
eddieh-xlnx
•
Draft
[EDIFTools] Adds support for lower hierarchy connection
#944
opened Jan 17, 2024 by
clavin-xlnx
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Adds a tieoff method for module instances with unconnected inputs
#811
opened Sep 7, 2023 by
clavin-xlnx
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Inconsistent behaviour for Cell.getSitePinFromLogicalPin()
bug
#473
opened Jul 14, 2022 by
eddieh-xlnx
•
Draft
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