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Issues: abs-tudelft/fletcher
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Mismatch between bus address width and addresses passed through vhdmmio
bug
Something isn't working
fletchgen
Fletchgen related issue
#243
opened Sep 28, 2020 by
johanpel
Use an existing standard for start/stop/reset MMIO control registers
enhancement
New feature or request
#193
opened Sep 24, 2019 by
jvanstraten
AXI read/write converter broken when slices depth > 0
bug
Something isn't working
lang:vhdl
VHDL related issue
#164
opened Jul 18, 2019 by
johanpel
Wrap AxiTop into an AxiTopSim for simulation
enhancement
New feature or request
fletchgen
Fletchgen related issue
#135
opened Jun 27, 2019 by
johanpel
Prevent ambiguity among Arrow data stream signals
hardware
Hardware related issue
#123
opened Jun 6, 2019 by
johanpel
Multi-clock domain support incomplete
enhancement
New feature or request
hardware
Hardware related issue
#93
opened Dec 6, 2018 by
jvanstraten
Arrow implicit null bitmap is not propagated during run time
enhancement
New feature or request
hardware
Hardware related issue
runtime
Runtime related issue
#66
opened Oct 15, 2018 by
johanpel
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