Widen flow control credit counters to support scaled flow control cre…

…dits and mask off appropriately

Signed-off-by: Alex Forencich <[email protected]>

cocotbext/pcie/core/port.py

@@ -52,7 +52,7 @@
 
 class FcStateData:
     def __init__(self, init=0, *args, **kwargs):
-        self.__dict__.setdefault('_base_field_size', 12)
+        self.__dict__.setdefault('_base_field_size', 16)
 
         self.tx_field_size = self._base_field_size
         self.tx_field_range = 2**self.tx_field_size
@@ -126,7 +126,7 @@ def rx_release_fc(self, fc):
 
 class FcStateHeader(FcStateData):
     def __init__(self, *args, **kwargs):
-        self._base_field_size = 8
+        self._base_field_size = 12
         super().__init__(*args, **kwargs)
 
 

cocotbext/pcie/intel/ptile/ptile_model.py

@@ -874,27 +874,27 @@ async def _run_tx_fc_logic(self):
         clock_edge_event = RisingEdge(self.coreclkout_hip)
 
         while True:
-            self.tx_cdts_limit.value = self.upstream_port.fc_state[0].ph.tx_credit_limit
+            self.tx_cdts_limit.value = self.upstream_port.fc_state[0].ph.tx_credit_limit & 0xfff
             self.tx_cdts_limit_tdm_idx.value = 0
             await clock_edge_event
 
-            self.tx_cdts_limit.value = self.upstream_port.fc_state[0].nph.tx_credit_limit
+            self.tx_cdts_limit.value = self.upstream_port.fc_state[0].nph.tx_credit_limit & 0xfff
             self.tx_cdts_limit_tdm_idx.value = 1
             await clock_edge_event
 
-            self.tx_cdts_limit.value = self.upstream_port.fc_state[0].cplh.tx_credit_limit
+            self.tx_cdts_limit.value = self.upstream_port.fc_state[0].cplh.tx_credit_limit & 0xfff
             self.tx_cdts_limit_tdm_idx.value = 2
             await clock_edge_event
 
-            self.tx_cdts_limit.value = self.upstream_port.fc_state[0].pd.tx_credit_limit
+            self.tx_cdts_limit.value = self.upstream_port.fc_state[0].pd.tx_credit_limit & 0xffff
             self.tx_cdts_limit_tdm_idx.value = 4
             await clock_edge_event
 
-            self.tx_cdts_limit.value = self.upstream_port.fc_state[0].npd.tx_credit_limit
+            self.tx_cdts_limit.value = self.upstream_port.fc_state[0].npd.tx_credit_limit & 0xffff
             self.tx_cdts_limit_tdm_idx.value = 5
             await clock_edge_event
 
-            self.tx_cdts_limit.value = self.upstream_port.fc_state[0].cpld.tx_credit_limit
+            self.tx_cdts_limit.value = self.upstream_port.fc_state[0].cpld.tx_credit_limit & 0xffff
             self.tx_cdts_limit_tdm_idx.value = 6
             await clock_edge_event
 

cocotbext/pcie/intel/s10/s10_model.py

@@ -752,18 +752,18 @@ async def _run_tx_fc_logic(self):
 
         while True:
             if self.tx_ph_cdts is not None:
-                self.tx_ph_cdts.value = self.upstream_port.fc_state[0].ph.tx_credits_available
+                self.tx_ph_cdts.value = self.upstream_port.fc_state[0].ph.tx_credits_available & 0xff
             if self.tx_pd_cdts is not None:
-                self.tx_pd_cdts.value = self.upstream_port.fc_state[0].pd.tx_credits_available
+                self.tx_pd_cdts.value = self.upstream_port.fc_state[0].pd.tx_credits_available & 0xfff
             if self.tx_nph_cdts is not None:
-                self.tx_nph_cdts.value = self.upstream_port.fc_state[0].nph.tx_credits_available
+                self.tx_nph_cdts.value = self.upstream_port.fc_state[0].nph.tx_credits_available & 0xff
             if self.tx_cplh_cdts is not None:
-                self.tx_cplh_cdts.value = self.upstream_port.fc_state[0].cplh.tx_credits_available
+                self.tx_cplh_cdts.value = self.upstream_port.fc_state[0].cplh.tx_credits_available & 0xff
             if self.l_tile:
                 if self.tx_npd_cdts is not None:
-                    self.tx_npd_cdts.value = self.upstream_port.fc_state[0].npd.tx_credits_available
+                    self.tx_npd_cdts.value = self.upstream_port.fc_state[0].npd.tx_credits_available & 0xfff
                 if self.tx_cpld_cdts is not None:
-                    self.tx_cpld_cdts.value = self.upstream_port.fc_state[0].cpld.tx_credits_available
+                    self.tx_cpld_cdts.value = self.upstream_port.fc_state[0].cpld.tx_credits_available & 0xfff
             # self.tx_hdr_cdts_consumed
             # self.tx_data_cdts_consumed
             # self.tx_cdts_type

cocotbext/pcie/xilinx/us/us_model.py

@@ -1280,17 +1280,17 @@ async def _run_cfg_fc_logic(self):
                 cfg_fc_cpld = 0
 
             if self.cfg_fc_ph is not None:
-                self.cfg_fc_ph.value = cfg_fc_ph
+                self.cfg_fc_ph.value = cfg_fc_ph & 0xff
             if self.cfg_fc_pd is not None:
-                self.cfg_fc_pd.value = cfg_fc_pd
+                self.cfg_fc_pd.value = cfg_fc_pd & 0xfff
             if self.cfg_fc_nph is not None:
-                self.cfg_fc_nph.value = cfg_fc_nph
+                self.cfg_fc_nph.value = cfg_fc_nph & 0xff
             if self.cfg_fc_npd is not None:
-                self.cfg_fc_npd.value = cfg_fc_npd
+                self.cfg_fc_npd.value = cfg_fc_npd & 0xfff
             if self.cfg_fc_cplh is not None:
-                self.cfg_fc_cplh.value = cfg_fc_cplh
+                self.cfg_fc_cplh.value = cfg_fc_cplh & 0xff
             if self.cfg_fc_cpld is not None:
-                self.cfg_fc_cpld.value = cfg_fc_cpld
+                self.cfg_fc_cpld.value = cfg_fc_cpld & 0xfff
 
     async def _run_cfg_ctrl_logic(self):
         clock_edge_event = RisingEdge(self.user_clk)

cocotbext/pcie/xilinx/us/usp_model.py

@@ -1362,17 +1362,17 @@ async def _run_cfg_fc_logic(self):
                 cfg_fc_cpld = 0
 
             if self.cfg_fc_ph is not None:
-                self.cfg_fc_ph.value = cfg_fc_ph
+                self.cfg_fc_ph.value = cfg_fc_ph & 0xff
             if self.cfg_fc_pd is not None:
-                self.cfg_fc_pd.value = cfg_fc_pd
+                self.cfg_fc_pd.value = cfg_fc_pd & 0xfff
             if self.cfg_fc_nph is not None:
-                self.cfg_fc_nph.value = cfg_fc_nph
+                self.cfg_fc_nph.value = cfg_fc_nph & 0xff
             if self.cfg_fc_npd is not None:
-                self.cfg_fc_npd.value = cfg_fc_npd
+                self.cfg_fc_npd.value = cfg_fc_npd & 0xfff
             if self.cfg_fc_cplh is not None:
-                self.cfg_fc_cplh.value = cfg_fc_cplh
+                self.cfg_fc_cplh.value = cfg_fc_cplh & 0xff
             if self.cfg_fc_cpld is not None:
-                self.cfg_fc_cpld.value = cfg_fc_cpld
+                self.cfg_fc_cpld.value = cfg_fc_cpld & 0xfff
 
     async def _run_cfg_ctrl_logic(self):
         clock_edge_event = RisingEdge(self.user_clk)