adrv9001/zcu102: Enable independent TX mode in CMOS

For CMOS case, lane rates are so low that reference clock of the source
synchronous interface can be routed on non-clock routes. The delays on
the clock line are adjusted by the digital interface tuning controlled
through software.

Lock down clock buffers on Rx and Tx interfaces, this avoids suboptimal
placement which causes large skew between clocks at the serdes pins.

projects/adrv9001/zcu102/cmos_constr.xdc

@@ -53,4 +53,18 @@ set_clock_latency -source -early -0.25 [get_clocks rx2_dclk_out]
 set_clock_latency -source -late 0.25 [get_clocks rx1_dclk_out]
 set_clock_latency -source -late 0.25 [get_clocks rx2_dclk_out]
 
+create_pblock SSI_REGION
+add_cells_to_pblock [get_pblocks SSI_REGION] [get_cells -quiet [list \
+    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_buf_fast \
+    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf \
+    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_buf_fast \
+    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf \
+    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_dac_clk_in_gbuf \
+    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_dac_div_clk_rbuf \
+    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_dac_clk_in_gbuf \
+    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_dac_div_clk_rbuf \
+    ]]
+resize_pblock SSI_REGION -add CLOCKREGION_X3Y2:CLOCKREGION_X3Y3
 
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_dac_clk_in_ibuf/O]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_dac_clk_in_ibuf/O]

projects/adrv9001/zcu102/system_bd.tcl

@@ -2,7 +2,7 @@
 source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
 source ../common/adrv9001_bd.tcl
 
-ad_ip_parameter axi_adrv9001 CONFIG.USE_RX_CLK_FOR_TX 1
+ad_ip_parameter axi_adrv9001 CONFIG.USE_RX_CLK_FOR_TX [expr $ad_project_params(CMOS_LVDS_N) == 0]
 
 #system ID
 ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9