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Merge pull request #98 from airbus-seclab/release
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bdcht authored May 14, 2024
2 parents f4081db + 6be7bbb commit 7f7e529
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17 changes: 15 additions & 2 deletions README.rst
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Expand Up @@ -57,15 +57,14 @@ User documentation and API can be found at
Todo
====

Some components of Amoco are still in the
Some components of amoco are still in the
process of being pushed to the release branch or further developed.
More precisely:

- x86 fpu instructions semantics are not implemented,
- arm SIMD, VFP, NEON, TrustZone, Jazelle instruction sets are not implemented,
- some solver-based disassembling strategies are not merged yet.
- idb import/export features are not implemented.
- 6502 and PPC archs are planned.

Contributions to fulfill uncomplete/unimplemented parts are welcome.

Expand All @@ -88,6 +87,19 @@ Please see `LICENSE`_.
Changelog
=========

- `v2.9.10`_

* x86: add support for real mode execution
* x86: add full support for segmentation/paging
* add baremetal-x86 system for bios firmware analysis
* merge new arch.io module to define IOs' stubs
* merge cas.blobs module
* add fast versions of rep stos/lods/scas/movs
* add tracepoint method in emul class
* add support for PE resources
* improve amoco app load/emul commands
* add set,display,nexti,until in emul ui.

- `v2.9.9`_

* add ppc32 (e200) architecture
Expand Down Expand Up @@ -397,6 +409,7 @@ Changelog
.. _sqlalchemy: http://www.sqlalchemy.org
.. _QDarkStyleSheet: https://github.com/ColinDuquesnoy/QDarkStyleSheet
.. _LICENSE: https://github.com/bdcht/amoco/blob/release/LICENSE
.. _v2.9.10: https://github.com/bdcht/amoco/releases/tag/v2.9.10
.. _v2.9.9: https://github.com/bdcht/amoco/releases/tag/v2.9.9
.. _v2.9.8: https://github.com/bdcht/amoco/releases/tag/v2.9.8
.. _v2.9.7: https://github.com/bdcht/amoco/releases/tag/v2.9.7
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2 changes: 1 addition & 1 deletion amoco/arch/arm/cpu_armv7.py
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Expand Up @@ -29,7 +29,7 @@
disassemble = disassembler([spec_armv7, spec_thumb], instruction_armv7, mode, endian)


def PC():
def PC(state=None):
return pc_


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2 changes: 1 addition & 1 deletion amoco/arch/arm/cpu_armv8.py
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Expand Up @@ -25,7 +25,7 @@
disassemble = disassembler([spec_armv8], endian=endian, iclass=instruction_armv8)


def PC():
def PC(state=None):
return pc


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2 changes: 1 addition & 1 deletion amoco/arch/avr/cpu.py
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Expand Up @@ -21,7 +21,7 @@
disassemble = disassembler([spec], iclass=instruction_avr)


def PC():
def PC(state=None):
return pc


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52 changes: 26 additions & 26 deletions amoco/arch/avr/env.py
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Expand Up @@ -81,30 +81,30 @@
EEPM1 = slc(EECR,5, 1, "EEPM1") # 10=WriteOnly 11:Reserved

vectors = [
ext("RESET",8),
ext("INT0",8),
ext("INT1",8),
ext("PCINT0",8),
ext("PCINT1",8),
ext("PCINT2",8),
ext("WDT",8),
ext("TIMER2_COMPA",8),
ext("TIMER2_COMPB",8),
ext("TIMER2_OVF",8),
ext("TIMER1_CAPT",8),
ext("TIMER1_COMPA",8),
ext("TIMER1_COMPB",8),
ext("TIMER1_OVF",8),
ext("TIMER0_COMPA",8),
ext("TIMER0_COMPB",8),
ext("TIMER0_OVF",8),
ext("SPI_STC",8),
ext("USART_RX",8),
ext("USART_UDRE",8),
ext("USART_TX",8),
ext("ADC",8),
ext("EE_READY",8),
ext("ANALOG_COMP",8),
ext("TWI",8),
ext("SPM_READY",8),
ext("RESET",size=8),
ext("INT0",size=8),
ext("INT1",size=8),
ext("PCINT0",size=8),
ext("PCINT1",size=8),
ext("PCINT2",size=8),
ext("WDT",size=8),
ext("TIMER2_COMPA",size=8),
ext("TIMER2_COMPB",size=8),
ext("TIMER2_OVF",size=8),
ext("TIMER1_CAPT",size=8),
ext("TIMER1_COMPA",size=8),
ext("TIMER1_COMPB",size=8),
ext("TIMER1_OVF",size=8),
ext("TIMER0_COMPA",size=8),
ext("TIMER0_COMPB",size=8),
ext("TIMER0_OVF",size=8),
ext("SPI_STC",size=8),
ext("USART_RX",size=8),
ext("USART_UDRE",size=8),
ext("USART_TX",size=8),
ext("ADC",size=8),
ext("EE_READY",size=8),
ext("ANALOG_COMP",size=8),
ext("TWI",size=8),
ext("SPM_READY",size=8),
]
2 changes: 1 addition & 1 deletion amoco/arch/dwarf/cpu.py
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Expand Up @@ -21,7 +21,7 @@
disassemble.maxlen = 21


def PC():
def PC(state=None):
return op_ptr


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2 changes: 1 addition & 1 deletion amoco/arch/eBPF/cpu.py
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Expand Up @@ -21,7 +21,7 @@
disassemble = disassembler([spec], iclass=instruction_eBPF)


def PC():
def PC(state=None):
return pc


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2 changes: 1 addition & 1 deletion amoco/arch/eBPF/cpu_bpf.py
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Expand Up @@ -22,7 +22,7 @@
disassemble = disassembler([spec_bpf], iclass=instruction_BPF)


def PC():
def PC(state=None):
return pc


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42 changes: 42 additions & 0 deletions amoco/arch/io.py
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@@ -0,0 +1,42 @@
from amoco.cas.expressions import top
from types import MethodType
from amoco.logger import Log

logger = Log(__name__)
logger.debug("loading module")

class DefineIO:

def __init__(self,port,name=None):
self.io = IO(port,name)

def __enter__(self):
return self

def __exit__(self, exc_type, exc_value, traceback):
IO.ports[self.io.port] = self.io

def In(self, func):
self.io.In = MethodType(func,self.io)
return func

def Out(self, func):
self.io.Out = MethodType(func,self.io)
return func

class IO:
ports = {}
@classmethod
def get_port(cls,port):
return cls.ports.get(port,cls(port))

def __init__(self,port,name=None):
self.port = port
self.name = name or "IO#0x%x"%port
def In(self,env,dl):
logger.warning("undefined %s IN"%str(self))
return top(dl*8)
def Out(self,env,src):
logger.warning("undefined %s OUT (%s)"%(str(self),src))
def __str__(self):
return self.name
2 changes: 1 addition & 1 deletion amoco/arch/mips/cpu_r3000.py
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Expand Up @@ -24,7 +24,7 @@
disassemble = disassembler([spec], iclass=instruction_r3000,endian=endian)


def PC():
def PC(state=None):
return pc

def get_data_endian():
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2 changes: 1 addition & 1 deletion amoco/arch/mips/cpu_r3000LE.py
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Expand Up @@ -22,7 +22,7 @@
disassemble = disassembler([spec], iclass=instruction_r3000)


def PC():
def PC(state=None):
return pc


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2 changes: 1 addition & 1 deletion amoco/arch/msp430/cpu.py
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Expand Up @@ -23,7 +23,7 @@
disassemble.maxlen = 6


def PC():
def PC(state=None):
return pc


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2 changes: 1 addition & 1 deletion amoco/arch/pic/cpu_pic18f46k22.py
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Expand Up @@ -21,7 +21,7 @@
disassemble = disassembler([spec_pic18], iclass=instruction_f46k22)


def PC():
def PC(state=None):
return pc


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2 changes: 1 addition & 1 deletion amoco/arch/ppc32/cpu.py
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Expand Up @@ -23,7 +23,7 @@
disassemble = disassembler([spec], iclass=instruction_ppc32,endian=endian)


def PC():
def PC(state=None):
return pc

def get_data_endian():
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2 changes: 1 addition & 1 deletion amoco/arch/ppc32/cpu_e200.py
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Expand Up @@ -23,7 +23,7 @@
disassemble = disassembler([spec_vle], iclass=instruction_e200,endian=endian)


def PC():
def PC(state=None):
return pc

def get_data_endian():
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2 changes: 1 addition & 1 deletion amoco/arch/ppc32/e200/spec_e200.py
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Expand Up @@ -8,5 +8,5 @@

# import generic PowerPC ISA (book E):

from amoco.arch.ppc32.spec import *
from amoco.arch.ppc32.spec_booke import *

2 changes: 1 addition & 1 deletion amoco/arch/riscv/cpu_rv32i.py
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Expand Up @@ -22,7 +22,7 @@
disassemble = disassembler([spec_rv32i], iclass=instruction_riscv)


def PC():
def PC(state=None):
return pc


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2 changes: 1 addition & 1 deletion amoco/arch/riscv/cpu_rv64i.py
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Expand Up @@ -22,7 +22,7 @@
disassemble = disassembler([spec_rv64i], iclass=instruction_riscv64)


def PC():
def PC(state=None):
return pc


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2 changes: 1 addition & 1 deletion amoco/arch/sparc/cpu_v8.py
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@
disassemble = disassembler([spec_v8], endian=lambda: -1, iclass=instruction_sparc)


def PC():
def PC(state=None):
return pc


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2 changes: 1 addition & 1 deletion amoco/arch/superh/cpu_sh2.py
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Expand Up @@ -21,7 +21,7 @@
disassemble = disassembler([spec_sh2], endian=lambda: -1, iclass=instruction_sh2)


def PC():
def PC(state=None):
return pc


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2 changes: 1 addition & 1 deletion amoco/arch/superh/cpu_sh4.py
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Expand Up @@ -22,5 +22,5 @@
disassemble = disassembler([spec_sh4], endian=lambda: -1, iclass=instruction_sh4)


def PC():
def PC(state=None):
return pc
2 changes: 1 addition & 1 deletion amoco/arch/tricore/cpu.py
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Expand Up @@ -21,7 +21,7 @@
disassemble = disassembler([spec], iclass=instruction_tricore)


def PC():
def PC(state=None):
return pc


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8 changes: 6 additions & 2 deletions amoco/arch/v850/asm.py
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Expand Up @@ -477,6 +477,7 @@ def i_HSW(i, fmap):
@_pc
def i_SHR(i, fmap):
shift, src = i.operands[0:2]
dst = None
if len(i.operands) == 3:
dst = i.operands[2]
if shift._is_reg:
Expand All @@ -490,12 +491,14 @@ def i_SHR(i, fmap):
fmap[Z] = r == 0
fmap[S] = r.bit(r.size - 1)
fmap[OV] = bit0
fmap[dst] = x
if dst is not None:
fmap[dst] = x


@_pc
def i_SHL(i, fmap):
shift, src = i.operands[0:2]
dst = None
if len(i.operands) == 3:
dst = i.operands[2]
if shift._is_reg:
Expand All @@ -509,7 +512,8 @@ def i_SHL(i, fmap):
fmap[Z] = r == 0
fmap[S] = r.bit(r.size - 1)
fmap[OV] = bit0
fmap[dst] = x
if dst is not None:
fmap[dst] = x


# conditionals :
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2 changes: 1 addition & 1 deletion amoco/arch/v850/cpu_v850e2s.py
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Expand Up @@ -21,7 +21,7 @@
disassemble = disassembler([spec], iclass=instruction_v850)


def PC():
def PC(state=None):
return pc


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2 changes: 1 addition & 1 deletion amoco/arch/w65c02/cpu.py
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Expand Up @@ -21,7 +21,7 @@
disassemble = disassembler([spec], iclass=instruction_w65c02)


def PC():
def PC(state=None):
return pc


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2 changes: 1 addition & 1 deletion amoco/arch/wasm/cpu.py
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Expand Up @@ -27,7 +27,7 @@
disassemble.maxlen = 16


def PC():
def PC(state=None):
return op_ptr


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4 changes: 2 additions & 2 deletions amoco/arch/x64/cpu_x64.py
Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,8 @@
disassemble.maxlen = 15


def PC():
return rip
def PC(state=None):
return rip if state is None else state(ptr(rip,seg=cs))


def get_data_endian():
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