Merge pull request #471 from betrusted-io/stability-refactor

Stability refactor

emulation/ec/betrusted-ec.repl

@@ -1,5 +1,5 @@
 cpu: CPU.VexRiscv @ sysbus
-    cpuType: "rv32i"
+    cpuType: "rv32i_zicsr_zifencei"
     PerformanceInMips: 6
 
 uart: UART.LiteX_UART @ {

emulation/peripherals/ComConnector.cs

@@ -13,13 +13,13 @@
 
 namespace Antmicro.Renode.Peripherals.SPI.Betrusted
 {
-    public interface IComPeripheral : IPeripheral, IInterestingType
+    public interface IComPeripheral : IPeripheral
     {
         ushort Transmit(ushort data);
         bool HasData();
         void FinishTransmission();
     }
-    public interface IComController : IPeripheral, IInterestingType, IGPIOReceiver
+    public interface IComController : IPeripheral, IGPIOReceiver
     {
         ushort Transmit(ushort data);
         void FinishTransmission();

emulation/soc/betrusted-soc.repl

@@ -1,7 +1,7 @@
 // Renode Platform file generated by svd2repl
 // This file is automatically generated
 cpu: CPU.Betrusted.AesVexRiscv @ sysbus
-    cpuType: "rv32imac"
+    cpuType: "rv32imac_zicsr_zifencei"
     privilegeArchitecture: PrivilegeArchitecture.Priv1_10
     PerformanceInMips: 120
 // Platform Peripherals

kernel/assemble.ps1

@@ -13,17 +13,17 @@ Switch ($Arch) {
         # remove existing blobs because otherwise this will append object files to the old blobs
         Remove-Item -Force bin/riscv*.a
 
-        riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32imac src/arch/riscv/asm.S -o bin/$crate.o
-        riscv64-unknown-elf-ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
-        riscv64-unknown-elf-ar crs bin/riscv32imac-unknown-xous-elf.a bin/$crate.o
-        riscv64-unknown-elf-ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
+        riscv-none-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32imac_zicsr_zifencei src/arch/riscv/asm.S -o bin/$crate.o
+        riscv-none-elf-ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
+        riscv-none-elf-ar crs bin/riscv32imac-unknown-xous-elf.a bin/$crate.o
+        riscv-none-elf-ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
 
-        riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32i src/arch/riscv/asm.S -DSKIP_MULTICORE -o bin/$crate.o
-        riscv64-unknown-elf-ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
+        riscv-none-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32i_zicsr_zifencei src/arch/riscv/asm.S -o bin/$crate.o
+        riscv-none-elf-ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
 
-        riscv64-unknown-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64imac src/arch/riscv/asm.S -o bin/$crate.o
-        riscv64-unknown-elf-ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
-        riscv64-unknown-elf-ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
+        riscv-none-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64imac_zicsr_zifencei src/arch/riscv/asm.S -o bin/$crate.o
+        riscv-none-elf-ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
+        riscv-none-elf-ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
     }
     "arm" {
         Remove-Item -Force bin/arm*.a

kernel/assemble.sh

@@ -34,15 +34,15 @@ case $arch in
         # files to the old blobs
         rm -f bin/riscv*.a
 
-        riscv-none-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32imac src/arch/riscv/asm.S -o bin/$crate.o
+        riscv-none-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32imac_zicsr src/arch/riscv/asm.S -o bin/$crate.o
         ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
         ar crs bin/riscv32imac-unknown-xous-elf.a bin/$crate.o
         ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
 
-        riscv-none-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32i src/arch/riscv/asm.S -DSKIP_MULTICORE -o bin/$crate.o
+        riscv-none-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32i_zicsr src/arch/riscv/asm.S -DSKIP_MULTICORE -o bin/$crate.o
         ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
 
-        riscv-none-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64imac src/arch/riscv/asm.S -o bin/$crate.o
+        riscv-none-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64imac_zicsr src/arch/riscv/asm.S -o bin/$crate.o
         ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
         ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
         ;;

kernel/src/arch/riscv/asm.S

@@ -40,7 +40,7 @@ _start:
        handler to set up the remainder of the resume tasks.
     */
     // Restore a default stack pointer - used by interrupt handlers and considered temporary/smashable
-    li          sp, 0xfffefffc
+    li          sp, 0xfffefff0
 
     // setup sie [ssoft, sext]. This corresponds to bits 1 and 9, or 0b10_0000_0010
     li          t0, 0x202
@@ -49,7 +49,7 @@ _start:
     // restore the SIM with the value previously socked away by the interrupt handler routine during the suspend half
     jal         ra, _enable_all_irqs
 
-    // set scause to simulate an interrupt's occurence -- this makes the resume "feel like" an interrupt
+    // set scause to simulate an interrupt's occurrence -- this makes the resume "feel like" an interrupt
     // vectored into the same routine that caused the suspend, but without having gone through the typical
     // interrupt handler mechanisms
     li          t0, 0x80000000
@@ -137,7 +137,7 @@ _start_trap:
     STORE       t0, 1*REGBYTES(sp)
 
     // Restore a default stack pointer
-    li          sp, 0xfffefffc
+    li          sp, 0xfffefff0
 
     // Note that registers $a0-$a7 still contain the arguments
     j           _start_trap_rust
@@ -155,8 +155,8 @@ _xous_resume_context:
 
     LOAD        x1, 0*REGBYTES(sp)
     // Clear any reservations, invalidating any atomic operations
-#ifndef SKIP_MULTICORE
-    sc.w	    zero, x1, 0*REGBYTES(sp)
+#ifdef __riscv_atomic
+    sc.w.rl	    zero, x1, (sp)
 #endif
 
     // Skip SP for now
@@ -222,8 +222,8 @@ _xous_syscall_return_result:
     // one bit, and we can clear the bit by performing a dummy `sc`
     // here. This will cause a failure in any atomic operation in the
     // program we're switching to.
-#ifndef SKIP_MULTICORE
-    sc.w	    zero, x1, 0*REGBYTES(sp)
+#ifdef __riscv_atomic
+    sc.w.rl	    zero, x1, (sp)
 #endif
 
     // Skip SP for now
@@ -261,8 +261,10 @@ _xous_syscall_return_result:
     LOAD        x30, 29*REGBYTES(sp)
     LOAD        x31, 30*REGBYTES(sp)
 
+    fence
+
     // Restore SP
-    //csrr        t0, sscratch
+    //csrr      t0, sscratch
     LOAD        x2, 1*REGBYTES(sp)
     sret
 

kernel/src/arch/riscv/mem.rs

@@ -5,7 +5,7 @@ use crate::arch::process::InitialProcess;
 use crate::mem::MemoryManager;
 use core::fmt;
 use riscv::register::satp;
-#[cfg(feature="gdb-stub")]
+#[cfg(feature = "gdb-stub")]
 use riscv::register::sstatus;
 use xous_kernel::{MemoryFlags, PID};
 
@@ -259,12 +259,16 @@ impl MemoryMapping {
     }
 
     /// Get the "PID" (actually, ASID) from the current mapping
-    pub fn get_pid(&self) -> PID {
-        PID::new((self.satp >> 22 & ((1 << 9) - 1)) as _).unwrap()
+    pub fn get_pid(&self) -> Option<PID> {
+        PID::new((self.satp >> 22 & ((1 << 9) - 1)) as _)
+    }
+
+    pub fn is_allocated(&self) -> bool {
+        self.get_pid().is_some()
     }
 
     pub fn is_kernel(&self) -> bool {
-        self.get_pid().get() == 1
+        self.get_pid().map(|v| v.get() == 1).unwrap_or(false)
     }
 
     /// Set this mapping as the systemwide mapping.
@@ -279,8 +283,54 @@ impl MemoryMapping {
         Ok(())
     }
 
+    pub fn phys_to_virt(&self, phys: usize) -> Result<Option<u32>, xous_kernel::Error> {
+        let mut found = None;
+        let l1_pt = unsafe { &mut (*(PAGE_TABLE_ROOT_OFFSET as *mut RootPageTable)) };
+        if phys & PAGE_SIZE - 1 != 0 {
+            return Err(xous_kernel::Error::BadAlignment);
+        }
+        for (i, l1_entry) in l1_pt.entries.iter().enumerate() {
+            if *l1_entry == 0 {
+                continue;
+            }
+            let _superpage_addr = i as u32 * (1 << 22);
+
+            // Page 1023 is only available to PID1
+            if i == 1023 && !self.is_kernel() {
+                continue;
+            }
+            let l0_pt = unsafe { &mut (*((PAGE_TABLE_OFFSET + i * 4096) as *mut LeafPageTable)) };
+            for (j, l0_entry) in l0_pt.entries.iter().enumerate() {
+                if *l0_entry & 0x7 == 0 {
+                    continue;
+                }
+                let _page_addr = j as u32 * (1 << 12);
+                let virt_addr = _superpage_addr + _page_addr;
+                let phys_addr = (*l0_entry >> 10) << 12;
+                let valid = (l0_entry & MMUFlags::VALID.bits()) != 0;
+                let shared = (l0_entry & MMUFlags::S.bits()) != 0;
+                if phys_addr == phys && (valid || shared) {
+                    if found.is_none() {
+                        found = Some(virt_addr);
+                    } else {
+                        println!("Page is mapped twice within process {:08x}!", phys_addr);
+                        return Err(xous_kernel::Error::MemoryInUse);
+                    }
+                }
+            }
+        }
+        Ok(found)
+    }
+
     pub fn print_map(&self) {
-        println!("Memory Maps for PID {}:", self.get_pid());
+        if !self.is_allocated() {
+            println!("Process isn't allocated!");
+            return;
+        }
+        println!(
+            "Memory Maps for PID {}:",
+            self.get_pid().map(|v| v.get()).unwrap_or(0)
+        );
         let l1_pt = unsafe { &mut (*(PAGE_TABLE_ROOT_OFFSET as *mut RootPageTable)) };
         for (i, l1_entry) in l1_pt.entries.iter().enumerate() {
             if *l1_entry == 0 {
@@ -723,7 +773,7 @@ pub fn move_page_inner(
     result
 }
 
-/// Determine if a page has been lent.
+/// Determine if a virtual page has been lent.
 pub fn page_is_lent(src_addr: *mut u8) -> bool {
     pagetable_entry(src_addr as usize).map_or(
         false,

kernel/src/arch/riscv/process.rs

@@ -81,6 +81,21 @@ struct ProcessImpl {
     threads: [Thread; MAX_THREAD],
 }
 
+/// Compile-time assertion that the procesor-specific Process implementation
+/// is a multiple of the page size.
+fn _assert_processimpl_is_page_sized() {
+    unsafe {
+        mem::transmute::<ProcessImpl, [u8; crate::mem::PAGE_SIZE]>(ProcessImpl {
+            scratch: 0,
+            hardware_thread: 0,
+            inner: Default::default(),
+            last_tid_allocated: 0,
+            _padding: [0; 13],
+            threads: [Default::default(); MAX_THREAD],
+        });
+    }
+}
+
 /// Singleton process table. Each process in the system gets allocated from this table.
 struct ProcessTable {
     /// The process upon which the current syscall is operating
@@ -294,10 +309,10 @@ impl Process {
     }
 
     pub fn set_thread_result(&mut self, thread_nr: TID, result: xous_kernel::Result) {
-        let vals = unsafe { mem::transmute::<_, [usize; 8]>(result) };
+        let vals = result.to_args();
         let thread = self.thread_mut(thread_nr);
-        for (idx, reg) in vals.iter().enumerate() {
-            thread.registers[9 + idx] = *reg;
+        for (src, dest) in vals.iter().zip(thread.registers[9..].iter_mut()) {
+            *dest = *src;
         }
     }
 
@@ -365,7 +380,7 @@ impl Process {
 
         let thread = &mut process.threads[tid];
 
-        thread.sepc = unsafe { core::mem::transmute::<_, usize>(thread_init.call) };
+        thread.sepc = thread_init.call as usize;
         thread.registers[1] = thread_init.stack.as_ptr() as usize + thread_init.stack.len();
         thread.registers[9] = thread_init.arg1;
         thread.registers[10] = thread_init.arg2;
@@ -410,7 +425,7 @@ impl Process {
         new_tid: TID,
         setup: ThreadInit,
     ) -> Result<(), xous_kernel::Error> {
-        let entrypoint = unsafe { core::mem::transmute::<_, usize>(setup.call) };
+        let entrypoint = setup.call as usize;
         // Create the new context and set it to run in the new address space.
         let pid = self.pid.get();
         let thread = self.thread_mut(new_tid);

kernel/src/debug/shell.rs

@@ -100,6 +100,14 @@ fn handle_character(b: u8) {
                 });
             });
         }
+        #[cfg(all(baremetal, target_arch = "riscv32"))]
+        b'k' => {
+            println!("Checking RAM for duplicate pages (this will take a few minutes)");
+            crate::mem::MemoryManager::with(|mm| {
+                mm.check_for_duplicates();
+            });
+            println!("Check complete");
+        }
         b'm' => {
             println!("Printing memory page tables");
             crate::services::SystemServices::with(|system_services| {
@@ -228,6 +236,8 @@ fn print_help() {
     println!("--- + -----------------------");
     println!(" h  | print this message");
     println!(" i  | print irq handlers");
+    #[cfg(all(baremetal, target_arch = "riscv32"))]
+    println!(" k  | check RAM to make sure pages are unique");
     println!(" m  | print MMU page tables of all processes");
     println!(" p  | print all processes");
     println!(" P  | print all processes and threads");